diff --git a/library/SubcircuitLibrary/CD4017B/CD4017B-cache.lib b/library/SubcircuitLibrary/CD4017B/CD4017B-cache.lib new file mode 100644 index 000000000..93027b16b --- /dev/null +++ b/library/SubcircuitLibrary/CD4017B/CD4017B-cache.lib @@ -0,0 +1,143 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_buffer +# +DEF d_buffer U 0 40 Y Y 1 F N +F0 "U" 0 -50 60 H V C CNN +F1 "d_buffer" 0 50 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 4 0 1 0 -300 200 -300 -200 450 0 -300 200 N +X IN 1 -500 0 200 R 50 50 1 1 I +X OUT 2 650 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_dff +# +DEF d_dff U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_dff" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S 350 450 -350 -400 0 1 0 N +X Din 1 -550 350 200 R 50 50 1 1 I +X Clk 2 -550 -300 200 R 50 50 1 1 I C +X Set 3 0 650 200 D 50 50 1 1 I +X Reset 4 0 -600 200 U 50 50 1 1 I +X Dout 5 550 350 200 L 50 50 1 1 O +X Ndout 6 550 -300 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nand +# +DEF d_nand U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nand" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nor +# +DEF d_nor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nor" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/CD4017B/CD4017B.bak b/library/SubcircuitLibrary/CD4017B/CD4017B.bak new file mode 100644 index 000000000..f00f56a04 --- /dev/null +++ b/library/SubcircuitLibrary/CD4017B/CD4017B.bak @@ -0,0 +1,1203 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:CD4017B-cache +EELAYER 25 0 +EELAYER END +$Descr A1 33110 23386 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_dff U13 +U 1 1 68664336 +P 10050 13000 +F 0 "U13" H 10050 13000 60 0000 C CNN +F 1 "d_dff" H 10050 13150 60 0000 C CNN +F 2 "" H 10050 13000 60 0000 C CNN +F 3 "" H 10050 13000 60 0000 C CNN + 1 10050 13000 + 1 0 0 -1 +$EndComp +$Comp +L d_dff U30 +U 1 1 6866447A +P 17900 12800 +F 0 "U30" H 17900 12800 60 0000 C CNN +F 1 "d_dff" H 17900 12950 60 0000 C CNN +F 2 "" H 17900 12800 60 0000 C CNN +F 3 "" H 17900 12800 60 0000 C CNN + 1 17900 12800 + 1 0 0 -1 +$EndComp +$Comp +L d_dff U47 +U 1 1 686645F8 +P 26450 12550 +F 0 "U47" H 26450 12550 60 0000 C CNN +F 1 "d_dff" H 26450 12700 60 0000 C CNN +F 2 "" H 26450 12550 60 0000 C CNN +F 3 "" H 26450 12550 60 0000 C CNN + 1 26450 12550 + 1 0 0 -1 +$EndComp +$Comp +L d_buffer U3 +U 1 1 686647DD +P 5100 21550 +F 0 "U3" H 5100 21500 60 0000 C CNN +F 1 "d_buffer" H 5100 21600 60 0000 C CNN +F 2 "" H 5100 21550 60 0000 C CNN +F 3 "" H 5100 21550 60 0000 C CNN + 1 5100 21550 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U6 +U 1 1 68664852 +P 6550 21550 +F 0 "U6" H 6550 21450 60 0000 C CNN +F 1 "d_inverter" H 6550 21700 60 0000 C CNN +F 2 "" H 6600 21500 60 0000 C CNN +F 3 "" H 6600 21500 60 0000 C CNN + 1 6550 21550 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U8 +U 1 1 686648C7 +P 7650 21550 +F 0 "U8" H 7650 21450 60 0000 C CNN +F 1 "d_inverter" H 7650 21700 60 0000 C CNN +F 2 "" H 7700 21500 60 0000 C CNN +F 3 "" H 7700 21500 60 0000 C CNN + 1 7650 21550 + 1 0 0 -1 +$EndComp +$Comp +L d_buffer U12 +U 1 1 68664946 +P 8850 21550 +F 0 "U12" H 8850 21500 60 0000 C CNN +F 1 "d_buffer" H 8850 21600 60 0000 C CNN +F 2 "" H 8850 21550 60 0000 C CNN +F 3 "" H 8850 21550 60 0000 C CNN + 1 8850 21550 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U14 +U 1 1 68664AE0 +P 10150 20700 +F 0 "U14" H 10150 20700 60 0000 C CNN +F 1 "d_nor" H 10200 20800 60 0000 C CNN +F 2 "" H 10150 20700 60 0000 C CNN +F 3 "" H 10150 20700 60 0000 C CNN + 1 10150 20700 + 1 0 0 -1 +$EndComp +$Comp +L d_buffer U2 +U 1 1 686655EB +P 4250 13950 +F 0 "U2" H 4250 13900 60 0000 C CNN +F 1 "d_buffer" H 4250 14000 60 0000 C CNN +F 2 "" H 4250 13950 60 0000 C CNN +F 3 "" H 4250 13950 60 0000 C CNN + 1 4250 13950 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U4 +U 1 1 68665755 +P 5600 13950 +F 0 "U4" H 5600 13850 60 0000 C CNN +F 1 "d_inverter" H 5600 14100 60 0000 C CNN +F 2 "" H 5650 13900 60 0000 C CNN +F 3 "" H 5650 13900 60 0000 C CNN + 1 5600 13950 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U5 +U 1 1 68665840 +P 6450 13950 +F 0 "U5" H 6450 13850 60 0000 C CNN +F 1 "d_inverter" H 6450 14100 60 0000 C CNN +F 2 "" H 6500 13900 60 0000 C CNN +F 3 "" H 6500 13900 60 0000 C CNN + 1 6450 13950 + 1 0 0 -1 +$EndComp +$Comp +L d_buffer U7 +U 1 1 68665887 +P 7500 13950 +F 0 "U7" H 7500 13900 60 0000 C CNN +F 1 "d_buffer" H 7500 14000 60 0000 C CNN +F 2 "" H 7500 13950 60 0000 C CNN +F 3 "" H 7500 13950 60 0000 C CNN + 1 7500 13950 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U11 +U 1 1 68666477 +P 8300 4500 +F 0 "U11" H 8300 4500 60 0000 C CNN +F 1 "d_nand" H 8350 4600 60 0000 C CNN +F 2 "" H 8300 4500 60 0000 C CNN +F 3 "" H 8300 4500 60 0000 C CNN + 1 8300 4500 + 0 -1 -1 0 +$EndComp +$Comp +L d_nand U17 +U 1 1 686665F7 +P 10300 4500 +F 0 "U17" H 10300 4500 60 0000 C CNN +F 1 "d_nand" H 10350 4600 60 0000 C CNN +F 2 "" H 10300 4500 60 0000 C CNN +F 3 "" H 10300 4500 60 0000 C CNN + 1 10300 4500 + 0 -1 -1 0 +$EndComp +$Comp +L d_nand U20 +U 1 1 686666A4 +P 12250 4450 +F 0 "U20" H 12250 4450 60 0000 C CNN +F 1 "d_nand" H 12300 4550 60 0000 C CNN +F 2 "" H 12250 4450 60 0000 C CNN +F 3 "" H 12250 4450 60 0000 C CNN + 1 12250 4450 + 0 -1 -1 0 +$EndComp +$Comp +L d_nand U25 +U 1 1 686667BA +P 13950 4500 +F 0 "U25" H 13950 4500 60 0000 C CNN +F 1 "d_nand" H 14000 4600 60 0000 C CNN +F 2 "" H 13950 4500 60 0000 C CNN +F 3 "" H 13950 4500 60 0000 C CNN + 1 13950 4500 + 0 -1 -1 0 +$EndComp +$Comp +L d_nand U29 +U 1 1 68666843 +P 15800 4500 +F 0 "U29" H 15800 4500 60 0000 C CNN +F 1 "d_nand" H 15850 4600 60 0000 C CNN +F 2 "" H 15800 4500 60 0000 C CNN +F 3 "" H 15800 4500 60 0000 C CNN + 1 15800 4500 + 0 -1 -1 0 +$EndComp +$Comp +L d_nand U33 +U 1 1 686668C6 +P 17950 4500 +F 0 "U33" H 17950 4500 60 0000 C CNN +F 1 "d_nand" H 18000 4600 60 0000 C CNN +F 2 "" H 17950 4500 60 0000 C CNN +F 3 "" H 17950 4500 60 0000 C CNN + 1 17950 4500 + 0 -1 -1 0 +$EndComp +$Comp +L d_nand U36 +U 1 1 686669C1 +P 20050 4450 +F 0 "U36" H 20050 4450 60 0000 C CNN +F 1 "d_nand" H 20100 4550 60 0000 C CNN +F 2 "" H 20050 4450 60 0000 C CNN +F 3 "" H 20050 4450 60 0000 C CNN + 1 20050 4450 + 0 -1 -1 0 +$EndComp +$Comp +L d_nand U40 +U 1 1 68666A5C +P 21950 4450 +F 0 "U40" H 21950 4450 60 0000 C CNN +F 1 "d_nand" H 22000 4550 60 0000 C CNN +F 2 "" H 21950 4450 60 0000 C CNN +F 3 "" H 21950 4450 60 0000 C CNN + 1 21950 4450 + 0 -1 -1 0 +$EndComp +$Comp +L d_nand U43 +U 1 1 68666BA5 +P 23650 4450 +F 0 "U43" H 23650 4450 60 0000 C CNN +F 1 "d_nand" H 23700 4550 60 0000 C CNN +F 2 "" H 23650 4450 60 0000 C CNN +F 3 "" H 23650 4450 60 0000 C CNN + 1 23650 4450 + 0 -1 -1 0 +$EndComp +$Comp +L d_nand U46 +U 1 1 68666C44 +P 25300 4450 +F 0 "U46" H 25300 4450 60 0000 C CNN +F 1 "d_nand" H 25350 4550 60 0000 C CNN +F 2 "" H 25300 4450 60 0000 C CNN +F 3 "" H 25300 4450 60 0000 C CNN + 1 25300 4450 + 0 -1 -1 0 +$EndComp +$Comp +L d_and U21 +U 1 1 6866E2FD +P 13950 16200 +F 0 "U21" H 13950 16200 60 0000 C CNN +F 1 "d_and" H 14000 16300 60 0000 C CNN +F 2 "" H 13950 16200 60 0000 C CNN +F 3 "" H 13950 16200 60 0000 C CNN + 1 13950 16200 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U26 +U 1 1 6866E390 +P 15800 15650 +F 0 "U26" H 15800 15650 60 0000 C CNN +F 1 "d_nor" H 15850 15750 60 0000 C CNN +F 2 "" H 15800 15650 60 0000 C CNN +F 3 "" H 15800 15650 60 0000 C CNN + 1 15800 15650 + 1 0 0 -1 +$EndComp +$Comp +L d_buffer U53 +U 1 1 686742A7 +P 27900 8600 +F 0 "U53" H 27900 8550 60 0000 C CNN +F 1 "d_buffer" H 27900 8650 60 0000 C CNN +F 2 "" H 27900 8600 60 0000 C CNN +F 3 "" H 27900 8600 60 0000 C CNN + 1 27900 8600 + 0 -1 -1 0 +$EndComp +$Comp +L d_inverter U52 +U 1 1 68674360 +P 27900 7250 +F 0 "U52" H 27900 7150 60 0000 C CNN +F 1 "d_inverter" H 27900 7400 60 0000 C CNN +F 2 "" H 27950 7200 60 0000 C CNN +F 3 "" H 27950 7200 60 0000 C CNN + 1 27900 7250 + 0 -1 -1 0 +$EndComp +$Comp +L d_inverter U51 +U 1 1 686743E3 +P 27900 5950 +F 0 "U51" H 27900 5850 60 0000 C CNN +F 1 "d_inverter" H 27900 6100 60 0000 C CNN +F 2 "" H 27950 5900 60 0000 C CNN +F 3 "" H 27950 5900 60 0000 C CNN + 1 27900 5950 + 0 -1 -1 0 +$EndComp +$Comp +L d_buffer U50 +U 1 1 68674539 +P 27900 4800 +F 0 "U50" H 27900 4750 60 0000 C CNN +F 1 "d_buffer" H 27900 4850 60 0000 C CNN +F 2 "" H 27900 4800 60 0000 C CNN +F 3 "" H 27900 4800 60 0000 C CNN + 1 27900 4800 + 0 -1 -1 0 +$EndComp +$Comp +L d_buffer U49 +U 1 1 686745C8 +P 27900 3100 +F 0 "U49" H 27900 3050 60 0000 C CNN +F 1 "d_buffer" H 27900 3150 60 0000 C CNN +F 2 "" H 27900 3100 60 0000 C CNN +F 3 "" H 27900 3100 60 0000 C CNN + 1 27900 3100 + 0 -1 -1 0 +$EndComp +$Comp +L d_inverter U48 +U 1 1 68674685 +P 27900 1700 +F 0 "U48" H 27900 1600 60 0000 C CNN +F 1 "d_inverter" H 27900 1850 60 0000 C CNN +F 2 "" H 27950 1650 60 0000 C CNN +F 3 "" H 27950 1650 60 0000 C CNN + 1 27900 1700 + 0 -1 -1 0 +$EndComp +$Comp +L d_inverter U10 +U 1 1 686757F7 +P 8250 2650 +F 0 "U10" H 8250 2550 60 0000 C CNN +F 1 "d_inverter" H 8250 2800 60 0000 C CNN +F 2 "" H 8300 2600 60 0000 C CNN +F 3 "" H 8300 2600 60 0000 C CNN + 1 8250 2650 + 0 -1 -1 0 +$EndComp +$Comp +L d_buffer U9 +U 1 1 686758E8 +P 8250 1100 +F 0 "U9" H 8250 1050 60 0000 C CNN +F 1 "d_buffer" H 8250 1150 60 0000 C CNN +F 2 "" H 8250 1100 60 0000 C CNN +F 3 "" H 8250 1100 60 0000 C CNN + 1 8250 1100 + 0 -1 -1 0 +$EndComp +$Comp +L d_inverter U16 +U 1 1 68675D57 +P 10150 2650 +F 0 "U16" H 10150 2550 60 0000 C CNN +F 1 "d_inverter" H 10150 2800 60 0000 C CNN +F 2 "" H 10200 2600 60 0000 C CNN +F 3 "" H 10200 2600 60 0000 C CNN + 1 10150 2650 + 0 -1 -1 0 +$EndComp +$Comp +L d_buffer U15 +U 1 1 68675D5D +P 10150 1100 +F 0 "U15" H 10150 1050 60 0000 C CNN +F 1 "d_buffer" H 10150 1150 60 0000 C CNN +F 2 "" H 10150 1100 60 0000 C CNN +F 3 "" H 10150 1100 60 0000 C CNN + 1 10150 1100 + 0 -1 -1 0 +$EndComp +$Comp +L d_inverter U19 +U 1 1 68676262 +P 12150 2750 +F 0 "U19" H 12150 2650 60 0000 C CNN +F 1 "d_inverter" H 12150 2900 60 0000 C CNN +F 2 "" H 12200 2700 60 0000 C CNN +F 3 "" H 12200 2700 60 0000 C CNN + 1 12150 2750 + 0 -1 -1 0 +$EndComp +$Comp +L d_buffer U18 +U 1 1 68676268 +P 12150 1200 +F 0 "U18" H 12150 1150 60 0000 C CNN +F 1 "d_buffer" H 12150 1250 60 0000 C CNN +F 2 "" H 12150 1200 60 0000 C CNN +F 3 "" H 12150 1200 60 0000 C CNN + 1 12150 1200 + 0 -1 -1 0 +$EndComp +$Comp +L d_inverter U24 +U 1 1 6867626F +P 13900 2750 +F 0 "U24" H 13900 2650 60 0000 C CNN +F 1 "d_inverter" H 13900 2900 60 0000 C CNN +F 2 "" H 13950 2700 60 0000 C CNN +F 3 "" H 13950 2700 60 0000 C CNN + 1 13900 2750 + 0 -1 -1 0 +$EndComp +$Comp +L d_buffer U23 +U 1 1 68676275 +P 13900 1200 +F 0 "U23" H 13900 1150 60 0000 C CNN +F 1 "d_buffer" H 13900 1250 60 0000 C CNN +F 2 "" H 13900 1200 60 0000 C CNN +F 3 "" H 13900 1200 60 0000 C CNN + 1 13900 1200 + 0 -1 -1 0 +$EndComp +$Comp +L d_inverter U28 +U 1 1 6867676C +P 15750 2850 +F 0 "U28" H 15750 2750 60 0000 C CNN +F 1 "d_inverter" H 15750 3000 60 0000 C CNN +F 2 "" H 15800 2800 60 0000 C CNN +F 3 "" H 15800 2800 60 0000 C CNN + 1 15750 2850 + 0 -1 -1 0 +$EndComp +$Comp +L d_buffer U27 +U 1 1 68676772 +P 15750 1300 +F 0 "U27" H 15750 1250 60 0000 C CNN +F 1 "d_buffer" H 15750 1350 60 0000 C CNN +F 2 "" H 15750 1300 60 0000 C CNN +F 3 "" H 15750 1300 60 0000 C CNN + 1 15750 1300 + 0 -1 -1 0 +$EndComp +$Comp +L d_inverter U32 +U 1 1 68676779 +P 17900 2900 +F 0 "U32" H 17900 2800 60 0000 C CNN +F 1 "d_inverter" H 17900 3050 60 0000 C CNN +F 2 "" H 17950 2850 60 0000 C CNN +F 3 "" H 17950 2850 60 0000 C CNN + 1 17900 2900 + 0 -1 -1 0 +$EndComp +$Comp +L d_buffer U31 +U 1 1 6867677F +P 17900 1350 +F 0 "U31" H 17900 1300 60 0000 C CNN +F 1 "d_buffer" H 17900 1400 60 0000 C CNN +F 2 "" H 17900 1350 60 0000 C CNN +F 3 "" H 17900 1350 60 0000 C CNN + 1 17900 1350 + 0 -1 -1 0 +$EndComp +$Comp +L d_inverter U35 +U 1 1 68676786 +P 20000 2950 +F 0 "U35" H 20000 2850 60 0000 C CNN +F 1 "d_inverter" H 20000 3100 60 0000 C CNN +F 2 "" H 20050 2900 60 0000 C CNN +F 3 "" H 20050 2900 60 0000 C CNN + 1 20000 2950 + 0 -1 -1 0 +$EndComp +$Comp +L d_buffer U34 +U 1 1 6867678C +P 20000 1400 +F 0 "U34" H 20000 1350 60 0000 C CNN +F 1 "d_buffer" H 20000 1450 60 0000 C CNN +F 2 "" H 20000 1400 60 0000 C CNN +F 3 "" H 20000 1400 60 0000 C CNN + 1 20000 1400 + 0 -1 -1 0 +$EndComp +$Comp +L d_inverter U38 +U 1 1 68676793 +P 21400 2950 +F 0 "U38" H 21400 2850 60 0000 C CNN +F 1 "d_inverter" H 21400 3100 60 0000 C CNN +F 2 "" H 21450 2900 60 0000 C CNN +F 3 "" H 21450 2900 60 0000 C CNN + 1 21400 2950 + 0 -1 -1 0 +$EndComp +$Comp +L d_buffer U37 +U 1 1 68676799 +P 21400 1400 +F 0 "U37" H 21400 1350 60 0000 C CNN +F 1 "d_buffer" H 21400 1450 60 0000 C CNN +F 2 "" H 21400 1400 60 0000 C CNN +F 3 "" H 21400 1400 60 0000 C CNN + 1 21400 1400 + 0 -1 -1 0 +$EndComp +$Comp +L d_inverter U42 +U 1 1 68676C38 +P 23600 2950 +F 0 "U42" H 23600 2850 60 0000 C CNN +F 1 "d_inverter" H 23600 3100 60 0000 C CNN +F 2 "" H 23650 2900 60 0000 C CNN +F 3 "" H 23650 2900 60 0000 C CNN + 1 23600 2950 + 0 -1 -1 0 +$EndComp +$Comp +L d_buffer U41 +U 1 1 68676C3E +P 23600 1400 +F 0 "U41" H 23600 1350 60 0000 C CNN +F 1 "d_buffer" H 23600 1450 60 0000 C CNN +F 2 "" H 23600 1400 60 0000 C CNN +F 3 "" H 23600 1400 60 0000 C CNN + 1 23600 1400 + 0 -1 -1 0 +$EndComp +$Comp +L d_inverter U45 +U 1 1 68676C45 +P 25250 2950 +F 0 "U45" H 25250 2850 60 0000 C CNN +F 1 "d_inverter" H 25250 3100 60 0000 C CNN +F 2 "" H 25300 2900 60 0000 C CNN +F 3 "" H 25300 2900 60 0000 C CNN + 1 25250 2950 + 0 -1 -1 0 +$EndComp +$Comp +L d_buffer U44 +U 1 1 68676C4B +P 25250 1400 +F 0 "U44" H 25250 1350 60 0000 C CNN +F 1 "d_buffer" H 25250 1450 60 0000 C CNN +F 2 "" H 25250 1400 60 0000 C CNN +F 3 "" H 25250 1400 60 0000 C CNN + 1 25250 1400 + 0 -1 -1 0 +$EndComp +NoConn ~ 10050 12350 +NoConn ~ 14100 12250 +NoConn ~ 22050 12050 +NoConn ~ 26450 11900 +$Comp +L PORT U1 +U 15 1 6867C073 +P 2400 13950 +F 0 "U1" H 2450 14050 30 0000 C CNN +F 1 "PORT" H 2400 13950 30 0000 C CNN +F 2 "" H 2400 13950 60 0000 C CNN +F 3 "" H 2400 13950 60 0000 C CNN + 15 2400 13950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 14 1 6867C485 +P 4150 20550 +F 0 "U1" H 4200 20650 30 0000 C CNN +F 1 "PORT" H 4150 20550 30 0000 C CNN +F 2 "" H 4150 20550 60 0000 C CNN +F 3 "" H 4150 20550 60 0000 C CNN + 14 4150 20550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 6867C98A +P 4150 21550 +F 0 "U1" H 4200 21650 30 0000 C CNN +F 1 "PORT" H 4150 21550 30 0000 C CNN +F 2 "" H 4150 21550 60 0000 C CNN +F 3 "" H 4150 21550 60 0000 C CNN + 13 4150 21550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 6867CA21 +P 8000 -200 +F 0 "U1" H 8050 -100 30 0000 C CNN +F 1 "PORT" H 8000 -200 30 0000 C CNN +F 2 "" H 8000 -200 60 0000 C CNN +F 3 "" H 8000 -200 60 0000 C CNN + 3 8000 -200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 6867D1A2 +P 9900 -250 +F 0 "U1" H 9950 -150 30 0000 C CNN +F 1 "PORT" H 9900 -250 30 0000 C CNN +F 2 "" H 9900 -250 60 0000 C CNN +F 3 "" H 9900 -250 60 0000 C CNN + 2 9900 -250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 6867D490 +P 11900 -300 +F 0 "U1" H 11950 -200 30 0000 C CNN +F 1 "PORT" H 11900 -300 30 0000 C CNN +F 2 "" H 11900 -300 60 0000 C CNN +F 3 "" H 11900 -300 60 0000 C CNN + 4 11900 -300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 6867D78D +P 13650 -400 +F 0 "U1" H 13700 -300 30 0000 C CNN +F 1 "PORT" H 13650 -400 30 0000 C CNN +F 2 "" H 13650 -400 60 0000 C CNN +F 3 "" H 13650 -400 60 0000 C CNN + 7 13650 -400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 6867DA81 +P 15500 -450 +F 0 "U1" H 15550 -350 30 0000 C CNN +F 1 "PORT" H 15500 -450 30 0000 C CNN +F 2 "" H 15500 -450 60 0000 C CNN +F 3 "" H 15500 -450 60 0000 C CNN + 10 15500 -450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 6867DCF8 +P 17650 -450 +F 0 "U1" H 17700 -350 30 0000 C CNN +F 1 "PORT" H 17650 -450 30 0000 C CNN +F 2 "" H 17650 -450 60 0000 C CNN +F 3 "" H 17650 -450 60 0000 C CNN + 1 17650 -450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 6867E1B9 +P 19700 -500 +F 0 "U1" H 19750 -400 30 0000 C CNN +F 1 "PORT" H 19700 -500 30 0000 C CNN +F 2 "" H 19700 -500 60 0000 C CNN +F 3 "" H 19700 -500 60 0000 C CNN + 5 19700 -500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 6867E540 +P 21150 -500 +F 0 "U1" H 21200 -400 30 0000 C CNN +F 1 "PORT" H 21150 -500 30 0000 C CNN +F 2 "" H 21150 -500 60 0000 C CNN +F 3 "" H 21150 -500 60 0000 C CNN + 6 21150 -500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 6867E783 +P 23300 -500 +F 0 "U1" H 23350 -400 30 0000 C CNN +F 1 "PORT" H 23300 -500 30 0000 C CNN +F 2 "" H 23300 -500 60 0000 C CNN +F 3 "" H 23300 -500 60 0000 C CNN + 9 23300 -500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 6867ECB8 +P 25000 -550 +F 0 "U1" H 25050 -450 30 0000 C CNN +F 1 "PORT" H 25000 -550 30 0000 C CNN +F 2 "" H 25000 -550 60 0000 C CNN +F 3 "" H 25000 -550 60 0000 C CNN + 11 25000 -550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 6867F09D +P 27650 950 +F 0 "U1" H 27700 1050 30 0000 C CNN +F 1 "PORT" H 27650 950 30 0000 C CNN +F 2 "" H 27650 950 60 0000 C CNN +F 3 "" H 27650 950 60 0000 C CNN + 12 27650 950 + 1 0 0 -1 +$EndComp +$Comp +L d_dff U22 +U 1 1 68665BE0 +P 14100 12900 +F 0 "U22" H 14100 12900 60 0000 C CNN +F 1 "d_dff" H 14100 13050 60 0000 C CNN +F 2 "" H 14100 12900 60 0000 C CNN +F 3 "" H 14100 12900 60 0000 C CNN + 1 14100 12900 + 1 0 0 -1 +$EndComp +$Comp +L d_buffer U56 +U 1 1 686689C2 +P 23100 13000 +F 0 "U56" H 23100 12950 60 0000 C CNN +F 1 "d_buffer" H 23100 13050 60 0000 C CNN +F 2 "" H 23100 13000 60 0000 C CNN +F 3 "" H 23100 13000 60 0000 C CNN + 1 23100 13000 + 1 0 0 -1 +$EndComp +$Comp +L d_buffer U55 +U 1 1 68669858 +P 19250 13100 +F 0 "U55" H 19250 13050 60 0000 C CNN +F 1 "d_buffer" H 19250 13150 60 0000 C CNN +F 2 "" H 19250 13100 60 0000 C CNN +F 3 "" H 19250 13100 60 0000 C CNN + 1 19250 13100 + 1 0 0 -1 +$EndComp +$Comp +L d_buffer U57 +U 1 1 6866BF79 +P 27650 12850 +F 0 "U57" H 27650 12800 60 0000 C CNN +F 1 "d_buffer" H 27650 12900 60 0000 C CNN +F 2 "" H 27650 12850 60 0000 C CNN +F 3 "" H 27650 12850 60 0000 C CNN + 1 27650 12850 + 1 0 0 -1 +$EndComp +$Comp +L d_buffer U58 +U 1 1 6866E83D +P 11250 13300 +F 0 "U58" H 11250 13250 60 0000 C CNN +F 1 "d_buffer" H 11250 13350 60 0000 C CNN +F 2 "" H 11250 13300 60 0000 C CNN +F 3 "" H 11250 13300 60 0000 C CNN + 1 11250 13300 + 1 0 0 -1 +$EndComp +$Comp +L d_buffer U54 +U 1 1 6866DC5D +P 15350 13200 +F 0 "U54" H 15350 13150 60 0000 C CNN +F 1 "d_buffer" H 15350 13250 60 0000 C CNN +F 2 "" H 15350 13200 60 0000 C CNN +F 3 "" H 15350 13200 60 0000 C CNN + 1 15350 13200 + 1 0 0 -1 +$EndComp +Text Label 8250 250 0 60 ~ 0 +0 +Text Label 10150 100 0 60 ~ 0 +1 +Text Label 12150 150 0 60 ~ 0 +2 +Text Label 13900 -50 0 60 ~ 0 +3 +Text Label 15800 -100 0 60 ~ 0 +4 +Text Label 17900 -50 0 60 ~ 0 +5 +Text Label 20000 -100 0 60 ~ 0 +6 +Text Label 21400 -200 0 60 ~ 0 +7 +Text Label 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Wire Line + 20600 12950 20600 13100 +Connection ~ 20550 8450 +Wire Wire Line + 12600 16100 12600 8500 +Wire Wire Line + 12600 8500 12250 8500 +Connection ~ 12250 8450 +Wire Wire Line + 24100 7150 24100 12600 +Wire Wire Line + 24100 12600 23750 12600 +Connection ~ 24100 7150 +Wire Wire Line + 15800 11600 28400 11600 +Connection ~ 15800 5650 +Wire Wire Line + 10600 12550 13550 12550 +Wire Wire Line + 10600 12550 10600 12650 +Wire Wire Line + 11200 12550 11200 9850 +Connection ~ 11200 9850 +Connection ~ 11200 12550 +Wire Wire Line + 14650 12550 15050 12550 +Wire Wire Line + 15050 12550 15050 8850 +Connection ~ 15050 8850 +Wire Wire Line + 19300 7650 19300 12450 +Connection ~ 19300 7650 +Connection ~ 19300 12450 +Wire Wire Line + 25550 12350 22600 12350 +Wire Wire Line + 23000 6600 23000 12350 +Connection ~ 23000 12350 +Connection ~ 23000 6600 +Wire Wire Line + 25300 9400 27900 9400 +Connection ~ 25300 5600 +Wire Wire Line + 18750 13100 18450 13100 +Wire Wire Line + 17850 13400 17900 13400 +NoConn ~ 17900 12150 +$Comp +L d_dff U39 +U 1 1 686644FF +P 22050 12700 +F 0 "U39" H 22050 12700 60 0000 C CNN +F 1 "d_dff" H 22050 12850 60 0000 C CNN +F 2 "" H 22050 12700 60 0000 C CNN +F 3 "" H 22050 12700 60 0000 C CNN + 1 22050 12700 + 1 0 0 -1 +$EndComp +Wire Wire Line + 18450 12450 21500 12450 +Wire Wire Line + 21500 12450 21500 12350 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/CD4017B/CD4017B.cir b/library/SubcircuitLibrary/CD4017B/CD4017B.cir new file mode 100644 index 000000000..0ab310773 --- /dev/null +++ b/library/SubcircuitLibrary/CD4017B/CD4017B.cir @@ -0,0 +1,68 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\CD4017B\CD4017B.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 07/03/25 20:36:42 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U13 Net-_U11-Pad1_ Net-_U13-Pad2_ ? Net-_U13-Pad4_ Net-_U13-Pad5_ Net-_U13-Pad6_ d_dff +U30 Net-_U26-Pad3_ Net-_U13-Pad2_ ? Net-_U13-Pad4_ Net-_U25-Pad1_ Net-_U30-Pad6_ d_dff +U47 Net-_U29-Pad1_ Net-_U13-Pad2_ ? Net-_U13-Pad4_ Net-_U33-Pad2_ Net-_U47-Pad6_ d_dff +U3 Net-_U1-Pad13_ Net-_U3-Pad2_ d_buffer +U6 Net-_U3-Pad2_ Net-_U6-Pad2_ d_inverter +U8 Net-_U6-Pad2_ Net-_U12-Pad1_ d_inverter +U12 Net-_U12-Pad1_ Net-_U12-Pad2_ d_buffer +U14 Net-_U1-Pad14_ Net-_U12-Pad2_ Net-_U13-Pad2_ d_nor +U2 Net-_U1-Pad15_ Net-_U2-Pad2_ d_buffer +U4 Net-_U2-Pad2_ Net-_U4-Pad2_ d_inverter +U5 Net-_U4-Pad2_ Net-_U5-Pad2_ d_inverter +U7 Net-_U5-Pad2_ Net-_U13-Pad4_ d_buffer +U11 Net-_U11-Pad1_ Net-_U11-Pad2_ Net-_U10-Pad1_ d_nand +U17 Net-_U13-Pad5_ Net-_U17-Pad2_ Net-_U16-Pad1_ d_nand +U20 Net-_U20-Pad1_ Net-_U20-Pad2_ Net-_U19-Pad1_ d_nand +U25 Net-_U25-Pad1_ Net-_U25-Pad2_ Net-_U24-Pad1_ d_nand +U29 Net-_U29-Pad1_ Net-_U11-Pad1_ Net-_U28-Pad1_ d_nand +U33 Net-_U13-Pad5_ Net-_U33-Pad2_ Net-_U32-Pad1_ d_nand +U36 Net-_U11-Pad2_ Net-_U20-Pad1_ Net-_U35-Pad1_ d_nand +U40 Net-_U17-Pad2_ Net-_U25-Pad1_ Net-_U38-Pad1_ d_nand +U43 Net-_U20-Pad2_ Net-_U29-Pad1_ Net-_U42-Pad1_ d_nand +U46 Net-_U25-Pad2_ Net-_U33-Pad2_ Net-_U45-Pad1_ d_nand +U21 Net-_U20-Pad2_ Net-_U11-Pad2_ Net-_U21-Pad3_ d_and +U26 Net-_U17-Pad2_ Net-_U21-Pad3_ Net-_U26-Pad3_ d_nor +U53 Net-_U33-Pad2_ Net-_U52-Pad1_ d_buffer +U52 Net-_U52-Pad1_ Net-_U51-Pad1_ d_inverter +U51 Net-_U51-Pad1_ Net-_U50-Pad1_ d_inverter +U50 Net-_U50-Pad1_ Net-_U49-Pad1_ d_buffer +U49 Net-_U49-Pad1_ Net-_U48-Pad1_ d_buffer +U48 Net-_U48-Pad1_ Net-_U1-Pad12_ d_inverter +U10 Net-_U10-Pad1_ Net-_U10-Pad2_ d_inverter +U9 Net-_U10-Pad2_ /0 d_buffer +U16 Net-_U16-Pad1_ Net-_U15-Pad1_ d_inverter +U15 Net-_U15-Pad1_ /1 d_buffer +U19 Net-_U19-Pad1_ Net-_U18-Pad1_ d_inverter +U18 Net-_U18-Pad1_ /2 d_buffer +U24 Net-_U24-Pad1_ Net-_U23-Pad1_ d_inverter +U23 Net-_U23-Pad1_ /3 d_buffer +U28 Net-_U28-Pad1_ Net-_U27-Pad1_ d_inverter +U27 Net-_U27-Pad1_ /4 d_buffer +U32 Net-_U32-Pad1_ Net-_U31-Pad1_ d_inverter +U31 Net-_U31-Pad1_ /5 d_buffer +U35 Net-_U35-Pad1_ Net-_U34-Pad1_ d_inverter +U34 Net-_U34-Pad1_ /6 d_buffer +U38 Net-_U38-Pad1_ Net-_U37-Pad1_ d_inverter +U37 Net-_U37-Pad1_ /7 d_buffer +U42 Net-_U42-Pad1_ Net-_U41-Pad1_ d_inverter +U41 Net-_U41-Pad1_ /8 d_buffer +U45 Net-_U45-Pad1_ Net-_U44-Pad1_ d_inverter +U44 Net-_U44-Pad1_ /9 d_buffer +U1 /5 /1 /0 /2 /6 /7 /3 /8 /4 /9 Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ PORT +U22 Net-_U13-Pad5_ Net-_U13-Pad2_ ? Net-_U13-Pad4_ Net-_U20-Pad1_ Net-_U22-Pad6_ d_dff +U56 Net-_U39-Pad6_ Net-_U25-Pad2_ d_buffer +U55 Net-_U30-Pad6_ Net-_U20-Pad2_ d_buffer +U57 Net-_U47-Pad6_ Net-_U11-Pad1_ d_buffer +U58 Net-_U13-Pad6_ Net-_U11-Pad2_ d_buffer +U54 Net-_U22-Pad6_ Net-_U17-Pad2_ d_buffer +U39 Net-_U25-Pad1_ Net-_U13-Pad2_ ? Net-_U13-Pad4_ Net-_U29-Pad1_ Net-_U39-Pad6_ d_dff + +.end diff --git a/library/SubcircuitLibrary/CD4017B/CD4017B.cir.out b/library/SubcircuitLibrary/CD4017B/CD4017B.cir.out new file mode 100644 index 000000000..ff224cae0 --- /dev/null +++ b/library/SubcircuitLibrary/CD4017B/CD4017B.cir.out @@ -0,0 +1,240 @@ +* c:\fossee\esim\library\subcircuitlibrary\cd4017b\cd4017b.cir + +* u13 net-_u11-pad1_ net-_u13-pad2_ ? net-_u13-pad4_ net-_u13-pad5_ net-_u13-pad6_ d_dff +* u30 net-_u26-pad3_ net-_u13-pad2_ ? net-_u13-pad4_ net-_u25-pad1_ net-_u30-pad6_ d_dff +* u47 net-_u29-pad1_ net-_u13-pad2_ ? net-_u13-pad4_ net-_u33-pad2_ net-_u47-pad6_ d_dff +* u3 net-_u1-pad13_ net-_u3-pad2_ d_buffer +* u6 net-_u3-pad2_ net-_u6-pad2_ d_inverter +* u8 net-_u6-pad2_ net-_u12-pad1_ d_inverter +* u12 net-_u12-pad1_ net-_u12-pad2_ d_buffer +* u14 net-_u1-pad14_ net-_u12-pad2_ net-_u13-pad2_ d_nor +* u2 net-_u1-pad15_ net-_u2-pad2_ d_buffer +* u4 net-_u2-pad2_ net-_u4-pad2_ d_inverter +* u5 net-_u4-pad2_ net-_u5-pad2_ d_inverter +* u7 net-_u5-pad2_ net-_u13-pad4_ d_buffer +* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u10-pad1_ d_nand +* u17 net-_u13-pad5_ net-_u17-pad2_ net-_u16-pad1_ d_nand +* u20 net-_u20-pad1_ net-_u20-pad2_ net-_u19-pad1_ d_nand +* u25 net-_u25-pad1_ net-_u25-pad2_ net-_u24-pad1_ d_nand +* u29 net-_u29-pad1_ net-_u11-pad1_ net-_u28-pad1_ d_nand +* u33 net-_u13-pad5_ net-_u33-pad2_ net-_u32-pad1_ d_nand +* u36 net-_u11-pad2_ net-_u20-pad1_ net-_u35-pad1_ d_nand +* u40 net-_u17-pad2_ net-_u25-pad1_ net-_u38-pad1_ d_nand +* u43 net-_u20-pad2_ net-_u29-pad1_ net-_u42-pad1_ d_nand +* u46 net-_u25-pad2_ net-_u33-pad2_ net-_u45-pad1_ d_nand +* u21 net-_u20-pad2_ net-_u11-pad2_ net-_u21-pad3_ d_and +* u26 net-_u17-pad2_ net-_u21-pad3_ net-_u26-pad3_ d_nor +* u53 net-_u33-pad2_ net-_u52-pad1_ d_buffer +* u52 net-_u52-pad1_ net-_u51-pad1_ d_inverter +* u51 net-_u51-pad1_ net-_u50-pad1_ d_inverter +* u50 net-_u50-pad1_ net-_u49-pad1_ d_buffer +* u49 net-_u49-pad1_ net-_u48-pad1_ d_buffer +* u48 net-_u48-pad1_ net-_u1-pad12_ d_inverter +* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter +* u9 net-_u10-pad2_ /0 d_buffer +* u16 net-_u16-pad1_ net-_u15-pad1_ d_inverter +* u15 net-_u15-pad1_ /1 d_buffer +* u19 net-_u19-pad1_ net-_u18-pad1_ d_inverter +* u18 net-_u18-pad1_ /2 d_buffer +* u24 net-_u24-pad1_ net-_u23-pad1_ d_inverter +* u23 net-_u23-pad1_ /3 d_buffer +* u28 net-_u28-pad1_ net-_u27-pad1_ d_inverter +* u27 net-_u27-pad1_ /4 d_buffer +* u32 net-_u32-pad1_ net-_u31-pad1_ d_inverter +* u31 net-_u31-pad1_ /5 d_buffer +* u35 net-_u35-pad1_ net-_u34-pad1_ d_inverter +* u34 net-_u34-pad1_ /6 d_buffer +* u38 net-_u38-pad1_ net-_u37-pad1_ d_inverter +* u37 net-_u37-pad1_ /7 d_buffer +* u42 net-_u42-pad1_ net-_u41-pad1_ d_inverter +* u41 net-_u41-pad1_ /8 d_buffer +* u45 net-_u45-pad1_ net-_u44-pad1_ d_inverter +* u44 net-_u44-pad1_ /9 d_buffer +* u1 /5 /1 /0 /2 /6 /7 /3 /8 /4 /9 net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ port +* u22 net-_u13-pad5_ net-_u13-pad2_ ? net-_u13-pad4_ net-_u20-pad1_ net-_u22-pad6_ d_dff +* u56 net-_u39-pad6_ net-_u25-pad2_ d_buffer +* u55 net-_u30-pad6_ net-_u20-pad2_ d_buffer +* u57 net-_u47-pad6_ net-_u11-pad1_ d_buffer +* u58 net-_u13-pad6_ net-_u11-pad2_ d_buffer +* u54 net-_u22-pad6_ net-_u17-pad2_ d_buffer +* u39 net-_u25-pad1_ net-_u13-pad2_ ? net-_u13-pad4_ net-_u29-pad1_ net-_u39-pad6_ d_dff +a1 net-_u11-pad1_ net-_u13-pad2_ ? net-_u13-pad4_ net-_u13-pad5_ net-_u13-pad6_ u13 +a2 net-_u26-pad3_ net-_u13-pad2_ ? net-_u13-pad4_ net-_u25-pad1_ net-_u30-pad6_ u30 +a3 net-_u29-pad1_ net-_u13-pad2_ ? net-_u13-pad4_ net-_u33-pad2_ net-_u47-pad6_ u47 +a4 net-_u1-pad13_ net-_u3-pad2_ u3 +a5 net-_u3-pad2_ net-_u6-pad2_ u6 +a6 net-_u6-pad2_ net-_u12-pad1_ u8 +a7 net-_u12-pad1_ net-_u12-pad2_ u12 +a8 [net-_u1-pad14_ net-_u12-pad2_ ] net-_u13-pad2_ u14 +a9 net-_u1-pad15_ net-_u2-pad2_ u2 +a10 net-_u2-pad2_ net-_u4-pad2_ u4 +a11 net-_u4-pad2_ net-_u5-pad2_ u5 +a12 net-_u5-pad2_ net-_u13-pad4_ u7 +a13 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u10-pad1_ u11 +a14 [net-_u13-pad5_ net-_u17-pad2_ ] net-_u16-pad1_ u17 +a15 [net-_u20-pad1_ net-_u20-pad2_ ] net-_u19-pad1_ u20 +a16 [net-_u25-pad1_ net-_u25-pad2_ ] net-_u24-pad1_ u25 +a17 [net-_u29-pad1_ net-_u11-pad1_ ] net-_u28-pad1_ u29 +a18 [net-_u13-pad5_ net-_u33-pad2_ ] net-_u32-pad1_ u33 +a19 [net-_u11-pad2_ net-_u20-pad1_ ] net-_u35-pad1_ u36 +a20 [net-_u17-pad2_ net-_u25-pad1_ ] net-_u38-pad1_ u40 +a21 [net-_u20-pad2_ net-_u29-pad1_ ] net-_u42-pad1_ u43 +a22 [net-_u25-pad2_ net-_u33-pad2_ ] net-_u45-pad1_ u46 +a23 [net-_u20-pad2_ net-_u11-pad2_ ] net-_u21-pad3_ u21 +a24 [net-_u17-pad2_ net-_u21-pad3_ ] net-_u26-pad3_ u26 +a25 net-_u33-pad2_ net-_u52-pad1_ u53 +a26 net-_u52-pad1_ net-_u51-pad1_ u52 +a27 net-_u51-pad1_ net-_u50-pad1_ u51 +a28 net-_u50-pad1_ net-_u49-pad1_ u50 +a29 net-_u49-pad1_ net-_u48-pad1_ u49 +a30 net-_u48-pad1_ net-_u1-pad12_ u48 +a31 net-_u10-pad1_ net-_u10-pad2_ u10 +a32 net-_u10-pad2_ /0 u9 +a33 net-_u16-pad1_ net-_u15-pad1_ u16 +a34 net-_u15-pad1_ /1 u15 +a35 net-_u19-pad1_ net-_u18-pad1_ u19 +a36 net-_u18-pad1_ /2 u18 +a37 net-_u24-pad1_ net-_u23-pad1_ u24 +a38 net-_u23-pad1_ /3 u23 +a39 net-_u28-pad1_ net-_u27-pad1_ u28 +a40 net-_u27-pad1_ /4 u27 +a41 net-_u32-pad1_ net-_u31-pad1_ u32 +a42 net-_u31-pad1_ /5 u31 +a43 net-_u35-pad1_ net-_u34-pad1_ u35 +a44 net-_u34-pad1_ /6 u34 +a45 net-_u38-pad1_ net-_u37-pad1_ u38 +a46 net-_u37-pad1_ /7 u37 +a47 net-_u42-pad1_ net-_u41-pad1_ u42 +a48 net-_u41-pad1_ /8 u41 +a49 net-_u45-pad1_ net-_u44-pad1_ u45 +a50 net-_u44-pad1_ /9 u44 +a51 net-_u13-pad5_ net-_u13-pad2_ ? net-_u13-pad4_ net-_u20-pad1_ net-_u22-pad6_ u22 +a52 net-_u39-pad6_ net-_u25-pad2_ u56 +a53 net-_u30-pad6_ net-_u20-pad2_ u55 +a54 net-_u47-pad6_ net-_u11-pad1_ u57 +a55 net-_u13-pad6_ net-_u11-pad2_ u58 +a56 net-_u22-pad6_ net-_u17-pad2_ u54 +a57 net-_u25-pad1_ net-_u13-pad2_ ? net-_u13-pad4_ net-_u29-pad1_ net-_u39-pad6_ u39 +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u13 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u30 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u47 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u3 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u12 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u14 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u2 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u7 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u11 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u17 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u20 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u25 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u29 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u33 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u36 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u40 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u43 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u46 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u21 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u26 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u53 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u52 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u51 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u50 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u49 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u48 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u9 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u15 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u18 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u24 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u23 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u28 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u27 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u32 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u31 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u35 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u34 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u38 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u37 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u42 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u41 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u45 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u44 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u22 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u56 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u55 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u57 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u58 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u54 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u39 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/CD4017B/CD4017B.pro b/library/SubcircuitLibrary/CD4017B/CD4017B.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/CD4017B/CD4017B.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/CD4017B/CD4017B.sch b/library/SubcircuitLibrary/CD4017B/CD4017B.sch new file mode 100644 index 000000000..5b9828289 --- /dev/null +++ b/library/SubcircuitLibrary/CD4017B/CD4017B.sch @@ -0,0 +1,1203 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:CD4017B-cache +EELAYER 25 0 +EELAYER END +$Descr A0 46811 33110 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_dff U13 +U 1 1 68664336 +P 18600 19250 +F 0 "U13" H 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b/library/SubcircuitLibrary/CD4017B/CD4017B.sub @@ -0,0 +1,234 @@ +* Subcircuit CD4017B +.subckt CD4017B /5 /1 /0 /2 /6 /7 /3 /8 /4 /9 net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ +* c:\fossee\esim\library\subcircuitlibrary\cd4017b\cd4017b.cir +* u13 net-_u11-pad1_ net-_u13-pad2_ ? net-_u13-pad4_ net-_u13-pad5_ net-_u13-pad6_ d_dff +* u30 net-_u26-pad3_ net-_u13-pad2_ ? net-_u13-pad4_ net-_u25-pad1_ net-_u30-pad6_ d_dff +* u47 net-_u29-pad1_ net-_u13-pad2_ ? net-_u13-pad4_ net-_u33-pad2_ net-_u47-pad6_ d_dff +* u3 net-_u1-pad13_ net-_u3-pad2_ d_buffer +* u6 net-_u3-pad2_ net-_u6-pad2_ d_inverter +* u8 net-_u6-pad2_ net-_u12-pad1_ d_inverter +* u12 net-_u12-pad1_ net-_u12-pad2_ d_buffer +* u14 net-_u1-pad14_ net-_u12-pad2_ net-_u13-pad2_ d_nor +* u2 net-_u1-pad15_ net-_u2-pad2_ d_buffer +* u4 net-_u2-pad2_ net-_u4-pad2_ d_inverter +* u5 net-_u4-pad2_ net-_u5-pad2_ d_inverter +* u7 net-_u5-pad2_ net-_u13-pad4_ d_buffer +* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u10-pad1_ d_nand +* u17 net-_u13-pad5_ net-_u17-pad2_ net-_u16-pad1_ d_nand +* u20 net-_u20-pad1_ net-_u20-pad2_ net-_u19-pad1_ d_nand +* u25 net-_u25-pad1_ net-_u25-pad2_ net-_u24-pad1_ d_nand +* u29 net-_u29-pad1_ net-_u11-pad1_ net-_u28-pad1_ d_nand +* u33 net-_u13-pad5_ net-_u33-pad2_ net-_u32-pad1_ d_nand +* u36 net-_u11-pad2_ net-_u20-pad1_ net-_u35-pad1_ d_nand +* u40 net-_u17-pad2_ net-_u25-pad1_ net-_u38-pad1_ d_nand +* u43 net-_u20-pad2_ net-_u29-pad1_ net-_u42-pad1_ d_nand +* u46 net-_u25-pad2_ net-_u33-pad2_ net-_u45-pad1_ d_nand +* u21 net-_u20-pad2_ net-_u11-pad2_ net-_u21-pad3_ d_and +* u26 net-_u17-pad2_ net-_u21-pad3_ net-_u26-pad3_ d_nor +* u53 net-_u33-pad2_ net-_u52-pad1_ d_buffer +* u52 net-_u52-pad1_ net-_u51-pad1_ d_inverter +* u51 net-_u51-pad1_ net-_u50-pad1_ d_inverter +* u50 net-_u50-pad1_ net-_u49-pad1_ d_buffer +* u49 net-_u49-pad1_ net-_u48-pad1_ d_buffer +* u48 net-_u48-pad1_ net-_u1-pad12_ d_inverter +* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter +* u9 net-_u10-pad2_ /0 d_buffer +* u16 net-_u16-pad1_ net-_u15-pad1_ d_inverter +* u15 net-_u15-pad1_ /1 d_buffer +* u19 net-_u19-pad1_ net-_u18-pad1_ d_inverter +* u18 net-_u18-pad1_ /2 d_buffer +* u24 net-_u24-pad1_ net-_u23-pad1_ d_inverter +* u23 net-_u23-pad1_ /3 d_buffer +* u28 net-_u28-pad1_ net-_u27-pad1_ d_inverter +* u27 net-_u27-pad1_ /4 d_buffer +* u32 net-_u32-pad1_ net-_u31-pad1_ d_inverter +* u31 net-_u31-pad1_ /5 d_buffer +* u35 net-_u35-pad1_ net-_u34-pad1_ d_inverter +* u34 net-_u34-pad1_ /6 d_buffer +* u38 net-_u38-pad1_ net-_u37-pad1_ d_inverter +* u37 net-_u37-pad1_ /7 d_buffer +* u42 net-_u42-pad1_ net-_u41-pad1_ d_inverter +* u41 net-_u41-pad1_ /8 d_buffer +* u45 net-_u45-pad1_ net-_u44-pad1_ d_inverter +* u44 net-_u44-pad1_ /9 d_buffer +* u22 net-_u13-pad5_ net-_u13-pad2_ ? net-_u13-pad4_ net-_u20-pad1_ net-_u22-pad6_ d_dff +* u56 net-_u39-pad6_ net-_u25-pad2_ d_buffer +* u55 net-_u30-pad6_ net-_u20-pad2_ d_buffer +* u57 net-_u47-pad6_ net-_u11-pad1_ d_buffer +* u58 net-_u13-pad6_ net-_u11-pad2_ d_buffer +* u54 net-_u22-pad6_ net-_u17-pad2_ d_buffer +* u39 net-_u25-pad1_ net-_u13-pad2_ ? net-_u13-pad4_ net-_u29-pad1_ net-_u39-pad6_ d_dff +a1 net-_u11-pad1_ net-_u13-pad2_ ? net-_u13-pad4_ net-_u13-pad5_ net-_u13-pad6_ u13 +a2 net-_u26-pad3_ net-_u13-pad2_ ? net-_u13-pad4_ net-_u25-pad1_ net-_u30-pad6_ u30 +a3 net-_u29-pad1_ net-_u13-pad2_ ? net-_u13-pad4_ net-_u33-pad2_ net-_u47-pad6_ u47 +a4 net-_u1-pad13_ net-_u3-pad2_ u3 +a5 net-_u3-pad2_ net-_u6-pad2_ u6 +a6 net-_u6-pad2_ net-_u12-pad1_ u8 +a7 net-_u12-pad1_ net-_u12-pad2_ u12 +a8 [net-_u1-pad14_ net-_u12-pad2_ ] net-_u13-pad2_ u14 +a9 net-_u1-pad15_ net-_u2-pad2_ u2 +a10 net-_u2-pad2_ net-_u4-pad2_ u4 +a11 net-_u4-pad2_ net-_u5-pad2_ u5 +a12 net-_u5-pad2_ net-_u13-pad4_ u7 +a13 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u10-pad1_ u11 +a14 [net-_u13-pad5_ net-_u17-pad2_ ] net-_u16-pad1_ u17 +a15 [net-_u20-pad1_ net-_u20-pad2_ ] net-_u19-pad1_ u20 +a16 [net-_u25-pad1_ net-_u25-pad2_ ] net-_u24-pad1_ u25 +a17 [net-_u29-pad1_ net-_u11-pad1_ ] net-_u28-pad1_ u29 +a18 [net-_u13-pad5_ net-_u33-pad2_ ] net-_u32-pad1_ u33 +a19 [net-_u11-pad2_ net-_u20-pad1_ ] net-_u35-pad1_ u36 +a20 [net-_u17-pad2_ net-_u25-pad1_ ] net-_u38-pad1_ u40 +a21 [net-_u20-pad2_ net-_u29-pad1_ ] net-_u42-pad1_ u43 +a22 [net-_u25-pad2_ net-_u33-pad2_ ] net-_u45-pad1_ u46 +a23 [net-_u20-pad2_ net-_u11-pad2_ ] net-_u21-pad3_ u21 +a24 [net-_u17-pad2_ net-_u21-pad3_ ] net-_u26-pad3_ u26 +a25 net-_u33-pad2_ net-_u52-pad1_ u53 +a26 net-_u52-pad1_ net-_u51-pad1_ u52 +a27 net-_u51-pad1_ net-_u50-pad1_ u51 +a28 net-_u50-pad1_ net-_u49-pad1_ u50 +a29 net-_u49-pad1_ net-_u48-pad1_ u49 +a30 net-_u48-pad1_ net-_u1-pad12_ u48 +a31 net-_u10-pad1_ net-_u10-pad2_ u10 +a32 net-_u10-pad2_ /0 u9 +a33 net-_u16-pad1_ net-_u15-pad1_ u16 +a34 net-_u15-pad1_ /1 u15 +a35 net-_u19-pad1_ net-_u18-pad1_ u19 +a36 net-_u18-pad1_ /2 u18 +a37 net-_u24-pad1_ net-_u23-pad1_ u24 +a38 net-_u23-pad1_ /3 u23 +a39 net-_u28-pad1_ net-_u27-pad1_ u28 +a40 net-_u27-pad1_ /4 u27 +a41 net-_u32-pad1_ net-_u31-pad1_ u32 +a42 net-_u31-pad1_ /5 u31 +a43 net-_u35-pad1_ net-_u34-pad1_ u35 +a44 net-_u34-pad1_ /6 u34 +a45 net-_u38-pad1_ net-_u37-pad1_ u38 +a46 net-_u37-pad1_ /7 u37 +a47 net-_u42-pad1_ net-_u41-pad1_ u42 +a48 net-_u41-pad1_ /8 u41 +a49 net-_u45-pad1_ net-_u44-pad1_ u45 +a50 net-_u44-pad1_ /9 u44 +a51 net-_u13-pad5_ net-_u13-pad2_ ? net-_u13-pad4_ net-_u20-pad1_ net-_u22-pad6_ u22 +a52 net-_u39-pad6_ net-_u25-pad2_ u56 +a53 net-_u30-pad6_ net-_u20-pad2_ u55 +a54 net-_u47-pad6_ net-_u11-pad1_ u57 +a55 net-_u13-pad6_ net-_u11-pad2_ u58 +a56 net-_u22-pad6_ net-_u17-pad2_ u54 +a57 net-_u25-pad1_ net-_u13-pad2_ ? net-_u13-pad4_ net-_u29-pad1_ net-_u39-pad6_ u39 +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u13 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u30 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u47 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u3 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u12 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u14 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u2 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u7 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u11 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u17 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u20 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u25 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u29 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u33 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u36 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u40 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u43 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u46 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u21 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u26 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u53 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u52 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u51 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u50 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u49 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u48 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u9 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u15 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u18 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u24 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u23 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u28 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u27 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u32 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u31 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u35 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u34 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u38 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u37 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u42 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u41 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u45 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u44 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u22 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u56 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u55 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u57 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u58 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u54 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u39 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Control Statements + +.ends CD4017B \ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4017B/CD4017B_Previous_Values.xml b/library/SubcircuitLibrary/CD4017B/CD4017B_Previous_Values.xml new file mode 100644 index 000000000..3d9e27235 --- /dev/null +++ b/library/SubcircuitLibrary/CD4017B/CD4017B_Previous_Values.xml @@ -0,0 +1 @@ +d_dffd_dffd_dffd_dffd_dffd_bufferd_inverterd_inverterd_bufferd_nord_bufferd_inverterd_inverterd_bufferd_nandd_nandd_nandd_nandd_nandd_nandd_nandd_nandd_nandd_nandd_andd_nord_bufferd_inverterd_inverterd_bufferd_bufferd_inverterd_inverterd_bufferd_inverterd_bufferd_inverterd_bufferd_inverterd_bufferd_inverterd_bufferd_inverterd_bufferd_inverterd_bufferd_inverterd_bufferd_inverterd_bufferd_inverterd_bufferd_bufferd_bufferd_bufferd_bufferd_bufferd_bufferd_inverterd_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec \ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4017B/analysis b/library/SubcircuitLibrary/CD4017B/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/SubcircuitLibrary/CD4017B/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4030B/CD4030B-cache.lib b/library/SubcircuitLibrary/CD4030B/CD4030B-cache.lib new file mode 100644 index 000000000..348446c2e --- /dev/null +++ b/library/SubcircuitLibrary/CD4030B/CD4030B-cache.lib @@ -0,0 +1,100 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_MOS_N +# +DEF eSim_MOS_N M 0 0 Y N 1 F N +F0 "M" 0 -150 50 H V R CNN +F1 "eSim_MOS_N" 100 -50 50 H V R CNN +F2 "" 300 -300 29 H V C CNN +F3 "" 100 -200 60 H V C CNN +ALIAS mosfet_n +DRAW +C 150 -200 111 0 1 10 N +P 2 0 1 10 130 -290 130 -250 N +P 2 0 1 0 130 -270 200 -270 N +P 2 0 1 10 130 -220 130 -180 N +P 2 0 1 0 130 -200 200 -200 N +P 2 0 1 10 130 -150 130 -110 N +P 2 0 1 0 130 -130 200 -130 N +P 2 0 1 0 200 -300 200 -270 N +P 2 0 1 0 200 -130 200 -100 N +P 3 0 1 10 110 -275 110 -125 110 -125 N +P 3 0 1 0 200 -200 300 -200 300 -250 N +P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F +X D 1 200 0 100 D 50 50 1 1 P +X G 2 -100 -200 210 R 50 50 1 1 P +X S 3 200 -400 100 U 50 50 1 1 P +X B 4 300 -350 98 U 47 47 1 1 P +ENDDRAW +ENDDEF +# +# eSim_MOS_P +# +DEF eSim_MOS_P M 0 0 Y N 1 F N +F0 "M" -50 50 50 H V R CNN +F1 "eSim_MOS_P" 50 150 50 H V R CNN +F2 "" 250 100 29 H V C CNN +F3 "" 50 0 60 H V C CNN +ALIAS mosfet_p +DRAW +C 100 0 111 0 1 10 N +P 2 0 1 0 80 -70 150 -70 N +P 2 0 1 10 80 -50 80 -90 N +P 2 0 1 0 80 0 150 0 N +P 2 0 1 10 80 20 80 -20 N +P 2 0 1 0 80 70 150 70 N +P 2 0 1 10 80 90 80 50 N +P 2 0 1 0 150 -70 150 -100 N +P 2 0 1 0 150 100 150 70 N +P 3 0 1 10 60 75 60 -75 60 -75 N +P 3 0 1 0 150 0 250 0 250 -50 N +P 4 0 1 0 140 0 100 -15 100 15 140 0 F +X D 1 150 200 100 D 50 50 1 1 P +X G 2 -150 0 210 R 50 50 1 1 P +X S 3 150 -200 100 U 50 50 1 1 P +X B 4 250 -150 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/CD4030B/CD4030B.bak b/library/SubcircuitLibrary/CD4030B/CD4030B.bak new file mode 100644 index 000000000..3b3857f06 --- /dev/null +++ b/library/SubcircuitLibrary/CD4030B/CD4030B.bak @@ -0,0 +1,56 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/CD4030B/CD4030B.cir b/library/SubcircuitLibrary/CD4030B/CD4030B.cir new file mode 100644 index 000000000..0199aa42b --- /dev/null +++ b/library/SubcircuitLibrary/CD4030B/CD4030B.cir @@ -0,0 +1,55 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\CD4030B\CD4030B.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 07/04/25 22:40:03 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +M3 Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M11-Pad4_ Net-_M11-Pad4_ eSim_MOS_P +M1 Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +M4 Net-_M13-Pad3_ Net-_M11-Pad2_ Net-_M11-Pad4_ Net-_M11-Pad4_ eSim_MOS_P +M2 Net-_M13-Pad3_ Net-_M11-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +M9 Net-_M1-Pad1_ Net-_M13-Pad3_ Net-_M11-Pad1_ Net-_M1-Pad3_ eSim_MOS_N +M11 Net-_M11-Pad1_ Net-_M11-Pad2_ Net-_M1-Pad1_ Net-_M11-Pad4_ eSim_MOS_P +M14 Net-_M14-Pad1_ Net-_M13-Pad3_ Net-_M11-Pad4_ Net-_M11-Pad4_ eSim_MOS_P +M15 Net-_M11-Pad1_ Net-_M1-Pad1_ Net-_M14-Pad1_ Net-_M11-Pad4_ eSim_MOS_P +M13 Net-_M11-Pad1_ Net-_M1-Pad1_ Net-_M13-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +M20 Net-_M19-Pad1_ Net-_M11-Pad1_ Net-_M11-Pad4_ Net-_M11-Pad4_ eSim_MOS_P +M19 Net-_M19-Pad1_ Net-_M11-Pad1_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +U1 Net-_M1-Pad2_ Net-_M11-Pad2_ Net-_M19-Pad1_ Net-_M41-Pad1_ Net-_M23-Pad2_ Net-_M24-Pad2_ Net-_M1-Pad3_ Net-_M5-Pad2_ Net-_M12-Pad2_ Net-_M21-Pad1_ Net-_M43-Pad1_ Net-_M27-Pad2_ Net-_M28-Pad2_ Net-_M11-Pad4_ PORT +M25 Net-_M23-Pad1_ Net-_M23-Pad2_ Net-_M11-Pad4_ Net-_M11-Pad4_ eSim_MOS_P +M23 Net-_M23-Pad1_ Net-_M23-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +M26 Net-_M24-Pad1_ Net-_M24-Pad2_ Net-_M11-Pad4_ Net-_M11-Pad4_ eSim_MOS_P +M24 Net-_M24-Pad1_ Net-_M24-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +M31 Net-_M23-Pad1_ Net-_M24-Pad1_ Net-_M31-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +M33 Net-_M31-Pad3_ Net-_M24-Pad2_ Net-_M23-Pad1_ Net-_M11-Pad4_ eSim_MOS_P +M36 Net-_M36-Pad1_ Net-_M24-Pad1_ Net-_M11-Pad4_ Net-_M11-Pad4_ eSim_MOS_P +M37 Net-_M31-Pad3_ Net-_M23-Pad1_ Net-_M36-Pad1_ Net-_M11-Pad4_ eSim_MOS_P +M35 Net-_M31-Pad3_ Net-_M23-Pad1_ Net-_M24-Pad1_ Net-_M1-Pad3_ eSim_MOS_N +M42 Net-_M41-Pad1_ Net-_M31-Pad3_ Net-_M11-Pad4_ Net-_M11-Pad4_ eSim_MOS_P +M41 Net-_M41-Pad1_ Net-_M31-Pad3_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +M7 Net-_M10-Pad1_ Net-_M5-Pad2_ Net-_M11-Pad4_ Net-_M11-Pad4_ eSim_MOS_P +M5 Net-_M10-Pad1_ Net-_M5-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +M8 Net-_M10-Pad2_ Net-_M12-Pad2_ Net-_M11-Pad4_ Net-_M11-Pad4_ eSim_MOS_P +M6 Net-_M10-Pad2_ Net-_M12-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +M10 Net-_M10-Pad1_ Net-_M10-Pad2_ Net-_M10-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +M12 Net-_M10-Pad3_ Net-_M12-Pad2_ Net-_M10-Pad1_ Net-_M11-Pad4_ eSim_MOS_P +M17 Net-_M17-Pad1_ Net-_M10-Pad2_ Net-_M11-Pad4_ Net-_M11-Pad4_ eSim_MOS_P +M18 Net-_M10-Pad3_ Net-_M10-Pad1_ Net-_M17-Pad1_ Net-_M11-Pad4_ eSim_MOS_P +M16 Net-_M10-Pad3_ Net-_M10-Pad1_ Net-_M10-Pad2_ Net-_M1-Pad3_ eSim_MOS_N +M22 Net-_M21-Pad1_ Net-_M10-Pad3_ Net-_M11-Pad4_ Net-_M11-Pad4_ eSim_MOS_P +M21 Net-_M21-Pad1_ Net-_M10-Pad3_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +M29 Net-_M27-Pad1_ Net-_M27-Pad2_ Net-_M11-Pad4_ Net-_M11-Pad4_ eSim_MOS_P +M27 Net-_M27-Pad1_ Net-_M27-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +M30 Net-_M28-Pad1_ Net-_M28-Pad2_ Net-_M11-Pad4_ Net-_M11-Pad4_ eSim_MOS_P +M28 Net-_M28-Pad1_ Net-_M28-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +M32 Net-_M27-Pad1_ Net-_M28-Pad1_ Net-_M32-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +M34 Net-_M32-Pad3_ Net-_M28-Pad2_ Net-_M27-Pad1_ Net-_M11-Pad4_ eSim_MOS_P +M39 Net-_M39-Pad1_ Net-_M28-Pad1_ Net-_M11-Pad4_ Net-_M11-Pad4_ eSim_MOS_P +M40 Net-_M32-Pad3_ Net-_M27-Pad1_ Net-_M39-Pad1_ Net-_M11-Pad4_ eSim_MOS_P +M38 Net-_M32-Pad3_ Net-_M27-Pad1_ Net-_M28-Pad1_ Net-_M1-Pad3_ eSim_MOS_N +M44 Net-_M43-Pad1_ Net-_M32-Pad3_ Net-_M11-Pad4_ Net-_M11-Pad4_ eSim_MOS_P +M43 Net-_M43-Pad1_ Net-_M32-Pad3_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N + +.end diff --git a/library/SubcircuitLibrary/CD4030B/CD4030B.cir.out b/library/SubcircuitLibrary/CD4030B/CD4030B.cir.out new file mode 100644 index 000000000..137822064 --- /dev/null +++ b/library/SubcircuitLibrary/CD4030B/CD4030B.cir.out @@ -0,0 +1,58 @@ +* c:\fossee\esim\library\subcircuitlibrary\cd4030b\cd4030b.cir + +.include PMOS-5um.lib +.include NMOS-5um.lib +m3 net-_m1-pad1_ net-_m1-pad2_ net-_m11-pad4_ net-_m11-pad4_ mos_p W=100u L=100u M=1 +m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad3_ mos_n W=100u L=100u M=1 +m4 net-_m13-pad3_ net-_m11-pad2_ net-_m11-pad4_ net-_m11-pad4_ mos_p W=100u L=100u M=1 +m2 net-_m13-pad3_ net-_m11-pad2_ net-_m1-pad3_ net-_m1-pad3_ mos_n W=100u L=100u M=1 +m9 net-_m1-pad1_ net-_m13-pad3_ net-_m11-pad1_ net-_m1-pad3_ mos_n W=100u L=100u M=1 +m11 net-_m11-pad1_ net-_m11-pad2_ net-_m1-pad1_ net-_m11-pad4_ mos_p W=100u L=100u M=1 +m14 net-_m14-pad1_ net-_m13-pad3_ net-_m11-pad4_ net-_m11-pad4_ mos_p W=100u L=100u M=1 +m15 net-_m11-pad1_ net-_m1-pad1_ net-_m14-pad1_ net-_m11-pad4_ mos_p W=100u L=100u M=1 +m13 net-_m11-pad1_ net-_m1-pad1_ net-_m13-pad3_ net-_m1-pad3_ mos_n W=100u L=100u M=1 +m20 net-_m19-pad1_ net-_m11-pad1_ net-_m11-pad4_ net-_m11-pad4_ mos_p W=100u L=100u M=1 +m19 net-_m19-pad1_ net-_m11-pad1_ net-_m1-pad3_ net-_m1-pad3_ mos_n W=100u L=100u M=1 +* u1 net-_m1-pad2_ net-_m11-pad2_ net-_m19-pad1_ net-_m41-pad1_ net-_m23-pad2_ net-_m24-pad2_ net-_m1-pad3_ net-_m5-pad2_ net-_m12-pad2_ net-_m21-pad1_ net-_m43-pad1_ net-_m27-pad2_ net-_m28-pad2_ net-_m11-pad4_ port +m25 net-_m23-pad1_ net-_m23-pad2_ net-_m11-pad4_ net-_m11-pad4_ mos_p W=100u L=100u M=1 +m23 net-_m23-pad1_ net-_m23-pad2_ net-_m1-pad3_ net-_m1-pad3_ mos_n W=100u L=100u M=1 +m26 net-_m24-pad1_ net-_m24-pad2_ net-_m11-pad4_ net-_m11-pad4_ mos_p W=100u L=100u M=1 +m24 net-_m24-pad1_ net-_m24-pad2_ net-_m1-pad3_ net-_m1-pad3_ mos_n W=100u L=100u M=1 +m31 net-_m23-pad1_ net-_m24-pad1_ net-_m31-pad3_ net-_m1-pad3_ mos_n W=100u L=100u M=1 +m33 net-_m31-pad3_ net-_m24-pad2_ net-_m23-pad1_ net-_m11-pad4_ mos_p W=100u L=100u M=1 +m36 net-_m36-pad1_ net-_m24-pad1_ net-_m11-pad4_ net-_m11-pad4_ mos_p W=100u L=100u M=1 +m37 net-_m31-pad3_ net-_m23-pad1_ net-_m36-pad1_ net-_m11-pad4_ mos_p W=100u L=100u M=1 +m35 net-_m31-pad3_ net-_m23-pad1_ net-_m24-pad1_ net-_m1-pad3_ mos_n W=100u L=100u M=1 +m42 net-_m41-pad1_ net-_m31-pad3_ net-_m11-pad4_ net-_m11-pad4_ mos_p W=100u L=100u M=1 +m41 net-_m41-pad1_ net-_m31-pad3_ net-_m1-pad3_ net-_m1-pad3_ mos_n W=100u L=100u M=1 +m7 net-_m10-pad1_ net-_m5-pad2_ net-_m11-pad4_ net-_m11-pad4_ mos_p W=100u L=100u M=1 +m5 net-_m10-pad1_ net-_m5-pad2_ net-_m1-pad3_ net-_m1-pad3_ mos_n W=100u L=100u M=1 +m8 net-_m10-pad2_ net-_m12-pad2_ net-_m11-pad4_ net-_m11-pad4_ mos_p W=100u L=100u M=1 +m6 net-_m10-pad2_ net-_m12-pad2_ net-_m1-pad3_ net-_m1-pad3_ mos_n W=100u L=100u M=1 +m10 net-_m10-pad1_ net-_m10-pad2_ net-_m10-pad3_ net-_m1-pad3_ mos_n W=100u L=100u M=1 +m12 net-_m10-pad3_ net-_m12-pad2_ net-_m10-pad1_ net-_m11-pad4_ mos_p W=100u L=100u M=1 +m17 net-_m17-pad1_ net-_m10-pad2_ net-_m11-pad4_ net-_m11-pad4_ mos_p W=100u L=100u M=1 +m18 net-_m10-pad3_ net-_m10-pad1_ net-_m17-pad1_ net-_m11-pad4_ mos_p W=100u L=100u M=1 +m16 net-_m10-pad3_ net-_m10-pad1_ net-_m10-pad2_ net-_m1-pad3_ mos_n W=100u L=100u M=1 +m22 net-_m21-pad1_ net-_m10-pad3_ net-_m11-pad4_ net-_m11-pad4_ mos_p W=100u L=100u M=1 +m21 net-_m21-pad1_ net-_m10-pad3_ net-_m1-pad3_ net-_m1-pad3_ mos_n W=100u L=100u M=1 +m29 net-_m27-pad1_ net-_m27-pad2_ net-_m11-pad4_ net-_m11-pad4_ mos_p W=100u L=100u M=1 +m27 net-_m27-pad1_ net-_m27-pad2_ net-_m1-pad3_ net-_m1-pad3_ mos_n W=100u L=100u M=1 +m30 net-_m28-pad1_ net-_m28-pad2_ net-_m11-pad4_ net-_m11-pad4_ mos_p W=100u L=100u M=1 +m28 net-_m28-pad1_ net-_m28-pad2_ net-_m1-pad3_ net-_m1-pad3_ mos_n W=100u L=100u M=1 +m32 net-_m27-pad1_ net-_m28-pad1_ net-_m32-pad3_ net-_m1-pad3_ mos_n W=100u L=100u M=1 +m34 net-_m32-pad3_ net-_m28-pad2_ net-_m27-pad1_ net-_m11-pad4_ mos_p W=100u L=100u M=1 +m39 net-_m39-pad1_ net-_m28-pad1_ net-_m11-pad4_ net-_m11-pad4_ mos_p W=100u L=100u M=1 +m40 net-_m32-pad3_ net-_m27-pad1_ net-_m39-pad1_ net-_m11-pad4_ mos_p W=100u L=100u M=1 +m38 net-_m32-pad3_ net-_m27-pad1_ net-_m28-pad1_ net-_m1-pad3_ mos_n W=100u L=100u M=1 +m44 net-_m43-pad1_ net-_m32-pad3_ net-_m11-pad4_ net-_m11-pad4_ mos_p W=100u L=100u M=1 +m43 net-_m43-pad1_ net-_m32-pad3_ net-_m1-pad3_ net-_m1-pad3_ mos_n W=100u L=100u M=1 +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/CD4030B/CD4030B.pro b/library/SubcircuitLibrary/CD4030B/CD4030B.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/CD4030B/CD4030B.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/CD4030B/CD4030B.sch b/library/SubcircuitLibrary/CD4030B/CD4030B.sch new file mode 100644 index 000000000..d5b5ac21f --- /dev/null +++ b/library/SubcircuitLibrary/CD4030B/CD4030B.sch @@ -0,0 +1,1437 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:EXOR_S-cache +EELAYER 25 0 +EELAYER END +$Descr A1 33110 23386 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_MOS_P M3 +U 1 1 6868098D +P 5150 3150 +F 0 "M3" H 5100 3200 50 0000 R CNN +F 1 "eSim_MOS_P" H 5200 3300 50 0000 R CNN +F 2 "" H 5400 3250 29 0000 C CNN +F 3 "" H 5200 3150 60 0000 C CNN + 1 5150 3150 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M1 +U 1 1 6868098E +P 5100 3850 +F 0 "M1" H 5100 3700 50 0000 R CNN +F 1 "eSim_MOS_N" H 5200 3800 50 0000 R CNN +F 2 "" H 5400 3550 29 0000 C CNN +F 3 "" H 5200 3650 60 0000 C CNN + 1 5100 3850 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M4 +U 1 1 6868098F +P 5150 5200 +F 0 "M4" H 5100 5250 50 0000 R CNN +F 1 "eSim_MOS_P" H 5200 5350 50 0000 R CNN +F 2 "" H 5400 5300 29 0000 C CNN +F 3 "" H 5200 5200 60 0000 C CNN + 1 5150 5200 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M2 +U 1 1 68680990 +P 5100 5900 +F 0 "M2" H 5100 5750 50 0000 R CNN +F 1 "eSim_MOS_N" H 5200 5850 50 0000 R CNN +F 2 "" H 5400 5600 29 0000 C CNN +F 3 "" H 5200 5700 60 0000 C CNN + 1 5100 5900 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_N M9 +U 1 1 68680991 +P 7350 4400 +F 0 "M9" H 7350 4250 50 0000 R CNN +F 1 "eSim_MOS_N" H 7450 4350 50 0000 R CNN +F 2 "" H 7650 4100 29 0000 C CNN +F 3 "" H 7450 4200 60 0000 C CNN + 1 7350 4400 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M11 +U 1 1 68680992 +P 8500 4600 +F 0 "M11" H 8450 4650 50 0000 R CNN +F 1 "eSim_MOS_P" H 8550 4750 50 0000 R CNN +F 2 "" H 8750 4700 29 0000 C CNN +F 3 "" H 8550 4600 60 0000 C CNN + 1 8500 4600 + -1 0 0 1 +$EndComp +$Comp +L eSim_MOS_P M14 +U 1 1 68680993 +P 10600 3000 +F 0 "M14" H 10550 3050 50 0000 R CNN +F 1 "eSim_MOS_P" H 10650 3150 50 0000 R CNN +F 2 "" H 10850 3100 29 0000 C CNN +F 3 "" H 10650 3000 60 0000 C CNN + 1 10600 3000 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_P M15 +U 1 1 68680994 +P 10600 3950 +F 0 "M15" H 10550 4000 50 0000 R CNN +F 1 "eSim_MOS_P" H 10650 4100 50 0000 R CNN +F 2 "" H 10850 4050 29 0000 C CNN +F 3 "" H 10650 3950 60 0000 C CNN + 1 10600 3950 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M13 +U 1 1 68680995 +P 10550 4850 +F 0 "M13" H 10550 4700 50 0000 R CNN +F 1 "eSim_MOS_N" H 10650 4800 50 0000 R CNN +F 2 "" H 10850 4550 29 0000 C CNN +F 3 "" H 10650 4650 60 0000 C CNN + 1 10550 4850 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M20 +U 1 1 68680996 +P 12300 4250 +F 0 "M20" H 12250 4300 50 0000 R CNN +F 1 "eSim_MOS_P" H 12350 4400 50 0000 R CNN +F 2 "" H 12550 4350 29 0000 C CNN +F 3 "" H 12350 4250 60 0000 C CNN + 1 12300 4250 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M19 +U 1 1 68680997 +P 12250 4950 +F 0 "M19" H 12250 4800 50 0000 R CNN +F 1 "eSim_MOS_N" H 12350 4900 50 0000 R CNN +F 2 "" H 12550 4650 29 0000 C CNN +F 3 "" H 12350 4750 60 0000 C CNN + 1 12250 4950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 68680998 +P 3300 5650 +F 0 "U1" H 3350 5750 30 0000 C CNN +F 1 "PORT" H 3300 5650 30 0000 C CNN +F 2 "" H 3300 5650 60 0000 C CNN +F 3 "" H 3300 5650 60 0000 C CNN + 2 3300 5650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 68680999 +P 3400 3600 +F 0 "U1" H 3450 3700 30 0000 C CNN +F 1 "PORT" H 3400 3600 30 0000 C CNN +F 2 "" H 3400 3600 60 0000 C CNN +F 3 "" H 3400 3600 60 0000 C CNN + 1 3400 3600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 6868099A +P 13200 4700 +F 0 "U1" H 13250 4800 30 0000 C CNN +F 1 "PORT" H 13200 4700 30 0000 C CNN +F 2 "" H 13200 4700 60 0000 C CNN +F 3 "" H 13200 4700 60 0000 C CNN + 3 13200 4700 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 14 1 6868099B +P 8500 1650 +F 0 "U1" H 8550 1750 30 0000 C CNN +F 1 "PORT" H 8500 1650 30 0000 C CNN +F 2 "" H 8500 1650 60 0000 C CNN +F 3 "" H 8500 1650 60 0000 C CNN + 14 8500 1650 + 1 0 0 -1 +$EndComp +Connection ~ 8750 1950 +Wire Wire Line + 8750 1650 8750 1950 +Connection ~ 12450 7650 +Wire Wire Line + 12550 5300 12550 7700 +Connection ~ 10850 7650 +Wire Wire Line + 10850 5200 10850 7650 +Connection ~ 7650 7650 +Wire Wire Line + 12450 7650 12450 5350 +Connection ~ 8250 1950 +Wire Wire Line + 8250 4450 8250 1950 +Connection ~ 5600 7650 +Wire Wire Line + 5600 4500 5600 7650 +Wire Wire Line + 5400 4500 5600 4500 +Wire Wire Line + 5400 4200 5400 4500 +Connection ~ 5550 7650 +Wire Wire Line + 5550 4550 5550 7650 +Wire Wire Line + 5300 4550 5550 4550 +Wire Wire Line + 5300 4250 5300 4550 +Connection ~ 5400 7650 +Wire Wire Line + 2350 7650 12550 7650 +Wire Wire Line + 7650 7650 7650 4750 +Wire Wire Line + 5400 6250 5400 7650 +Wire Wire Line + 5300 6300 5300 7650 +Connection ~ 5950 1950 +Wire Wire Line + 5950 4900 5950 1950 +Wire Wire Line + 5400 4900 5950 4900 +Wire Wire Line + 5400 5050 5400 4900 +Connection ~ 5800 1950 +Wire Wire Line + 5800 4800 5800 1950 +Wire Wire Line + 5300 4800 5800 4800 +Wire Wire Line + 5300 5000 5300 4800 +Connection ~ 5400 1950 +Wire Wire Line + 5400 3000 5400 1950 +Connection ~ 12450 2600 +Wire Wire Line + 12550 2600 12550 4100 +Connection ~ 11000 2600 +Wire Wire Line + 11000 3500 11000 2600 +Wire Wire Line + 10850 3500 11000 3500 +Wire Wire Line + 10850 3800 10850 3500 +Connection ~ 10850 2600 +Wire Wire Line + 10850 2850 10850 2600 +Connection ~ 10750 2600 +Wire Wire Line + 5300 1950 10750 1950 +Wire Wire Line + 5300 2950 5300 1950 +Connection ~ 4650 3600 +Wire Wire Line + 4650 3600 3650 3600 +Wire Wire Line + 4650 4050 5000 4050 +Wire Wire Line + 4650 3150 4650 4050 +Wire Wire Line + 5000 3150 4650 3150 +Connection ~ 12450 4700 +Wire Wire Line + 12450 4700 12950 4700 +Wire Wire Line + 12450 4950 12450 4450 +Wire Wire Line + 10750 1950 10750 2800 +Wire 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Line + 23900 13450 25050 13450 +Wire Wire Line + 25050 14000 25300 14000 +Wire Wire Line + 25050 13100 25050 14000 +Wire Wire Line + 25300 13100 25050 13100 +Wire Wire Line + 23900 13000 23900 13700 +Connection ~ 17400 14500 +Wire Wire Line + 22050 13450 21800 13450 +Wire Wire Line + 22050 15350 22050 13450 +Wire Wire Line + 17400 15350 22050 15350 +Wire Wire Line + 17400 14500 17400 15350 +Connection ~ 17750 14500 +Wire Wire Line + 17750 14500 16700 14500 +Wire Wire Line + 17750 14950 18150 14950 +Wire Wire Line + 17750 14050 17750 14950 +Wire Wire Line + 18150 14050 17750 14050 +Connection ~ 19850 14500 +Wire Wire Line + 19850 13450 19850 14500 +Wire Wire Line + 20400 13450 19850 13450 +Connection ~ 18450 14500 +Wire Wire Line + 23900 14500 18450 14500 +Wire Wire Line + 23900 14100 23900 14500 +Wire Wire Line + 18450 14250 18450 14750 +Wire Wire Line + 21500 13950 21500 13650 +Wire Wire Line + 20700 13950 21500 13950 +Wire Wire Line + 20700 13650 20700 13950 +Connection ~ 21100 13100 +Connection ~ 21100 12450 +Wire Wire Line + 21100 13100 21100 12450 +Connection ~ 23300 13350 +Connection ~ 18450 12450 +Wire Wire Line + 22450 12450 18450 12450 +Wire Wire Line + 22450 13350 22450 12450 +Wire Wire Line + 23300 13350 22450 13350 +Wire Wire Line + 23300 13900 23600 13900 +Wire Wire Line + 23300 12800 23300 13900 +Wire Wire Line + 23600 12800 23300 12800 +Wire Wire Line + 21500 13100 21500 13250 +Wire Wire Line + 20700 13100 21500 13100 +Wire Wire Line + 20700 13250 20700 13100 +Wire Wire Line + 18450 12200 18450 12700 +Wire Wire Line + 18200 16450 18200 16500 +Connection ~ 18450 16500 +Connection ~ 13250 16450 +Wire Wire Line + 2350 7650 2350 16450 +Connection ~ 6000 16450 +Connection ~ 5300 7650 +Connection ~ 12550 7650 +Connection ~ 17750 7700 +Connection ~ 18450 10800 +Connection ~ 11450 10750 +Wire Wire Line + 29150 10800 29150 2000 +Connection ~ 23200 2000 +Connection ~ 23900 10800 +Connection ~ 10750 2000 +Connection ~ 17750 2000 +Wire Wire Line + 2350 12400 1900 12400 +Wire Wire Line + 1900 12400 1900 12350 +Connection ~ 2350 12400 +$Comp +L PORT U1 +U 7 1 6868755F +P 1650 12350 +F 0 "U1" H 1700 12450 30 0000 C CNN +F 1 "PORT" H 1650 12350 30 0000 C CNN +F 2 "" H 1650 12350 60 0000 C CNN +F 3 "" H 1650 12350 60 0000 C CNN + 7 1650 12350 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/CD4030B/CD4030B.sub b/library/SubcircuitLibrary/CD4030B/CD4030B.sub new file mode 100644 index 000000000..54f53f3d5 --- /dev/null +++ b/library/SubcircuitLibrary/CD4030B/CD4030B.sub @@ -0,0 +1,52 @@ +* Subcircuit CD4030B +.subckt CD4030B net-_m1-pad2_ net-_m11-pad2_ net-_m19-pad1_ net-_m41-pad1_ net-_m23-pad2_ net-_m24-pad2_ net-_m1-pad3_ net-_m5-pad2_ net-_m12-pad2_ net-_m21-pad1_ net-_m43-pad1_ net-_m27-pad2_ net-_m28-pad2_ net-_m11-pad4_ +* c:\fossee\esim\library\subcircuitlibrary\cd4030b\cd4030b.cir +.include PMOS-5um.lib +.include NMOS-5um.lib +m3 net-_m1-pad1_ net-_m1-pad2_ net-_m11-pad4_ net-_m11-pad4_ mos_p W=40u L=5u M=8 +m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad3_ mos_n W=20u L=5u M=4 +m4 net-_m13-pad3_ net-_m11-pad2_ net-_m11-pad4_ net-_m11-pad4_ mos_p W=40u L=5u M=8 +m2 net-_m13-pad3_ net-_m11-pad2_ net-_m1-pad3_ net-_m1-pad3_ mos_n W=20u L=5u M=4 +m9 net-_m1-pad1_ net-_m13-pad3_ net-_m11-pad1_ net-_m1-pad3_ mos_n W=20u L=5u M=4 +m11 net-_m11-pad1_ net-_m11-pad2_ net-_m1-pad1_ net-_m11-pad4_ mos_p W=40u L=5u M=8 +m14 net-_m14-pad1_ net-_m13-pad3_ net-_m11-pad4_ net-_m11-pad4_ mos_p W=40u L=5u M=8 +m15 net-_m11-pad1_ net-_m1-pad1_ net-_m14-pad1_ net-_m11-pad4_ mos_p W=40u L=5u M=8 +m13 net-_m11-pad1_ net-_m1-pad1_ net-_m13-pad3_ net-_m1-pad3_ mos_n W=20u L=5u M=4 +m20 net-_m19-pad1_ net-_m11-pad1_ net-_m11-pad4_ net-_m11-pad4_ mos_p W=40u L=5u M=8 +m19 net-_m19-pad1_ net-_m11-pad1_ net-_m1-pad3_ net-_m1-pad3_ mos_n W=20u L=5u M=4 +m25 net-_m23-pad1_ net-_m23-pad2_ net-_m11-pad4_ net-_m11-pad4_ mos_p W=40u L=5u M=8 +m23 net-_m23-pad1_ net-_m23-pad2_ net-_m1-pad3_ net-_m1-pad3_ mos_n W=20u L=5u M=4 +m26 net-_m24-pad1_ net-_m24-pad2_ net-_m11-pad4_ net-_m11-pad4_ mos_p W=40u L=5u M=8 +m24 net-_m24-pad1_ net-_m24-pad2_ net-_m1-pad3_ net-_m1-pad3_ mos_n W=20u L=5u M=4 +m31 net-_m23-pad1_ net-_m24-pad1_ net-_m31-pad3_ net-_m1-pad3_ mos_n W=20u L=5u M=4 +m33 net-_m31-pad3_ net-_m24-pad2_ net-_m23-pad1_ net-_m11-pad4_ mos_p W=40u L=5u M=8 +m36 net-_m36-pad1_ net-_m24-pad1_ net-_m11-pad4_ net-_m11-pad4_ mos_p W=40u L=5u M=8 +m37 net-_m31-pad3_ net-_m23-pad1_ net-_m36-pad1_ net-_m11-pad4_ mos_p W=40u L=5u M=8 +m35 net-_m31-pad3_ net-_m23-pad1_ net-_m24-pad1_ net-_m1-pad3_ mos_n W=20u L=5u M=4 +m42 net-_m41-pad1_ net-_m31-pad3_ net-_m11-pad4_ net-_m11-pad4_ mos_p W=40u L=5u M=8 +m41 net-_m41-pad1_ net-_m31-pad3_ net-_m1-pad3_ net-_m1-pad3_ mos_n W=20u L=5u M=4 +m7 net-_m10-pad1_ net-_m5-pad2_ net-_m11-pad4_ net-_m11-pad4_ mos_p W=40u L=5u M=8 +m5 net-_m10-pad1_ net-_m5-pad2_ net-_m1-pad3_ net-_m1-pad3_ mos_n W=20u L=5u M=4 +m8 net-_m10-pad2_ net-_m12-pad2_ net-_m11-pad4_ net-_m11-pad4_ mos_p W=40u L=5u M=8 +m6 net-_m10-pad2_ net-_m12-pad2_ net-_m1-pad3_ net-_m1-pad3_ mos_n W=20u L=5u M=4 +m10 net-_m10-pad1_ net-_m10-pad2_ net-_m10-pad3_ net-_m1-pad3_ mos_n W=20u L=5u M=4 +m12 net-_m10-pad3_ net-_m12-pad2_ net-_m10-pad1_ net-_m11-pad4_ mos_p W=40u L=5u M=8 +m17 net-_m17-pad1_ net-_m10-pad2_ net-_m11-pad4_ net-_m11-pad4_ mos_p W=40u L=5u M=8 +m18 net-_m10-pad3_ net-_m10-pad1_ net-_m17-pad1_ net-_m11-pad4_ mos_p W=40u L=5u M=8 +m16 net-_m10-pad3_ net-_m10-pad1_ net-_m10-pad2_ net-_m1-pad3_ mos_n W=20u L=5u M=4 +m22 net-_m21-pad1_ net-_m10-pad3_ net-_m11-pad4_ net-_m11-pad4_ mos_p W=40u L=5u M=8 +m21 net-_m21-pad1_ net-_m10-pad3_ net-_m1-pad3_ net-_m1-pad3_ mos_n W=20u L=5u M=4 +m29 net-_m27-pad1_ net-_m27-pad2_ net-_m11-pad4_ net-_m11-pad4_ mos_p W=40u L=5u M=8 +m27 net-_m27-pad1_ net-_m27-pad2_ net-_m1-pad3_ net-_m1-pad3_ mos_n W=20u L=5u M=4 +m30 net-_m28-pad1_ net-_m28-pad2_ net-_m11-pad4_ net-_m11-pad4_ mos_p W=40u L=5u M=8 +m28 net-_m28-pad1_ net-_m28-pad2_ net-_m1-pad3_ net-_m1-pad3_ mos_n W=20u L=5u M=4 +m32 net-_m27-pad1_ net-_m28-pad1_ net-_m32-pad3_ net-_m1-pad3_ mos_n W=20u L=5u M=4 +m34 net-_m32-pad3_ net-_m28-pad2_ net-_m27-pad1_ net-_m11-pad4_ mos_p W=40u L=5u M=8 +m39 net-_m39-pad1_ net-_m28-pad1_ net-_m11-pad4_ net-_m11-pad4_ mos_p W=40u L=5u M=8 +m40 net-_m32-pad3_ net-_m27-pad1_ net-_m39-pad1_ net-_m11-pad4_ mos_p W=40u L=5u M=8 +m38 net-_m32-pad3_ net-_m27-pad1_ net-_m28-pad1_ net-_m1-pad3_ mos_n W=20u L=5u M=4 +m44 net-_m43-pad1_ net-_m32-pad3_ net-_m11-pad4_ net-_m11-pad4_ mos_p W=40u L=5u M=8 +m43 net-_m43-pad1_ net-_m32-pad3_ net-_m1-pad3_ net-_m1-pad3_ mos_n W=20u L=5u M=4 +* Control Statements + +.ends CD4030B \ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4030B/CD4030B_Previous_Values.xml b/library/SubcircuitLibrary/CD4030B/CD4030B_Previous_Values.xml new file mode 100644 index 000000000..6bffbd3a1 --- /dev/null +++ b/library/SubcircuitLibrary/CD4030B/CD4030B_Previous_Values.xml @@ -0,0 +1 @@ +C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec \ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4030B/NMOS-5um.lib b/library/SubcircuitLibrary/CD4030B/NMOS-5um.lib new file mode 100644 index 000000000..a237e1fe3 --- /dev/null +++ b/library/SubcircuitLibrary/CD4030B/NMOS-5um.lib @@ -0,0 +1,5 @@ +* 5um technology + +.model mos_n NMOS( Cgso=0.4n Tox=85n Vto=1 phi=0.7 ++ Level=1 ++ Mj=.5 UO=750 Cgdo=0.4n Gamma=1.4 LAMBDA=0.01 LD=0.7u JS=1u CJ=0.4m CJSW=0.8n MJSW=0.5 PB=0.7 CGBO=0.2n ) diff --git a/library/SubcircuitLibrary/CD4030B/PMOS-5um.lib b/library/SubcircuitLibrary/CD4030B/PMOS-5um.lib new file mode 100644 index 000000000..9c3ed9760 --- /dev/null +++ b/library/SubcircuitLibrary/CD4030B/PMOS-5um.lib @@ -0,0 +1,5 @@ +*5um technology + +.model mos_p PMOS( Cgso=0.4n Tox=85n Vto=-1 phi=0.65 ++ Level=1 ++ Mj=.5 UO=250 Cgdo=0.4n Gamma=0.65 LAMBDA=0.03 LD=0.6u JS=1u CJ=0.18m CJSW=0.6n MJSW=0.5 PB=0.7 CGBO=0.2n ) diff --git a/library/SubcircuitLibrary/CD4030B/analysis b/library/SubcircuitLibrary/CD4030B/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/SubcircuitLibrary/CD4030B/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4085B/CD4085B-cache.lib b/library/SubcircuitLibrary/CD4085B/CD4085B-cache.lib new file mode 100644 index 000000000..348446c2e --- /dev/null +++ b/library/SubcircuitLibrary/CD4085B/CD4085B-cache.lib @@ -0,0 +1,100 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_MOS_N +# +DEF eSim_MOS_N M 0 0 Y N 1 F N +F0 "M" 0 -150 50 H V R CNN +F1 "eSim_MOS_N" 100 -50 50 H V R CNN +F2 "" 300 -300 29 H V C CNN +F3 "" 100 -200 60 H V C CNN +ALIAS mosfet_n +DRAW +C 150 -200 111 0 1 10 N +P 2 0 1 10 130 -290 130 -250 N +P 2 0 1 0 130 -270 200 -270 N +P 2 0 1 10 130 -220 130 -180 N +P 2 0 1 0 130 -200 200 -200 N +P 2 0 1 10 130 -150 130 -110 N +P 2 0 1 0 130 -130 200 -130 N +P 2 0 1 0 200 -300 200 -270 N +P 2 0 1 0 200 -130 200 -100 N +P 3 0 1 10 110 -275 110 -125 110 -125 N +P 3 0 1 0 200 -200 300 -200 300 -250 N +P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F +X D 1 200 0 100 D 50 50 1 1 P +X G 2 -100 -200 210 R 50 50 1 1 P +X S 3 200 -400 100 U 50 50 1 1 P +X B 4 300 -350 98 U 47 47 1 1 P +ENDDRAW +ENDDEF +# +# eSim_MOS_P +# +DEF eSim_MOS_P M 0 0 Y N 1 F N +F0 "M" -50 50 50 H V R CNN +F1 "eSim_MOS_P" 50 150 50 H V R CNN +F2 "" 250 100 29 H V C CNN +F3 "" 50 0 60 H V C CNN +ALIAS mosfet_p +DRAW +C 100 0 111 0 1 10 N +P 2 0 1 0 80 -70 150 -70 N +P 2 0 1 10 80 -50 80 -90 N +P 2 0 1 0 80 0 150 0 N +P 2 0 1 10 80 20 80 -20 N +P 2 0 1 0 80 70 150 70 N +P 2 0 1 10 80 90 80 50 N +P 2 0 1 0 150 -70 150 -100 N +P 2 0 1 0 150 100 150 70 N +P 3 0 1 10 60 75 60 -75 60 -75 N +P 3 0 1 0 150 0 250 0 250 -50 N +P 4 0 1 0 140 0 100 -15 100 15 140 0 F +X D 1 150 200 100 D 50 50 1 1 P +X G 2 -150 0 210 R 50 50 1 1 P +X S 3 150 -200 100 U 50 50 1 1 P +X B 4 250 -150 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/CD4085B/CD4085B.bak b/library/SubcircuitLibrary/CD4085B/CD4085B.bak new file mode 100644 index 000000000..5dcca9bb8 --- /dev/null +++ b/library/SubcircuitLibrary/CD4085B/CD4085B.bak @@ -0,0 +1,1384 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:AOI-cache +EELAYER 25 0 +EELAYER END +$Descr A1 33110 23386 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_MOS_P M3 +U 1 1 685581CA +P 8450 3050 +F 0 "M3" H 8400 3100 50 0000 R CNN +F 1 "eSim_MOS_P" H 8500 3200 50 0000 R CNN +F 2 "" H 8700 3150 29 0000 C CNN +F 3 "" H 8500 3050 60 0000 C CNN + 1 8450 3050 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_P M11 +U 1 1 685581CB +P 10050 3050 +F 0 "M11" H 10000 3100 50 0000 R CNN +F 1 "eSim_MOS_P" H 10100 3200 50 0000 R CNN +F 2 "" H 10300 3150 29 0000 C CNN +F 3 "" H 10100 3050 60 0000 C CNN + 1 10050 3050 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M12 +U 1 1 685581CC +P 10050 4300 +F 0 "M12" H 10050 4150 50 0000 R CNN +F 1 "eSim_MOS_N" H 10150 4250 50 0000 R CNN +F 2 "" H 10350 4000 29 0000 C CNN +F 3 "" H 10150 4100 60 0000 C CNN + 1 10050 4300 + 1 0 0 -1 +$EndComp +$Comp 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4750 14750 30 0000 C CNN +F 2 "" H 4750 14750 60 0000 C CNN +F 3 "" H 4750 14750 60 0000 C CNN + 5 4750 14750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 6855ADA0 +P 4800 16250 +F 0 "U1" H 4850 16350 30 0000 C CNN +F 1 "PORT" H 4800 16250 30 0000 C CNN +F 2 "" H 4800 16250 60 0000 C CNN +F 3 "" H 4800 16250 60 0000 C CNN + 6 4800 16250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 6855ADA6 +P 6300 19300 +F 0 "U1" H 6350 19400 30 0000 C CNN +F 1 "PORT" H 6300 19300 30 0000 C CNN +F 2 "" H 6300 19300 60 0000 C CNN +F 3 "" H 6300 19300 60 0000 C CNN + 8 6300 19300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 6855ADAC +P 6450 20750 +F 0 "U1" H 6500 20850 30 0000 C CNN +F 1 "PORT" H 6450 20750 30 0000 C CNN +F 2 "" H 6450 20750 60 0000 C CNN +F 3 "" H 6450 20750 60 0000 C CNN + 9 6450 20750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 6855ADB2 +P 25450 15350 +F 0 "U1" H 25500 15450 30 0000 C CNN +F 1 "PORT" H 25450 15350 30 0000 C CNN +F 2 "" H 25450 15350 60 0000 C CNN +F 3 "" H 25450 15350 60 0000 C CNN + 4 25450 15350 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 7 1 6855ADB8 +P 13750 22400 +F 0 "U1" H 13800 22500 30 0000 C CNN +F 1 "PORT" H 13750 22400 30 0000 C CNN +F 2 "" H 13750 22400 60 0000 C CNN +F 3 "" H 13750 22400 60 0000 C CNN + 7 13750 22400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 6855ADC4 +P 15100 12050 +F 0 "U1" H 15150 12150 30 0000 C CNN +F 1 "PORT" H 15100 12050 30 0000 C CNN +F 2 "" H 15100 12050 60 0000 C CNN +F 3 "" H 15100 12050 60 0000 C CNN + 11 15100 12050 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7700 13600 7700 12950 +Wire Wire Line + 7700 12950 9400 12950 +Wire Wire Line + 9300 12950 9300 13600 +Wire Wire Line + 9400 12950 9400 13650 +Connection ~ 9300 12950 +Wire Wire Line + 7800 13650 7800 12950 +Connection ~ 7800 12950 +Wire Wire Line + 7700 14000 7700 14450 +Wire Wire Line + 7700 14450 9350 14450 +Wire Wire Line + 9350 14050 9350 15050 +Wire Wire Line + 9300 14000 9300 14050 +Wire Wire Line + 9300 14050 9350 14050 +Connection ~ 9350 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10650 +Wire Wire Line + 4150 1600 4150 12350 +Connection ~ 5850 12350 +Connection ~ 6750 1600 +Text Label 14600 1300 0 60 ~ 0 +VDD +Text Label 14000 21950 0 60 ~ 0 +VSS +Text Label 6050 3950 0 60 ~ 0 +A1 +Text Label 5300 14700 0 60 ~ 0 +A2 +Text Label 6150 5500 0 60 ~ 0 +B1 +Text Label 5200 16250 0 60 ~ 0 +B2 +Text Label 7650 8450 0 60 ~ 0 +C1 +Text Label 6700 19200 0 60 ~ 0 +C2 +Text Label 7850 10100 0 60 ~ 0 +D1 +Text Label 6850 20850 0 60 ~ 0 +D2 +Text Label 16250 1450 0 60 ~ 0 +INHIBIT1 +Text Label 15350 12200 0 60 ~ 0 +INHIBIT2 +Text Label 25750 4600 0 60 ~ 0 +E1 +Text Label 24850 15350 0 60 ~ 0 +E2 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/CD4085B/CD4085B.cir b/library/SubcircuitLibrary/CD4085B/CD4085B.cir new file mode 100644 index 000000000..6b68ca025 --- /dev/null +++ b/library/SubcircuitLibrary/CD4085B/CD4085B.cir @@ -0,0 +1,51 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\CD4085B\CD4085B.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/20/25 21:32:25 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +M3 Net-_M11-Pad1_ /A1 /VDD /VDD eSim_MOS_P +M11 Net-_M11-Pad1_ /B1 /VDD /VDD eSim_MOS_P +M12 Net-_M11-Pad1_ /A1 Net-_M12-Pad3_ /VSS eSim_MOS_N +M13 Net-_M12-Pad3_ /B1 /VSS /VSS eSim_MOS_N +M4 Net-_M14-Pad1_ /C1 /VDD /VDD eSim_MOS_P +M14 Net-_M14-Pad1_ /D1 /VDD /VDD eSim_MOS_P +M15 Net-_M14-Pad1_ /C1 Net-_M15-Pad3_ /VSS eSim_MOS_N +M16 Net-_M15-Pad3_ /D1 /VSS /VSS eSim_MOS_N +M18 Net-_M18-Pad1_ Net-_M11-Pad1_ /VDD /VDD eSim_MOS_P +M22 Net-_M18-Pad1_ Net-_M14-Pad1_ /VDD /VDD eSim_MOS_P +M23 Net-_M18-Pad1_ Net-_M11-Pad1_ Net-_M23-Pad3_ /VSS eSim_MOS_N +M24 Net-_M23-Pad3_ Net-_M14-Pad1_ /VSS /VSS eSim_MOS_N +M31 Net-_M31-Pad1_ /INHIBIT1 /VDD /VDD eSim_MOS_P +M32 Net-_M26-Pad1_ Net-_M18-Pad1_ Net-_M31-Pad1_ /VDD eSim_MOS_P +M30 Net-_M26-Pad1_ Net-_M18-Pad1_ /VSS /VSS eSim_MOS_N +M26 Net-_M26-Pad1_ /INHIBIT1 /VSS /VSS eSim_MOS_N +M35 Net-_M35-Pad1_ Net-_M26-Pad1_ /VSS /VSS eSim_MOS_N +M36 Net-_M35-Pad1_ Net-_M26-Pad1_ /VDD /VDD eSim_MOS_P +M39 /E1 Net-_M35-Pad1_ /VSS /VSS eSim_MOS_N +M40 /E1 Net-_M35-Pad1_ /VDD /VDD eSim_MOS_P +U1 /A1 /B1 /E1 /E2 /A2 /B2 /VSS /C2 /D2 /INHIBIT1 /INHIBIT2 /C1 /D1 /VDD PORT +M1 Net-_M1-Pad1_ /A2 /VDD /VDD eSim_MOS_P +M5 Net-_M1-Pad1_ /B2 /VDD /VDD eSim_MOS_P +M6 Net-_M1-Pad1_ /A2 Net-_M6-Pad3_ /VSS eSim_MOS_N +M7 Net-_M6-Pad3_ /B2 /VSS /VSS eSim_MOS_N +M2 Net-_M19-Pad2_ /C2 /VDD /VDD eSim_MOS_P +M8 Net-_M19-Pad2_ /D2 /VDD /VDD eSim_MOS_P +M9 Net-_M19-Pad2_ /C2 Net-_M10-Pad1_ /VSS eSim_MOS_N +M10 Net-_M10-Pad1_ /D2 /VSS /VSS eSim_MOS_N +M17 Net-_M17-Pad1_ Net-_M1-Pad1_ /VDD /VDD eSim_MOS_P +M19 Net-_M17-Pad1_ Net-_M19-Pad2_ /VDD /VDD eSim_MOS_P +M20 Net-_M17-Pad1_ Net-_M1-Pad1_ Net-_M20-Pad3_ /VSS eSim_MOS_N +M21 Net-_M20-Pad3_ Net-_M19-Pad2_ /VSS /VSS eSim_MOS_N +M28 Net-_M28-Pad1_ /INHIBIT2 /VDD /VDD eSim_MOS_P +M29 Net-_M25-Pad1_ Net-_M17-Pad1_ Net-_M28-Pad1_ /VDD eSim_MOS_P +M27 Net-_M25-Pad1_ Net-_M17-Pad1_ /VSS /VSS eSim_MOS_N +M25 Net-_M25-Pad1_ /INHIBIT2 /VSS /VSS eSim_MOS_N +M33 Net-_M33-Pad1_ Net-_M25-Pad1_ /VSS /VSS eSim_MOS_N +M34 Net-_M33-Pad1_ Net-_M25-Pad1_ /VDD /VDD eSim_MOS_P +M37 /E2 Net-_M33-Pad1_ /VSS /VSS eSim_MOS_N +M38 /E2 Net-_M33-Pad1_ /VDD /VDD eSim_MOS_P + +.end diff --git a/library/SubcircuitLibrary/CD4085B/CD4085B.cir.out b/library/SubcircuitLibrary/CD4085B/CD4085B.cir.out new file mode 100644 index 000000000..50e2e9e0a --- /dev/null +++ b/library/SubcircuitLibrary/CD4085B/CD4085B.cir.out @@ -0,0 +1,54 @@ +* c:\fossee\esim\library\subcircuitlibrary\cd4085b\cd4085b.cir + +.include NMOS-5um.lib +.include PMOS-5um.lib +m3 net-_m11-pad1_ /a1 /vdd /vdd mos_p W=100u L=100u M=1 +m11 net-_m11-pad1_ /b1 /vdd /vdd mos_p W=100u L=100u M=1 +m12 net-_m11-pad1_ /a1 net-_m12-pad3_ /vss mos_n W=100u L=100u M=1 +m13 net-_m12-pad3_ /b1 /vss /vss mos_n W=100u L=100u M=1 +m4 net-_m14-pad1_ /c1 /vdd /vdd mos_p W=100u L=100u M=1 +m14 net-_m14-pad1_ /d1 /vdd /vdd mos_p W=100u L=100u M=1 +m15 net-_m14-pad1_ /c1 net-_m15-pad3_ /vss mos_n W=100u L=100u M=1 +m16 net-_m15-pad3_ /d1 /vss /vss mos_n W=100u L=100u M=1 +m18 net-_m18-pad1_ net-_m11-pad1_ /vdd /vdd mos_p W=100u L=100u M=1 +m22 net-_m18-pad1_ net-_m14-pad1_ /vdd /vdd mos_p W=100u L=100u M=1 +m23 net-_m18-pad1_ net-_m11-pad1_ net-_m23-pad3_ /vss mos_n W=100u L=100u M=1 +m24 net-_m23-pad3_ net-_m14-pad1_ /vss /vss mos_n W=100u L=100u M=1 +m31 net-_m31-pad1_ /inhibit1 /vdd /vdd mos_p W=100u L=100u M=1 +m32 net-_m26-pad1_ net-_m18-pad1_ net-_m31-pad1_ /vdd mos_p W=100u L=100u M=1 +m30 net-_m26-pad1_ net-_m18-pad1_ /vss /vss mos_n W=100u L=100u M=1 +m26 net-_m26-pad1_ /inhibit1 /vss /vss mos_n W=100u L=100u M=1 +m35 net-_m35-pad1_ net-_m26-pad1_ /vss /vss mos_n W=100u L=100u M=1 +m36 net-_m35-pad1_ net-_m26-pad1_ /vdd /vdd mos_p W=100u L=100u M=1 +m39 /e1 net-_m35-pad1_ /vss /vss mos_n W=100u L=100u M=1 +m40 /e1 net-_m35-pad1_ /vdd /vdd mos_p W=100u L=100u M=1 +* u1 /a1 /b1 /e1 /e2 /a2 /b2 /vss /c2 /d2 /inhibit1 /inhibit2 /c1 /d1 /vdd port +m1 net-_m1-pad1_ /a2 /vdd /vdd mos_p W=100u L=100u M=1 +m5 net-_m1-pad1_ /b2 /vdd /vdd mos_p W=100u L=100u M=1 +m6 net-_m1-pad1_ /a2 net-_m6-pad3_ /vss mos_n W=100u L=100u M=1 +m7 net-_m6-pad3_ /b2 /vss /vss mos_n W=100u L=100u M=1 +m2 net-_m19-pad2_ /c2 /vdd /vdd mos_p W=100u L=100u M=1 +m8 net-_m19-pad2_ /d2 /vdd /vdd mos_p W=100u L=100u M=1 +m9 net-_m19-pad2_ /c2 net-_m10-pad1_ /vss mos_n W=100u L=100u M=1 +m10 net-_m10-pad1_ /d2 /vss /vss mos_n W=100u L=100u M=1 +m17 net-_m17-pad1_ net-_m1-pad1_ /vdd /vdd mos_p W=100u L=100u M=1 +m19 net-_m17-pad1_ net-_m19-pad2_ /vdd /vdd mos_p W=100u L=100u M=1 +m20 net-_m17-pad1_ net-_m1-pad1_ net-_m20-pad3_ /vss mos_n W=100u L=100u M=1 +m21 net-_m20-pad3_ net-_m19-pad2_ /vss /vss mos_n W=100u L=100u M=1 +m28 net-_m28-pad1_ /inhibit2 /vdd /vdd mos_p W=100u L=100u M=1 +m29 net-_m25-pad1_ net-_m17-pad1_ net-_m28-pad1_ /vdd mos_p W=100u L=100u M=1 +m27 net-_m25-pad1_ net-_m17-pad1_ /vss /vss mos_n W=100u L=100u M=1 +m25 net-_m25-pad1_ /inhibit2 /vss /vss mos_n W=100u L=100u M=1 +m33 net-_m33-pad1_ net-_m25-pad1_ /vss /vss mos_n W=100u L=100u M=1 +m34 net-_m33-pad1_ net-_m25-pad1_ /vdd /vdd mos_p W=100u L=100u M=1 +m37 /e2 net-_m33-pad1_ /vss /vss mos_n W=100u L=100u M=1 +m38 /e2 net-_m33-pad1_ /vdd /vdd mos_p W=100u L=100u M=1 +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/CD4085B/CD4085B.pro b/library/SubcircuitLibrary/CD4085B/CD4085B.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/CD4085B/CD4085B.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/CD4085B/CD4085B.sch b/library/SubcircuitLibrary/CD4085B/CD4085B.sch new file mode 100644 index 000000000..8bb704423 --- /dev/null +++ b/library/SubcircuitLibrary/CD4085B/CD4085B.sch @@ -0,0 +1,1384 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors 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CNN +F 1 "eSim_MOS_N" H 9250 16050 50 0000 R CNN +F 2 "" H 9450 15800 29 0000 C CNN +F 3 "" H 9250 15900 60 0000 C CNN + 1 9150 16100 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M2 +U 1 1 6855AD3A +P 7700 18350 +F 0 "M2" H 7650 18400 50 0000 R CNN +F 1 "eSim_MOS_P" H 7750 18500 50 0000 R CNN +F 2 "" H 7950 18450 29 0000 C CNN +F 3 "" H 7750 18350 60 0000 C CNN + 1 7700 18350 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_P M8 +U 1 1 6855AD40 +P 9300 18350 +F 0 "M8" H 9250 18400 50 0000 R CNN +F 1 "eSim_MOS_P" H 9350 18500 50 0000 R CNN +F 2 "" H 9550 18450 29 0000 C CNN +F 3 "" H 9350 18350 60 0000 C CNN + 1 9300 18350 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M9 +U 1 1 6855AD46 +P 9300 19600 +F 0 "M9" H 9300 19450 50 0000 R CNN +F 1 "eSim_MOS_N" H 9400 19550 50 0000 R CNN +F 2 "" H 9600 19300 29 0000 C CNN +F 3 "" H 9400 19400 60 0000 C CNN + 1 9300 19600 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_N M10 +U 1 1 6855AD4C +P 9300 20650 +F 0 "M10" H 9300 20500 50 0000 R CNN +F 1 "eSim_MOS_N" H 9400 20600 50 0000 R CNN +F 2 "" H 9600 20350 29 0000 C CNN +F 3 "" H 9400 20450 60 0000 C CNN + 1 9300 20650 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M17 +U 1 1 6855AD52 +P 12200 15050 +F 0 "M17" H 12150 15100 50 0000 R CNN +F 1 "eSim_MOS_P" H 12250 15200 50 0000 R CNN +F 2 "" H 12450 15150 29 0000 C CNN +F 3 "" H 12250 15050 60 0000 C CNN + 1 12200 15050 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_P M19 +U 1 1 6855AD58 +P 13800 15050 +F 0 "M19" H 13750 15100 50 0000 R CNN +F 1 "eSim_MOS_P" H 13850 15200 50 0000 R CNN +F 2 "" H 14050 15150 29 0000 C CNN +F 3 "" H 13850 15050 60 0000 C CNN + 1 13800 15050 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M20 +U 1 1 6855AD5E +P 13800 16300 +F 0 "M20" H 13800 16150 50 0000 R CNN +F 1 "eSim_MOS_N" H 13900 16250 50 0000 R CNN +F 2 "" H 14100 16000 29 0000 C CNN +F 3 "" H 13900 16100 60 0000 C CNN + 1 13800 16300 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_N M21 +U 1 1 6855AD64 +P 13800 17350 +F 0 "M21" H 13800 17200 50 0000 R CNN +F 1 "eSim_MOS_N" H 13900 17300 50 0000 R CNN +F 2 "" H 14100 17050 29 0000 C CNN +F 3 "" H 13900 17150 60 0000 C CNN + 1 13800 17350 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M28 +U 1 1 6855AD6A +P 17750 13650 +F 0 "M28" H 17700 13700 50 0000 R CNN +F 1 "eSim_MOS_P" H 17800 13800 50 0000 R CNN +F 2 "" H 18000 13750 29 0000 C CNN +F 3 "" H 17800 13650 60 0000 C CNN + 1 17750 13650 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_P M29 +U 1 1 6855AD70 +P 17750 14800 +F 0 "M29" H 17700 14850 50 0000 R CNN +F 1 "eSim_MOS_P" H 17800 14950 50 0000 R CNN +F 2 "" H 18000 14900 29 0000 C CNN +F 3 "" H 17800 14800 60 0000 C CNN + 1 17750 14800 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M27 +U 1 1 6855AD76 +P 17700 15600 +F 0 "M27" H 17700 15450 50 0000 R CNN +F 1 "eSim_MOS_N" H 17800 15550 50 0000 R CNN +F 2 "" H 18000 15300 29 0000 C CNN +F 3 "" H 17800 15400 60 0000 C CNN + 1 17700 15600 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_N M25 +U 1 1 6855AD7C +P 16100 15650 +F 0 "M25" H 16100 15500 50 0000 R CNN +F 1 "eSim_MOS_N" H 16200 15600 50 0000 R CNN +F 2 "" H 16400 15350 29 0000 C CNN +F 3 "" H 16200 15450 60 0000 C CNN + 1 16100 15650 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_N M33 +U 1 1 6855AD82 +P 20500 15850 +F 0 "M33" H 20500 15700 50 0000 R CNN +F 1 "eSim_MOS_N" H 20600 15800 50 0000 R CNN +F 2 "" H 20800 15550 29 0000 C CNN +F 3 "" H 20600 15650 60 0000 C CNN + 1 20500 15850 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M34 +U 1 1 6855AD88 +P 20550 14750 +F 0 "M34" H 20500 14800 50 0000 R CNN +F 1 "eSim_MOS_P" H 20600 14900 50 0000 R CNN +F 2 "" H 20800 14850 29 0000 C CNN +F 3 "" H 20600 14750 60 0000 C CNN + 1 20550 14750 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M37 +U 1 1 6855AD8E +P 23450 15900 +F 0 "M37" H 23450 15750 50 0000 R CNN +F 1 "eSim_MOS_N" H 23550 15850 50 0000 R CNN +F 2 "" H 23750 15600 29 0000 C CNN +F 3 "" H 23550 15700 60 0000 C CNN + 1 23450 15900 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M38 +U 1 1 6855AD94 +P 23500 14800 +F 0 "M38" H 23450 14850 50 0000 R CNN +F 1 "eSim_MOS_P" H 23550 14950 50 0000 R CNN +F 2 "" H 23750 14900 29 0000 C CNN +F 3 "" H 23550 14800 60 0000 C CNN + 1 23500 14800 + 1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 5 1 6855AD9A +P 4750 14750 +F 0 "U1" H 4800 14850 30 0000 C CNN +F 1 "PORT" H 4750 14750 30 0000 C CNN +F 2 "" H 4750 14750 60 0000 C CNN +F 3 "" H 4750 14750 60 0000 C CNN + 5 4750 14750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 6855ADA0 +P 4800 16250 +F 0 "U1" H 4850 16350 30 0000 C CNN +F 1 "PORT" H 4800 16250 30 0000 C CNN +F 2 "" H 4800 16250 60 0000 C CNN +F 3 "" H 4800 16250 60 0000 C CNN + 6 4800 16250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 6855ADA6 +P 6300 19300 +F 0 "U1" H 6350 19400 30 0000 C CNN +F 1 "PORT" H 6300 19300 30 0000 C CNN +F 2 "" H 6300 19300 60 0000 C CNN +F 3 "" H 6300 19300 60 0000 C CNN + 8 6300 19300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 6855ADAC +P 6450 20750 +F 0 "U1" H 6500 20850 30 0000 C CNN +F 1 "PORT" H 6450 20750 30 0000 C CNN +F 2 "" H 6450 20750 60 0000 C CNN +F 3 "" H 6450 20750 60 0000 C CNN + 9 6450 20750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 6855ADB2 +P 25450 15350 +F 0 "U1" H 25500 15450 30 0000 C CNN +F 1 "PORT" H 25450 15350 30 0000 C CNN +F 2 "" H 25450 15350 60 0000 C CNN +F 3 "" H 25450 15350 60 0000 C CNN + 4 25450 15350 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 7 1 6855ADB8 +P 13750 22400 +F 0 "U1" H 13800 22500 30 0000 C CNN +F 1 "PORT" H 13750 22400 30 0000 C CNN +F 2 "" H 13750 22400 60 0000 C CNN +F 3 "" H 13750 22400 60 0000 C CNN + 7 13750 22400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 6855ADC4 +P 15100 12050 +F 0 "U1" H 15150 12150 30 0000 C CNN +F 1 "PORT" H 15100 12050 30 0000 C CNN +F 2 "" H 15100 12050 60 0000 C CNN +F 3 "" H 15100 12050 60 0000 C CNN + 11 15100 12050 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7700 13600 7700 12950 +Wire Wire Line + 7700 12950 9400 12950 +Wire Wire Line + 9300 12950 9300 13600 +Wire Wire Line + 9400 12950 9400 13650 +Connection ~ 9300 12950 +Wire Wire Line + 7800 13650 7800 12950 +Connection ~ 7800 12950 +Wire Wire Line + 7700 14000 7700 14450 +Wire Wire Line + 7700 14450 9350 14450 +Wire Wire Line + 9350 14050 9350 15050 +Wire Wire Line + 9300 14000 9300 14050 +Wire Wire Line + 9300 14050 9350 14050 +Connection ~ 9350 14450 +Wire Wire Line + 9350 15450 9350 16100 +Wire Wire Line + 9350 16500 9350 16850 +Wire Wire Line + 9450 16450 9450 16600 +Wire Wire Line + 9450 16600 9350 16600 +Connection ~ 9350 16600 +Wire Wire Line + 9450 15400 9450 15450 +Wire Wire Line + 9450 15450 9500 15450 +Wire Wire Line + 9500 15450 9500 16750 +Wire Wire Line + 9500 16750 9350 16750 +Connection ~ 9350 16750 +Wire Wire Line + 7400 13800 7100 13800 +Wire Wire Line + 7100 13800 7100 15250 +Wire Wire Line + 7100 15250 9050 15250 +Wire Wire Line + 9000 13800 8400 13800 +Wire Wire Line + 8400 13800 8400 16300 +Wire Wire Line + 6550 16300 9050 16300 +Wire Wire Line + 6550 16250 6550 16300 +Connection ~ 8400 16300 +Wire Wire Line + 7100 14650 6400 14650 +Wire Wire Line + 6400 14650 6400 14700 +Connection ~ 7100 14650 +Wire Wire Line + 7850 18150 7850 17500 +Wire Wire Line + 7850 17500 9550 17500 +Wire Wire Line + 9450 17500 9450 18150 +Wire Wire Line + 9550 17500 9550 18200 +Connection ~ 9450 17500 +Wire Wire Line + 7950 18200 7950 17500 +Connection ~ 7950 17500 +Wire Wire Line + 7850 18550 7850 19000 +Wire Wire Line + 7850 19000 9500 19000 +Wire Wire Line + 9500 18600 9500 19600 +Wire Wire Line + 9450 18550 9450 18600 +Wire Wire Line + 9450 18600 9500 18600 +Connection ~ 9500 19000 +Wire Wire Line + 9500 20000 9500 20650 +Wire Wire Line + 9500 21050 9500 21400 +Wire Wire Line + 9600 21000 9600 21150 +Wire Wire Line + 9600 21150 9500 21150 +Connection ~ 9500 21150 +Wire Wire Line + 9600 19950 9600 20000 +Wire Wire Line + 9600 20000 9650 20000 +Wire Wire Line + 9650 20000 9650 21300 +Wire Wire Line + 9650 21300 9500 21300 +Connection ~ 9500 21300 +Wire Wire Line + 7550 18350 7250 18350 +Wire Wire Line + 7250 18350 7250 19800 +Wire Wire Line + 7250 19800 9200 19800 +Wire Wire Line + 9150 18350 8550 18350 +Wire Wire Line + 8550 18350 8550 20850 +Wire Wire Line + 6700 20850 9200 20850 +Wire Wire Line + 6700 20750 6700 20850 +Connection ~ 8550 20850 +Wire Wire Line + 7250 19200 6550 19200 +Wire Wire Line + 6550 19200 6550 19300 +Connection ~ 7250 19200 +Wire Wire Line + 12350 14850 12350 14200 +Wire Wire Line + 12350 14200 14050 14200 +Wire Wire Line + 13950 14200 13950 14850 +Wire Wire Line + 14050 14200 14050 14900 +Connection ~ 13950 14200 +Wire Wire Line + 12450 14900 12450 14200 +Connection ~ 12450 14200 +Wire Wire Line + 12350 15250 12350 15700 +Wire Wire Line + 12350 15700 14000 15700 +Wire Wire Line + 14000 15300 14000 16300 +Wire Wire Line + 13950 15250 13950 15300 +Wire Wire Line + 13950 15300 14000 15300 +Connection ~ 14000 15700 +Wire Wire Line + 14000 16700 14000 17350 +Wire Wire Line + 14000 17750 14000 22400 +Wire Wire Line + 14100 17700 14100 17850 +Wire Wire Line + 14100 17850 14000 17850 +Connection ~ 14000 17850 +Wire Wire Line + 14100 16650 14100 16700 +Wire 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+Wire Wire Line + 23650 18150 23650 16300 +Wire Wire Line + 23750 18150 23750 16250 +Connection ~ 20700 15400 +Wire Wire Line + 20800 18150 23750 18150 +Connection ~ 20800 18100 +Connection ~ 23650 18150 +Connection ~ 20800 12800 +Connection ~ 23650 12800 +Wire Wire Line + 23650 15400 24850 15400 +Wire Wire Line + 24850 15400 24850 15350 +Connection ~ 23650 15400 +Wire Wire Line + 13150 12350 13150 14200 +Wire Wire Line + 4150 12350 20950 12350 +Wire Wire Line + 20950 12350 20950 12800 +Connection ~ 20950 12800 +Connection ~ 13150 14200 +Connection ~ 8300 12950 +Wire Wire Line + 5850 12350 5850 17050 +Wire Wire Line + 5850 17050 8650 17050 +Wire Wire Line + 8650 17050 8650 17500 +Connection ~ 8650 17500 +Wire Wire Line + 9350 16850 10100 16850 +Wire Wire Line + 10100 16850 10100 21400 +Wire Wire Line + 9500 21400 26800 21400 +Connection ~ 14000 18100 +Connection ~ 10100 21400 +Connection ~ 14000 21400 +Wire Wire Line + 5050 16250 6550 16250 +Wire Wire Line + 6400 14700 5000 14700 +Wire Wire Line + 5000 14700 5000 14750 +Wire Wire Line + 24850 15350 25200 15350 +Wire Wire Line + 8300 12350 8300 12950 +Connection ~ 13150 12350 +Connection ~ 8300 12350 +Wire Wire Line + 26800 21400 26800 10650 +Connection ~ 14900 10650 +Wire Wire Line + 4150 1600 4150 12350 +Connection ~ 5850 12350 +Connection ~ 6750 1600 +Text Label 14600 1300 0 60 ~ 0 +VDD +Text Label 14000 21950 0 60 ~ 0 +VSS +Text Label 7700 3900 0 60 ~ 0 +A1 +Text Label 5300 14700 0 60 ~ 0 +A2 +Text Label 7750 5550 0 60 ~ 0 +B1 +Text Label 5200 16250 0 60 ~ 0 +B2 +Text Label 7650 8450 0 60 ~ 0 +C1 +Text Label 6700 19200 0 60 ~ 0 +C2 +Text Label 7850 10100 0 60 ~ 0 +D1 +Text Label 6850 20850 0 60 ~ 0 +D2 +Text Label 16250 1450 0 60 ~ 0 +INHIBIT1 +Text Label 15350 12200 0 60 ~ 0 +INHIBIT2 +Text Label 25750 4600 0 60 ~ 0 +E1 +Text Label 24850 15350 0 60 ~ 0 +E2 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/CD4085B/CD4085B.sub b/library/SubcircuitLibrary/CD4085B/CD4085B.sub new file mode 100644 index 000000000..474a06a9c --- /dev/null +++ b/library/SubcircuitLibrary/CD4085B/CD4085B.sub @@ -0,0 +1,48 @@ +* Subcircuit CD4085B +.subckt CD4085B /a1 /b1 /e1 /e2 /a2 /b2 /vss /c2 /d2 /inhibit1 /inhibit2 /c1 /d1 /vdd +* c:\fossee\esim\library\subcircuitlibrary\cd4085b\cd4085b.cir +.include NMOS-5um.lib +.include PMOS-5um.lib +m3 net-_m11-pad1_ /a1 /vdd /vdd mos_p W=40u L=5u M=8 +m11 net-_m11-pad1_ /b1 /vdd /vdd mos_p W=40u L=5u M=8 +m12 net-_m11-pad1_ /a1 net-_m12-pad3_ /vss mos_n W=20u L=5u M=4 +m13 net-_m12-pad3_ /b1 /vss /vss mos_n W=20u L=5u M=4 +m4 net-_m14-pad1_ /c1 /vdd /vdd mos_p W=40u L=5u M=8 +m14 net-_m14-pad1_ /d1 /vdd /vdd mos_p W=40u L=5u M=8 +m15 net-_m14-pad1_ /c1 net-_m15-pad3_ /vss mos_n W=20u L=5u M=4 +m16 net-_m15-pad3_ /d1 /vss /vss mos_n W=20u L=5u M=4 +m18 net-_m18-pad1_ net-_m11-pad1_ /vdd /vdd mos_p W=40u L=5u M=8 +m22 net-_m18-pad1_ net-_m14-pad1_ /vdd /vdd mos_p W=40u L=5u M=8 +m23 net-_m18-pad1_ net-_m11-pad1_ net-_m23-pad3_ /vss mos_n W=20u L=5u M=4 +m24 net-_m23-pad3_ net-_m14-pad1_ /vss /vss mos_n W=20u L=5u M=4 +m31 net-_m31-pad1_ /inhibit1 /vdd /vdd mos_p W=40u L=5u M=8 +m32 net-_m26-pad1_ net-_m18-pad1_ net-_m31-pad1_ /vdd mos_p W=40u L=5u M=8 +m30 net-_m26-pad1_ net-_m18-pad1_ /vss /vss mos_n W=20u L=5u M=4 +m26 net-_m26-pad1_ /inhibit1 /vss /vss mos_n W=20u L=5u M=4 +m35 net-_m35-pad1_ net-_m26-pad1_ /vss /vss mos_n W=20u L=5u M=4 +m36 net-_m35-pad1_ net-_m26-pad1_ /vdd /vdd mos_p W=40u L=5u M=8 +m39 /e1 net-_m35-pad1_ /vss /vss mos_n W=20u L=5u M=4 +m40 /e1 net-_m35-pad1_ /vdd /vdd mos_p W=40u L=5u M=8 +m1 net-_m1-pad1_ /a2 /vdd /vdd mos_p W=40u L=5u M=8 +m5 net-_m1-pad1_ /b2 /vdd /vdd mos_p W=40u L=5u M=8 +m6 net-_m1-pad1_ /a2 net-_m6-pad3_ /vss mos_n W=20u L=5u M=4 +m7 net-_m6-pad3_ /b2 /vss /vss mos_n W=20u L=5u M=4 +m2 net-_m19-pad2_ /c2 /vdd /vdd mos_p W=40u L=5u M=8 +m8 net-_m19-pad2_ /d2 /vdd /vdd mos_p W=40u L=5u M=8 +m9 net-_m19-pad2_ /c2 net-_m10-pad1_ /vss mos_n W=20u L=5u M=4 +m10 net-_m10-pad1_ /d2 /vss /vss mos_n W=20u L=5u M=4 +m17 net-_m17-pad1_ net-_m1-pad1_ /vdd /vdd mos_p W=40u L=5u M=8 +m19 net-_m17-pad1_ net-_m19-pad2_ /vdd /vdd mos_p W=40u L=5u M=8 +m20 net-_m17-pad1_ net-_m1-pad1_ net-_m20-pad3_ /vss mos_n W=20u L=5u M=4 +m21 net-_m20-pad3_ net-_m19-pad2_ /vss /vss mos_n W=20u L=5u M=4 +m28 net-_m28-pad1_ /inhibit2 /vdd /vdd mos_p W=40u L=5u M=8 +m29 net-_m25-pad1_ net-_m17-pad1_ net-_m28-pad1_ /vdd mos_p W=40u L=5u M=8 +m27 net-_m25-pad1_ net-_m17-pad1_ /vss /vss mos_n W=20u L=5u M=4 +m25 net-_m25-pad1_ /inhibit2 /vss /vss mos_n W=20u L=5u M=4 +m33 net-_m33-pad1_ net-_m25-pad1_ /vss /vss mos_n W=20u L=5u M=4 +m34 net-_m33-pad1_ net-_m25-pad1_ /vdd /vdd mos_p W=40u L=5u M=8 +m37 /e2 net-_m33-pad1_ /vss /vss mos_n W=20u L=5u M=4 +m38 /e2 net-_m33-pad1_ /vdd /vdd mos_p W=40u L=5u M=8 +* Control Statements + +.ends CD4085B \ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4085B/CD4085B_Previous_Values.xml b/library/SubcircuitLibrary/CD4085B/CD4085B_Previous_Values.xml new file mode 100644 index 000000000..c072b50bf --- /dev/null +++ b/library/SubcircuitLibrary/CD4085B/CD4085B_Previous_Values.xml @@ -0,0 +1 @@ +truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperessecsecsecC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.lib \ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4085B/NMOS-5um.lib b/library/SubcircuitLibrary/CD4085B/NMOS-5um.lib new file mode 100644 index 000000000..a237e1fe3 --- /dev/null +++ b/library/SubcircuitLibrary/CD4085B/NMOS-5um.lib @@ -0,0 +1,5 @@ +* 5um technology + +.model mos_n NMOS( Cgso=0.4n Tox=85n Vto=1 phi=0.7 ++ Level=1 ++ Mj=.5 UO=750 Cgdo=0.4n Gamma=1.4 LAMBDA=0.01 LD=0.7u JS=1u CJ=0.4m CJSW=0.8n MJSW=0.5 PB=0.7 CGBO=0.2n ) diff --git a/library/SubcircuitLibrary/CD4085B/PMOS-5um.lib b/library/SubcircuitLibrary/CD4085B/PMOS-5um.lib new file mode 100644 index 000000000..9c3ed9760 --- /dev/null +++ b/library/SubcircuitLibrary/CD4085B/PMOS-5um.lib @@ -0,0 +1,5 @@ +*5um technology + +.model mos_p PMOS( Cgso=0.4n Tox=85n Vto=-1 phi=0.65 ++ Level=1 ++ Mj=.5 UO=250 Cgdo=0.4n Gamma=0.65 LAMBDA=0.03 LD=0.6u JS=1u CJ=0.18m CJSW=0.6n MJSW=0.5 PB=0.7 CGBO=0.2n ) diff --git a/library/SubcircuitLibrary/CD4085B/analysis b/library/SubcircuitLibrary/CD4085B/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/SubcircuitLibrary/CD4085B/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/library/SubcircuitLibrary/CD74HC4050/CD74HC4050-cache.lib b/library/SubcircuitLibrary/CD74HC4050/CD74HC4050-cache.lib new file mode 100644 index 000000000..5c77f56cc --- /dev/null +++ b/library/SubcircuitLibrary/CD74HC4050/CD74HC4050-cache.lib @@ -0,0 +1,72 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_buffer +# +DEF d_buffer U 0 40 Y Y 1 F N +F0 "U" 0 -50 60 H V C CNN +F1 "d_buffer" 0 50 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 4 0 1 0 -300 200 -300 -200 450 0 -300 200 N +X IN 1 -500 0 200 R 50 50 1 1 I +X OUT 2 650 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/CD74HC4050/CD74HC4050.bak b/library/SubcircuitLibrary/CD74HC4050/CD74HC4050.bak new file mode 100644 index 000000000..4a38fca85 --- /dev/null +++ b/library/SubcircuitLibrary/CD74HC4050/CD74HC4050.bak @@ -0,0 +1,537 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:CD74HC4050-cache +EELAYER 25 0 +EELAYER END +$Descr A1 33110 23386 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_buffer U3 +U 1 1 685D658A +P 4250 2750 +F 0 "U3" H 4250 2700 60 0000 C CNN +F 1 "d_buffer" H 4250 2800 60 0000 C CNN +F 2 "" H 4250 2750 60 0000 C CNN +F 3 "" H 4250 2750 60 0000 C CNN + 1 4250 2750 + 1 0 0 -1 +$EndComp +$Comp +L d_buffer U9 +U 1 1 685D658B +P 7950 2750 +F 0 "U9" H 7950 2700 60 0000 C CNN +F 1 "d_buffer" H 7950 2800 60 0000 C CNN +F 2 "" H 7950 2750 60 0000 C CNN +F 3 "" H 7950 2750 60 0000 C CNN + 1 7950 2750 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U5 +U 1 1 685D658C +P 5550 2750 +F 0 "U5" H 5550 2650 60 0000 C CNN +F 1 "d_inverter" H 5550 2900 60 0000 C CNN +F 2 "" H 5600 2700 60 0000 C CNN +F 3 "" H 5600 2700 60 0000 C CNN + 1 5550 2750 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U6 +U 1 1 685D658D +P 6600 2750 +F 0 "U6" H 6600 2650 60 0000 C CNN +F 1 "d_inverter" H 6600 2900 60 0000 C CNN +F 2 "" H 6650 2700 60 0000 C CNN +F 3 "" H 6650 2700 60 0000 C CNN + 1 6600 2750 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5850 2750 6300 2750 +Wire Wire Line + 6900 2750 7450 2750 +Wire Wire Line + 8600 2750 9200 2750 +Wire Wire Line + 4900 2750 5250 2750 +Wire Wire Line + 1500 2750 3750 2750 +$Comp +L PORT U1 +U 3 1 685D658E +P 1250 2750 +F 0 "U1" H 1300 2850 30 0000 C CNN +F 1 "PORT" H 1250 2750 30 0000 C CNN +F 2 "" H 1250 2750 60 0000 C CNN +F 3 "" H 1250 2750 60 0000 C CNN + 3 1250 2750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 685D658F +P 9450 2750 +F 0 "U1" H 9500 2850 30 0000 C CNN +F 1 "PORT" H 9450 2750 30 0000 C CNN +F 2 "" H 9450 2750 60 0000 C CNN +F 3 "" H 9450 2750 60 0000 C CNN + 2 9450 2750 + -1 0 0 1 +$EndComp +Text Label 2000 2750 0 60 ~ 0 +A1 +Text Label 9050 2750 0 60 ~ 0 +Y1 +$Comp +L d_buffer U8 +U 1 1 685D720A +P 6700 4500 +F 0 "U8" H 6700 4450 60 0000 C CNN +F 1 "d_buffer" H 6700 4550 60 0000 C CNN +F 2 "" H 6700 4500 60 0000 C CNN +F 3 "" H 6700 4500 60 0000 C CNN + 1 6700 4500 + 1 0 0 -1 +$EndComp +$Comp +L d_buffer U17 +U 1 1 685D7210 +P 10400 4500 +F 0 "U17" H 10400 4450 60 0000 C CNN +F 1 "d_buffer" H 10400 4550 60 0000 C CNN +F 2 "" H 10400 4500 60 0000 C CNN +F 3 "" H 10400 4500 60 0000 C CNN + 1 10400 4500 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U10 +U 1 1 685D7216 +P 8000 4500 +F 0 "U10" H 8000 4400 60 0000 C CNN +F 1 "d_inverter" H 8000 4650 60 0000 C CNN +F 2 "" H 8050 4450 60 0000 C CNN +F 3 "" H 8050 4450 60 0000 C CNN + 1 8000 4500 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U12 +U 1 1 685D721C +P 9050 4500 +F 0 "U12" H 9050 4400 60 0000 C CNN +F 1 "d_inverter" H 9050 4650 60 0000 C CNN +F 2 "" H 9100 4450 60 0000 C CNN +F 3 "" H 9100 4450 60 0000 C CNN + 1 9050 4500 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8300 4500 8750 4500 +Wire Wire Line + 9350 4500 9900 4500 +Wire Wire Line + 11050 4500 11650 4500 +Wire Wire Line + 7350 4500 7700 4500 +Wire Wire Line + 5100 4500 6200 4500 +$Comp +L PORT U1 +U 5 1 685D7227 +P 4850 4500 +F 0 "U1" H 4900 4600 30 0000 C CNN +F 1 "PORT" H 4850 4500 30 0000 C CNN +F 2 "" H 4850 4500 60 0000 C CNN +F 3 "" H 4850 4500 60 0000 C CNN + 5 4850 4500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 685D722D +P 11900 4500 +F 0 "U1" H 11950 4600 30 0000 C CNN +F 1 "PORT" H 11900 4500 30 0000 C CNN +F 2 "" H 11900 4500 60 0000 C CNN +F 3 "" H 11900 4500 60 0000 C CNN + 4 11900 4500 + -1 0 0 1 +$EndComp +Text Label 11500 4500 0 60 ~ 0 +2Y +$Comp +L d_buffer U11 +U 1 1 685D7573 +P 8000 6850 +F 0 "U11" H 8000 6800 60 0000 C CNN +F 1 "d_buffer" H 8000 6900 60 0000 C CNN +F 2 "" H 8000 6850 60 0000 C CNN +F 3 "" H 8000 6850 60 0000 C CNN + 1 8000 6850 + 1 0 0 -1 +$EndComp +$Comp +L d_buffer U19 +U 1 1 685D7579 +P 11700 6850 +F 0 "U19" H 11700 6800 60 0000 C CNN +F 1 "d_buffer" H 11700 6900 60 0000 C CNN +F 2 "" H 11700 6850 60 0000 C CNN +F 3 "" H 11700 6850 60 0000 C CNN + 1 11700 6850 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U15 +U 1 1 685D757F +P 9300 6850 +F 0 "U15" H 9300 6750 60 0000 C CNN +F 1 "d_inverter" H 9300 7000 60 0000 C CNN +F 2 "" H 9350 6800 60 0000 C CNN +F 3 "" H 9350 6800 60 0000 C CNN + 1 9300 6850 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U16 +U 1 1 685D7585 +P 10350 6850 +F 0 "U16" H 10350 6750 60 0000 C CNN +F 1 "d_inverter" H 10350 7000 60 0000 C CNN +F 2 "" H 10400 6800 60 0000 C CNN +F 3 "" H 10400 6800 60 0000 C CNN + 1 10350 6850 + 1 0 0 -1 +$EndComp +Wire Wire Line + 9600 6850 10050 6850 +Wire Wire Line + 10650 6850 11200 6850 +Wire Wire Line + 12350 6850 12950 6850 +Wire Wire Line + 8650 6850 9000 6850 +Wire Wire Line + 6400 6850 7500 6850 +$Comp +L PORT U1 +U 7 1 685D7590 +P 6150 6850 +F 0 "U1" H 6200 6950 30 0000 C CNN +F 1 "PORT" H 6150 6850 30 0000 C CNN +F 2 "" H 6150 6850 60 0000 C CNN +F 3 "" H 6150 6850 60 0000 C CNN + 7 6150 6850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 685D7596 +P 13200 6850 +F 0 "U1" H 13250 6950 30 0000 C CNN +F 1 "PORT" H 13200 6850 30 0000 C CNN +F 2 "" H 13200 6850 60 0000 C CNN +F 3 "" H 13200 6850 60 0000 C CNN + 6 13200 6850 + -1 0 0 1 +$EndComp +Text Label 6950 6850 0 60 ~ 0 +3A +Text Label 12800 6850 0 60 ~ 0 +3Y +$Comp +L d_buffer U18 +U 1 1 685D75AC +P 10450 8600 +F 0 "U18" H 10450 8550 60 0000 C CNN +F 1 "d_buffer" H 10450 8650 60 0000 C CNN +F 2 "" H 10450 8600 60 0000 C CNN +F 3 "" H 10450 8600 60 0000 C CNN + 1 10450 8600 + 1 0 0 -1 +$EndComp +$Comp +L d_buffer U25 +U 1 1 685D75B2 +P 14150 8600 +F 0 "U25" H 14150 8550 60 0000 C CNN +F 1 "d_buffer" H 14150 8650 60 0000 C CNN +F 2 "" H 14150 8600 60 0000 C CNN +F 3 "" H 14150 8600 60 0000 C CNN + 1 14150 8600 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U21 +U 1 1 685D75B8 +P 11750 8600 +F 0 "U21" H 11750 8500 60 0000 C CNN +F 1 "d_inverter" H 11750 8750 60 0000 C CNN +F 2 "" H 11800 8550 60 0000 C CNN +F 3 "" H 11800 8550 60 0000 C CNN + 1 11750 8600 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U22 +U 1 1 685D75BE +P 12800 8600 +F 0 "U22" H 12800 8500 60 0000 C CNN +F 1 "d_inverter" H 12800 8750 60 0000 C CNN +F 2 "" H 12850 8550 60 0000 C CNN +F 3 "" H 12850 8550 60 0000 C CNN + 1 12800 8600 + 1 0 0 -1 +$EndComp +Wire Wire Line + 12050 8600 12500 8600 +Wire Wire Line + 13100 8600 13650 8600 +Wire Wire Line + 14800 8600 15400 8600 +Wire Wire Line + 11100 8600 11450 8600 +Wire Wire Line + 8850 8600 9950 8600 +$Comp +L PORT U1 +U 9 1 685D75C9 +P 8600 8600 +F 0 "U1" H 8650 8700 30 0000 C CNN +F 1 "PORT" H 8600 8600 30 0000 C CNN +F 2 "" H 8600 8600 60 0000 C CNN +F 3 "" H 8600 8600 60 0000 C CNN + 9 8600 8600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 685D75CF +P 15650 8600 +F 0 "U1" H 15700 8700 30 0000 C CNN +F 1 "PORT" H 15650 8600 30 0000 C CNN +F 2 "" H 15650 8600 60 0000 C CNN +F 3 "" H 15650 8600 60 0000 C CNN + 10 15650 8600 + -1 0 0 1 +$EndComp +Text Label 9350 8600 0 60 ~ 0 +4A +Text Label 15250 8600 0 60 ~ 0 +4Y +$Comp +L d_buffer U26 +U 1 1 685D7925 +P 14450 10600 +F 0 "U26" H 14450 10550 60 0000 C CNN +F 1 "d_buffer" H 14450 10650 60 0000 C CNN +F 2 "" H 14450 10600 60 0000 C CNN +F 3 "" H 14450 10600 60 0000 C CNN + 1 14450 10600 + 1 0 0 -1 +$EndComp +$Comp +L d_buffer U32 +U 1 1 685D792B +P 18150 10600 +F 0 "U32" H 18150 10550 60 0000 C CNN +F 1 "d_buffer" H 18150 10650 60 0000 C CNN +F 2 "" H 18150 10600 60 0000 C CNN +F 3 "" H 18150 10600 60 0000 C CNN + 1 18150 10600 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U29 +U 1 1 685D7931 +P 15750 10600 +F 0 "U29" H 15750 10500 60 0000 C CNN +F 1 "d_inverter" H 15750 10750 60 0000 C CNN +F 2 "" H 15800 10550 60 0000 C CNN +F 3 "" H 15800 10550 60 0000 C CNN + 1 15750 10600 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U30 +U 1 1 685D7937 +P 16800 10600 +F 0 "U30" H 16800 10500 60 0000 C CNN +F 1 "d_inverter" H 16800 10750 60 0000 C CNN +F 2 "" H 16850 10550 60 0000 C CNN +F 3 "" H 16850 10550 60 0000 C CNN + 1 16800 10600 + 1 0 0 -1 +$EndComp +Wire Wire Line + 16050 10600 16500 10600 +Wire Wire Line + 17100 10600 17650 10600 +Wire Wire Line + 18800 10600 19400 10600 +Wire Wire Line + 15100 10600 15450 10600 +Wire Wire Line + 12850 10600 13950 10600 +$Comp +L PORT U1 +U 11 1 685D7942 +P 12600 10600 +F 0 "U1" H 12650 10700 30 0000 C CNN +F 1 "PORT" H 12600 10600 30 0000 C CNN +F 2 "" H 12600 10600 60 0000 C CNN +F 3 "" H 12600 10600 60 0000 C CNN + 11 12600 10600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 685D7948 +P 19650 10600 +F 0 "U1" H 19700 10700 30 0000 C CNN +F 1 "PORT" H 19650 10600 30 0000 C CNN +F 2 "" H 19650 10600 60 0000 C CNN +F 3 "" H 19650 10600 60 0000 C CNN + 12 19650 10600 + -1 0 0 1 +$EndComp +Text Label 13350 10600 0 60 ~ 0 +5A +Text Label 19250 10600 0 60 ~ 0 +5Y +$Comp +L d_buffer U31 +U 1 1 685D795E +P 16900 12350 +F 0 "U31" H 16900 12300 60 0000 C CNN +F 1 "d_buffer" H 16900 12400 60 0000 C CNN +F 2 "" H 16900 12350 60 0000 C CNN +F 3 "" H 16900 12350 60 0000 C CNN + 1 16900 12350 + 1 0 0 -1 +$EndComp +$Comp +L d_buffer U36 +U 1 1 685D7964 +P 20600 12350 +F 0 "U36" H 20600 12300 60 0000 C CNN +F 1 "d_buffer" H 20600 12400 60 0000 C CNN +F 2 "" H 20600 12350 60 0000 C CNN +F 3 "" H 20600 12350 60 0000 C CNN + 1 20600 12350 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U33 +U 1 1 685D796A +P 18200 12350 +F 0 "U33" H 18200 12250 60 0000 C CNN +F 1 "d_inverter" H 18200 12500 60 0000 C CNN +F 2 "" H 18250 12300 60 0000 C CNN +F 3 "" H 18250 12300 60 0000 C CNN + 1 18200 12350 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U34 +U 1 1 685D7970 +P 19250 12350 +F 0 "U34" H 19250 12250 60 0000 C CNN +F 1 "d_inverter" H 19250 12500 60 0000 C CNN +F 2 "" H 19300 12300 60 0000 C CNN +F 3 "" H 19300 12300 60 0000 C CNN + 1 19250 12350 + 1 0 0 -1 +$EndComp +Wire Wire Line + 18500 12350 18950 12350 +Wire Wire Line + 19550 12350 20100 12350 +Wire Wire Line + 21250 12350 21850 12350 +Wire Wire Line + 17550 12350 17900 12350 +Wire Wire Line + 15300 12350 16400 12350 +$Comp +L PORT U1 +U 14 1 685D797B +P 15050 12350 +F 0 "U1" H 15100 12450 30 0000 C CNN +F 1 "PORT" H 15050 12350 30 0000 C CNN +F 2 "" H 15050 12350 60 0000 C CNN +F 3 "" H 15050 12350 60 0000 C CNN + 14 15050 12350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 15 1 685D7981 +P 22100 12350 +F 0 "U1" H 22150 12450 30 0000 C CNN +F 1 "PORT" H 22100 12350 30 0000 C CNN +F 2 "" H 22100 12350 60 0000 C CNN +F 3 "" H 22100 12350 60 0000 C CNN + 15 22100 12350 + -1 0 0 1 +$EndComp +Text Label 15800 12350 0 60 ~ 0 +6A +Text Label 21700 12350 0 60 ~ 0 +6Y +Text Label 5600 4500 0 60 ~ 0 +2A +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/CD74HC4050/CD74HC4050.cir b/library/SubcircuitLibrary/CD74HC4050/CD74HC4050.cir new file mode 100644 index 000000000..e8541409d --- /dev/null +++ b/library/SubcircuitLibrary/CD74HC4050/CD74HC4050.cir @@ -0,0 +1,35 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\CD74HC4050\CD74HC4050.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/27/25 16:18:46 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U3 /A1 Net-_U3-Pad2_ d_buffer +U9 Net-_U6-Pad2_ /Y1 d_buffer +U5 Net-_U3-Pad2_ Net-_U5-Pad2_ d_inverter +U6 Net-_U5-Pad2_ Net-_U6-Pad2_ d_inverter +U1 /Y1 /A1 /2Y /2A /3Y /3A /4A /4Y /5A /5Y /6A /6Y PORT +U8 /2A Net-_U10-Pad1_ d_buffer +U17 Net-_U12-Pad2_ /2Y d_buffer +U10 Net-_U10-Pad1_ Net-_U10-Pad2_ d_inverter +U12 Net-_U10-Pad2_ Net-_U12-Pad2_ d_inverter +U11 /3A Net-_U11-Pad2_ d_buffer +U19 Net-_U16-Pad2_ /3Y d_buffer +U15 Net-_U11-Pad2_ Net-_U15-Pad2_ d_inverter +U16 Net-_U15-Pad2_ Net-_U16-Pad2_ d_inverter +U18 /4A Net-_U18-Pad2_ d_buffer +U25 Net-_U22-Pad2_ /4Y d_buffer +U21 Net-_U18-Pad2_ Net-_U21-Pad2_ d_inverter +U22 Net-_U21-Pad2_ Net-_U22-Pad2_ d_inverter +U26 /5A Net-_U26-Pad2_ d_buffer +U32 Net-_U30-Pad2_ /5Y d_buffer +U29 Net-_U26-Pad2_ Net-_U29-Pad2_ d_inverter +U30 Net-_U29-Pad2_ Net-_U30-Pad2_ d_inverter +U31 /6A Net-_U31-Pad2_ d_buffer +U36 Net-_U34-Pad2_ /6Y d_buffer +U33 Net-_U31-Pad2_ Net-_U33-Pad2_ d_inverter +U34 Net-_U33-Pad2_ Net-_U34-Pad2_ d_inverter + +.end diff --git a/library/SubcircuitLibrary/CD74HC4050/CD74HC4050.cir.out b/library/SubcircuitLibrary/CD74HC4050/CD74HC4050.cir.out new file mode 100644 index 000000000..dcab5954f --- /dev/null +++ b/library/SubcircuitLibrary/CD74HC4050/CD74HC4050.cir.out @@ -0,0 +1,108 @@ +* c:\fossee\esim\library\subcircuitlibrary\cd74hc4050\cd74hc4050.cir + +* u3 /a1 net-_u3-pad2_ d_buffer +* u9 net-_u6-pad2_ /y1 d_buffer +* u5 net-_u3-pad2_ net-_u5-pad2_ d_inverter +* u6 net-_u5-pad2_ net-_u6-pad2_ d_inverter +* u1 /y1 /a1 /2y /2a /3y /3a /4a /4y /5a /5y /6a /6y port +* u8 /2a net-_u10-pad1_ d_buffer +* u17 net-_u12-pad2_ /2y d_buffer +* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter +* u12 net-_u10-pad2_ net-_u12-pad2_ d_inverter +* u11 /3a net-_u11-pad2_ d_buffer +* u19 net-_u16-pad2_ /3y d_buffer +* u15 net-_u11-pad2_ net-_u15-pad2_ d_inverter +* u16 net-_u15-pad2_ net-_u16-pad2_ d_inverter +* u18 /4a net-_u18-pad2_ d_buffer +* u25 net-_u22-pad2_ /4y d_buffer +* u21 net-_u18-pad2_ net-_u21-pad2_ d_inverter +* u22 net-_u21-pad2_ net-_u22-pad2_ d_inverter +* u26 /5a net-_u26-pad2_ d_buffer +* u32 net-_u30-pad2_ /5y d_buffer +* u29 net-_u26-pad2_ net-_u29-pad2_ d_inverter +* u30 net-_u29-pad2_ net-_u30-pad2_ d_inverter +* u31 /6a net-_u31-pad2_ d_buffer +* u36 net-_u34-pad2_ /6y d_buffer +* u33 net-_u31-pad2_ net-_u33-pad2_ d_inverter +* u34 net-_u33-pad2_ net-_u34-pad2_ d_inverter +a1 /a1 net-_u3-pad2_ u3 +a2 net-_u6-pad2_ /y1 u9 +a3 net-_u3-pad2_ net-_u5-pad2_ u5 +a4 net-_u5-pad2_ net-_u6-pad2_ u6 +a5 /2a net-_u10-pad1_ u8 +a6 net-_u12-pad2_ /2y u17 +a7 net-_u10-pad1_ net-_u10-pad2_ u10 +a8 net-_u10-pad2_ net-_u12-pad2_ u12 +a9 /3a net-_u11-pad2_ u11 +a10 net-_u16-pad2_ /3y u19 +a11 net-_u11-pad2_ net-_u15-pad2_ u15 +a12 net-_u15-pad2_ net-_u16-pad2_ u16 +a13 /4a net-_u18-pad2_ u18 +a14 net-_u22-pad2_ /4y u25 +a15 net-_u18-pad2_ net-_u21-pad2_ u21 +a16 net-_u21-pad2_ net-_u22-pad2_ u22 +a17 /5a net-_u26-pad2_ u26 +a18 net-_u30-pad2_ /5y u32 +a19 net-_u26-pad2_ net-_u29-pad2_ u29 +a20 net-_u29-pad2_ net-_u30-pad2_ u30 +a21 /6a net-_u31-pad2_ u31 +a22 net-_u34-pad2_ /6y u36 +a23 net-_u31-pad2_ net-_u33-pad2_ u33 +a24 net-_u33-pad2_ net-_u34-pad2_ u34 +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u3 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u9 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u8 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u17 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u11 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u19 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u18 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u25 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u22 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u26 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u32 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u29 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u30 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u31 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u36 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u33 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u34 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/CD74HC4050/CD74HC4050.pro b/library/SubcircuitLibrary/CD74HC4050/CD74HC4050.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/CD74HC4050/CD74HC4050.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/CD74HC4050/CD74HC4050.sch b/library/SubcircuitLibrary/CD74HC4050/CD74HC4050.sch new file mode 100644 index 000000000..6c8d82654 --- /dev/null +++ b/library/SubcircuitLibrary/CD74HC4050/CD74HC4050.sch @@ -0,0 +1,537 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:CD74HC4050-cache +EELAYER 25 0 +EELAYER END +$Descr A2 23386 16535 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_buffer U3 +U 1 1 685D658A +P 4250 2750 +F 0 "U3" H 4250 2700 60 0000 C CNN +F 1 "d_buffer" H 4250 2800 60 0000 C CNN +F 2 "" H 4250 2750 60 0000 C CNN +F 3 "" H 4250 2750 60 0000 C CNN + 1 4250 2750 + 1 0 0 -1 +$EndComp +$Comp +L d_buffer U9 +U 1 1 685D658B +P 7950 2750 +F 0 "U9" H 7950 2700 60 0000 C CNN +F 1 "d_buffer" H 7950 2800 60 0000 C CNN +F 2 "" H 7950 2750 60 0000 C CNN +F 3 "" H 7950 2750 60 0000 C CNN + 1 7950 2750 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U5 +U 1 1 685D658C +P 5550 2750 +F 0 "U5" H 5550 2650 60 0000 C CNN +F 1 "d_inverter" H 5550 2900 60 0000 C CNN +F 2 "" H 5600 2700 60 0000 C CNN +F 3 "" H 5600 2700 60 0000 C CNN + 1 5550 2750 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U6 +U 1 1 685D658D +P 6600 2750 +F 0 "U6" H 6600 2650 60 0000 C CNN +F 1 "d_inverter" H 6600 2900 60 0000 C CNN +F 2 "" H 6650 2700 60 0000 C CNN +F 3 "" H 6650 2700 60 0000 C CNN + 1 6600 2750 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5850 2750 6300 2750 +Wire Wire Line + 6900 2750 7450 2750 +Wire Wire Line + 8600 2750 9200 2750 +Wire Wire Line + 4900 2750 5250 2750 +Wire Wire Line + 1500 2750 3750 2750 +$Comp +L PORT U1 +U 3 1 685D658E +P 1250 2750 +F 0 "U1" H 1300 2850 30 0000 C CNN +F 1 "PORT" H 1250 2750 30 0000 C CNN +F 2 "" H 1250 2750 60 0000 C CNN +F 3 "" H 1250 2750 60 0000 C CNN + 3 1250 2750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 685D658F +P 9450 2750 +F 0 "U1" H 9500 2850 30 0000 C CNN +F 1 "PORT" H 9450 2750 30 0000 C CNN +F 2 "" H 9450 2750 60 0000 C CNN +F 3 "" H 9450 2750 60 0000 C CNN + 2 9450 2750 + -1 0 0 1 +$EndComp +Text Label 2000 2750 0 60 ~ 0 +A1 +Text Label 9050 2750 0 60 ~ 0 +Y1 +$Comp +L d_buffer U8 +U 1 1 685D720A +P 6700 4500 +F 0 "U8" H 6700 4450 60 0000 C CNN +F 1 "d_buffer" H 6700 4550 60 0000 C CNN +F 2 "" H 6700 4500 60 0000 C CNN +F 3 "" H 6700 4500 60 0000 C CNN + 1 6700 4500 + 1 0 0 -1 +$EndComp +$Comp +L d_buffer U17 +U 1 1 685D7210 +P 10400 4500 +F 0 "U17" H 10400 4450 60 0000 C CNN +F 1 "d_buffer" H 10400 4550 60 0000 C CNN +F 2 "" H 10400 4500 60 0000 C CNN +F 3 "" H 10400 4500 60 0000 C CNN + 1 10400 4500 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U10 +U 1 1 685D7216 +P 8000 4500 +F 0 "U10" H 8000 4400 60 0000 C CNN +F 1 "d_inverter" H 8000 4650 60 0000 C CNN +F 2 "" H 8050 4450 60 0000 C CNN +F 3 "" H 8050 4450 60 0000 C CNN + 1 8000 4500 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U12 +U 1 1 685D721C +P 9050 4500 +F 0 "U12" H 9050 4400 60 0000 C CNN +F 1 "d_inverter" H 9050 4650 60 0000 C CNN +F 2 "" H 9100 4450 60 0000 C CNN +F 3 "" H 9100 4450 60 0000 C CNN + 1 9050 4500 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8300 4500 8750 4500 +Wire Wire Line + 9350 4500 9900 4500 +Wire Wire Line + 11050 4500 11650 4500 +Wire Wire Line + 7350 4500 7700 4500 +Wire Wire Line + 5100 4500 6200 4500 +$Comp +L PORT U1 +U 5 1 685D7227 +P 4850 4500 +F 0 "U1" H 4900 4600 30 0000 C CNN +F 1 "PORT" H 4850 4500 30 0000 C CNN +F 2 "" H 4850 4500 60 0000 C CNN +F 3 "" H 4850 4500 60 0000 C CNN + 5 4850 4500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 685D722D +P 11900 4500 +F 0 "U1" H 11950 4600 30 0000 C CNN +F 1 "PORT" H 11900 4500 30 0000 C CNN +F 2 "" H 11900 4500 60 0000 C CNN +F 3 "" H 11900 4500 60 0000 C CNN + 4 11900 4500 + -1 0 0 1 +$EndComp +Text Label 11500 4500 0 60 ~ 0 +2Y +$Comp +L d_buffer U11 +U 1 1 685D7573 +P 8000 6850 +F 0 "U11" H 8000 6800 60 0000 C CNN +F 1 "d_buffer" H 8000 6900 60 0000 C CNN +F 2 "" H 8000 6850 60 0000 C CNN +F 3 "" H 8000 6850 60 0000 C CNN + 1 8000 6850 + 1 0 0 -1 +$EndComp +$Comp +L d_buffer U19 +U 1 1 685D7579 +P 11700 6850 +F 0 "U19" H 11700 6800 60 0000 C CNN +F 1 "d_buffer" H 11700 6900 60 0000 C CNN +F 2 "" H 11700 6850 60 0000 C CNN +F 3 "" H 11700 6850 60 0000 C CNN + 1 11700 6850 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U15 +U 1 1 685D757F +P 9300 6850 +F 0 "U15" H 9300 6750 60 0000 C CNN +F 1 "d_inverter" H 9300 7000 60 0000 C CNN +F 2 "" H 9350 6800 60 0000 C CNN +F 3 "" H 9350 6800 60 0000 C CNN + 1 9300 6850 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U16 +U 1 1 685D7585 +P 10350 6850 +F 0 "U16" H 10350 6750 60 0000 C CNN +F 1 "d_inverter" H 10350 7000 60 0000 C CNN +F 2 "" H 10400 6800 60 0000 C CNN +F 3 "" H 10400 6800 60 0000 C CNN + 1 10350 6850 + 1 0 0 -1 +$EndComp +Wire Wire Line + 9600 6850 10050 6850 +Wire Wire Line + 10650 6850 11200 6850 +Wire Wire Line + 12350 6850 12950 6850 +Wire Wire Line + 8650 6850 9000 6850 +Wire Wire Line + 6400 6850 7500 6850 +$Comp +L PORT U1 +U 7 1 685D7590 +P 6150 6850 +F 0 "U1" H 6200 6950 30 0000 C CNN +F 1 "PORT" H 6150 6850 30 0000 C CNN +F 2 "" H 6150 6850 60 0000 C CNN +F 3 "" H 6150 6850 60 0000 C CNN + 7 6150 6850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 685D7596 +P 13200 6850 +F 0 "U1" H 13250 6950 30 0000 C CNN +F 1 "PORT" H 13200 6850 30 0000 C CNN +F 2 "" H 13200 6850 60 0000 C CNN +F 3 "" H 13200 6850 60 0000 C CNN + 6 13200 6850 + -1 0 0 1 +$EndComp +Text Label 6950 6850 0 60 ~ 0 +3A +Text Label 12800 6850 0 60 ~ 0 +3Y +$Comp +L d_buffer U18 +U 1 1 685D75AC +P 10450 8600 +F 0 "U18" H 10450 8550 60 0000 C CNN +F 1 "d_buffer" H 10450 8650 60 0000 C CNN +F 2 "" H 10450 8600 60 0000 C CNN +F 3 "" H 10450 8600 60 0000 C CNN + 1 10450 8600 + 1 0 0 -1 +$EndComp +$Comp +L d_buffer U25 +U 1 1 685D75B2 +P 14150 8600 +F 0 "U25" H 14150 8550 60 0000 C CNN +F 1 "d_buffer" H 14150 8650 60 0000 C CNN +F 2 "" H 14150 8600 60 0000 C CNN +F 3 "" H 14150 8600 60 0000 C CNN + 1 14150 8600 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U21 +U 1 1 685D75B8 +P 11750 8600 +F 0 "U21" H 11750 8500 60 0000 C CNN +F 1 "d_inverter" H 11750 8750 60 0000 C CNN +F 2 "" H 11800 8550 60 0000 C CNN +F 3 "" H 11800 8550 60 0000 C CNN + 1 11750 8600 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U22 +U 1 1 685D75BE +P 12800 8600 +F 0 "U22" H 12800 8500 60 0000 C CNN +F 1 "d_inverter" H 12800 8750 60 0000 C CNN +F 2 "" H 12850 8550 60 0000 C CNN +F 3 "" H 12850 8550 60 0000 C CNN + 1 12800 8600 + 1 0 0 -1 +$EndComp +Wire Wire Line + 12050 8600 12500 8600 +Wire Wire Line + 13100 8600 13650 8600 +Wire Wire Line + 14800 8600 15400 8600 +Wire Wire Line + 11100 8600 11450 8600 +Wire Wire Line + 8850 8600 9950 8600 +$Comp +L PORT U1 +U 9 1 685D75C9 +P 8600 8600 +F 0 "U1" H 8650 8700 30 0000 C CNN +F 1 "PORT" H 8600 8600 30 0000 C CNN +F 2 "" H 8600 8600 60 0000 C CNN +F 3 "" H 8600 8600 60 0000 C CNN + 9 8600 8600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 685D75CF +P 15650 8600 +F 0 "U1" H 15700 8700 30 0000 C CNN +F 1 "PORT" H 15650 8600 30 0000 C CNN +F 2 "" H 15650 8600 60 0000 C CNN +F 3 "" H 15650 8600 60 0000 C CNN + 10 15650 8600 + -1 0 0 1 +$EndComp +Text Label 9350 8600 0 60 ~ 0 +4A +Text Label 15250 8600 0 60 ~ 0 +4Y +$Comp +L d_buffer U26 +U 1 1 685D7925 +P 14450 10600 +F 0 "U26" H 14450 10550 60 0000 C CNN +F 1 "d_buffer" H 14450 10650 60 0000 C CNN +F 2 "" H 14450 10600 60 0000 C CNN +F 3 "" H 14450 10600 60 0000 C CNN + 1 14450 10600 + 1 0 0 -1 +$EndComp +$Comp +L d_buffer U32 +U 1 1 685D792B +P 18150 10600 +F 0 "U32" H 18150 10550 60 0000 C CNN +F 1 "d_buffer" H 18150 10650 60 0000 C CNN +F 2 "" H 18150 10600 60 0000 C CNN +F 3 "" H 18150 10600 60 0000 C CNN + 1 18150 10600 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U29 +U 1 1 685D7931 +P 15750 10600 +F 0 "U29" H 15750 10500 60 0000 C CNN +F 1 "d_inverter" H 15750 10750 60 0000 C CNN +F 2 "" H 15800 10550 60 0000 C CNN +F 3 "" H 15800 10550 60 0000 C CNN + 1 15750 10600 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U30 +U 1 1 685D7937 +P 16800 10600 +F 0 "U30" H 16800 10500 60 0000 C CNN +F 1 "d_inverter" H 16800 10750 60 0000 C CNN +F 2 "" H 16850 10550 60 0000 C CNN +F 3 "" H 16850 10550 60 0000 C CNN + 1 16800 10600 + 1 0 0 -1 +$EndComp +Wire Wire Line + 16050 10600 16500 10600 +Wire Wire Line + 17100 10600 17650 10600 +Wire Wire Line + 18800 10600 19400 10600 +Wire Wire Line + 15100 10600 15450 10600 +Wire Wire Line + 12850 10600 13950 10600 +$Comp +L PORT U1 +U 11 1 685D7942 +P 12600 10600 +F 0 "U1" H 12650 10700 30 0000 C CNN +F 1 "PORT" H 12600 10600 30 0000 C CNN +F 2 "" H 12600 10600 60 0000 C CNN +F 3 "" H 12600 10600 60 0000 C CNN + 11 12600 10600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 685D7948 +P 19650 10600 +F 0 "U1" H 19700 10700 30 0000 C CNN +F 1 "PORT" H 19650 10600 30 0000 C CNN +F 2 "" H 19650 10600 60 0000 C CNN +F 3 "" H 19650 10600 60 0000 C CNN + 12 19650 10600 + -1 0 0 1 +$EndComp +Text Label 13350 10600 0 60 ~ 0 +5A +Text Label 19250 10600 0 60 ~ 0 +5Y +$Comp +L d_buffer U31 +U 1 1 685D795E +P 16900 12350 +F 0 "U31" H 16900 12300 60 0000 C CNN +F 1 "d_buffer" H 16900 12400 60 0000 C CNN +F 2 "" H 16900 12350 60 0000 C CNN +F 3 "" H 16900 12350 60 0000 C CNN + 1 16900 12350 + 1 0 0 -1 +$EndComp +$Comp +L d_buffer U36 +U 1 1 685D7964 +P 20600 12350 +F 0 "U36" H 20600 12300 60 0000 C CNN +F 1 "d_buffer" H 20600 12400 60 0000 C CNN +F 2 "" H 20600 12350 60 0000 C CNN +F 3 "" H 20600 12350 60 0000 C CNN + 1 20600 12350 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U33 +U 1 1 685D796A +P 18200 12350 +F 0 "U33" H 18200 12250 60 0000 C CNN +F 1 "d_inverter" H 18200 12500 60 0000 C CNN +F 2 "" H 18250 12300 60 0000 C CNN +F 3 "" H 18250 12300 60 0000 C CNN + 1 18200 12350 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U34 +U 1 1 685D7970 +P 19250 12350 +F 0 "U34" H 19250 12250 60 0000 C CNN +F 1 "d_inverter" H 19250 12500 60 0000 C CNN +F 2 "" H 19300 12300 60 0000 C CNN +F 3 "" H 19300 12300 60 0000 C CNN + 1 19250 12350 + 1 0 0 -1 +$EndComp +Wire Wire Line + 18500 12350 18950 12350 +Wire Wire Line + 19550 12350 20100 12350 +Wire Wire Line + 21250 12350 21850 12350 +Wire Wire Line + 17550 12350 17900 12350 +Wire Wire Line + 15300 12350 16400 12350 +$Comp +L PORT U1 +U 14 1 685D797B +P 15050 12350 +F 0 "U1" H 15100 12450 30 0000 C CNN +F 1 "PORT" H 15050 12350 30 0000 C CNN +F 2 "" H 15050 12350 60 0000 C CNN +F 3 "" H 15050 12350 60 0000 C CNN + 14 15050 12350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 15 1 685D7981 +P 22100 12350 +F 0 "U1" H 22150 12450 30 0000 C CNN +F 1 "PORT" H 22100 12350 30 0000 C CNN +F 2 "" H 22100 12350 60 0000 C CNN +F 3 "" H 22100 12350 60 0000 C CNN + 15 22100 12350 + -1 0 0 1 +$EndComp +Text Label 15800 12350 0 60 ~ 0 +6A +Text Label 21700 12350 0 60 ~ 0 +6Y +Text Label 5600 4500 0 60 ~ 0 +2A +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/CD74HC4050/CD74HC4050.sub b/library/SubcircuitLibrary/CD74HC4050/CD74HC4050.sub new file mode 100644 index 000000000..421154d93 --- /dev/null +++ b/library/SubcircuitLibrary/CD74HC4050/CD74HC4050.sub @@ -0,0 +1,102 @@ +* Subcircuit CD74HC4050 +.subckt CD74HC4050 /y1 /a1 /2y /2a /3y /3a /4a /4y /5a /5y /6a /6y +* c:\fossee\esim\library\subcircuitlibrary\cd74hc4050\cd74hc4050.cir +* u3 /a1 net-_u3-pad2_ d_buffer +* u9 net-_u6-pad2_ /y1 d_buffer +* u5 net-_u3-pad2_ net-_u5-pad2_ d_inverter +* u6 net-_u5-pad2_ net-_u6-pad2_ d_inverter +* u8 /2a net-_u10-pad1_ d_buffer +* u17 net-_u12-pad2_ /2y d_buffer +* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter +* u12 net-_u10-pad2_ net-_u12-pad2_ d_inverter +* u11 /3a net-_u11-pad2_ d_buffer +* u19 net-_u16-pad2_ /3y d_buffer +* u15 net-_u11-pad2_ net-_u15-pad2_ d_inverter +* u16 net-_u15-pad2_ net-_u16-pad2_ d_inverter +* u18 /4a net-_u18-pad2_ d_buffer +* u25 net-_u22-pad2_ /4y d_buffer +* u21 net-_u18-pad2_ net-_u21-pad2_ d_inverter +* u22 net-_u21-pad2_ net-_u22-pad2_ d_inverter +* u26 /5a net-_u26-pad2_ d_buffer +* u32 net-_u30-pad2_ /5y d_buffer +* u29 net-_u26-pad2_ net-_u29-pad2_ d_inverter +* u30 net-_u29-pad2_ net-_u30-pad2_ d_inverter +* u31 /6a net-_u31-pad2_ d_buffer +* u36 net-_u34-pad2_ /6y d_buffer +* u33 net-_u31-pad2_ net-_u33-pad2_ d_inverter +* u34 net-_u33-pad2_ net-_u34-pad2_ d_inverter +a1 /a1 net-_u3-pad2_ u3 +a2 net-_u6-pad2_ /y1 u9 +a3 net-_u3-pad2_ net-_u5-pad2_ u5 +a4 net-_u5-pad2_ net-_u6-pad2_ u6 +a5 /2a net-_u10-pad1_ u8 +a6 net-_u12-pad2_ /2y u17 +a7 net-_u10-pad1_ net-_u10-pad2_ u10 +a8 net-_u10-pad2_ net-_u12-pad2_ u12 +a9 /3a net-_u11-pad2_ u11 +a10 net-_u16-pad2_ /3y u19 +a11 net-_u11-pad2_ net-_u15-pad2_ u15 +a12 net-_u15-pad2_ net-_u16-pad2_ u16 +a13 /4a net-_u18-pad2_ u18 +a14 net-_u22-pad2_ /4y u25 +a15 net-_u18-pad2_ net-_u21-pad2_ u21 +a16 net-_u21-pad2_ net-_u22-pad2_ u22 +a17 /5a net-_u26-pad2_ u26 +a18 net-_u30-pad2_ /5y u32 +a19 net-_u26-pad2_ net-_u29-pad2_ u29 +a20 net-_u29-pad2_ net-_u30-pad2_ u30 +a21 /6a net-_u31-pad2_ u31 +a22 net-_u34-pad2_ /6y u36 +a23 net-_u31-pad2_ net-_u33-pad2_ u33 +a24 net-_u33-pad2_ net-_u34-pad2_ u34 +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u3 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u9 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u8 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u17 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u11 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u19 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u18 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u25 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u22 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u26 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u32 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u29 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u30 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u31 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u36 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u33 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u34 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends CD74HC4050 \ No newline at end of file diff --git a/library/SubcircuitLibrary/CD74HC4050/CD74HC4050_Previous_Values.xml b/library/SubcircuitLibrary/CD74HC4050/CD74HC4050_Previous_Values.xml new file mode 100644 index 000000000..5a2aa2f5c --- /dev/null +++ b/library/SubcircuitLibrary/CD74HC4050/CD74HC4050_Previous_Values.xml @@ -0,0 +1 @@ +dc5d_bufferd_bufferd_inverterd_inverteradc_bridgedac_bridged_bufferd_bufferd_inverterd_inverteradc_bridgedac_bridged_bufferd_bufferd_inverterd_inverteradc_bridgedac_bridged_bufferd_bufferd_inverterd_inverteradc_bridgedac_bridged_bufferd_bufferd_inverterd_inverteradc_bridgedac_bridged_bufferd_bufferd_inverterd_inverteradc_bridgedac_bridgetruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec \ No newline at end of file diff --git a/library/SubcircuitLibrary/CD74HC4050/analysis b/library/SubcircuitLibrary/CD74HC4050/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/SubcircuitLibrary/CD74HC4050/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/library/SubcircuitLibrary/DSR_LATCH/3_and-cache.lib b/library/SubcircuitLibrary/DSR_LATCH/3_and-cache.lib new file mode 100644 index 000000000..0a3ccf7f9 --- /dev/null +++ b/library/SubcircuitLibrary/DSR_LATCH/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/DSR_LATCH/3_and.cir b/library/SubcircuitLibrary/DSR_LATCH/3_and.cir new file mode 100644 index 000000000..15f8954df --- /dev/null +++ b/library/SubcircuitLibrary/DSR_LATCH/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/library/SubcircuitLibrary/DSR_LATCH/3_and.cir.out b/library/SubcircuitLibrary/DSR_LATCH/3_and.cir.out new file mode 100644 index 000000000..e3c966454 --- /dev/null +++ b/library/SubcircuitLibrary/DSR_LATCH/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/DSR_LATCH/3_and.pro b/library/SubcircuitLibrary/DSR_LATCH/3_and.pro new file mode 100644 index 000000000..a4cdec482 --- /dev/null +++ b/library/SubcircuitLibrary/DSR_LATCH/3_and.pro @@ -0,0 +1,43 @@ +update=05/31/19 15:26:09 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_User +LibName9=eSim_Sources +LibName10=eSim_Subckt diff --git a/library/SubcircuitLibrary/DSR_LATCH/3_and.sch b/library/SubcircuitLibrary/DSR_LATCH/3_and.sch new file mode 100644 index 000000000..c853bf49d --- /dev/null +++ b/library/SubcircuitLibrary/DSR_LATCH/3_and.sch @@ -0,0 +1,130 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:3_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +Text Notes 3500 2600 0 60 ~ 12 +in1 +Text Notes 3450 2800 0 60 ~ 12 +in2\n +Text Notes 3500 3100 0 60 ~ 12 +in3 +Text Notes 6100 2850 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/DSR_LATCH/3_and.sub b/library/SubcircuitLibrary/DSR_LATCH/3_and.sub new file mode 100644 index 000000000..b949ae4fb --- /dev/null +++ b/library/SubcircuitLibrary/DSR_LATCH/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and \ No newline at end of file diff --git a/library/SubcircuitLibrary/DSR_LATCH/3_and_Previous_Values.xml b/library/SubcircuitLibrary/DSR_LATCH/3_and_Previous_Values.xml new file mode 100644 index 000000000..abc5faaae --- /dev/null +++ b/library/SubcircuitLibrary/DSR_LATCH/3_and_Previous_Values.xml @@ -0,0 +1 @@ +d_andd_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/library/SubcircuitLibrary/DSR_LATCH/DSR_LATCH-cache.lib b/library/SubcircuitLibrary/DSR_LATCH/DSR_LATCH-cache.lib new file mode 100644 index 000000000..c7697d09b --- /dev/null +++ b/library/SubcircuitLibrary/DSR_LATCH/DSR_LATCH-cache.lib @@ -0,0 +1,143 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 100 -50 60 H V C CNN +F1 "3_and" 150 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 150 50 158 716 -716 0 1 0 N 200 200 200 -100 +P 2 0 1 0 -150 200 200 200 N +P 3 0 1 0 -150 200 -150 -100 200 -100 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X out 4 500 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_buffer +# +DEF d_buffer U 0 40 Y Y 1 F N +F0 "U" 0 -50 60 H V C CNN +F1 "d_buffer" 0 50 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 4 0 1 0 -300 200 -300 -200 450 0 -300 200 N +X IN 1 -500 0 200 R 50 50 1 1 I +X OUT 2 650 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nand +# +DEF d_nand U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nand" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nor +# +DEF d_nor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nor" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/DSR_LATCH/DSR_LATCH.bak b/library/SubcircuitLibrary/DSR_LATCH/DSR_LATCH.bak new file mode 100644 index 000000000..a586761a6 --- /dev/null +++ b/library/SubcircuitLibrary/DSR_LATCH/DSR_LATCH.bak @@ -0,0 +1,1143 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:DSR_LATCH-cache +EELAYER 25 0 +EELAYER END +$Descr A0 46811 33110 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_buffer U3 +U 1 1 68501ACE +P 7800 12400 +F 0 "U3" H 7800 12350 60 0000 C CNN +F 1 "d_buffer" H 7800 12450 60 0000 C CNN +F 2 "" H 7800 12400 60 0000 C CNN +F 3 "" H 7800 12400 60 0000 C CNN + 1 7800 12400 + 0 1 1 0 +$EndComp +$Comp +L d_buffer U5 +U 1 1 68501B69 +P 9350 12350 +F 0 "U5" H 9350 12300 60 0000 C CNN +F 1 "d_buffer" H 9350 12400 60 0000 C CNN +F 2 "" H 9350 12350 60 0000 C CNN +F 3 "" H 9350 12350 60 0000 C CNN + 1 9350 12350 + 0 1 1 0 +$EndComp +$Comp +L d_buffer U7 +U 1 1 68501BAA +P 10800 12350 +F 0 "U7" H 10800 12300 60 0000 C CNN +F 1 "d_buffer" H 10800 12400 60 0000 C CNN +F 2 "" H 10800 12350 60 0000 C CNN +F 3 "" H 10800 12350 60 0000 C CNN + 1 10800 12350 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U2 +U 1 1 68501C0D +P 7800 11300 +F 0 "U2" H 7800 11200 60 0000 C CNN +F 1 "d_inverter" H 7800 11450 60 0000 C CNN +F 2 "" H 7850 11250 60 0000 C CNN +F 3 "" H 7850 11250 60 0000 C CNN + 1 7800 11300 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U4 +U 1 1 68501C84 +P 9350 11300 +F 0 "U4" H 9350 11200 60 0000 C CNN +F 1 "d_inverter" H 9350 11450 60 0000 C CNN +F 2 "" H 9400 11250 60 0000 C CNN +F 3 "" H 9400 11250 60 0000 C CNN + 1 9350 11300 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U6 +U 1 1 68501CD1 +P 10800 11250 +F 0 "U6" H 10800 11150 60 0000 C CNN +F 1 "d_inverter" H 10800 11400 60 0000 C CNN +F 2 "" H 10850 11200 60 0000 C CNN +F 3 "" H 10850 11200 60 0000 C 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68655617 +P 19750 10000 +F 0 "U1" H 19800 10100 30 0000 C CNN +F 1 "PORT" H 19750 10000 30 0000 C CNN +F 2 "" H 19750 10000 60 0000 C CNN +F 3 "" H 19750 10000 60 0000 C CNN + 14 19750 10000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 6865561D +P 21000 11300 +F 0 "U1" H 21050 11400 30 0000 C CNN +F 1 "PORT" H 21000 11300 30 0000 C CNN +F 2 "" H 21000 11300 60 0000 C CNN +F 3 "" H 21000 11300 60 0000 C CNN + 4 21000 11300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 68655623 +P 20850 20250 +F 0 "U1" H 20900 20350 30 0000 C CNN +F 1 "PORT" H 20850 20250 30 0000 C CNN +F 2 "" H 20850 20250 60 0000 C CNN +F 3 "" H 20850 20250 60 0000 C CNN + 13 20850 20250 + 1 0 0 -1 +$EndComp +$Comp +L d_buffer U35 +U 1 1 686567BD +P 28150 12400 +F 0 "U35" H 28150 12350 60 0000 C CNN +F 1 "d_buffer" H 28150 12450 60 0000 C CNN +F 2 "" H 28150 12400 60 0000 C CNN +F 3 "" H 28150 12400 60 0000 C CNN + 1 28150 12400 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U34 +U 1 1 686567CF +P 28150 11300 +F 0 "U34" H 28150 11200 60 0000 C CNN +F 1 "d_inverter" H 28150 11450 60 0000 C CNN +F 2 "" H 28200 11250 60 0000 C CNN +F 3 "" H 28200 11250 60 0000 C CNN + 1 28150 11300 + 0 1 1 0 +$EndComp +Wire Wire Line + 28150 11900 28150 11600 +$Comp +L 3_and X3 +U 1 1 686567D8 +P 28100 14000 +F 0 "X3" H 28200 13950 60 0000 C CNN +F 1 "3_and" H 28250 14150 60 0000 C CNN +F 2 "" H 28100 14000 60 0000 C CNN +F 3 "" H 28100 14000 60 0000 C CNN + 1 28100 14000 + 0 1 1 0 +$EndComp +Wire Wire Line + 28150 13050 28150 13650 +Wire Wire Line + 28250 13650 28250 13400 +Wire Wire Line + 26700 13400 28650 13400 +Wire Wire Line + 26700 8200 26700 13400 +$Comp +L d_and U40 +U 1 1 686567E3 +P 29350 14100 +F 0 "U40" H 29350 14100 60 0000 C CNN +F 1 "d_and" H 29400 14200 60 0000 C CNN +F 2 "" H 29350 14100 60 0000 C CNN +F 3 "" H 29350 14100 60 0000 C CNN + 1 29350 14100 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U42 +U 1 1 686567E9 +P 30800 13100 +F 0 "U42" H 30800 13000 60 0000 C CNN +F 1 "d_inverter" H 30800 13250 60 0000 C CNN +F 2 "" H 30850 13050 60 0000 C CNN +F 3 "" H 30850 13050 60 0000 C CNN + 1 30800 13100 + 0 1 1 0 +$EndComp +Wire Wire Line + 30800 13750 30800 13400 +Wire Wire Line + 30900 13750 30900 13500 +Wire Wire Line + 29450 13500 31300 13500 +Wire Wire Line + 29450 13500 29450 13650 +Wire Wire Line + 29350 11700 29350 13650 +Wire Wire Line + 28050 13650 28050 13500 +Wire Wire Line + 28050 13500 29350 13500 +Connection ~ 29350 13500 +Wire Wire Line + 30800 12800 30800 12650 +Wire Wire Line + 30800 12650 28650 12650 +Wire Wire Line + 28650 12650 28650 13400 +Connection ~ 28250 13400 +$Comp +L d_nor U37 +U 1 1 686567FD +P 28750 15550 +F 0 "U37" H 28750 15550 60 0000 C CNN +F 1 "d_nor" H 28800 15650 60 0000 C CNN +F 2 "" H 28750 15550 60 0000 C CNN +F 3 "" H 28750 15550 60 0000 C CNN + 1 28750 15550 + 0 1 1 0 +$EndComp +Wire Wire Line + 28850 15100 29400 15100 +Wire Wire Line + 29400 15100 29400 14550 +Wire Wire Line + 28750 15100 28150 15100 +Wire Wire Line + 28150 15100 28150 14500 +$Comp +L d_and U39 +U 1 1 68656807 +P 29300 16900 +F 0 "U39" H 29300 16900 60 0000 C CNN +F 1 "d_and" H 29350 17000 60 0000 C CNN +F 2 "" H 29300 16900 60 0000 C CNN +F 3 "" H 29300 16900 60 0000 C CNN + 1 29300 16900 + 0 1 1 0 +$EndComp +Wire Wire Line + 28800 16000 28800 16350 +Wire Wire Line + 28800 16350 29300 16350 +Wire Wire Line + 29300 16350 29300 16450 +Wire Wire Line + 29400 16450 29400 16350 +Wire Wire Line + 29400 16350 30850 16350 +Wire Wire Line + 30850 16350 30850 14650 +$Comp +L d_nand U43 +U 1 1 68656813 +P 30800 14200 +F 0 "U43" H 30800 14200 60 0000 C CNN +F 1 "d_nand" H 30850 14300 60 0000 C CNN +F 2 "" H 30800 14200 60 0000 C CNN +F 3 "" H 30800 14200 60 0000 C CNN + 1 30800 14200 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U36 +U 1 1 68656819 +P 28550 17950 +F 0 "U36" H 28550 17850 60 0000 C CNN +F 1 "d_inverter" H 28550 18100 60 0000 C CNN +F 2 "" H 28600 17900 60 0000 C CNN +F 3 "" H 28600 17900 60 0000 C CNN + 1 28550 17950 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U41 +U 1 1 6865681F +P 29750 17950 +F 0 "U41" H 29750 17850 60 0000 C CNN +F 1 "d_inverter" H 29750 18100 60 0000 C CNN +F 2 "" H 29800 17900 60 0000 C CNN +F 3 "" H 29800 17900 60 0000 C CNN + 1 29750 17950 + 0 1 1 0 +$EndComp +Wire Wire Line + 28550 17650 29350 17650 +Wire Wire Line + 29350 17650 29350 17350 +Wire Wire Line + 29750 17650 29600 17650 +Wire Wire Line + 29600 17650 29600 17450 +Wire Wire Line + 29600 17450 25150 17450 +Wire Wire Line + 25150 17450 25150 9200 +$Comp +L d_and U38 +U 1 1 6865682B +P 29150 19550 +F 0 "U38" H 29150 19550 60 0000 C CNN +F 1 "d_and" H 29200 19650 60 0000 C CNN +F 2 "" H 29150 19550 60 0000 C CNN +F 3 "" H 29150 19550 60 0000 C CNN + 1 29150 19550 + 0 1 1 0 +$EndComp +Wire Wire Line + 28550 18250 28550 18750 +Wire Wire Line + 28550 18750 29150 18750 +Wire Wire Line + 29150 18750 29150 19100 +Wire Wire Line + 29750 18250 29750 18750 +Wire Wire Line + 29750 18750 29250 18750 +Wire Wire Line + 29250 18750 29250 19100 +Wire Wire Line + 29200 20000 29200 20650 +Wire Wire Line + 29200 20300 31300 20300 +Wire Wire Line + 31300 20300 31300 13500 +Connection ~ 30900 13500 +Connection ~ 29200 20300 +Wire Wire Line + 28150 11000 28150 10400 +Wire Wire Line + 28150 10400 28100 10400 +$Comp +L PORT U1 +U 5 1 6865684D +P 27850 10400 +F 0 "U1" H 27900 10500 30 0000 C CNN +F 1 "PORT" H 27850 10400 30 0000 C CNN +F 2 "" H 27850 10400 60 0000 C CNN +F 3 "" H 27850 10400 60 0000 C CNN + 5 27850 10400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 68656853 +P 29100 11700 +F 0 "U1" H 29150 11800 30 0000 C CNN +F 1 "PORT" H 29100 11700 30 0000 C CNN +F 2 "" H 29100 11700 60 0000 C CNN +F 3 "" H 29100 11700 60 0000 C CNN + 6 29100 11700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 68656859 +P 28950 20650 +F 0 "U1" H 29000 20750 30 0000 C CNN +F 1 "PORT" H 28950 20650 30 0000 C CNN +F 2 "" H 28950 20650 60 0000 C CNN +F 3 "" H 28950 20650 60 0000 C CNN + 12 28950 20650 + 1 0 0 -1 +$EndComp +$Comp +L d_buffer U49 +U 1 1 6865686B +P 37400 12050 +F 0 "U49" H 37400 12000 60 0000 C CNN +F 1 "d_buffer" H 37400 12100 60 0000 C CNN +F 2 "" H 37400 12050 60 0000 C CNN +F 3 "" H 37400 12050 60 0000 C CNN + 1 37400 12050 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U48 +U 1 1 6865687D +P 37400 10950 +F 0 "U48" H 37400 10850 60 0000 C CNN +F 1 "d_inverter" H 37400 11100 60 0000 C CNN +F 2 "" H 37450 10900 60 0000 C CNN +F 3 "" H 37450 10900 60 0000 C CNN + 1 37400 10950 + 0 1 1 0 +$EndComp +Wire Wire Line + 37400 11550 37400 11250 +$Comp +L 3_and X4 +U 1 1 68656886 +P 37350 13650 +F 0 "X4" H 37450 13600 60 0000 C CNN +F 1 "3_and" H 37500 13800 60 0000 C CNN +F 2 "" H 37350 13650 60 0000 C CNN +F 3 "" H 37350 13650 60 0000 C CNN + 1 37350 13650 + 0 1 1 0 +$EndComp +Wire Wire Line + 37400 12700 37400 13300 +Wire Wire Line + 37500 13300 37500 13050 +Wire Wire Line + 35950 13050 37900 13050 +Wire Wire Line + 35950 8200 35950 13050 +$Comp +L d_and U54 +U 1 1 68656891 +P 38600 13750 +F 0 "U54" H 38600 13750 60 0000 C CNN +F 1 "d_and" H 38650 13850 60 0000 C CNN +F 2 "" H 38600 13750 60 0000 C CNN +F 3 "" H 38600 13750 60 0000 C CNN + 1 38600 13750 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U56 +U 1 1 68656897 +P 40050 12750 +F 0 "U56" H 40050 12650 60 0000 C CNN +F 1 "d_inverter" H 40050 12900 60 0000 C CNN +F 2 "" H 40100 12700 60 0000 C CNN +F 3 "" H 40100 12700 60 0000 C CNN + 1 40050 12750 + 0 1 1 0 +$EndComp +Wire Wire Line + 40050 13400 40050 13050 +Wire Wire Line + 40150 13400 40150 13150 +Wire Wire Line + 38700 13150 40550 13150 +Wire Wire Line + 38700 13150 38700 13300 +Wire Wire Line + 38600 11350 38600 13300 +Wire Wire Line + 37300 13300 37300 13150 +Wire Wire Line + 37300 13150 38600 13150 +Connection ~ 38600 13150 +Wire Wire Line + 40050 12450 40050 12300 +Wire Wire Line + 40050 12300 37900 12300 +Wire Wire Line + 37900 12300 37900 13050 +Connection ~ 37500 13050 +$Comp +L d_nor U51 +U 1 1 686568AB +P 38000 15200 +F 0 "U51" H 38000 15200 60 0000 C CNN +F 1 "d_nor" H 38050 15300 60 0000 C CNN +F 2 "" H 38000 15200 60 0000 C CNN +F 3 "" H 38000 15200 60 0000 C CNN + 1 38000 15200 + 0 1 1 0 +$EndComp +Wire Wire Line + 38100 14750 38650 14750 +Wire Wire Line + 38650 14750 38650 14200 +Wire Wire Line + 38000 14750 37400 14750 +Wire Wire Line + 37400 14750 37400 14150 +$Comp +L d_and U53 +U 1 1 686568B5 +P 38550 16550 +F 0 "U53" H 38550 16550 60 0000 C CNN +F 1 "d_and" H 38600 16650 60 0000 C CNN +F 2 "" H 38550 16550 60 0000 C CNN +F 3 "" H 38550 16550 60 0000 C CNN + 1 38550 16550 + 0 1 1 0 +$EndComp +Wire Wire Line + 38050 15650 38050 16000 +Wire Wire Line + 38050 16000 38550 16000 +Wire Wire Line + 38550 16000 38550 16100 +Wire Wire Line + 38650 16100 38650 16000 +Wire Wire Line + 38650 16000 40100 16000 +Wire Wire Line + 40100 16000 40100 14300 +$Comp +L d_nand U57 +U 1 1 686568C1 +P 40050 13850 +F 0 "U57" H 40050 13850 60 0000 C CNN +F 1 "d_nand" H 40100 13950 60 0000 C CNN +F 2 "" H 40050 13850 60 0000 C CNN +F 3 "" H 40050 13850 60 0000 C CNN + 1 40050 13850 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U50 +U 1 1 686568C7 +P 37800 17600 +F 0 "U50" H 37800 17500 60 0000 C CNN +F 1 "d_inverter" H 37800 17750 60 0000 C CNN +F 2 "" H 37850 17550 60 0000 C CNN +F 3 "" H 37850 17550 60 0000 C CNN + 1 37800 17600 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U55 +U 1 1 686568CD +P 39000 17600 +F 0 "U55" H 39000 17500 60 0000 C CNN +F 1 "d_inverter" H 39000 17750 60 0000 C CNN +F 2 "" H 39050 17550 60 0000 C CNN +F 3 "" H 39050 17550 60 0000 C CNN + 1 39000 17600 + 0 1 1 0 +$EndComp +Wire Wire Line + 37800 17300 38600 17300 +Wire Wire Line + 38600 17300 38600 17000 +Wire Wire Line + 39000 17300 38850 17300 +Wire Wire Line + 38850 17300 38850 17100 +Wire Wire Line + 38850 17100 34400 17100 +Wire Wire Line + 34400 17100 34400 9200 +$Comp +L d_and U52 +U 1 1 686568D9 +P 38400 19200 +F 0 "U52" H 38400 19200 60 0000 C CNN +F 1 "d_and" H 38450 19300 60 0000 C CNN +F 2 "" H 38400 19200 60 0000 C CNN +F 3 "" H 38400 19200 60 0000 C CNN + 1 38400 19200 + 0 1 1 0 +$EndComp +Wire Wire Line + 37800 17900 37800 18400 +Wire Wire Line + 37800 18400 38400 18400 +Wire Wire Line + 38400 18400 38400 18750 +Wire Wire Line + 39000 17900 39000 18400 +Wire Wire Line + 39000 18400 38500 18400 +Wire Wire Line + 38500 18400 38500 18750 +Wire Wire Line + 38450 19650 38450 20300 +Wire Wire Line + 38450 19950 40550 19950 +Wire Wire Line + 40550 19950 40550 13150 +Connection ~ 40150 13150 +Connection ~ 38450 19950 +Wire Wire Line + 37400 10650 37400 10050 +Wire Wire Line + 37400 10050 37350 10050 +$Comp +L PORT U1 +U 11 1 686568FB +P 37100 10050 +F 0 "U1" H 37150 10150 30 0000 C CNN +F 1 "PORT" H 37100 10050 30 0000 C CNN +F 2 "" H 37100 10050 60 0000 C CNN +F 3 "" H 37100 10050 60 0000 C CNN + 11 37100 10050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 68656901 +P 38350 11350 +F 0 "U1" H 38400 11450 30 0000 C CNN +F 1 "PORT" H 38350 11350 30 0000 C CNN +F 2 "" H 38350 11350 60 0000 C CNN +F 3 "" H 38350 11350 60 0000 C CNN + 7 38350 11350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 68656907 +P 38200 20300 +F 0 "U1" H 38250 20400 30 0000 C CNN +F 1 "PORT" H 38200 20300 30 0000 C CNN +F 2 "" H 38200 20300 60 0000 C CNN +F 3 "" H 38200 20300 60 0000 C CNN + 10 38200 20300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 34400 9200 8650 9200 +Connection ~ 25150 9200 +Wire Wire Line + 8650 9200 8650 14200 +Connection ~ 17050 9200 +Wire Wire Line + 16200 8200 35950 8200 +Connection ~ 26700 8200 +Wire Wire Line + 16200 12600 16200 8200 +Connection ~ 18600 8200 +Connection ~ 13450 12600 +Text Label 7800 10700 0 60 ~ 0 +MR_Bar +Text Label 9350 10650 0 60 ~ 0 +E_Bar +Text Label 10800 10600 0 60 ~ 0 +S0_Bar +Text Label 12000 11800 0 60 ~ 0 +D0 +Text Label 20050 10150 0 60 ~ 0 +S1_Bar +Text Label 21250 11500 0 60 ~ 0 +D1 +Text Label 28150 10600 0 60 ~ 0 +S2_Bar +Text Label 29350 12000 0 60 ~ 0 +D2 +Text Label 38600 11650 0 60 ~ 0 +D3 +Text Label 37400 10250 0 60 ~ 0 +S3_Bar +Text Label 11850 20450 0 60 ~ 0 +Q0 +Text Label 21100 20100 0 60 ~ 0 +Q1 +Text Label 29200 20500 0 60 ~ 0 +Q2 +Text Label 38450 20100 0 60 ~ 0 +Q3 +Wire Wire Line + 8650 14200 7800 14200 +Connection ~ 7800 14200 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/DSR_LATCH/DSR_LATCH.cir b/library/SubcircuitLibrary/DSR_LATCH/DSR_LATCH.cir new file mode 100644 index 000000000..300b515e4 --- /dev/null +++ b/library/SubcircuitLibrary/DSR_LATCH/DSR_LATCH.cir @@ -0,0 +1,59 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\DSR_LATCH\DSR_LATCH.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 07/04/25 20:03:14 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U3 Net-_U2-Pad2_ Net-_U13-Pad1_ d_buffer +U5 Net-_U4-Pad2_ Net-_U14-Pad1_ d_buffer +U7 Net-_U6-Pad2_ Net-_U7-Pad2_ d_buffer +U2 /MR_Bar Net-_U2-Pad2_ d_inverter +U4 /E_Bar Net-_U4-Pad2_ d_inverter +U6 /S0_Bar Net-_U6-Pad2_ d_inverter +X1 Net-_U14-Pad1_ Net-_U7-Pad2_ /D0 Net-_U9-Pad2_ 3_and +U12 /Q0 /D0 Net-_U12-Pad3_ d_and +U14 Net-_U14-Pad1_ Net-_U14-Pad2_ d_inverter +U9 Net-_U12-Pad3_ Net-_U9-Pad2_ Net-_U11-Pad2_ d_nor +U11 Net-_U11-Pad1_ Net-_U11-Pad2_ Net-_U11-Pad3_ d_and +U15 /Q0 Net-_U14-Pad2_ Net-_U11-Pad1_ d_nand +U8 Net-_U11-Pad3_ Net-_U10-Pad2_ d_inverter +U13 Net-_U13-Pad1_ Net-_U10-Pad1_ d_inverter +U10 Net-_U10-Pad1_ Net-_U10-Pad2_ /Q0 d_and +U1 /E_Bar /S0_Bar /D0 /D1 /S2_Bar /D2 /D3 /MR_Bar /Q3 /S3_Bar /Q2 /Q1 /S1_Bar /Q0 PORT +U21 Net-_U20-Pad2_ Net-_U21-Pad2_ d_buffer +U20 /S1_Bar Net-_U20-Pad2_ d_inverter +X2 Net-_U14-Pad1_ Net-_U21-Pad2_ /D1 Net-_U23-Pad2_ 3_and +U26 /Q1 /D1 Net-_U23-Pad1_ d_and +U28 Net-_U14-Pad1_ Net-_U28-Pad2_ d_inverter +U23 Net-_U23-Pad1_ Net-_U23-Pad2_ Net-_U23-Pad3_ d_nor +U25 Net-_U25-Pad1_ Net-_U23-Pad3_ Net-_U22-Pad1_ d_and +U29 /Q1 Net-_U28-Pad2_ Net-_U25-Pad1_ d_nand +U22 Net-_U22-Pad1_ Net-_U22-Pad2_ d_inverter +U27 Net-_U13-Pad1_ Net-_U24-Pad1_ d_inverter +U24 Net-_U24-Pad1_ Net-_U22-Pad2_ /Q1 d_and +U35 Net-_U34-Pad2_ Net-_U35-Pad2_ d_buffer +U34 /S2_Bar Net-_U34-Pad2_ d_inverter +X3 Net-_U14-Pad1_ Net-_U35-Pad2_ /D2 Net-_U37-Pad2_ 3_and +U40 /Q2 /D2 Net-_U37-Pad1_ d_and +U42 Net-_U14-Pad1_ Net-_U42-Pad2_ d_inverter +U37 Net-_U37-Pad1_ Net-_U37-Pad2_ Net-_U37-Pad3_ d_nor +U39 Net-_U39-Pad1_ Net-_U37-Pad3_ Net-_U36-Pad1_ d_and +U43 /Q2 Net-_U42-Pad2_ Net-_U39-Pad1_ d_nand +U36 Net-_U36-Pad1_ Net-_U36-Pad2_ d_inverter +U41 Net-_U13-Pad1_ Net-_U38-Pad1_ d_inverter +U38 Net-_U38-Pad1_ Net-_U36-Pad2_ /Q2 d_and +U49 Net-_U48-Pad2_ Net-_U49-Pad2_ d_buffer +U48 /S3_Bar Net-_U48-Pad2_ d_inverter +X4 Net-_U14-Pad1_ Net-_U49-Pad2_ /D3 Net-_U51-Pad2_ 3_and +U54 /Q3 /D3 Net-_U51-Pad1_ d_and +U56 Net-_U14-Pad1_ Net-_U56-Pad2_ d_inverter +U51 Net-_U51-Pad1_ Net-_U51-Pad2_ Net-_U51-Pad3_ d_nor +U53 Net-_U53-Pad1_ Net-_U51-Pad3_ Net-_U50-Pad1_ d_and +U57 /Q3 Net-_U56-Pad2_ Net-_U53-Pad1_ d_nand +U50 Net-_U50-Pad1_ Net-_U50-Pad2_ d_inverter +U55 Net-_U13-Pad1_ Net-_U52-Pad1_ d_inverter +U52 Net-_U52-Pad1_ Net-_U50-Pad2_ /Q3 d_and + +.end diff --git a/library/SubcircuitLibrary/DSR_LATCH/DSR_LATCH.cir.out b/library/SubcircuitLibrary/DSR_LATCH/DSR_LATCH.cir.out new file mode 100644 index 000000000..ead328265 --- /dev/null +++ b/library/SubcircuitLibrary/DSR_LATCH/DSR_LATCH.cir.out @@ -0,0 +1,193 @@ +* c:\fossee\esim\library\subcircuitlibrary\dsr_latch\dsr_latch.cir + +.include 3_and.sub +* u3 net-_u2-pad2_ net-_u13-pad1_ d_buffer +* u5 net-_u4-pad2_ net-_u14-pad1_ d_buffer +* u7 net-_u6-pad2_ net-_u7-pad2_ d_buffer +* u2 /mr_bar net-_u2-pad2_ d_inverter +* u4 /e_bar net-_u4-pad2_ d_inverter +* u6 /s0_bar net-_u6-pad2_ d_inverter +x1 net-_u14-pad1_ net-_u7-pad2_ /d0 net-_u9-pad2_ 3_and +* u12 /q0 /d0 net-_u12-pad3_ d_and +* u14 net-_u14-pad1_ net-_u14-pad2_ d_inverter +* u9 net-_u12-pad3_ net-_u9-pad2_ net-_u11-pad2_ d_nor +* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_and +* u15 /q0 net-_u14-pad2_ net-_u11-pad1_ d_nand +* u8 net-_u11-pad3_ net-_u10-pad2_ d_inverter +* u13 net-_u13-pad1_ net-_u10-pad1_ d_inverter +* u10 net-_u10-pad1_ net-_u10-pad2_ /q0 d_and +* u1 /e_bar /s0_bar /d0 /d1 /s2_bar /d2 /d3 /mr_bar /q3 /s3_bar /q2 /q1 /s1_bar /q0 port +* u21 net-_u20-pad2_ net-_u21-pad2_ d_buffer +* u20 /s1_bar net-_u20-pad2_ d_inverter +x2 net-_u14-pad1_ net-_u21-pad2_ /d1 net-_u23-pad2_ 3_and +* u26 /q1 /d1 net-_u23-pad1_ d_and +* u28 net-_u14-pad1_ net-_u28-pad2_ d_inverter +* u23 net-_u23-pad1_ net-_u23-pad2_ net-_u23-pad3_ d_nor +* u25 net-_u25-pad1_ net-_u23-pad3_ net-_u22-pad1_ d_and +* u29 /q1 net-_u28-pad2_ net-_u25-pad1_ d_nand +* u22 net-_u22-pad1_ net-_u22-pad2_ d_inverter +* u27 net-_u13-pad1_ net-_u24-pad1_ d_inverter +* u24 net-_u24-pad1_ net-_u22-pad2_ /q1 d_and +* u35 net-_u34-pad2_ net-_u35-pad2_ d_buffer +* u34 /s2_bar net-_u34-pad2_ d_inverter +x3 net-_u14-pad1_ net-_u35-pad2_ /d2 net-_u37-pad2_ 3_and +* u40 /q2 /d2 net-_u37-pad1_ d_and +* u42 net-_u14-pad1_ net-_u42-pad2_ d_inverter +* u37 net-_u37-pad1_ net-_u37-pad2_ net-_u37-pad3_ d_nor +* u39 net-_u39-pad1_ net-_u37-pad3_ net-_u36-pad1_ d_and +* u43 /q2 net-_u42-pad2_ net-_u39-pad1_ d_nand +* u36 net-_u36-pad1_ net-_u36-pad2_ d_inverter +* u41 net-_u13-pad1_ net-_u38-pad1_ d_inverter +* u38 net-_u38-pad1_ net-_u36-pad2_ /q2 d_and +* u49 net-_u48-pad2_ net-_u49-pad2_ d_buffer +* u48 /s3_bar net-_u48-pad2_ d_inverter +x4 net-_u14-pad1_ net-_u49-pad2_ /d3 net-_u51-pad2_ 3_and +* u54 /q3 /d3 net-_u51-pad1_ d_and +* u56 net-_u14-pad1_ net-_u56-pad2_ d_inverter +* u51 net-_u51-pad1_ net-_u51-pad2_ net-_u51-pad3_ d_nor +* u53 net-_u53-pad1_ net-_u51-pad3_ net-_u50-pad1_ d_and +* u57 /q3 net-_u56-pad2_ net-_u53-pad1_ d_nand +* u50 net-_u50-pad1_ net-_u50-pad2_ d_inverter +* u55 net-_u13-pad1_ net-_u52-pad1_ d_inverter +* u52 net-_u52-pad1_ net-_u50-pad2_ /q3 d_and +a1 net-_u2-pad2_ net-_u13-pad1_ u3 +a2 net-_u4-pad2_ net-_u14-pad1_ u5 +a3 net-_u6-pad2_ net-_u7-pad2_ u7 +a4 /mr_bar net-_u2-pad2_ u2 +a5 /e_bar net-_u4-pad2_ u4 +a6 /s0_bar net-_u6-pad2_ u6 +a7 [/q0 /d0 ] net-_u12-pad3_ u12 +a8 net-_u14-pad1_ net-_u14-pad2_ u14 +a9 [net-_u12-pad3_ net-_u9-pad2_ ] net-_u11-pad2_ u9 +a10 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11 +a11 [/q0 net-_u14-pad2_ ] net-_u11-pad1_ u15 +a12 net-_u11-pad3_ net-_u10-pad2_ u8 +a13 net-_u13-pad1_ net-_u10-pad1_ u13 +a14 [net-_u10-pad1_ net-_u10-pad2_ ] /q0 u10 +a15 net-_u20-pad2_ net-_u21-pad2_ u21 +a16 /s1_bar net-_u20-pad2_ u20 +a17 [/q1 /d1 ] net-_u23-pad1_ u26 +a18 net-_u14-pad1_ net-_u28-pad2_ u28 +a19 [net-_u23-pad1_ net-_u23-pad2_ ] net-_u23-pad3_ u23 +a20 [net-_u25-pad1_ net-_u23-pad3_ ] net-_u22-pad1_ u25 +a21 [/q1 net-_u28-pad2_ ] net-_u25-pad1_ u29 +a22 net-_u22-pad1_ net-_u22-pad2_ u22 +a23 net-_u13-pad1_ net-_u24-pad1_ u27 +a24 [net-_u24-pad1_ net-_u22-pad2_ ] /q1 u24 +a25 net-_u34-pad2_ net-_u35-pad2_ u35 +a26 /s2_bar net-_u34-pad2_ u34 +a27 [/q2 /d2 ] net-_u37-pad1_ u40 +a28 net-_u14-pad1_ net-_u42-pad2_ u42 +a29 [net-_u37-pad1_ net-_u37-pad2_ ] net-_u37-pad3_ u37 +a30 [net-_u39-pad1_ net-_u37-pad3_ ] net-_u36-pad1_ u39 +a31 [/q2 net-_u42-pad2_ ] net-_u39-pad1_ u43 +a32 net-_u36-pad1_ net-_u36-pad2_ u36 +a33 net-_u13-pad1_ net-_u38-pad1_ u41 +a34 [net-_u38-pad1_ net-_u36-pad2_ ] /q2 u38 +a35 net-_u48-pad2_ net-_u49-pad2_ u49 +a36 /s3_bar net-_u48-pad2_ u48 +a37 [/q3 /d3 ] net-_u51-pad1_ u54 +a38 net-_u14-pad1_ net-_u56-pad2_ u56 +a39 [net-_u51-pad1_ net-_u51-pad2_ ] net-_u51-pad3_ u51 +a40 [net-_u53-pad1_ net-_u51-pad3_ ] net-_u50-pad1_ u53 +a41 [/q3 net-_u56-pad2_ ] net-_u53-pad1_ u57 +a42 net-_u50-pad1_ net-_u50-pad2_ u50 +a43 net-_u13-pad1_ net-_u52-pad1_ u55 +a44 [net-_u52-pad1_ net-_u50-pad2_ ] /q3 u52 +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u3 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u5 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u7 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u12 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u9 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u11 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u15 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u10 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u21 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u26 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u28 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u23 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u25 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u29 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u22 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u27 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u24 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u35 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u34 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u40 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u42 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u37 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u39 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u43 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u36 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u41 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u38 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u49 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u48 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u54 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u56 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u51 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u53 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u57 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u50 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u55 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u52 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/DSR_LATCH/DSR_LATCH.pro b/library/SubcircuitLibrary/DSR_LATCH/DSR_LATCH.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/DSR_LATCH/DSR_LATCH.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/DSR_LATCH/DSR_LATCH.sch b/library/SubcircuitLibrary/DSR_LATCH/DSR_LATCH.sch new file mode 100644 index 000000000..5ec94bedc --- /dev/null +++ b/library/SubcircuitLibrary/DSR_LATCH/DSR_LATCH.sch @@ -0,0 +1,1141 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:DSR_LATCH-cache +EELAYER 25 0 +EELAYER END +$Descr A0 46811 33110 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_buffer U3 +U 1 1 68501ACE +P 7800 12400 +F 0 "U3" H 7800 12350 60 0000 C CNN +F 1 "d_buffer" H 7800 12450 60 0000 C CNN +F 2 "" H 7800 12400 60 0000 C CNN +F 3 "" H 7800 12400 60 0000 C CNN + 1 7800 12400 + 0 1 1 0 +$EndComp +$Comp +L d_buffer U5 +U 1 1 68501B69 +P 9350 12350 +F 0 "U5" H 9350 12300 60 0000 C CNN +F 1 "d_buffer" H 9350 12400 60 0000 C CNN +F 2 "" H 9350 12350 60 0000 C CNN +F 3 "" H 9350 12350 60 0000 C CNN + 1 9350 12350 + 0 1 1 0 +$EndComp +$Comp +L d_buffer U7 +U 1 1 68501BAA +P 10800 12350 +F 0 "U7" H 10800 12300 60 0000 C CNN +F 1 "d_buffer" H 10800 12400 60 0000 C CNN +F 2 "" H 10800 12350 60 0000 C CNN +F 3 "" H 10800 12350 60 0000 C CNN + 1 10800 12350 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U2 +U 1 1 68501C0D +P 7800 11300 +F 0 "U2" H 7800 11200 60 0000 C CNN +F 1 "d_inverter" H 7800 11450 60 0000 C CNN +F 2 "" H 7850 11250 60 0000 C CNN +F 3 "" H 7850 11250 60 0000 C CNN + 1 7800 11300 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U4 +U 1 1 68501C84 +P 9350 11300 +F 0 "U4" H 9350 11200 60 0000 C CNN +F 1 "d_inverter" H 9350 11450 60 0000 C CNN +F 2 "" H 9400 11250 60 0000 C CNN +F 3 "" H 9400 11250 60 0000 C CNN + 1 9350 11300 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U6 +U 1 1 68501CD1 +P 10800 11250 +F 0 "U6" H 10800 11150 60 0000 C CNN +F 1 "d_inverter" H 10800 11400 60 0000 C CNN +F 2 "" H 10850 11200 60 0000 C CNN +F 3 "" H 10850 11200 60 0000 C CNN + 1 10800 11250 + 0 1 1 0 +$EndComp +$Comp +L 3_and X1 +U 1 1 68501E1D +P 10750 13950 +F 0 "X1" H 10850 13900 60 0000 C CNN +F 1 "3_and" H 10900 14100 60 0000 C CNN +F 2 "" H 10750 13950 60 0000 C CNN +F 3 "" H 10750 13950 60 0000 C CNN + 1 10750 13950 + 0 1 1 0 +$EndComp +$Comp +L d_and U12 +U 1 1 68501EA4 +P 12000 14050 +F 0 "U12" H 12000 14050 60 0000 C CNN +F 1 "d_and" H 12050 14150 60 0000 C CNN +F 2 "" H 12000 14050 60 0000 C CNN +F 3 "" H 12000 14050 60 0000 C CNN + 1 12000 14050 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U14 +U 1 1 68501EFD +P 13450 13050 +F 0 "U14" H 13450 12950 60 0000 C CNN +F 1 "d_inverter" H 13450 13200 60 0000 C CNN +F 2 "" H 13500 13000 60 0000 C CNN +F 3 "" H 13500 13000 60 0000 C CNN + 1 13450 13050 + 0 1 1 0 +$EndComp +$Comp +L d_nor U9 +U 1 1 685022FF +P 11400 15500 +F 0 "U9" H 11400 15500 60 0000 C CNN +F 1 "d_nor" H 11450 15600 60 0000 C CNN +F 2 "" H 11400 15500 60 0000 C CNN +F 3 "" H 11400 15500 60 0000 C CNN + 1 11400 15500 + 0 1 1 0 +$EndComp +$Comp +L d_and U11 +U 1 1 685023D7 +P 11950 16850 +F 0 "U11" H 11950 16850 60 0000 C CNN +F 1 "d_and" H 12000 16950 60 0000 C CNN +F 2 "" H 11950 16850 60 0000 C CNN +F 3 "" H 11950 16850 60 0000 C CNN + 1 11950 16850 + 0 1 1 0 +$EndComp +$Comp +L d_nand U15 +U 1 1 685025AA +P 13450 14150 +F 0 "U15" H 13450 14150 60 0000 C CNN +F 1 "d_nand" H 13500 14250 60 0000 C CNN +F 2 "" H 13450 14150 60 0000 C CNN +F 3 "" H 13450 14150 60 0000 C CNN + 1 13450 14150 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U8 +U 1 1 68502657 +P 11200 17900 +F 0 "U8" H 11200 17800 60 0000 C CNN +F 1 "d_inverter" H 11200 18050 60 0000 C CNN +F 2 "" H 11250 17850 60 0000 C CNN +F 3 "" H 11250 17850 60 0000 C CNN + 1 11200 17900 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U13 +U 1 1 685026C0 +P 12400 17900 +F 0 "U13" H 12400 17800 60 0000 C CNN +F 1 "d_inverter" H 12400 18050 60 0000 C CNN +F 2 "" H 12450 17850 60 0000 C CNN +F 3 "" H 12450 17850 60 0000 C CNN + 1 12400 17900 + 0 1 1 0 +$EndComp +$Comp +L d_and U10 +U 1 1 685029B5 +P 11800 19500 +F 0 "U10" H 11800 19500 60 0000 C CNN +F 1 "d_and" H 11850 19600 60 0000 C CNN +F 2 "" H 11800 19500 60 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b/library/SubcircuitLibrary/DSR_LATCH/DSR_LATCH.sub new file mode 100644 index 000000000..843dc5120 --- /dev/null +++ b/library/SubcircuitLibrary/DSR_LATCH/DSR_LATCH.sub @@ -0,0 +1,187 @@ +* Subcircuit DSR_LATCH +.subckt DSR_LATCH /e_bar /s0_bar /d0 /d1 /s2_bar /d2 /d3 /mr_bar /q3 /s3_bar /q2 /q1 /s1_bar /q0 +* c:\fossee\esim\library\subcircuitlibrary\dsr_latch\dsr_latch.cir +.include 3_and.sub +* u3 net-_u2-pad2_ net-_u13-pad1_ d_buffer +* u5 net-_u4-pad2_ net-_u14-pad1_ d_buffer +* u7 net-_u6-pad2_ net-_u7-pad2_ d_buffer +* u2 /mr_bar net-_u2-pad2_ d_inverter +* u4 /e_bar net-_u4-pad2_ d_inverter +* u6 /s0_bar net-_u6-pad2_ d_inverter +x1 net-_u14-pad1_ net-_u7-pad2_ /d0 net-_u9-pad2_ 3_and +* u12 /q0 /d0 net-_u12-pad3_ d_and +* u14 net-_u14-pad1_ net-_u14-pad2_ d_inverter +* u9 net-_u12-pad3_ net-_u9-pad2_ net-_u11-pad2_ d_nor +* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_and +* u15 /q0 net-_u14-pad2_ net-_u11-pad1_ d_nand +* u8 net-_u11-pad3_ net-_u10-pad2_ d_inverter +* u13 net-_u13-pad1_ net-_u10-pad1_ d_inverter +* u10 net-_u10-pad1_ net-_u10-pad2_ /q0 d_and +* u21 net-_u20-pad2_ net-_u21-pad2_ d_buffer +* u20 /s1_bar net-_u20-pad2_ d_inverter +x2 net-_u14-pad1_ net-_u21-pad2_ /d1 net-_u23-pad2_ 3_and +* u26 /q1 /d1 net-_u23-pad1_ d_and +* u28 net-_u14-pad1_ net-_u28-pad2_ d_inverter +* u23 net-_u23-pad1_ net-_u23-pad2_ net-_u23-pad3_ d_nor +* u25 net-_u25-pad1_ net-_u23-pad3_ net-_u22-pad1_ d_and +* u29 /q1 net-_u28-pad2_ net-_u25-pad1_ d_nand +* u22 net-_u22-pad1_ net-_u22-pad2_ d_inverter +* u27 net-_u13-pad1_ net-_u24-pad1_ d_inverter +* u24 net-_u24-pad1_ net-_u22-pad2_ /q1 d_and +* u35 net-_u34-pad2_ net-_u35-pad2_ d_buffer +* u34 /s2_bar net-_u34-pad2_ d_inverter +x3 net-_u14-pad1_ net-_u35-pad2_ /d2 net-_u37-pad2_ 3_and +* u40 /q2 /d2 net-_u37-pad1_ d_and +* u42 net-_u14-pad1_ net-_u42-pad2_ d_inverter +* u37 net-_u37-pad1_ net-_u37-pad2_ net-_u37-pad3_ d_nor +* u39 net-_u39-pad1_ net-_u37-pad3_ net-_u36-pad1_ d_and +* u43 /q2 net-_u42-pad2_ net-_u39-pad1_ d_nand +* u36 net-_u36-pad1_ net-_u36-pad2_ d_inverter +* u41 net-_u13-pad1_ net-_u38-pad1_ d_inverter +* u38 net-_u38-pad1_ net-_u36-pad2_ /q2 d_and +* u49 net-_u48-pad2_ net-_u49-pad2_ d_buffer +* u48 /s3_bar net-_u48-pad2_ d_inverter +x4 net-_u14-pad1_ net-_u49-pad2_ /d3 net-_u51-pad2_ 3_and +* u54 /q3 /d3 net-_u51-pad1_ d_and +* u56 net-_u14-pad1_ net-_u56-pad2_ d_inverter +* u51 net-_u51-pad1_ net-_u51-pad2_ net-_u51-pad3_ d_nor +* u53 net-_u53-pad1_ net-_u51-pad3_ net-_u50-pad1_ d_and +* u57 /q3 net-_u56-pad2_ net-_u53-pad1_ d_nand +* u50 net-_u50-pad1_ net-_u50-pad2_ d_inverter +* u55 net-_u13-pad1_ net-_u52-pad1_ d_inverter +* u52 net-_u52-pad1_ net-_u50-pad2_ /q3 d_and +a1 net-_u2-pad2_ net-_u13-pad1_ u3 +a2 net-_u4-pad2_ net-_u14-pad1_ u5 +a3 net-_u6-pad2_ net-_u7-pad2_ u7 +a4 /mr_bar net-_u2-pad2_ u2 +a5 /e_bar net-_u4-pad2_ u4 +a6 /s0_bar net-_u6-pad2_ u6 +a7 [/q0 /d0 ] net-_u12-pad3_ u12 +a8 net-_u14-pad1_ net-_u14-pad2_ u14 +a9 [net-_u12-pad3_ net-_u9-pad2_ ] net-_u11-pad2_ u9 +a10 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11 +a11 [/q0 net-_u14-pad2_ ] net-_u11-pad1_ u15 +a12 net-_u11-pad3_ net-_u10-pad2_ u8 +a13 net-_u13-pad1_ net-_u10-pad1_ u13 +a14 [net-_u10-pad1_ net-_u10-pad2_ ] /q0 u10 +a15 net-_u20-pad2_ net-_u21-pad2_ u21 +a16 /s1_bar net-_u20-pad2_ u20 +a17 [/q1 /d1 ] net-_u23-pad1_ u26 +a18 net-_u14-pad1_ net-_u28-pad2_ u28 +a19 [net-_u23-pad1_ net-_u23-pad2_ ] net-_u23-pad3_ u23 +a20 [net-_u25-pad1_ net-_u23-pad3_ ] net-_u22-pad1_ u25 +a21 [/q1 net-_u28-pad2_ ] net-_u25-pad1_ u29 +a22 net-_u22-pad1_ net-_u22-pad2_ u22 +a23 net-_u13-pad1_ net-_u24-pad1_ u27 +a24 [net-_u24-pad1_ net-_u22-pad2_ ] /q1 u24 +a25 net-_u34-pad2_ net-_u35-pad2_ u35 +a26 /s2_bar net-_u34-pad2_ u34 +a27 [/q2 /d2 ] net-_u37-pad1_ u40 +a28 net-_u14-pad1_ net-_u42-pad2_ u42 +a29 [net-_u37-pad1_ net-_u37-pad2_ ] net-_u37-pad3_ u37 +a30 [net-_u39-pad1_ net-_u37-pad3_ ] net-_u36-pad1_ u39 +a31 [/q2 net-_u42-pad2_ ] net-_u39-pad1_ u43 +a32 net-_u36-pad1_ net-_u36-pad2_ u36 +a33 net-_u13-pad1_ net-_u38-pad1_ u41 +a34 [net-_u38-pad1_ net-_u36-pad2_ ] /q2 u38 +a35 net-_u48-pad2_ net-_u49-pad2_ u49 +a36 /s3_bar net-_u48-pad2_ u48 +a37 [/q3 /d3 ] net-_u51-pad1_ u54 +a38 net-_u14-pad1_ net-_u56-pad2_ u56 +a39 [net-_u51-pad1_ net-_u51-pad2_ ] net-_u51-pad3_ u51 +a40 [net-_u53-pad1_ net-_u51-pad3_ ] net-_u50-pad1_ u53 +a41 [/q3 net-_u56-pad2_ ] net-_u53-pad1_ u57 +a42 net-_u50-pad1_ net-_u50-pad2_ u50 +a43 net-_u13-pad1_ net-_u52-pad1_ u55 +a44 [net-_u52-pad1_ net-_u50-pad2_ ] /q3 u52 +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u3 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u5 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u7 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u12 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u9 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u11 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u15 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u10 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u21 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u26 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u28 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u23 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u25 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u29 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u22 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u27 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u24 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u35 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u34 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u40 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u42 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u37 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u39 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u43 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u36 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u41 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u38 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u49 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u48 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u54 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u56 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u51 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u53 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u57 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u50 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u55 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u52 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends DSR_LATCH \ No newline at end of file diff --git a/library/SubcircuitLibrary/DSR_LATCH/DSR_LATCH_Previous_Values.xml b/library/SubcircuitLibrary/DSR_LATCH/DSR_LATCH_Previous_Values.xml new file mode 100644 index 000000000..fab8123be --- /dev/null +++ b/library/SubcircuitLibrary/DSR_LATCH/DSR_LATCH_Previous_Values.xml @@ -0,0 +1 @@ +d_bufferd_bufferd_bufferd_inverterd_inverterd_inverterd_andd_inverterd_nord_andd_nandd_inverterd_inverterd_andd_bufferd_inverterd_andd_inverterd_nord_andd_nandd_inverterd_inverterd_andd_bufferd_inverterd_andd_inverterd_nord_andd_nandd_inverterd_inverterd_andd_bufferd_inverterd_andd_inverterd_nord_andd_nandd_inverterd_inverterd_andC:\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE\eSim\library\SubcircuitLibrary\3_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec \ No newline at end of file diff --git a/library/SubcircuitLibrary/DSR_LATCH/analysis b/library/SubcircuitLibrary/DSR_LATCH/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/SubcircuitLibrary/DSR_LATCH/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/library/SubcircuitLibrary/ICL7611/D.lib b/library/SubcircuitLibrary/ICL7611/D.lib new file mode 100644 index 000000000..f53bf3e03 --- /dev/null +++ b/library/SubcircuitLibrary/ICL7611/D.lib @@ -0,0 +1,2 @@ +.model 1N4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04) + diff --git a/library/SubcircuitLibrary/ICL7611/ICL7611-cache.lib b/library/SubcircuitLibrary/ICL7611/ICL7611-cache.lib new file mode 100644 index 000000000..fef1592e2 --- /dev/null +++ b/library/SubcircuitLibrary/ICL7611/ICL7611-cache.lib @@ -0,0 +1,162 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_C +# +DEF eSim_C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "eSim_C" 25 -100 50 H V L CNN +F2 "" 38 -150 30 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS capacitor +$FPLIST + C_* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 40 40 1 1 P +X ~ 2 0 -150 110 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_Diode +# +DEF eSim_Diode D 0 40 N N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "eSim_Diode" 0 -100 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + TO-???* + *SingleDiode + *_Diode_* + *SingleDiode* + D_* +$ENDFPLIST +DRAW +T 0 -100 50 60 0 0 0 A Normal 0 C C +T 0 100 50 60 0 0 0 K Normal 0 C C +P 2 0 1 6 50 50 50 -50 N +P 3 0 1 0 -50 50 50 0 -50 -50 F +X A 1 -150 0 100 R 40 40 1 1 P +X K 2 150 0 100 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_MOS_N +# +DEF eSim_MOS_N M 0 0 Y N 1 F N +F0 "M" 0 -150 50 H V R CNN +F1 "eSim_MOS_N" 100 -50 50 H V R CNN +F2 "" 300 -300 29 H V C CNN +F3 "" 100 -200 60 H V C CNN +ALIAS mosfet_n +DRAW +C 150 -200 111 0 1 10 N +P 2 0 1 10 130 -290 130 -250 N +P 2 0 1 0 130 -270 200 -270 N +P 2 0 1 10 130 -220 130 -180 N +P 2 0 1 0 130 -200 200 -200 N +P 2 0 1 10 130 -150 130 -110 N +P 2 0 1 0 130 -130 200 -130 N +P 2 0 1 0 200 -300 200 -270 N +P 2 0 1 0 200 -130 200 -100 N +P 3 0 1 10 110 -275 110 -125 110 -125 N +P 3 0 1 0 200 -200 300 -200 300 -250 N +P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F +X D 1 200 0 100 D 50 50 1 1 P +X G 2 -100 -200 210 R 50 50 1 1 P +X S 3 200 -400 100 U 50 50 1 1 P +X B 4 300 -350 98 U 47 47 1 1 P +ENDDRAW +ENDDEF +# +# eSim_MOS_P +# +DEF eSim_MOS_P M 0 0 Y N 1 F N +F0 "M" -50 50 50 H V R CNN +F1 "eSim_MOS_P" 50 150 50 H V R CNN +F2 "" 250 100 29 H V C CNN +F3 "" 50 0 60 H V C CNN +ALIAS mosfet_p +DRAW +C 100 0 111 0 1 10 N +P 2 0 1 0 80 -70 150 -70 N +P 2 0 1 10 80 -50 80 -90 N +P 2 0 1 0 80 0 150 0 N +P 2 0 1 10 80 20 80 -20 N +P 2 0 1 0 80 70 150 70 N +P 2 0 1 10 80 90 80 50 N +P 2 0 1 0 150 -70 150 -100 N +P 2 0 1 0 150 100 150 70 N +P 3 0 1 10 60 75 60 -75 60 -75 N +P 3 0 1 0 150 0 250 0 250 -50 N +P 4 0 1 0 140 0 100 -15 100 15 140 0 F +X D 1 150 200 100 D 50 50 1 1 P +X G 2 -150 0 210 R 50 50 1 1 P +X S 3 150 -200 100 U 50 50 1 1 P +X B 4 250 -150 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/ICL7611/ICL7611.bak b/library/SubcircuitLibrary/ICL7611/ICL7611.bak new file mode 100644 index 000000000..efdb5b3a4 --- /dev/null +++ b/library/SubcircuitLibrary/ICL7611/ICL7611.bak @@ -0,0 +1,926 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +EELAYER 25 0 +EELAYER END +$Descr A1 33110 23386 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_MOS_P M2 +U 1 1 68596BF9 +P 5150 6000 +F 0 "M2" H 5100 6050 50 0000 R CNN +F 1 "eSim_MOS_P" H 5200 6150 50 0000 R CNN +F 2 "" H 5400 6100 29 0000 C CNN +F 3 "" H 5200 6000 60 0000 C CNN + 1 5150 6000 + -1 0 0 1 +$EndComp +$Comp +L eSim_MOS_P M4 +U 1 1 68596C54 +P 6400 6000 +F 0 "M4" H 6350 6050 50 0000 R CNN +F 1 "eSim_MOS_P" H 6450 6150 50 0000 R CNN +F 2 "" H 6650 6100 29 0000 C CNN +F 3 "" H 6450 6000 60 0000 C CNN + 1 6400 6000 + 1 0 0 1 +$EndComp +$Comp +L resistor R3 +U 1 1 68596C8C +P 4950 4800 +F 0 "R3" H 5000 4930 50 0000 C CNN +F 1 "resistor" H 5000 4750 50 0000 C CNN +F 2 "" H 5000 4780 30 0000 C CNN +F 3 "" V 5000 4850 30 0000 C CNN + 1 4950 4800 + 0 1 1 0 +$EndComp +$Comp +L resistor R4 +U 1 1 68596CD5 +P 6500 4800 +F 0 "R4" H 6550 4930 50 0000 C CNN +F 1 "resistor" H 6550 4750 50 0000 C CNN +F 2 "" H 6550 4780 30 0000 C CNN +F 3 "" V 6550 4850 30 0000 C CNN + 1 6500 4800 + 0 1 1 0 +$EndComp +$Comp +L eSim_MOS_N M1 +U 1 1 68596DA8 +P 4800 6850 +F 0 "M1" H 4800 6700 50 0000 R CNN +F 1 "eSim_MOS_N" H 4900 6800 50 0000 R CNN +F 2 "" H 5100 6550 29 0000 C CNN +F 3 "" H 4900 6650 60 0000 C CNN + 1 4800 6850 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_N M5 +U 1 1 68596DF1 +P 6750 6800 +F 0 "M5" H 6750 6650 50 0000 R CNN +F 1 "eSim_MOS_N" H 6850 6750 50 0000 R CNN +F 2 "" H 7050 6500 29 0000 C CNN +F 3 "" H 6850 6600 60 0000 C CNN + 1 6750 6800 + -1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_N M3 +U 1 1 68596FB8 +P 6000 12200 +F 0 "M3" H 6000 12050 50 0000 R CNN +F 1 "eSim_MOS_N" H 6100 12150 50 0000 R CNN +F 2 "" H 6300 11900 29 0000 C CNN +F 3 "" H 6100 12000 60 0000 C CNN + 1 6000 12200 + -1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_N M6 +U 1 1 685976F9 +P 8650 11500 +F 0 "M6" H 8650 11350 50 0000 R CNN +F 1 "eSim_MOS_N" H 8750 11450 50 0000 R CNN +F 2 "" H 8950 11200 29 0000 C CNN +F 3 "" H 8750 11300 60 0000 C CNN + 1 8650 11500 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_N M7 +U 1 1 68597A10 +P 10300 11500 +F 0 "M7" H 10300 11350 50 0000 R CNN +F 1 "eSim_MOS_N" H 10400 11450 50 0000 R CNN +F 2 "" H 10600 11200 29 0000 C CNN +F 3 "" H 10400 11300 60 0000 C CNN + 1 10300 11500 + -1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_N M10 +U 1 1 68597AEE +P 11650 12750 +F 0 "M10" H 11650 12600 50 0000 R CNN +F 1 "eSim_MOS_N" H 11750 12700 50 0000 R CNN +F 2 "" H 11950 12450 29 0000 C CNN +F 3 "" H 11750 12550 60 0000 C CNN + 1 11650 12750 + -1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_N M12 +U 1 1 68597B63 +P 12500 11500 +F 0 "M12" H 12500 11350 50 0000 R CNN +F 1 "eSim_MOS_N" H 12600 11450 50 0000 R CNN +F 2 "" H 12800 11200 29 0000 C CNN +F 3 "" H 12600 11300 60 0000 C CNN + 1 12500 11500 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6550 5800 6550 5000 +Wire Wire Line + 6650 5850 6650 5600 +Wire Wire Line + 6650 5600 6550 5600 +Connection ~ 6550 5600 +Wire Wire Line + 5000 5800 5000 5000 +Wire Wire Line + 4900 5850 4900 5600 +Wire Wire Line + 4900 5600 5000 5600 +Connection ~ 5000 5600 +Wire Wire Line + 5300 6000 6250 6000 +Wire Wire Line + 5000 6850 5000 6200 +Wire Wire Line + 6550 6800 6550 6200 +Wire Wire Line + 6050 6000 6050 6500 +Wire Wire Line + 6050 6500 6550 6500 +Connection ~ 6550 6500 +Connection ~ 6050 6000 +Wire Wire Line + 5000 7250 5000 7800 +Wire Wire Line + 5000 7800 6550 7800 +Wire Wire Line + 6550 7800 6550 7200 +Wire Wire Line + 5800 12200 5800 7800 +Connection ~ 5800 7800 +Wire Wire Line + 5800 12600 5800 14400 +Wire Wire Line + 2800 14400 28900 14400 +Wire Wire Line + 5700 12550 5700 14400 +Connection ~ 5800 14400 +Wire Wire Line + 5000 4700 5000 2650 +Wire Wire Line + 2500 2650 29050 2650 +Wire Wire Line + 6550 4700 6550 2650 +Connection ~ 6550 2650 +Wire Wire Line + 5000 5200 3300 5200 +Wire Wire Line + 3300 5200 3300 5150 +Connection ~ 5000 5200 +Wire Wire Line + 7350 12400 6100 12400 +Wire Wire Line + 7350 11150 7350 12400 +Wire Wire Line + 7350 11700 8550 11700 +Wire Wire Line + 7350 11150 11450 11150 +Wire Wire Line + 8850 11150 8850 11500 +Connection ~ 7350 11700 +Wire Wire Line + 8850 11900 8850 14400 +Connection ~ 8850 14400 +Wire Wire Line + 8950 11850 8950 14400 +Connection ~ 8950 14400 +Wire Wire Line + 10400 11700 12400 11700 +Wire Wire Line + 10100 11900 10100 12400 +Wire Wire Line + 10000 12400 12800 12400 +Wire Wire Line + 12700 12400 12700 11900 +Wire Wire Line + 11450 12750 11450 12400 +Connection ~ 11450 12400 +Wire Wire Line + 10100 11150 10100 11500 +Connection ~ 8850 11150 +Wire Wire Line + 11450 11150 11450 12000 +Connection ~ 11450 11700 +Connection ~ 10100 11150 +Wire Wire Line + 11450 13150 11450 14400 +Connection ~ 11450 14400 +Wire Wire Line + 11350 13100 11350 14400 +Connection ~ 11350 14400 +Wire Wire Line + 10000 11850 10000 12400 +Connection ~ 10100 12400 +Wire Wire Line + 12800 12400 12800 11850 +Connection ~ 12700 12400 +$Comp +L eSim_MOS_N M13 +U 1 1 68598199 +P 15050 11500 +F 0 "M13" H 15050 11350 50 0000 R CNN +F 1 "eSim_MOS_N" H 15150 11450 50 0000 R CNN +F 2 "" H 15350 11200 29 0000 C CNN +F 3 "" H 15150 11300 60 0000 C CNN + 1 15050 11500 + -1 0 0 -1 +$EndComp +Wire Wire Line + 12700 11500 12700 11250 +Wire Wire Line + 12400 11250 14850 11250 +Wire Wire Line + 14850 11250 14850 11500 +Wire Wire Line + 14850 11900 14850 14400 +Connection ~ 14850 14400 +Wire Wire Line + 14750 11850 14750 14400 +Connection ~ 14750 14400 +Wire Wire Line + 11450 12000 15650 12000 +Wire Wire Line + 15650 12000 15650 11700 +Wire Wire Line + 15150 11700 18600 11700 +$Comp +L eSim_MOS_N M15 +U 1 1 68598842 +P 18700 11500 +F 0 "M15" H 18700 11350 50 0000 R CNN +F 1 "eSim_MOS_N" H 18800 11450 50 0000 R CNN +F 2 "" H 19000 11200 29 0000 C CNN +F 3 "" H 18800 11300 60 0000 C CNN + 1 18700 11500 + 1 0 0 -1 +$EndComp +Connection ~ 15650 11700 +Wire Wire Line + 18900 11900 18900 14400 +Connection ~ 18900 14400 +Wire Wire Line + 19000 11850 19000 14400 +Connection ~ 19000 14400 +$Comp +L eSim_MOS_N M18 +U 1 1 68598CA3 +P 22300 11500 +F 0 "M18" H 22300 11350 50 0000 R CNN +F 1 "eSim_MOS_N" H 22400 11450 50 0000 R CNN +F 2 "" H 22600 11200 29 0000 C CNN +F 3 "" H 22400 11300 60 0000 C CNN + 1 22300 11500 + -1 0 0 -1 +$EndComp +Wire Wire Line + 22100 11900 22100 14400 +Connection ~ 22100 14400 +Wire Wire Line + 22000 11850 22000 14400 +Connection ~ 22000 14400 +$Comp +L eSim_MOS_N M19 +U 1 1 68599072 +P 24850 11500 +F 0 "M19" H 24850 11350 50 0000 R CNN +F 1 "eSim_MOS_N" H 24950 11450 50 0000 R CNN +F 2 "" H 25150 11200 29 0000 C CNN +F 3 "" H 24950 11300 60 0000 C CNN + 1 24850 11500 + 1 0 0 -1 +$EndComp +Wire Wire Line + 25050 11900 25050 14400 +Connection ~ 25050 14400 +Wire Wire Line + 25150 11850 25150 14400 +Connection ~ 25150 14400 +Wire Wire Line + 22400 11700 24750 11700 +$Comp +L resistor R7 +U 1 1 685995FF +P 16100 14950 +F 0 "R7" H 16150 15080 50 0000 C CNN +F 1 "470k" H 16150 14900 50 0000 C CNN +F 2 "" H 16150 14930 30 0000 C CNN +F 3 "" V 16150 15000 30 0000 C CNN + 1 16100 14950 + 0 1 1 0 +$EndComp +$Comp +L resistor R5 +U 1 1 68599992 +P 10500 3200 +F 0 "R5" H 10550 3330 50 0000 C CNN +F 1 "900k" H 10550 3150 50 0000 C CNN +F 2 "" H 10550 3180 30 0000 C CNN +F 3 "" V 10550 3250 30 0000 C CNN + 1 10500 3200 + 0 1 1 0 +$EndComp +$Comp +L resistor R6 +U 1 1 68599B69 +P 10500 4350 +F 0 "R6" H 10550 4480 50 0000 C CNN +F 1 "100k" H 10550 4300 50 0000 C CNN +F 2 "" H 10550 4330 30 0000 C CNN +F 3 "" V 10550 4400 30 0000 C CNN + 1 10500 4350 + 0 1 1 0 +$EndComp +$Comp +L eSim_MOS_P M8 +U 1 1 68599C9A +P 10700 5450 +F 0 "M8" H 10650 5500 50 0000 R CNN +F 1 "eSim_MOS_P" H 10750 5600 50 0000 R CNN +F 2 "" H 10950 5550 29 0000 C CNN +F 3 "" H 10750 5450 60 0000 C CNN + 1 10700 5450 + -1 0 0 1 +$EndComp +Wire Wire Line + 10550 5650 10550 11150 +Connection ~ 10550 11150 +Wire Wire Line + 10550 5250 10550 4550 +Wire Wire Line + 10550 4250 10550 3400 +Wire Wire Line + 10550 3100 10550 2650 +Connection ~ 10550 2650 +$Comp +L eSim_MOS_P M11 +U 1 1 6859A1ED +P 12250 5400 +F 0 "M11" H 12200 5450 50 0000 R CNN +F 1 "eSim_MOS_P" H 12300 5550 50 0000 R CNN +F 2 "" H 12500 5500 29 0000 C CNN +F 3 "" H 12300 5400 60 0000 C CNN + 1 12250 5400 + 1 0 0 1 +$EndComp +Wire Wire Line + 10850 5450 12100 5450 +Wire Wire Line + 12100 5450 12100 5400 +Wire Wire Line + 12400 5600 12400 11250 +Connection ~ 12700 11250 +Wire Wire Line + 11450 5450 11450 6550 +Wire Wire Line + 11450 6550 12400 6550 +Connection ~ 12400 6550 +Connection ~ 11450 5450 +Wire Wire Line + 10450 5300 10450 5150 +Wire Wire Line + 10450 5150 10550 5150 +Connection ~ 10550 5150 +Wire Wire Line + 12400 5200 12400 2650 +Connection ~ 12400 2650 +Wire Wire Line + 12500 5250 12500 5050 +Wire Wire Line + 12500 5050 12400 5050 +Connection ~ 12400 5050 +$Comp +L eSim_MOS_P M9 +U 1 1 6859AB95 +P 11600 3450 +F 0 "M9" H 11550 3500 50 0000 R CNN +F 1 "eSim_MOS_P" H 11650 3600 50 0000 R CNN +F 2 "" H 11850 3550 29 0000 C CNN +F 3 "" H 11650 3450 60 0000 C CNN + 1 11600 3450 + -1 0 0 1 +$EndComp +Wire Wire Line + 11450 3650 11450 3800 +Wire Wire Line + 11450 3800 10550 3800 +Connection ~ 10550 3800 +Wire Wire Line + 11450 3250 11450 2650 +Connection ~ 11450 2650 +Wire Wire Line + 11350 3300 11350 3050 +Wire Wire Line + 11350 3050 11450 3050 +Connection ~ 11450 3050 +Wire Wire Line + 16150 14850 16150 3450 +Wire Wire Line + 16150 3450 11750 3450 +Wire Wire Line + 16150 15150 16150 15600 +Wire Wire Line + 11750 12950 16150 12950 +Connection ~ 16150 12950 +$Comp +L eSim_MOS_P M14 +U 1 1 6859B9E9 +P 18500 4400 +F 0 "M14" H 18450 4450 50 0000 R CNN +F 1 "eSim_MOS_P" H 18550 4550 50 0000 R CNN +F 2 "" H 18750 4500 29 0000 C CNN +F 3 "" H 18550 4400 60 0000 C CNN + 1 18500 4400 + 1 0 0 1 +$EndComp +Wire Wire Line + 18900 11500 18900 5000 +Wire Wire Line + 18650 5000 19250 5000 +Wire Wire Line + 18650 5000 18650 4600 +$Comp +L eSim_MOS_P M16 +U 1 1 6859C510 +P 19400 4400 +F 0 "M16" H 19350 4450 50 0000 R CNN +F 1 "eSim_MOS_P" H 19450 4550 50 0000 R CNN +F 2 "" H 19650 4500 29 0000 C CNN +F 3 "" H 19450 4400 60 0000 C CNN + 1 19400 4400 + -1 0 0 1 +$EndComp +Wire Wire Line + 19250 5000 19250 4600 +Connection ~ 18900 5000 +Wire Wire Line + 19250 4200 19250 3750 +Wire Wire Line + 19250 3750 18650 3750 +Wire Wire Line + 18650 3750 18650 4200 +Wire Wire Line + 18750 4250 18750 3900 +Wire Wire Line + 18750 3900 18650 3900 +Connection ~ 18650 3900 +Wire Wire Line + 19150 4250 19150 3900 +Wire Wire Line + 19150 3900 19250 3900 +Connection ~ 19250 3900 +Wire Wire Line + 18950 3750 18950 2650 +Connection ~ 18950 2650 +Connection ~ 18950 3750 +$Comp +L eSim_MOS_P M20 +U 1 1 6859CA78 +P 24900 5450 +F 0 "M20" H 24850 5500 50 0000 R CNN +F 1 "eSim_MOS_P" H 24950 5600 50 0000 R CNN +F 2 "" H 25150 5550 29 0000 C CNN +F 3 "" H 24950 5450 60 0000 C CNN + 1 24900 5450 + 1 0 0 1 +$EndComp +Wire Wire Line + 25050 11500 25050 5650 +Wire Wire Line + 25050 5250 25050 2650 +Connection ~ 25050 2650 +Wire Wire Line + 25150 5300 25150 5100 +Wire Wire Line + 25150 5100 25050 5100 +Connection ~ 25050 5100 +Wire Wire Line + 5000 6700 24550 6700 +Wire Wire Line + 24550 6700 24550 5450 +Wire Wire Line + 24550 5450 24750 5450 +Connection ~ 5000 6700 +Wire Wire Line + 18350 4400 17350 4400 +Wire Wire Line + 17350 4400 17350 6700 +Connection ~ 17350 6700 +$Comp +L eSim_MOS_P M17 +U 1 1 6859DCC7 +P 21950 4400 +F 0 "M17" H 21900 4450 50 0000 R CNN +F 1 "eSim_MOS_P" H 22000 4550 50 0000 R CNN +F 2 "" H 22200 4500 29 0000 C CNN +F 3 "" H 22000 4400 60 0000 C CNN + 1 21950 4400 + 1 0 0 1 +$EndComp +Wire Wire Line + 22100 11500 22100 4600 +Wire Wire Line + 22100 4200 22100 2650 +Connection ~ 22100 2650 +Wire Wire Line + 22200 4250 22200 4000 +Wire Wire Line + 22200 4000 22100 4000 +Connection ~ 22100 4000 +Wire Wire Line + 19550 4400 21800 4400 +Wire Wire Line + 20600 4400 20600 5900 +Wire Wire Line + 20600 5900 18900 5900 +Connection ~ 18900 5900 +Connection ~ 20600 4400 +$Comp +L capacitor C1 +U 1 1 6859EBA0 +P 23200 7550 +F 0 "C1" H 23225 7650 50 0000 L CNN +F 1 "9p" H 23225 7450 50 0000 L CNN +F 2 "" H 23238 7400 30 0000 C CNN +F 3 "" H 23200 7550 60 0000 C CNN + 1 23200 7550 + 0 1 1 0 +$EndComp +Wire Wire Line + 23600 7550 23350 7550 +Wire Wire Line + 23600 4450 23600 7550 +Connection ~ 23600 6700 +Wire Wire Line + 23050 7550 22100 7550 +Connection ~ 22100 7550 +$Comp +L eSim_Diode D7 +U 1 1 6859F3FA +P 23600 4300 +F 0 "D7" H 23600 4400 50 0000 C CNN +F 1 "eSim_Diode" H 23600 4200 50 0000 C CNN +F 2 "" H 23600 4300 60 0000 C CNN +F 3 "" H 23600 4300 60 0000 C CNN + 1 23600 4300 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 23600 4150 23600 2650 +Connection ~ 23600 2650 +Wire Wire Line + 20500 6700 20500 9050 +Wire Wire Line + 20500 9050 23100 9050 +Connection ~ 20500 6700 +$Comp +L capacitor C2 +U 1 1 6859F985 +P 23250 9050 +F 0 "C2" H 23275 9150 50 0000 L CNN +F 1 "33p" H 23275 8950 50 0000 L CNN +F 2 "" H 23288 8900 30 0000 C CNN +F 3 "" H 23250 9050 60 0000 C CNN + 1 23250 9050 + 0 1 1 0 +$EndComp +Connection ~ 25050 9050 +Wire Wire Line + 22100 10100 23550 10100 +Wire Wire Line + 23550 10100 23550 12800 +Connection ~ 23550 11700 +Connection ~ 22100 10100 +$Comp +L eSim_Diode D6 +U 1 1 685A0135 +P 23550 12950 +F 0 "D6" H 23550 13050 50 0000 C CNN +F 1 "eSim_Diode" H 23550 12850 50 0000 C CNN +F 2 "" H 23550 12950 60 0000 C CNN +F 3 "" H 23550 12950 60 0000 C CNN + 1 23550 12950 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 23550 13100 23550 14400 +Connection ~ 23550 14400 +Wire Wire Line + 6900 7000 6900 10000 +Wire Wire Line + 4700 7050 3600 7050 +Wire Wire Line + 6900 7000 6850 7000 +Wire Wire Line + 6450 7150 6450 7450 +Wire Wire Line + 6450 7450 6550 7450 +Connection ~ 6550 7450 +Wire Wire Line + 5100 7200 5100 7550 +Wire Wire Line + 5100 7550 5000 7550 +Connection ~ 5000 7550 +Wire Wire Line + 15450 15600 16800 15600 +Connection ~ 16150 15600 +$Comp +L eSim_Diode D5 +U 1 1 685A1C84 +P 15300 15600 +F 0 "D5" H 15300 15700 50 0000 C CNN +F 1 "eSim_Diode" H 15300 15500 50 0000 C CNN +F 2 "" H 15300 15600 60 0000 C CNN +F 3 "" H 15300 15600 60 0000 C CNN + 1 15300 15600 + -1 0 0 1 +$EndComp +Wire Wire Line + 15150 15600 14550 15600 +$Comp +L eSim_Diode D3 +U 1 1 685A2164 +P 3000 9450 +F 0 "D3" H 3000 9550 50 0000 C CNN +F 1 "eSim_Diode" H 3000 9350 50 0000 C CNN +F 2 "" H 3000 9450 60 0000 C CNN +F 3 "" H 3000 9450 60 0000 C CNN + 1 3000 9450 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_Diode D4 +U 1 1 685A221F +P 3000 10650 +F 0 "D4" H 3000 10750 50 0000 C CNN +F 1 "eSim_Diode" H 3000 10550 50 0000 C CNN +F 2 "" H 3000 10650 60 0000 C CNN +F 3 "" H 3000 10650 60 0000 C CNN + 1 3000 10650 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 3000 9600 3000 10500 +Connection ~ 3000 10000 +Wire Wire Line + 3000 9300 3000 9100 +Wire Wire Line + 3000 9100 2800 9100 +Wire Wire Line + 3000 10800 3000 11000 +Wire Wire Line + 3000 11000 2800 11000 +Wire Wire Line + 2800 11000 2800 14400 +Connection ~ 5700 14400 +$Comp +L resistor R1 +U 1 1 685A2EB7 +P 3400 7100 +F 0 "R1" H 3450 7230 50 0000 C CNN +F 1 "10k" H 3450 7050 50 0000 C CNN +F 2 "" H 3450 7080 30 0000 C CNN +F 3 "" V 3450 7150 30 0000 C CNN + 1 3400 7100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3300 7050 1400 7050 +Wire Wire Line + 1400 7050 1400 6950 +$Comp +L eSim_Diode D1 +U 1 1 685A3192 +P 2500 6550 +F 0 "D1" H 2500 6650 50 0000 C CNN +F 1 "eSim_Diode" H 2500 6450 50 0000 C CNN +F 2 "" H 2500 6550 60 0000 C CNN +F 3 "" H 2500 6550 60 0000 C CNN + 1 2500 6550 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_Diode D2 +U 1 1 685A329F +P 2500 7450 +F 0 "D2" H 2500 7550 50 0000 C CNN +F 1 "eSim_Diode" H 2500 7350 50 0000 C CNN +F 2 "" H 2500 7450 60 0000 C CNN +F 3 "" H 2500 7450 60 0000 C CNN + 1 2500 7450 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 2500 6700 2500 7300 +Connection ~ 2500 7050 +Wire Wire Line + 2500 7600 2500 8450 +Wire Wire Line + 2500 8450 4050 8450 +Wire Wire Line + 4050 8450 4050 14400 +Connection ~ 4050 14400 +Wire Wire Line + 2500 6400 2500 2650 +Connection ~ 5000 2650 +Wire Wire Line + 2800 9100 2800 2650 +Connection ~ 2800 2650 +Wire Wire Line + 14550 15600 14550 17000 +Wire Wire Line + 14550 17000 27000 17000 +Wire Wire Line + 27000 17000 27000 2650 +Connection ~ 27000 2650 +$Comp +L resistor R2 +U 1 1 685A5751 +P 4900 10100 +F 0 "R2" H 4950 10230 50 0000 C CNN +F 1 "10k" H 4950 10050 50 0000 C CNN +F 2 "" H 4950 10080 30 0000 C CNN +F 3 "" V 4950 10150 30 0000 C CNN + 1 4900 10100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6900 10000 5100 10000 +Wire Wire Line + 5100 10000 5100 10050 +Wire Wire Line + 3150 10050 4800 10050 +Wire Wire Line + 3150 10000 3150 10050 +Wire Wire Line + 1300 10000 3150 10000 +Wire Wire Line + 1300 10000 1300 9900 +$Comp +L PORT U1 +U 3 1 685A6C2B +P 1150 6950 +F 0 "U1" H 1200 7050 30 0000 C CNN +F 1 "PORT" H 1150 6950 30 0000 C CNN +F 2 "" H 1150 6950 60 0000 C CNN +F 3 "" H 1150 6950 60 0000 C CNN + 3 1150 6950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 685A6E1C +P 1050 9900 +F 0 "U1" H 1100 10000 30 0000 C CNN +F 1 "PORT" H 1050 9900 30 0000 C CNN +F 2 "" H 1050 9900 60 0000 C CNN +F 3 "" H 1050 9900 60 0000 C CNN + 2 1050 9900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 685A70A1 +P 3050 5150 +F 0 "U1" H 3100 5250 30 0000 C CNN +F 1 "PORT" H 3050 5150 30 0000 C CNN +F 2 "" H 3050 5150 60 0000 C CNN +F 3 "" H 3050 5150 60 0000 C CNN + 1 3050 5150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 685A7658 +P 17050 15600 +F 0 "U1" H 17100 15700 30 0000 C CNN +F 1 "PORT" H 17050 15600 30 0000 C CNN +F 2 "" H 17050 15600 60 0000 C CNN +F 3 "" H 17050 15600 60 0000 C CNN + 8 17050 15600 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 7 1 685A7793 +P 29300 2650 +F 0 "U1" H 29350 2750 30 0000 C CNN +F 1 "PORT" H 29300 2650 30 0000 C CNN +F 2 "" H 29300 2650 60 0000 C CNN +F 3 "" H 29300 2650 60 0000 C CNN + 7 29300 2650 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 4 1 685A7DD7 +P 29150 14400 +F 0 "U1" H 29200 14500 30 0000 C CNN +F 1 "PORT" H 29150 14400 30 0000 C CNN +F 2 "" H 29150 14400 60 0000 C CNN +F 3 "" H 29150 14400 60 0000 C CNN + 4 29150 14400 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 6 1 685A856C +P 27800 9050 +F 0 "U1" H 27850 9150 30 0000 C CNN +F 1 "PORT" H 27800 9050 30 0000 C CNN +F 2 "" H 27800 9050 60 0000 C CNN +F 3 "" H 27800 9050 60 0000 C CNN + 6 27800 9050 + -1 0 0 1 +$EndComp +Text Label 3600 5200 0 60 ~ 0 +Bal +Text Label 1700 7050 0 60 ~ 0 +Input+ +Text Label 1550 10000 0 60 ~ 0 +Input- +Wire Wire Line + 23400 9050 27550 9050 +Text Label 27150 9050 0 60 ~ 0 +Out +Text Label 28600 2650 0 60 ~ 0 +V+ +Text Label 28750 14400 0 60 ~ 0 +V- +Text Label 16600 15600 0 60 ~ 0 +Iqset +Wire Wire Line + 6550 5150 7200 5150 +Connection ~ 6550 5150 +$Comp +L PORT U? +U 5 1 685ACDAE +P 7450 5150 +F 0 "U?" H 7500 5250 30 0000 C CNN +F 1 "PORT" H 7450 5150 30 0000 C CNN +F 2 "" H 7450 5150 60 0000 C CNN +F 3 "" H 7450 5150 60 0000 C CNN + 5 7450 5150 + -1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/ICL7611/ICL7611.cir b/library/SubcircuitLibrary/ICL7611/ICL7611.cir new file mode 100644 index 000000000..5b15871dd --- /dev/null +++ b/library/SubcircuitLibrary/ICL7611/ICL7611.cir @@ -0,0 +1,47 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\ICL7611\ICL7611.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/24/25 08:09:14 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +M2 Net-_C1-Pad1_ Net-_M2-Pad2_ /Bal /Bal eSim_MOS_P +M4 Net-_M2-Pad2_ Net-_M2-Pad2_ Net-_M4-Pad3_ Net-_M4-Pad3_ eSim_MOS_P +R3 /V+ /Bal 3k +R4 /V+ Net-_M4-Pad3_ 3k +M1 Net-_C1-Pad1_ Net-_M1-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +M5 Net-_M2-Pad2_ Net-_M5-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +M3 Net-_M1-Pad3_ Net-_M12-Pad2_ /V- /V- eSim_MOS_N +M6 Net-_M12-Pad2_ Net-_M12-Pad2_ /V- /V- eSim_MOS_N +M7 Net-_M12-Pad2_ Net-_M12-Pad2_ Net-_M10-Pad1_ Net-_M10-Pad1_ eSim_MOS_N +M10 Net-_M10-Pad1_ Net-_M10-Pad2_ /V- /V- eSim_MOS_N +M12 Net-_M11-Pad1_ Net-_M12-Pad2_ Net-_M10-Pad1_ Net-_M10-Pad1_ eSim_MOS_N +M13 Net-_M11-Pad1_ Net-_M12-Pad2_ /V- /V- eSim_MOS_N +M15 Net-_M14-Pad1_ Net-_M12-Pad2_ /V- /V- eSim_MOS_N +M18 Net-_C1-Pad2_ Net-_C1-Pad2_ /V- /V- eSim_MOS_N +M19 /Out Net-_C1-Pad2_ /V- /V- eSim_MOS_N +R7 Net-_M10-Pad2_ /Iqset 470k +R5 /V+ Net-_M9-Pad1_ 900k +R6 Net-_M9-Pad1_ Net-_M8-Pad3_ 100k +M8 Net-_M12-Pad2_ Net-_M11-Pad1_ Net-_M8-Pad3_ Net-_M8-Pad3_ eSim_MOS_P +M11 Net-_M11-Pad1_ Net-_M11-Pad1_ /V+ /V+ eSim_MOS_P +M9 Net-_M9-Pad1_ Net-_M10-Pad2_ /V+ /V+ eSim_MOS_P +M14 Net-_M14-Pad1_ Net-_C1-Pad1_ /V+ /V+ eSim_MOS_P +M16 Net-_M14-Pad1_ Net-_M14-Pad1_ /V+ /V+ eSim_MOS_P +M20 /Out Net-_C1-Pad1_ /V+ /V+ eSim_MOS_P +M17 Net-_C1-Pad2_ Net-_M14-Pad1_ /V+ /V+ eSim_MOS_P +C1 Net-_C1-Pad1_ Net-_C1-Pad2_ 9p +D7 Net-_C1-Pad1_ /V+ eSim_Diode +C2 /Out Net-_C1-Pad1_ 33p +D6 /V- Net-_C1-Pad2_ eSim_Diode +D5 /Iqset /V+ eSim_Diode +D3 /Input- /V+ eSim_Diode +D4 /V- /Input- eSim_Diode +R1 /Input+ Net-_M1-Pad2_ 10k +D1 /Input+ /V+ eSim_Diode +D2 /V- /Input+ eSim_Diode +R2 /Input- Net-_M5-Pad2_ 10k +U1 /Bal /Input- /Input+ /V- Net-_M4-Pad3_ /Out /V+ /Iqset PORT + +.end diff --git a/library/SubcircuitLibrary/ICL7611/ICL7611.cir.out b/library/SubcircuitLibrary/ICL7611/ICL7611.cir.out new file mode 100644 index 000000000..ca28bd2fa --- /dev/null +++ b/library/SubcircuitLibrary/ICL7611/ICL7611.cir.out @@ -0,0 +1,52 @@ +* c:\fossee\esim\library\subcircuitlibrary\icl7611\icl7611.cir + +.include NMOS-5um.lib +.include ZenerD1N750.lib +.include D.lib +.include PMOS-5um.lib +m2 net-_c1-pad1_ net-_m2-pad2_ /bal /bal mos_p W=100u L=100u M=1 +m4 net-_m2-pad2_ net-_m2-pad2_ net-_m4-pad3_ net-_m4-pad3_ mos_p W=100u L=100u M=1 +r3 /v+ /bal resistor +r4 /v+ net-_m4-pad3_ resistor +m1 net-_c1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad3_ mos_n W=100u L=100u M=1 +m5 net-_m2-pad2_ net-_m5-pad2_ net-_m1-pad3_ net-_m1-pad3_ mos_n W=100u L=100u M=1 +m3 net-_m1-pad3_ net-_m12-pad2_ /v- /v- mos_n W=100u L=100u M=1 +m6 net-_m12-pad2_ net-_m12-pad2_ /v- /v- mos_n W=100u L=100u M=1 +m7 net-_m12-pad2_ net-_m12-pad2_ net-_m10-pad1_ net-_m10-pad1_ mos_n W=100u L=100u M=1 +m10 net-_m10-pad1_ net-_m10-pad2_ /v- /v- mos_n W=100u L=100u M=1 +m12 net-_m11-pad1_ net-_m12-pad2_ net-_m10-pad1_ net-_m10-pad1_ mos_n W=100u L=100u M=1 +m13 net-_m11-pad1_ net-_m12-pad2_ /v- /v- mos_n W=100u L=100u M=1 +m15 net-_m14-pad1_ net-_m12-pad2_ /v- /v- mos_n W=100u L=100u M=1 +m18 net-_c1-pad2_ net-_c1-pad2_ /v- /v- mos_n W=100u L=100u M=1 +m19 /out net-_c1-pad2_ /v- /v- mos_n W=100u L=100u M=1 +r7 net-_m10-pad2_ /iqset 470k +r5 /v+ net-_m9-pad1_ 900k +r6 net-_m9-pad1_ net-_m8-pad3_ 100k +m8 net-_m12-pad2_ net-_m11-pad1_ net-_m8-pad3_ net-_m8-pad3_ mos_p W=100u L=100u M=1 +m11 net-_m11-pad1_ net-_m11-pad1_ /v+ /v+ mos_p W=100u L=100u M=1 +m9 net-_m9-pad1_ net-_m10-pad2_ /v+ /v+ mos_p W=100u L=100u M=1 +m14 net-_m14-pad1_ net-_c1-pad1_ /v+ /v+ mos_p W=100u L=100u M=1 +m16 net-_m14-pad1_ net-_m14-pad1_ /v+ /v+ mos_p W=100u L=100u M=1 +m20 /out net-_c1-pad1_ /v+ /v+ mos_p W=100u L=100u M=1 +m17 net-_c1-pad2_ net-_m14-pad1_ /v+ /v+ mos_p W=100u L=100u M=1 +c1 net-_c1-pad1_ net-_c1-pad2_ 9p +d7 net-_c1-pad1_ /v+ D1N750 +c2 /out net-_c1-pad1_ 33p +d6 /v- net-_c1-pad2_ D1N750 +d5 /iqset /v+ 1N4148 +d3 /input- /v+ 1N4148 +d4 /v- /input- 1N4148 +r1 /input+ net-_m1-pad2_ 10k +d1 /input+ /v+ 1N4148 +d2 /v- /input+ 1N4148 +r2 /input- net-_m5-pad2_ 10k +* u1 /bal /input- /input+ /v- net-_m4-pad3_ /out /v+ /iqset port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/ICL7611/ICL7611.pro b/library/SubcircuitLibrary/ICL7611/ICL7611.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/ICL7611/ICL7611.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/ICL7611/ICL7611.sch b/library/SubcircuitLibrary/ICL7611/ICL7611.sch new file mode 100644 index 000000000..316eb0a19 --- /dev/null +++ b/library/SubcircuitLibrary/ICL7611/ICL7611.sch @@ -0,0 +1,926 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +EELAYER 25 0 +EELAYER END +$Descr A1 33110 23386 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_MOS_P M2 +U 1 1 68596BF9 +P 5150 6000 +F 0 "M2" H 5100 6050 50 0000 R CNN +F 1 "eSim_MOS_P" H 5200 6150 50 0000 R CNN +F 2 "" H 5400 6100 29 0000 C CNN +F 3 "" H 5200 6000 60 0000 C CNN + 1 5150 6000 + -1 0 0 1 +$EndComp +$Comp +L eSim_MOS_P M4 +U 1 1 68596C54 +P 6400 6000 +F 0 "M4" H 6350 6050 50 0000 R CNN +F 1 "eSim_MOS_P" H 6450 6150 50 0000 R CNN +F 2 "" H 6650 6100 29 0000 C CNN +F 3 "" H 6450 6000 60 0000 C CNN + 1 6400 6000 + 1 0 0 1 +$EndComp +$Comp +L resistor R3 +U 1 1 68596C8C +P 4950 4800 +F 0 "R3" H 5000 4930 50 0000 C CNN +F 1 "3k" H 5000 4750 50 0000 C CNN +F 2 "" H 5000 4780 30 0000 C CNN +F 3 "" V 5000 4850 30 0000 C CNN + 1 4950 4800 + 0 1 1 0 +$EndComp +$Comp +L resistor R4 +U 1 1 68596CD5 +P 6500 4800 +F 0 "R4" H 6550 4930 50 0000 C CNN +F 1 "3k" H 6550 4750 50 0000 C CNN +F 2 "" H 6550 4780 30 0000 C CNN +F 3 "" V 6550 4850 30 0000 C CNN + 1 6500 4800 + 0 1 1 0 +$EndComp +$Comp +L eSim_MOS_N M1 +U 1 1 68596DA8 +P 4800 6850 +F 0 "M1" H 4800 6700 50 0000 R CNN +F 1 "eSim_MOS_N" H 4900 6800 50 0000 R CNN +F 2 "" H 5100 6550 29 0000 C CNN +F 3 "" H 4900 6650 60 0000 C CNN + 1 4800 6850 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_N M5 +U 1 1 68596DF1 +P 6750 6800 +F 0 "M5" H 6750 6650 50 0000 R CNN +F 1 "eSim_MOS_N" H 6850 6750 50 0000 R CNN +F 2 "" H 7050 6500 29 0000 C CNN +F 3 "" H 6850 6600 60 0000 C CNN + 1 6750 6800 + -1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_N M3 +U 1 1 68596FB8 +P 6000 12200 +F 0 "M3" H 6000 12050 50 0000 R CNN +F 1 "eSim_MOS_N" H 6100 12150 50 0000 R CNN +F 2 "" H 6300 11900 29 0000 C CNN +F 3 "" H 6100 12000 60 0000 C CNN + 1 6000 12200 + -1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_N M6 +U 1 1 685976F9 +P 8650 11500 +F 0 "M6" H 8650 11350 50 0000 R CNN +F 1 "eSim_MOS_N" H 8750 11450 50 0000 R CNN +F 2 "" H 8950 11200 29 0000 C CNN +F 3 "" H 8750 11300 60 0000 C CNN + 1 8650 11500 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_N M7 +U 1 1 68597A10 +P 10300 11500 +F 0 "M7" H 10300 11350 50 0000 R CNN +F 1 "eSim_MOS_N" H 10400 11450 50 0000 R CNN +F 2 "" H 10600 11200 29 0000 C CNN +F 3 "" H 10400 11300 60 0000 C CNN + 1 10300 11500 + -1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_N M10 +U 1 1 68597AEE +P 11650 12750 +F 0 "M10" H 11650 12600 50 0000 R CNN +F 1 "eSim_MOS_N" H 11750 12700 50 0000 R CNN +F 2 "" H 11950 12450 29 0000 C CNN +F 3 "" H 11750 12550 60 0000 C CNN + 1 11650 12750 + -1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_N M12 +U 1 1 68597B63 +P 12500 11500 +F 0 "M12" H 12500 11350 50 0000 R CNN +F 1 "eSim_MOS_N" H 12600 11450 50 0000 R CNN +F 2 "" H 12800 11200 29 0000 C CNN +F 3 "" H 12600 11300 60 0000 C CNN + 1 12500 11500 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6550 5800 6550 5000 +Wire Wire Line + 6650 5850 6650 5600 +Wire Wire Line + 6650 5600 6550 5600 +Connection ~ 6550 5600 +Wire Wire Line + 5000 5800 5000 5000 +Wire Wire Line + 4900 5850 4900 5600 +Wire Wire Line + 4900 5600 5000 5600 +Connection ~ 5000 5600 +Wire Wire Line + 5300 6000 6250 6000 +Wire Wire Line + 5000 6850 5000 6200 +Wire Wire Line + 6550 6800 6550 6200 +Wire Wire Line + 6050 6000 6050 6500 +Wire Wire Line + 6050 6500 6550 6500 +Connection ~ 6550 6500 +Connection ~ 6050 6000 +Wire Wire Line + 5000 7250 5000 7800 +Wire Wire Line + 5000 7800 6550 7800 +Wire Wire Line + 6550 7800 6550 7200 +Wire Wire Line + 5800 12200 5800 7800 +Connection ~ 5800 7800 +Wire Wire Line + 5800 12600 5800 14400 +Wire Wire Line + 2800 14400 28900 14400 +Wire Wire Line + 5700 12550 5700 14400 +Connection ~ 5800 14400 +Wire Wire Line + 5000 4700 5000 2650 +Wire Wire Line + 2500 2650 29050 2650 +Wire Wire Line + 6550 4700 6550 2650 +Connection ~ 6550 2650 +Wire Wire Line + 5000 5200 3300 5200 +Wire Wire Line + 3300 5200 3300 5150 +Connection ~ 5000 5200 +Wire Wire Line + 7350 12400 6100 12400 +Wire Wire Line + 7350 11150 7350 12400 +Wire Wire Line + 7350 11700 8550 11700 +Wire Wire Line + 7350 11150 11450 11150 +Wire Wire Line + 8850 11150 8850 11500 +Connection ~ 7350 11700 +Wire Wire Line + 8850 11900 8850 14400 +Connection ~ 8850 14400 +Wire Wire Line + 8950 11850 8950 14400 +Connection ~ 8950 14400 +Wire Wire Line + 10400 11700 12400 11700 +Wire Wire Line + 10100 11900 10100 12400 +Wire Wire Line + 10000 12400 12800 12400 +Wire Wire Line + 12700 12400 12700 11900 +Wire Wire Line + 11450 12750 11450 12400 +Connection ~ 11450 12400 +Wire Wire Line + 10100 11150 10100 11500 +Connection ~ 8850 11150 +Wire Wire Line + 11450 11150 11450 12000 +Connection ~ 11450 11700 +Connection ~ 10100 11150 +Wire Wire Line + 11450 13150 11450 14400 +Connection ~ 11450 14400 +Wire Wire Line + 11350 13100 11350 14400 +Connection ~ 11350 14400 +Wire Wire Line + 10000 11850 10000 12400 +Connection ~ 10100 12400 +Wire Wire Line + 12800 12400 12800 11850 +Connection ~ 12700 12400 +$Comp +L eSim_MOS_N M13 +U 1 1 68598199 +P 15050 11500 +F 0 "M13" H 15050 11350 50 0000 R CNN +F 1 "eSim_MOS_N" H 15150 11450 50 0000 R CNN +F 2 "" H 15350 11200 29 0000 C CNN +F 3 "" H 15150 11300 60 0000 C CNN + 1 15050 11500 + -1 0 0 -1 +$EndComp +Wire Wire Line + 12700 11500 12700 11250 +Wire Wire Line + 12400 11250 14850 11250 +Wire Wire Line + 14850 11250 14850 11500 +Wire Wire Line + 14850 11900 14850 14400 +Connection ~ 14850 14400 +Wire Wire Line + 14750 11850 14750 14400 +Connection ~ 14750 14400 +Wire Wire Line + 11450 12000 15650 12000 +Wire Wire Line + 15650 12000 15650 11700 +Wire Wire Line + 15150 11700 18600 11700 +$Comp +L eSim_MOS_N M15 +U 1 1 68598842 +P 18700 11500 +F 0 "M15" H 18700 11350 50 0000 R CNN +F 1 "eSim_MOS_N" H 18800 11450 50 0000 R CNN +F 2 "" H 19000 11200 29 0000 C CNN +F 3 "" H 18800 11300 60 0000 C CNN + 1 18700 11500 + 1 0 0 -1 +$EndComp +Connection ~ 15650 11700 +Wire Wire Line + 18900 11900 18900 14400 +Connection ~ 18900 14400 +Wire Wire Line + 19000 11850 19000 14400 +Connection ~ 19000 14400 +$Comp +L eSim_MOS_N M18 +U 1 1 68598CA3 +P 22300 11500 +F 0 "M18" H 22300 11350 50 0000 R CNN +F 1 "eSim_MOS_N" H 22400 11450 50 0000 R CNN +F 2 "" H 22600 11200 29 0000 C CNN +F 3 "" H 22400 11300 60 0000 C CNN + 1 22300 11500 + -1 0 0 -1 +$EndComp +Wire Wire Line + 22100 11900 22100 14400 +Connection ~ 22100 14400 +Wire Wire Line + 22000 11850 22000 14400 +Connection ~ 22000 14400 +$Comp +L eSim_MOS_N M19 +U 1 1 68599072 +P 24850 11500 +F 0 "M19" H 24850 11350 50 0000 R CNN +F 1 "eSim_MOS_N" H 24950 11450 50 0000 R CNN +F 2 "" H 25150 11200 29 0000 C CNN +F 3 "" H 24950 11300 60 0000 C CNN + 1 24850 11500 + 1 0 0 -1 +$EndComp +Wire Wire Line + 25050 11900 25050 14400 +Connection ~ 25050 14400 +Wire Wire Line + 25150 11850 25150 14400 +Connection ~ 25150 14400 +Wire Wire Line + 22400 11700 24750 11700 +$Comp +L resistor R7 +U 1 1 685995FF +P 16100 14950 +F 0 "R7" H 16150 15080 50 0000 C CNN +F 1 "470k" H 16150 14900 50 0000 C CNN +F 2 "" H 16150 14930 30 0000 C CNN +F 3 "" V 16150 15000 30 0000 C CNN + 1 16100 14950 + 0 1 1 0 +$EndComp +$Comp +L resistor R5 +U 1 1 68599992 +P 10500 3200 +F 0 "R5" H 10550 3330 50 0000 C CNN +F 1 "900k" H 10550 3150 50 0000 C CNN +F 2 "" H 10550 3180 30 0000 C CNN +F 3 "" V 10550 3250 30 0000 C CNN + 1 10500 3200 + 0 1 1 0 +$EndComp +$Comp +L resistor R6 +U 1 1 68599B69 +P 10500 4350 +F 0 "R6" H 10550 4480 50 0000 C CNN +F 1 "100k" H 10550 4300 50 0000 C CNN +F 2 "" H 10550 4330 30 0000 C CNN +F 3 "" V 10550 4400 30 0000 C CNN + 1 10500 4350 + 0 1 1 0 +$EndComp +$Comp +L eSim_MOS_P M8 +U 1 1 68599C9A +P 10700 5450 +F 0 "M8" H 10650 5500 50 0000 R CNN +F 1 "eSim_MOS_P" H 10750 5600 50 0000 R CNN +F 2 "" H 10950 5550 29 0000 C CNN +F 3 "" H 10750 5450 60 0000 C CNN + 1 10700 5450 + -1 0 0 1 +$EndComp +Wire Wire Line + 10550 5650 10550 11150 +Connection ~ 10550 11150 +Wire Wire Line + 10550 5250 10550 4550 +Wire Wire Line + 10550 4250 10550 3400 +Wire Wire Line + 10550 3100 10550 2650 +Connection ~ 10550 2650 +$Comp +L eSim_MOS_P M11 +U 1 1 6859A1ED +P 12250 5400 +F 0 "M11" H 12200 5450 50 0000 R CNN +F 1 "eSim_MOS_P" H 12300 5550 50 0000 R CNN +F 2 "" H 12500 5500 29 0000 C CNN +F 3 "" H 12300 5400 60 0000 C CNN + 1 12250 5400 + 1 0 0 1 +$EndComp +Wire Wire Line + 10850 5450 12100 5450 +Wire Wire Line + 12100 5450 12100 5400 +Wire Wire Line + 12400 5600 12400 11250 +Connection ~ 12700 11250 +Wire Wire Line + 11450 5450 11450 6550 +Wire Wire Line + 11450 6550 12400 6550 +Connection ~ 12400 6550 +Connection ~ 11450 5450 +Wire Wire Line + 10450 5300 10450 5150 +Wire Wire Line + 10450 5150 10550 5150 +Connection ~ 10550 5150 +Wire Wire Line + 12400 5200 12400 2650 +Connection ~ 12400 2650 +Wire Wire Line + 12500 5250 12500 5050 +Wire Wire Line + 12500 5050 12400 5050 +Connection ~ 12400 5050 +$Comp +L eSim_MOS_P M9 +U 1 1 6859AB95 +P 11600 3450 +F 0 "M9" H 11550 3500 50 0000 R CNN +F 1 "eSim_MOS_P" H 11650 3600 50 0000 R CNN +F 2 "" H 11850 3550 29 0000 C CNN +F 3 "" H 11650 3450 60 0000 C CNN + 1 11600 3450 + -1 0 0 1 +$EndComp +Wire Wire Line + 11450 3650 11450 3800 +Wire Wire Line + 11450 3800 10550 3800 +Connection ~ 10550 3800 +Wire Wire Line + 11450 3250 11450 2650 +Connection ~ 11450 2650 +Wire Wire Line + 11350 3300 11350 3050 +Wire Wire Line + 11350 3050 11450 3050 +Connection ~ 11450 3050 +Wire Wire Line + 16150 14850 16150 3450 +Wire Wire Line + 16150 3450 11750 3450 +Wire Wire Line + 16150 15150 16150 15600 +Wire Wire Line + 11750 12950 16150 12950 +Connection ~ 16150 12950 +$Comp +L eSim_MOS_P M14 +U 1 1 6859B9E9 +P 18500 4400 +F 0 "M14" H 18450 4450 50 0000 R CNN +F 1 "eSim_MOS_P" H 18550 4550 50 0000 R CNN +F 2 "" H 18750 4500 29 0000 C CNN +F 3 "" H 18550 4400 60 0000 C CNN + 1 18500 4400 + 1 0 0 1 +$EndComp +Wire Wire Line + 18900 11500 18900 5000 +Wire Wire Line + 18650 5000 19250 5000 +Wire Wire Line + 18650 5000 18650 4600 +$Comp +L eSim_MOS_P M16 +U 1 1 6859C510 +P 19400 4400 +F 0 "M16" H 19350 4450 50 0000 R CNN +F 1 "eSim_MOS_P" H 19450 4550 50 0000 R CNN +F 2 "" H 19650 4500 29 0000 C CNN +F 3 "" H 19450 4400 60 0000 C CNN + 1 19400 4400 + -1 0 0 1 +$EndComp +Wire Wire Line + 19250 5000 19250 4600 +Connection ~ 18900 5000 +Wire Wire Line + 19250 4200 19250 3750 +Wire Wire Line + 19250 3750 18650 3750 +Wire Wire Line + 18650 3750 18650 4200 +Wire Wire Line + 18750 4250 18750 3900 +Wire Wire Line + 18750 3900 18650 3900 +Connection ~ 18650 3900 +Wire Wire Line + 19150 4250 19150 3900 +Wire Wire Line + 19150 3900 19250 3900 +Connection ~ 19250 3900 +Wire Wire Line + 18950 3750 18950 2650 +Connection ~ 18950 2650 +Connection ~ 18950 3750 +$Comp +L eSim_MOS_P M20 +U 1 1 6859CA78 +P 24900 5450 +F 0 "M20" H 24850 5500 50 0000 R CNN +F 1 "eSim_MOS_P" H 24950 5600 50 0000 R CNN +F 2 "" H 25150 5550 29 0000 C CNN +F 3 "" H 24950 5450 60 0000 C CNN + 1 24900 5450 + 1 0 0 1 +$EndComp +Wire Wire Line + 25050 11500 25050 5650 +Wire Wire Line + 25050 5250 25050 2650 +Connection ~ 25050 2650 +Wire Wire Line + 25150 5300 25150 5100 +Wire Wire Line + 25150 5100 25050 5100 +Connection ~ 25050 5100 +Wire Wire Line + 5000 6700 24550 6700 +Wire Wire Line + 24550 6700 24550 5450 +Wire Wire Line + 24550 5450 24750 5450 +Connection ~ 5000 6700 +Wire Wire Line + 18350 4400 17350 4400 +Wire Wire Line + 17350 4400 17350 6700 +Connection ~ 17350 6700 +$Comp +L eSim_MOS_P M17 +U 1 1 6859DCC7 +P 21950 4400 +F 0 "M17" H 21900 4450 50 0000 R CNN +F 1 "eSim_MOS_P" H 22000 4550 50 0000 R CNN +F 2 "" H 22200 4500 29 0000 C CNN +F 3 "" H 22000 4400 60 0000 C CNN + 1 21950 4400 + 1 0 0 1 +$EndComp +Wire Wire Line + 22100 11500 22100 4600 +Wire Wire Line + 22100 4200 22100 2650 +Connection ~ 22100 2650 +Wire Wire Line + 22200 4250 22200 4000 +Wire Wire Line + 22200 4000 22100 4000 +Connection ~ 22100 4000 +Wire Wire Line + 19550 4400 21800 4400 +Wire Wire Line + 20600 4400 20600 5900 +Wire Wire Line + 20600 5900 18900 5900 +Connection ~ 18900 5900 +Connection ~ 20600 4400 +$Comp +L capacitor C1 +U 1 1 6859EBA0 +P 23200 7550 +F 0 "C1" H 23225 7650 50 0000 L CNN +F 1 "9p" H 23225 7450 50 0000 L CNN +F 2 "" H 23238 7400 30 0000 C CNN +F 3 "" H 23200 7550 60 0000 C CNN + 1 23200 7550 + 0 1 1 0 +$EndComp +Wire Wire Line + 23600 7550 23350 7550 +Wire Wire Line + 23600 4450 23600 7550 +Connection ~ 23600 6700 +Wire Wire Line + 23050 7550 22100 7550 +Connection ~ 22100 7550 +$Comp +L eSim_Diode D7 +U 1 1 6859F3FA +P 23600 4300 +F 0 "D7" H 23600 4400 50 0000 C CNN +F 1 "eSim_Diode" H 23600 4200 50 0000 C CNN +F 2 "" H 23600 4300 60 0000 C CNN +F 3 "" H 23600 4300 60 0000 C CNN + 1 23600 4300 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 23600 4150 23600 2650 +Connection ~ 23600 2650 +Wire Wire Line + 20500 6700 20500 9050 +Wire Wire Line + 20500 9050 23100 9050 +Connection ~ 20500 6700 +$Comp +L capacitor C2 +U 1 1 6859F985 +P 23250 9050 +F 0 "C2" H 23275 9150 50 0000 L CNN +F 1 "33p" H 23275 8950 50 0000 L CNN +F 2 "" H 23288 8900 30 0000 C CNN +F 3 "" H 23250 9050 60 0000 C CNN + 1 23250 9050 + 0 1 1 0 +$EndComp +Connection ~ 25050 9050 +Wire Wire Line + 22100 10100 23550 10100 +Wire Wire Line + 23550 10100 23550 12800 +Connection ~ 23550 11700 +Connection ~ 22100 10100 +$Comp +L eSim_Diode D6 +U 1 1 685A0135 +P 23550 12950 +F 0 "D6" H 23550 13050 50 0000 C CNN +F 1 "eSim_Diode" H 23550 12850 50 0000 C CNN +F 2 "" H 23550 12950 60 0000 C CNN +F 3 "" H 23550 12950 60 0000 C CNN + 1 23550 12950 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 23550 13100 23550 14400 +Connection ~ 23550 14400 +Wire Wire Line + 6900 7000 6900 10000 +Wire Wire Line + 4700 7050 3600 7050 +Wire Wire Line + 6900 7000 6850 7000 +Wire Wire Line + 6450 7150 6450 7450 +Wire Wire Line + 6450 7450 6550 7450 +Connection ~ 6550 7450 +Wire Wire Line + 5100 7200 5100 7550 +Wire Wire Line + 5100 7550 5000 7550 +Connection ~ 5000 7550 +Wire Wire Line + 15450 15600 16800 15600 +Connection ~ 16150 15600 +$Comp +L eSim_Diode D5 +U 1 1 685A1C84 +P 15300 15600 +F 0 "D5" H 15300 15700 50 0000 C CNN +F 1 "eSim_Diode" H 15300 15500 50 0000 C CNN +F 2 "" H 15300 15600 60 0000 C CNN +F 3 "" H 15300 15600 60 0000 C CNN + 1 15300 15600 + -1 0 0 1 +$EndComp +Wire Wire Line + 15150 15600 14550 15600 +$Comp +L eSim_Diode D3 +U 1 1 685A2164 +P 3000 9450 +F 0 "D3" H 3000 9550 50 0000 C CNN +F 1 "eSim_Diode" H 3000 9350 50 0000 C CNN +F 2 "" H 3000 9450 60 0000 C CNN +F 3 "" H 3000 9450 60 0000 C CNN + 1 3000 9450 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_Diode D4 +U 1 1 685A221F +P 3000 10650 +F 0 "D4" H 3000 10750 50 0000 C CNN +F 1 "eSim_Diode" H 3000 10550 50 0000 C CNN +F 2 "" H 3000 10650 60 0000 C CNN +F 3 "" H 3000 10650 60 0000 C CNN + 1 3000 10650 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 3000 9600 3000 10500 +Connection ~ 3000 10000 +Wire Wire Line + 3000 9300 3000 9100 +Wire Wire Line + 3000 9100 2800 9100 +Wire Wire Line + 3000 10800 3000 11000 +Wire Wire Line + 3000 11000 2800 11000 +Wire Wire Line + 2800 11000 2800 14400 +Connection ~ 5700 14400 +$Comp +L resistor R1 +U 1 1 685A2EB7 +P 3400 7100 +F 0 "R1" H 3450 7230 50 0000 C CNN +F 1 "10k" H 3450 7050 50 0000 C CNN +F 2 "" H 3450 7080 30 0000 C CNN +F 3 "" V 3450 7150 30 0000 C CNN + 1 3400 7100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3300 7050 1400 7050 +Wire Wire Line + 1400 7050 1400 6950 +$Comp +L eSim_Diode D1 +U 1 1 685A3192 +P 2500 6550 +F 0 "D1" H 2500 6650 50 0000 C CNN +F 1 "eSim_Diode" H 2500 6450 50 0000 C CNN +F 2 "" H 2500 6550 60 0000 C CNN +F 3 "" H 2500 6550 60 0000 C CNN + 1 2500 6550 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_Diode D2 +U 1 1 685A329F +P 2500 7450 +F 0 "D2" H 2500 7550 50 0000 C CNN +F 1 "eSim_Diode" H 2500 7350 50 0000 C CNN +F 2 "" H 2500 7450 60 0000 C CNN +F 3 "" H 2500 7450 60 0000 C CNN + 1 2500 7450 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 2500 6700 2500 7300 +Connection ~ 2500 7050 +Wire Wire Line + 2500 7600 2500 8450 +Wire Wire Line + 2500 8450 4050 8450 +Wire Wire Line + 4050 8450 4050 14400 +Connection ~ 4050 14400 +Wire Wire Line + 2500 6400 2500 2650 +Connection ~ 5000 2650 +Wire Wire Line + 2800 9100 2800 2650 +Connection ~ 2800 2650 +Wire Wire Line + 14550 15600 14550 17000 +Wire Wire Line + 14550 17000 27000 17000 +Wire Wire Line + 27000 17000 27000 2650 +Connection ~ 27000 2650 +$Comp +L resistor R2 +U 1 1 685A5751 +P 4900 10100 +F 0 "R2" H 4950 10230 50 0000 C CNN +F 1 "10k" H 4950 10050 50 0000 C CNN +F 2 "" H 4950 10080 30 0000 C CNN +F 3 "" V 4950 10150 30 0000 C CNN + 1 4900 10100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6900 10000 5100 10000 +Wire Wire Line + 5100 10000 5100 10050 +Wire Wire Line + 3150 10050 4800 10050 +Wire Wire Line + 3150 10000 3150 10050 +Wire Wire Line + 1300 10000 3150 10000 +Wire Wire Line + 1300 10000 1300 9900 +$Comp +L PORT U1 +U 3 1 685A6C2B +P 1150 6950 +F 0 "U1" H 1200 7050 30 0000 C CNN +F 1 "PORT" H 1150 6950 30 0000 C CNN +F 2 "" H 1150 6950 60 0000 C CNN +F 3 "" H 1150 6950 60 0000 C CNN + 3 1150 6950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 685A6E1C +P 1050 9900 +F 0 "U1" H 1100 10000 30 0000 C CNN +F 1 "PORT" H 1050 9900 30 0000 C CNN +F 2 "" H 1050 9900 60 0000 C CNN +F 3 "" H 1050 9900 60 0000 C CNN + 2 1050 9900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 685A70A1 +P 3050 5150 +F 0 "U1" H 3100 5250 30 0000 C CNN +F 1 "PORT" H 3050 5150 30 0000 C CNN +F 2 "" H 3050 5150 60 0000 C CNN +F 3 "" H 3050 5150 60 0000 C CNN + 1 3050 5150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 685A7658 +P 17050 15600 +F 0 "U1" H 17100 15700 30 0000 C CNN +F 1 "PORT" H 17050 15600 30 0000 C CNN +F 2 "" H 17050 15600 60 0000 C CNN +F 3 "" H 17050 15600 60 0000 C CNN + 8 17050 15600 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 7 1 685A7793 +P 29300 2650 +F 0 "U1" H 29350 2750 30 0000 C CNN +F 1 "PORT" H 29300 2650 30 0000 C CNN +F 2 "" H 29300 2650 60 0000 C CNN +F 3 "" H 29300 2650 60 0000 C CNN + 7 29300 2650 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 4 1 685A7DD7 +P 29150 14400 +F 0 "U1" H 29200 14500 30 0000 C CNN +F 1 "PORT" H 29150 14400 30 0000 C CNN +F 2 "" H 29150 14400 60 0000 C CNN +F 3 "" H 29150 14400 60 0000 C CNN + 4 29150 14400 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 6 1 685A856C +P 27800 9050 +F 0 "U1" H 27850 9150 30 0000 C CNN +F 1 "PORT" H 27800 9050 30 0000 C CNN +F 2 "" H 27800 9050 60 0000 C CNN +F 3 "" H 27800 9050 60 0000 C CNN + 6 27800 9050 + -1 0 0 1 +$EndComp +Text Label 3600 5200 0 60 ~ 0 +Bal +Text Label 1700 7050 0 60 ~ 0 +Input+ +Text Label 1550 10000 0 60 ~ 0 +Input- +Wire Wire Line + 23400 9050 27550 9050 +Text Label 27150 9050 0 60 ~ 0 +Out +Text Label 28600 2650 0 60 ~ 0 +V+ +Text Label 28750 14400 0 60 ~ 0 +V- +Text Label 16600 15600 0 60 ~ 0 +Iqset +Wire Wire Line + 6550 5150 7200 5150 +Connection ~ 6550 5150 +$Comp +L PORT U1 +U 5 1 685ACDAE +P 7450 5150 +F 0 "U1" H 7500 5250 30 0000 C CNN +F 1 "PORT" H 7450 5150 30 0000 C CNN +F 2 "" H 7450 5150 60 0000 C CNN +F 3 "" H 7450 5150 60 0000 C CNN + 5 7450 5150 + -1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/ICL7611/ICL7611.sub b/library/SubcircuitLibrary/ICL7611/ICL7611.sub new file mode 100644 index 000000000..37d210aa0 --- /dev/null +++ b/library/SubcircuitLibrary/ICL7611/ICL7611.sub @@ -0,0 +1,46 @@ +* Subcircuit ICL7611 +.subckt ICL7611 /bal /input- /input+ /v- net-_m4-pad3_ /out /v+ /iqset +* c:\fossee\esim\library\subcircuitlibrary\icl7611\icl7611.cir +.include NMOS-5um.lib +.include ZenerD1N750.lib +.include D.lib +.include PMOS-5um.lib +m2 net-_c1-pad1_ net-_m2-pad2_ /bal /bal mos_p W=100u L=100u M=1 +m4 net-_m2-pad2_ net-_m2-pad2_ net-_m4-pad3_ net-_m4-pad3_ mos_p W=100u L=100u M=1 +r3 /v+ /bal 3k +r4 /v+ net-_m4-pad3_ 3k +m1 net-_c1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad3_ mos_n W=100u L=100u M=1 +m5 net-_m2-pad2_ net-_m5-pad2_ net-_m1-pad3_ net-_m1-pad3_ mos_n W=100u L=100u M=1 +m3 net-_m1-pad3_ net-_m12-pad2_ /v- /v- mos_n W=100u L=100u M=1 +m6 net-_m12-pad2_ net-_m12-pad2_ /v- /v- mos_n W=100u L=100u M=1 +m7 net-_m12-pad2_ net-_m12-pad2_ net-_m10-pad1_ net-_m10-pad1_ mos_n W=100u L=100u M=1 +m10 net-_m10-pad1_ net-_m10-pad2_ /v- /v- mos_n W=100u L=100u M=1 +m12 net-_m11-pad1_ net-_m12-pad2_ net-_m10-pad1_ net-_m10-pad1_ mos_n W=100u L=100u M=1 +m13 net-_m11-pad1_ net-_m12-pad2_ /v- /v- mos_n W=100u L=100u M=1 +m15 net-_m14-pad1_ net-_m12-pad2_ /v- /v- mos_n W=100u L=100u M=1 +m18 net-_c1-pad2_ net-_c1-pad2_ /v- /v- mos_n W=100u L=100u M=1 +m19 /out net-_c1-pad2_ /v- /v- mos_n W=100u L=100u M=1 +r7 net-_m10-pad2_ /iqset 470k +r5 /v+ net-_m9-pad1_ 900k +r6 net-_m9-pad1_ net-_m8-pad3_ 100k +m8 net-_m12-pad2_ net-_m11-pad1_ net-_m8-pad3_ net-_m8-pad3_ mos_p W=100u L=100u M=1 +m11 net-_m11-pad1_ net-_m11-pad1_ /v+ /v+ mos_p W=100u L=100u M=1 +m9 net-_m9-pad1_ net-_m10-pad2_ /v+ /v+ mos_p W=100u L=100u M=1 +m14 net-_m14-pad1_ net-_c1-pad1_ /v+ /v+ mos_p W=100u L=100u M=1 +m16 net-_m14-pad1_ net-_m14-pad1_ /v+ /v+ mos_p W=100u L=100u M=1 +m20 /out net-_c1-pad1_ /v+ /v+ mos_p W=100u L=100u M=1 +m17 net-_c1-pad2_ net-_m14-pad1_ /v+ /v+ mos_p W=100u L=100u M=1 +c1 net-_c1-pad1_ net-_c1-pad2_ 9p +d7 net-_c1-pad1_ /v+ D1N750 +c2 /out net-_c1-pad1_ 33p +d6 /v- net-_c1-pad2_ D1N750 +d5 /iqset /v+ 1N4148 +d3 /input- /v+ 1N4148 +d4 /v- /input- 1N4148 +r1 /input+ net-_m1-pad2_ 10k +d1 /input+ /v+ 1N4148 +d2 /v- /input+ 1N4148 +r2 /input- net-_m5-pad2_ 10k +* Control Statements + +.ends ICL7611 \ No newline at end of file diff --git a/library/SubcircuitLibrary/ICL7611/ICL7611_Previous_Values.xml b/library/SubcircuitLibrary/ICL7611/ICL7611_Previous_Values.xml new file mode 100644 index 000000000..6023b1471 --- /dev/null +++ b/library/SubcircuitLibrary/ICL7611/ICL7611_Previous_Values.xml @@ -0,0 +1 @@ +C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\ZenerD1N750.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\ZenerD1N750.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec \ No newline at end of file diff --git a/library/SubcircuitLibrary/ICL7611/NMOS-5um.lib b/library/SubcircuitLibrary/ICL7611/NMOS-5um.lib new file mode 100644 index 000000000..a237e1fe3 --- /dev/null +++ b/library/SubcircuitLibrary/ICL7611/NMOS-5um.lib @@ -0,0 +1,5 @@ +* 5um technology + +.model mos_n NMOS( Cgso=0.4n Tox=85n Vto=1 phi=0.7 ++ Level=1 ++ Mj=.5 UO=750 Cgdo=0.4n Gamma=1.4 LAMBDA=0.01 LD=0.7u JS=1u CJ=0.4m CJSW=0.8n MJSW=0.5 PB=0.7 CGBO=0.2n ) diff --git a/library/SubcircuitLibrary/ICL7611/PMOS-5um.lib b/library/SubcircuitLibrary/ICL7611/PMOS-5um.lib new file mode 100644 index 000000000..9c3ed9760 --- /dev/null +++ b/library/SubcircuitLibrary/ICL7611/PMOS-5um.lib @@ -0,0 +1,5 @@ +*5um technology + +.model mos_p PMOS( Cgso=0.4n Tox=85n Vto=-1 phi=0.65 ++ Level=1 ++ Mj=.5 UO=250 Cgdo=0.4n Gamma=0.65 LAMBDA=0.03 LD=0.6u JS=1u CJ=0.18m CJSW=0.6n MJSW=0.5 PB=0.7 CGBO=0.2n ) diff --git a/library/SubcircuitLibrary/ICL7611/ZenerD1N750.lib b/library/SubcircuitLibrary/ICL7611/ZenerD1N750.lib new file mode 100644 index 000000000..890c37fe2 --- /dev/null +++ b/library/SubcircuitLibrary/ICL7611/ZenerD1N750.lib @@ -0,0 +1,3 @@ +.model D1N750 D( Is=880.5E-18 Rs=.25 Ikf=0 N=1 Xti=3 Eg=1.11 Cjo=175p M=.5516 ++ Vj=.75 Fc=.5 Isr=1.859n Nr=2 Bv=8.1 Ibv=20.245m Nbv=1.6989 Ibvl=1.9556m ++ Nbvl=14.976 Tbv1=-21.277u) diff --git a/library/SubcircuitLibrary/ICL7611/analysis b/library/SubcircuitLibrary/ICL7611/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/SubcircuitLibrary/ICL7611/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/library/SubcircuitLibrary/L702/L702-cache.lib b/library/SubcircuitLibrary/L702/L702-cache.lib new file mode 100644 index 000000000..1568691ef --- /dev/null +++ b/library/SubcircuitLibrary/L702/L702-cache.lib @@ -0,0 +1,83 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/L702/L702.bak b/library/SubcircuitLibrary/L702/L702.bak new file mode 100644 index 000000000..9325922b3 --- /dev/null +++ b/library/SubcircuitLibrary/L702/L702.bak @@ -0,0 +1,624 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L resistor R2 +U 1 1 685BADF2 +P 1800 1650 +F 0 "R2" H 1850 1780 50 0000 C CNN +F 1 "340" H 1850 1600 50 0000 C CNN +F 2 "" H 1850 1630 30 0000 C CNN +F 3 "" V 1850 1700 30 0000 C CNN + 1 1800 1650 + 1 0 0 -1 +$EndComp +$Comp +L resistor R4 +U 1 1 685BAE4F +P 2700 2150 +F 0 "R4" H 2750 2280 50 0000 C CNN +F 1 "7k" H 2750 2100 50 0000 C CNN +F 2 "" H 2750 2130 30 0000 C CNN +F 3 "" V 2750 2200 30 0000 C CNN + 1 2700 2150 + 1 0 0 -1 +$EndComp +$Comp +L resistor R6 +U 1 1 685BAE96 +P 3250 2800 +F 0 "R6" H 3300 2930 50 0000 C CNN +F 1 "500" H 3300 2750 50 0000 C CNN +F 2 "" H 3300 2780 30 0000 C CNN +F 3 "" V 3300 2850 30 0000 C CNN + 1 3250 2800 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q2 +U 1 1 685BAEF9 +P 3250 1600 +F 0 "Q2" H 3150 1650 50 0000 R CNN +F 1 "eSim_NPN" H 3200 1750 50 0000 R CNN +F 2 "" H 3450 1700 29 0000 C CNN +F 3 "" H 3250 1600 60 0000 C CNN + 1 3250 1600 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q4 +U 1 1 685BAF52 +P 3950 2100 +F 0 "Q4" H 3850 2150 50 0000 R CNN +F 1 "eSim_NPN" H 3900 2250 50 0000 R CNN +F 2 "" H 4150 2200 29 0000 C CNN +F 3 "" H 3950 2100 60 0000 C CNN + 1 3950 2100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2000 1600 3050 1600 +Wire Wire Line + 2600 2100 2350 2100 +Wire Wire Line + 2350 2100 2350 1600 +Connection ~ 2350 1600 +Wire Wire Line + 2900 2100 3750 2100 +Wire Wire Line + 3350 1800 3350 2150 +Wire Wire Line + 3300 2700 3300 2150 +Wire Wire Line + 3300 2150 3350 2150 +Connection ~ 3350 2100 +Wire Wire Line + 3300 3000 3300 3500 +Wire Wire Line + 4050 3500 4050 2300 +Wire Wire Line + 1700 1600 1350 1600 +Wire Wire Line + 4050 800 4050 1900 +Wire Wire Line + 4050 1250 3350 1250 +Wire Wire Line + 3350 1250 3350 1400 +Connection ~ 4050 1250 +$Comp +L resistor R8 +U 1 1 685BEA05 +P 5400 1600 +F 0 "R8" H 5450 1730 50 0000 C CNN +F 1 "340" H 5450 1550 50 0000 C CNN +F 2 "" H 5450 1580 30 0000 C CNN +F 3 "" V 5450 1650 30 0000 C CNN + 1 5400 1600 + 1 0 0 -1 +$EndComp +$Comp +L resistor R10 +U 1 1 685BEA0B +P 6300 2100 +F 0 "R10" H 6350 2230 50 0000 C CNN +F 1 "7k" H 6350 2050 50 0000 C CNN +F 2 "" H 6350 2080 30 0000 C CNN +F 3 "" V 6350 2150 30 0000 C CNN + 1 6300 2100 + 1 0 0 -1 +$EndComp +$Comp +L resistor R12 +U 1 1 685BEA11 +P 6850 2750 +F 0 "R12" H 6900 2880 50 0000 C CNN +F 1 "500" H 6900 2700 50 0000 C CNN +F 2 "" H 6900 2730 30 0000 C CNN +F 3 "" V 6900 2800 30 0000 C CNN + 1 6850 2750 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q6 +U 1 1 685BEA17 +P 6850 1550 +F 0 "Q6" H 6750 1600 50 0000 R CNN +F 1 "eSim_NPN" H 6800 1700 50 0000 R CNN +F 2 "" H 7050 1650 29 0000 C CNN +F 3 "" H 6850 1550 60 0000 C CNN + 1 6850 1550 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q8 +U 1 1 685BEA1D +P 7550 2050 +F 0 "Q8" H 7450 2100 50 0000 R CNN +F 1 "eSim_NPN" H 7500 2200 50 0000 R CNN +F 2 "" H 7750 2150 29 0000 C CNN +F 3 "" H 7550 2050 60 0000 C CNN + 1 7550 2050 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5600 1550 6650 1550 +Wire Wire Line + 6200 2050 5950 2050 +Wire Wire Line + 5950 2050 5950 1550 +Connection ~ 5950 1550 +Wire Wire Line + 6500 2050 7350 2050 +Wire Wire Line + 6950 1750 6950 2100 +Wire Wire Line + 6900 2650 6900 2100 +Wire Wire Line + 6900 2100 6950 2100 +Connection ~ 6950 2050 +Wire Wire Line + 6900 2950 6900 3450 +Wire Wire Line + 7650 3450 7650 2250 +Wire Wire Line + 5300 1550 4950 1550 +Wire Wire Line + 7650 750 7650 1850 +Wire Wire Line + 7650 1200 6950 1200 +Wire Wire Line + 6950 1200 6950 1350 +Connection ~ 7650 1200 +$Comp +L resistor R1 +U 1 1 685BEBBB +P 1750 5400 +F 0 "R1" H 1800 5530 50 0000 C CNN +F 1 "340" H 1800 5350 50 0000 C CNN +F 2 "" H 1800 5380 30 0000 C CNN +F 3 "" V 1800 5450 30 0000 C CNN + 1 1750 5400 + 1 0 0 -1 +$EndComp +$Comp +L resistor R3 +U 1 1 685BEBC1 +P 2650 5900 +F 0 "R3" H 2700 6030 50 0000 C CNN +F 1 "7k" H 2700 5850 50 0000 C CNN +F 2 "" H 2700 5880 30 0000 C CNN +F 3 "" V 2700 5950 30 0000 C CNN + 1 2650 5900 + 1 0 0 -1 +$EndComp +$Comp +L resistor R5 +U 1 1 685BEBC7 +P 3200 6550 +F 0 "R5" H 3250 6680 50 0000 C CNN +F 1 "500" H 3250 6500 50 0000 C CNN +F 2 "" H 3250 6530 30 0000 C CNN +F 3 "" V 3250 6600 30 0000 C CNN + 1 3200 6550 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q1 +U 1 1 685BEBCD +P 3200 5350 +F 0 "Q1" H 3100 5400 50 0000 R CNN +F 1 "eSim_NPN" H 3150 5500 50 0000 R CNN +F 2 "" H 3400 5450 29 0000 C CNN +F 3 "" H 3200 5350 60 0000 C CNN + 1 3200 5350 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q3 +U 1 1 685BEBD3 +P 3900 5850 +F 0 "Q3" H 3800 5900 50 0000 R CNN +F 1 "eSim_NPN" H 3850 6000 50 0000 R CNN +F 2 "" H 4100 5950 29 0000 C CNN +F 3 "" H 3900 5850 60 0000 C CNN + 1 3900 5850 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1950 5350 3000 5350 +Wire Wire Line + 2550 5850 2300 5850 +Wire Wire Line + 2300 5850 2300 5350 +Connection ~ 2300 5350 +Wire Wire Line + 2850 5850 3700 5850 +Wire Wire Line + 3300 5550 3300 5900 +Wire Wire Line + 3250 6450 3250 5900 +Wire Wire Line + 3250 5900 3300 5900 +Connection ~ 3300 5850 +Wire Wire Line + 3250 6750 3250 7250 +Wire Wire Line + 4000 7250 4000 6050 +Wire Wire Line + 1650 5350 1300 5350 +Wire Wire Line + 4000 4550 4000 5650 +Wire Wire Line + 4000 5000 3300 5000 +Wire Wire Line + 3300 5000 3300 5150 +Connection ~ 4000 5000 +$Comp +L resistor R7 +U 1 1 685BEBEB +P 5350 5350 +F 0 "R7" H 5400 5480 50 0000 C CNN +F 1 "340" H 5400 5300 50 0000 C CNN +F 2 "" H 5400 5330 30 0000 C CNN +F 3 "" V 5400 5400 30 0000 C CNN + 1 5350 5350 + 1 0 0 -1 +$EndComp +$Comp +L resistor R9 +U 1 1 685BEBF1 +P 6250 5850 +F 0 "R9" H 6300 5980 50 0000 C CNN +F 1 "7k" H 6300 5800 50 0000 C CNN +F 2 "" H 6300 5830 30 0000 C CNN +F 3 "" V 6300 5900 30 0000 C CNN + 1 6250 5850 + 1 0 0 -1 +$EndComp +$Comp +L resistor R11 +U 1 1 685BEBF7 +P 6800 6500 +F 0 "R11" H 6850 6630 50 0000 C CNN +F 1 "500" H 6850 6450 50 0000 C CNN +F 2 "" H 6850 6480 30 0000 C CNN +F 3 "" V 6850 6550 30 0000 C CNN + 1 6800 6500 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q5 +U 1 1 685BEBFD +P 6800 5300 +F 0 "Q5" H 6700 5350 50 0000 R CNN +F 1 "eSim_NPN" H 6750 5450 50 0000 R CNN +F 2 "" H 7000 5400 29 0000 C CNN +F 3 "" H 6800 5300 60 0000 C CNN + 1 6800 5300 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q7 +U 1 1 685BEC03 +P 7500 5800 +F 0 "Q7" H 7400 5850 50 0000 R CNN +F 1 "eSim_NPN" H 7450 5950 50 0000 R CNN +F 2 "" H 7700 5900 29 0000 C CNN +F 3 "" H 7500 5800 60 0000 C CNN + 1 7500 5800 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5550 5300 6600 5300 +Wire Wire Line + 6150 5800 5900 5800 +Wire Wire Line + 5900 5800 5900 5300 +Connection ~ 5900 5300 +Wire Wire Line + 6450 5800 7300 5800 +Wire Wire Line + 6900 5500 6900 5850 +Wire Wire Line + 6850 6400 6850 5850 +Wire Wire Line + 6850 5850 6900 5850 +Connection ~ 6900 5800 +Wire Wire Line + 6850 7250 6850 6700 +Wire Wire Line + 7600 7250 7600 6000 +Wire Wire Line + 5250 5300 4900 5300 +Wire Wire Line + 7600 4500 7600 5600 +Wire Wire Line + 7600 4950 6900 4950 +Wire Wire Line + 6900 4950 6900 5100 +Connection ~ 7600 4950 +Wire Wire Line + 3250 7250 9400 7250 +Connection ~ 4000 7250 +Connection ~ 6850 7250 +Wire Wire Line + 9400 7250 9400 3450 +Wire Wire Line + 4200 3450 9650 3450 +Connection ~ 7600 7250 +Connection ~ 7650 3450 +Wire Wire Line + 4200 3450 4200 3500 +Wire Wire Line + 4200 3500 3300 3500 +Connection ~ 6900 3450 +Connection ~ 4050 3500 +Connection ~ 9400 3450 +Wire Wire Line + 9400 3650 9650 3650 +Connection ~ 9400 3650 +Wire Wire Line + 9400 3850 9650 3850 +Connection ~ 9400 3850 +Wire Wire Line + 9400 4050 9650 4050 +Connection ~ 9400 4050 +Wire Wire Line + 9400 4300 9650 4300 +Connection ~ 9400 4300 +Wire Wire Line + 9400 4550 9650 4550 +Connection ~ 9400 4550 +Text Label 1500 1600 0 60 ~ 0 +B1 +Text Label 1450 5350 0 60 ~ 0 +B2 +Text Label 5100 5300 0 60 ~ 0 +B3 +Text Label 5200 1550 0 60 ~ 0 +B4 +Text Label 4050 1050 0 60 ~ 0 +C1 +Text Label 4000 4800 0 60 ~ 0 +C2 +Text Label 7600 4750 0 60 ~ 0 +C3 +Text Label 7650 950 0 60 ~ 0 +C4 +$Comp +L PORT U1 +U 1 1 685C0791 +P 1100 1600 +F 0 "U1" H 1150 1700 30 0000 C CNN +F 1 "PORT" H 1100 1600 30 0000 C CNN +F 2 "" H 1100 1600 60 0000 C CNN +F 3 "" H 1100 1600 60 0000 C CNN + 1 1100 1600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 685C092E +P 1050 5350 +F 0 "U1" H 1100 5450 30 0000 C CNN +F 1 "PORT" H 1050 5350 30 0000 C CNN +F 2 "" H 1050 5350 60 0000 C CNN +F 3 "" H 1050 5350 60 0000 C CNN + 2 1050 5350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 685C0ADD +P 3800 800 +F 0 "U1" H 3850 900 30 0000 C CNN +F 1 "PORT" H 3800 800 30 0000 C CNN +F 2 "" H 3800 800 60 0000 C CNN +F 3 "" H 3800 800 60 0000 C CNN + 3 3800 800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 685C0D14 +P 3750 4550 +F 0 "U1" H 3800 4650 30 0000 C CNN +F 1 "PORT" H 3750 4550 30 0000 C CNN +F 2 "" H 3750 4550 60 0000 C CNN +F 3 "" H 3750 4550 60 0000 C CNN + 4 3750 4550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 685C101B +P 4700 1550 +F 0 "U1" H 4750 1650 30 0000 C CNN +F 1 "PORT" H 4700 1550 30 0000 C CNN +F 2 "" H 4700 1550 60 0000 C CNN +F 3 "" H 4700 1550 60 0000 C CNN + 8 4700 1550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 685C10B9 +P 7400 750 +F 0 "U1" H 7450 850 30 0000 C CNN +F 1 "PORT" H 7400 750 30 0000 C CNN +F 2 "" H 7400 750 60 0000 C CNN +F 3 "" H 7400 750 60 0000 C CNN + 6 7400 750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 685C12C6 +P 4650 5300 +F 0 "U1" H 4700 5400 30 0000 C CNN +F 1 "PORT" H 4650 5300 30 0000 C CNN +F 2 "" H 4650 5300 60 0000 C CNN +F 3 "" H 4650 5300 60 0000 C CNN + 7 4650 5300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 685C1552 +P 7350 4500 +F 0 "U1" H 7400 4600 30 0000 C CNN +F 1 "PORT" H 7350 4500 30 0000 C CNN +F 2 "" H 7350 4500 60 0000 C CNN +F 3 "" H 7350 4500 60 0000 C CNN + 5 7350 4500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 685C1705 +P 9900 3450 +F 0 "U1" H 9950 3550 30 0000 C CNN +F 1 "PORT" H 9900 3450 30 0000 C CNN +F 2 "" H 9900 3450 60 0000 C CNN +F 3 "" H 9900 3450 60 0000 C CNN + 9 9900 3450 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 10 1 685C1962 +P 9900 3650 +F 0 "U1" H 9950 3750 30 0000 C CNN +F 1 "PORT" H 9900 3650 30 0000 C CNN +F 2 "" H 9900 3650 60 0000 C CNN +F 3 "" H 9900 3650 60 0000 C CNN + 10 9900 3650 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 11 1 685C19D3 +P 9900 3850 +F 0 "U1" H 9950 3950 30 0000 C CNN +F 1 "PORT" H 9900 3850 30 0000 C CNN +F 2 "" H 9900 3850 60 0000 C CNN +F 3 "" H 9900 3850 60 0000 C CNN + 11 9900 3850 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 12 1 685C1A5C +P 9900 4050 +F 0 "U1" H 9950 4150 30 0000 C CNN +F 1 "PORT" H 9900 4050 30 0000 C CNN +F 2 "" H 9900 4050 60 0000 C CNN +F 3 "" H 9900 4050 60 0000 C CNN + 12 9900 4050 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 13 1 685C1AC1 +P 9900 4300 +F 0 "U1" H 9950 4400 30 0000 C CNN +F 1 "PORT" H 9900 4300 30 0000 C CNN +F 2 "" H 9900 4300 60 0000 C CNN +F 3 "" H 9900 4300 60 0000 C CNN + 13 9900 4300 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 14 1 685C1B2C +P 9900 4550 +F 0 "U1" H 9950 4650 30 0000 C CNN +F 1 "PORT" H 9900 4550 30 0000 C CNN +F 2 "" H 9900 4550 60 0000 C CNN +F 3 "" H 9900 4550 60 0000 C CNN + 14 9900 4550 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 15 1 685C2250 +P 9900 4850 +F 0 "U1" H 9950 4950 30 0000 C CNN +F 1 "PORT" H 9900 4850 30 0000 C CNN +F 2 "" H 9900 4850 60 0000 C CNN +F 3 "" H 9900 4850 60 0000 C CNN + 15 9900 4850 + -1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 16 1 685C22BD +P 9900 5150 +F 0 "U1" H 9950 5250 30 0000 C CNN +F 1 "PORT" H 9900 5150 30 0000 C CNN +F 2 "" H 9900 5150 60 0000 C CNN +F 3 "" H 9900 5150 60 0000 C CNN + 16 9900 5150 + -1 0 0 -1 +$EndComp +Wire Wire Line + 9650 4850 9400 4850 +Connection ~ 9400 4850 +Wire Wire Line + 9650 5150 9400 5150 +Connection ~ 9400 5150 +Text Label 8800 3450 0 60 ~ 0 +GND +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/L702/L702.cir b/library/SubcircuitLibrary/L702/L702.cir new file mode 100644 index 000000000..051251d86 --- /dev/null +++ b/library/SubcircuitLibrary/L702/L702.cir @@ -0,0 +1,31 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\L702\L702.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 07/03/25 23:21:56 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +R2 /B1 Net-_Q2-Pad2_ 340 +R4 Net-_Q2-Pad2_ Net-_Q2-Pad3_ 7k +R6 Net-_Q2-Pad3_ /GND 500 +Q2 /C1 Net-_Q2-Pad2_ Net-_Q2-Pad3_ eSim_NPN +Q4 /C1 Net-_Q2-Pad3_ /GND eSim_NPN +R8 /B4 Net-_Q6-Pad2_ 340 +R10 Net-_Q6-Pad2_ Net-_Q6-Pad3_ 7k +R12 Net-_Q6-Pad3_ /GND 500 +Q6 /C4 Net-_Q6-Pad2_ Net-_Q6-Pad3_ eSim_NPN +Q8 /C4 Net-_Q6-Pad3_ /GND eSim_NPN +R1 /B2 Net-_Q1-Pad2_ 340 +R3 Net-_Q1-Pad2_ Net-_Q1-Pad3_ 7k +R5 Net-_Q1-Pad3_ /GND 500 +Q1 /C2 Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_NPN +Q3 /C2 Net-_Q1-Pad3_ /GND eSim_NPN +R7 /B3 Net-_Q5-Pad2_ 340 +R9 Net-_Q5-Pad2_ Net-_Q5-Pad3_ 7k +R11 Net-_Q5-Pad3_ /GND 500 +Q5 /C3 Net-_Q5-Pad2_ Net-_Q5-Pad3_ eSim_NPN +Q7 /C3 Net-_Q5-Pad3_ /GND eSim_NPN +U1 /B4 /B3 ? /C4 /C3 /GND /C2 /C1 ? /B2 /B1 PORT + +.end diff --git a/library/SubcircuitLibrary/L702/L702.cir.out b/library/SubcircuitLibrary/L702/L702.cir.out new file mode 100644 index 000000000..ddb606c64 --- /dev/null +++ b/library/SubcircuitLibrary/L702/L702.cir.out @@ -0,0 +1,33 @@ +* c:\fossee\esim\library\subcircuitlibrary\l702\l702.cir + +.include NPN.lib +r2 /b1 net-_q2-pad2_ 340 +r4 net-_q2-pad2_ net-_q2-pad3_ 7k +r6 net-_q2-pad3_ /gnd 500 +q2 /c1 net-_q2-pad2_ net-_q2-pad3_ Q2N2222 +q4 /c1 net-_q2-pad3_ /gnd Q2N2222 +r8 /b4 net-_q6-pad2_ 340 +r10 net-_q6-pad2_ net-_q6-pad3_ 7k +r12 net-_q6-pad3_ /gnd 500 +q6 /c4 net-_q6-pad2_ net-_q6-pad3_ Q2N2222 +q8 /c4 net-_q6-pad3_ /gnd Q2N2222 +r1 /b2 net-_q1-pad2_ 340 +r3 net-_q1-pad2_ net-_q1-pad3_ 7k +r5 net-_q1-pad3_ /gnd 500 +q1 /c2 net-_q1-pad2_ net-_q1-pad3_ Q2N2222 +q3 /c2 net-_q1-pad3_ /gnd Q2N2222 +r7 /b3 net-_q5-pad2_ 340 +r9 net-_q5-pad2_ net-_q5-pad3_ 7k +r11 net-_q5-pad3_ /gnd 500 +q5 /c3 net-_q5-pad2_ net-_q5-pad3_ Q2N2222 +q7 /c3 net-_q5-pad3_ /gnd Q2N2222 +* u1 /b4 /b3 ? /c4 /c3 /gnd /c2 /c1 ? /b2 /b1 port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/L702/L702.pro b/library/SubcircuitLibrary/L702/L702.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/L702/L702.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/L702/L702.sch b/library/SubcircuitLibrary/L702/L702.sch new file mode 100644 index 000000000..10d2c0710 --- /dev/null +++ b/library/SubcircuitLibrary/L702/L702.sch @@ -0,0 +1,555 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:L702-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L resistor R2 +U 1 1 685BADF2 +P 1800 1650 +F 0 "R2" H 1850 1780 50 0000 C CNN +F 1 "340" H 1850 1600 50 0000 C CNN +F 2 "" H 1850 1630 30 0000 C CNN +F 3 "" V 1850 1700 30 0000 C CNN + 1 1800 1650 + 1 0 0 -1 +$EndComp +$Comp +L resistor R4 +U 1 1 685BAE4F +P 2700 2150 +F 0 "R4" H 2750 2280 50 0000 C CNN +F 1 "7k" H 2750 2100 50 0000 C CNN +F 2 "" H 2750 2130 30 0000 C CNN +F 3 "" V 2750 2200 30 0000 C CNN + 1 2700 2150 + 1 0 0 -1 +$EndComp +$Comp +L resistor R6 +U 1 1 685BAE96 +P 3250 2800 +F 0 "R6" H 3300 2930 50 0000 C CNN +F 1 "500" H 3300 2750 50 0000 C CNN +F 2 "" H 3300 2780 30 0000 C CNN +F 3 "" V 3300 2850 30 0000 C CNN + 1 3250 2800 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q2 +U 1 1 685BAEF9 +P 3250 1600 +F 0 "Q2" H 3150 1650 50 0000 R CNN +F 1 "eSim_NPN" H 3200 1750 50 0000 R CNN +F 2 "" H 3450 1700 29 0000 C CNN +F 3 "" H 3250 1600 60 0000 C CNN + 1 3250 1600 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q4 +U 1 1 685BAF52 +P 3950 2100 +F 0 "Q4" H 3850 2150 50 0000 R CNN +F 1 "eSim_NPN" H 3900 2250 50 0000 R CNN +F 2 "" H 4150 2200 29 0000 C CNN +F 3 "" H 3950 2100 60 0000 C CNN + 1 3950 2100 + 1 0 0 -1 +$EndComp +$Comp +L resistor R8 +U 1 1 685BEA05 +P 5400 1600 +F 0 "R8" H 5450 1730 50 0000 C CNN +F 1 "340" H 5450 1550 50 0000 C CNN +F 2 "" H 5450 1580 30 0000 C CNN +F 3 "" V 5450 1650 30 0000 C CNN + 1 5400 1600 + 1 0 0 -1 +$EndComp +$Comp +L resistor R10 +U 1 1 685BEA0B +P 6300 2100 +F 0 "R10" H 6350 2230 50 0000 C CNN +F 1 "7k" H 6350 2050 50 0000 C CNN +F 2 "" H 6350 2080 30 0000 C CNN +F 3 "" V 6350 2150 30 0000 C CNN + 1 6300 2100 + 1 0 0 -1 +$EndComp +$Comp +L resistor R12 +U 1 1 685BEA11 +P 6850 2750 +F 0 "R12" H 6900 2880 50 0000 C CNN +F 1 "500" H 6900 2700 50 0000 C CNN +F 2 "" H 6900 2730 30 0000 C CNN +F 3 "" V 6900 2800 30 0000 C CNN + 1 6850 2750 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q6 +U 1 1 685BEA17 +P 6850 1550 +F 0 "Q6" H 6750 1600 50 0000 R CNN +F 1 "eSim_NPN" H 6800 1700 50 0000 R CNN +F 2 "" H 7050 1650 29 0000 C CNN +F 3 "" H 6850 1550 60 0000 C CNN + 1 6850 1550 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q8 +U 1 1 685BEA1D +P 7550 2050 +F 0 "Q8" H 7450 2100 50 0000 R CNN +F 1 "eSim_NPN" H 7500 2200 50 0000 R CNN +F 2 "" H 7750 2150 29 0000 C CNN +F 3 "" H 7550 2050 60 0000 C CNN + 1 7550 2050 + 1 0 0 -1 +$EndComp +$Comp +L resistor R1 +U 1 1 685BEBBB +P 1750 5400 +F 0 "R1" H 1800 5530 50 0000 C CNN +F 1 "340" H 1800 5350 50 0000 C CNN +F 2 "" H 1800 5380 30 0000 C CNN +F 3 "" V 1800 5450 30 0000 C CNN + 1 1750 5400 + 1 0 0 -1 +$EndComp +$Comp +L resistor R3 +U 1 1 685BEBC1 +P 2650 5900 +F 0 "R3" H 2700 6030 50 0000 C CNN +F 1 "7k" H 2700 5850 50 0000 C CNN +F 2 "" H 2700 5880 30 0000 C CNN +F 3 "" V 2700 5950 30 0000 C CNN + 1 2650 5900 + 1 0 0 -1 +$EndComp +$Comp +L resistor R5 +U 1 1 685BEBC7 +P 3200 6550 +F 0 "R5" H 3250 6680 50 0000 C CNN +F 1 "500" H 3250 6500 50 0000 C CNN +F 2 "" H 3250 6530 30 0000 C CNN +F 3 "" V 3250 6600 30 0000 C CNN + 1 3200 6550 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q1 +U 1 1 685BEBCD +P 3200 5350 +F 0 "Q1" H 3100 5400 50 0000 R CNN +F 1 "eSim_NPN" H 3150 5500 50 0000 R CNN +F 2 "" H 3400 5450 29 0000 C CNN +F 3 "" H 3200 5350 60 0000 C CNN + 1 3200 5350 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q3 +U 1 1 685BEBD3 +P 3900 5850 +F 0 "Q3" H 3800 5900 50 0000 R CNN +F 1 "eSim_NPN" H 3850 6000 50 0000 R CNN +F 2 "" H 4100 5950 29 0000 C CNN +F 3 "" H 3900 5850 60 0000 C CNN + 1 3900 5850 + 1 0 0 -1 +$EndComp +$Comp +L resistor R7 +U 1 1 685BEBEB +P 5350 5350 +F 0 "R7" H 5400 5480 50 0000 C CNN +F 1 "340" H 5400 5300 50 0000 C CNN +F 2 "" H 5400 5330 30 0000 C CNN +F 3 "" V 5400 5400 30 0000 C CNN + 1 5350 5350 + 1 0 0 -1 +$EndComp +$Comp +L resistor R9 +U 1 1 685BEBF1 +P 6250 5850 +F 0 "R9" H 6300 5980 50 0000 C CNN +F 1 "7k" H 6300 5800 50 0000 C CNN +F 2 "" H 6300 5830 30 0000 C CNN +F 3 "" V 6300 5900 30 0000 C CNN + 1 6250 5850 + 1 0 0 -1 +$EndComp +$Comp +L resistor R11 +U 1 1 685BEBF7 +P 6800 6500 +F 0 "R11" H 6850 6630 50 0000 C CNN +F 1 "500" H 6850 6450 50 0000 C CNN +F 2 "" H 6850 6480 30 0000 C CNN +F 3 "" V 6850 6550 30 0000 C CNN + 1 6800 6500 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q5 +U 1 1 685BEBFD +P 6800 5300 +F 0 "Q5" H 6700 5350 50 0000 R CNN +F 1 "eSim_NPN" H 6750 5450 50 0000 R CNN +F 2 "" H 7000 5400 29 0000 C CNN +F 3 "" H 6800 5300 60 0000 C CNN + 1 6800 5300 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q7 +U 1 1 685BEC03 +P 7500 5800 +F 0 "Q7" H 7400 5850 50 0000 R CNN +F 1 "eSim_NPN" H 7450 5950 50 0000 R CNN +F 2 "" H 7700 5900 29 0000 C CNN +F 3 "" H 7500 5800 60 0000 C CNN + 1 7500 5800 + 1 0 0 -1 +$EndComp +Text Label 1500 1600 0 60 ~ 0 +B1 +Text Label 1450 5350 0 60 ~ 0 +B2 +Text Label 5100 5300 0 60 ~ 0 +B3 +Text Label 5200 1550 0 60 ~ 0 +B4 +Text Label 4050 1050 0 60 ~ 0 +C1 +Text Label 4000 4800 0 60 ~ 0 +C2 +Text Label 7600 4750 0 60 ~ 0 +C3 +Text Label 7650 950 0 60 ~ 0 +C4 +$Comp +L PORT U1 +U 11 1 685C0791 +P 1100 1600 +F 0 "U1" H 1150 1700 30 0000 C CNN +F 1 "PORT" H 1100 1600 30 0000 C CNN +F 2 "" H 1100 1600 60 0000 C CNN +F 3 "" H 1100 1600 60 0000 C CNN + 11 1100 1600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 685C092E +P 1050 5350 +F 0 "U1" H 1100 5450 30 0000 C CNN +F 1 "PORT" H 1050 5350 30 0000 C CNN +F 2 "" H 1050 5350 60 0000 C CNN +F 3 "" H 1050 5350 60 0000 C CNN + 10 1050 5350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 685C0ADD +P 3800 800 +F 0 "U1" H 3850 900 30 0000 C CNN +F 1 "PORT" H 3800 800 30 0000 C CNN +F 2 "" H 3800 800 60 0000 C CNN +F 3 "" H 3800 800 60 0000 C CNN + 8 3800 800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 685C0D14 +P 3750 4550 +F 0 "U1" H 3800 4650 30 0000 C CNN +F 1 "PORT" H 3750 4550 30 0000 C CNN +F 2 "" H 3750 4550 60 0000 C CNN +F 3 "" H 3750 4550 60 0000 C CNN + 7 3750 4550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 685C101B +P 4700 1550 +F 0 "U1" H 4750 1650 30 0000 C CNN +F 1 "PORT" H 4700 1550 30 0000 C CNN +F 2 "" H 4700 1550 60 0000 C CNN +F 3 "" H 4700 1550 60 0000 C CNN + 1 4700 1550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 685C10B9 +P 7400 750 +F 0 "U1" H 7450 850 30 0000 C CNN +F 1 "PORT" H 7400 750 30 0000 C CNN +F 2 "" H 7400 750 60 0000 C CNN +F 3 "" H 7400 750 60 0000 C CNN + 4 7400 750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 685C12C6 +P 4650 5300 +F 0 "U1" H 4700 5400 30 0000 C CNN +F 1 "PORT" H 4650 5300 30 0000 C CNN +F 2 "" H 4650 5300 60 0000 C CNN +F 3 "" H 4650 5300 60 0000 C CNN + 2 4650 5300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 685C1552 +P 7350 4500 +F 0 "U1" H 7400 4600 30 0000 C CNN +F 1 "PORT" H 7350 4500 30 0000 C CNN +F 2 "" H 7350 4500 60 0000 C CNN +F 3 "" H 7350 4500 60 0000 C CNN + 5 7350 4500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 685C1705 +P 10400 3400 +F 0 "U1" H 10450 3500 30 0000 C CNN +F 1 "PORT" H 10400 3400 30 0000 C CNN +F 2 "" H 10400 3400 60 0000 C CNN +F 3 "" H 10400 3400 60 0000 C CNN + 9 10400 3400 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 6 1 685C1962 +P 10400 3600 +F 0 "U1" H 10450 3700 30 0000 C CNN +F 1 "PORT" H 10400 3600 30 0000 C CNN +F 2 "" H 10400 3600 60 0000 C CNN +F 3 "" H 10400 3600 60 0000 C CNN + 6 10400 3600 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 3 1 685C19D3 +P 10400 3800 +F 0 "U1" H 10450 3900 30 0000 C CNN +F 1 "PORT" H 10400 3800 30 0000 C CNN +F 2 "" H 10400 3800 60 0000 C CNN +F 3 "" H 10400 3800 60 0000 C CNN + 3 10400 3800 + -1 0 0 1 +$EndComp +Text Label 8800 3450 0 60 ~ 0 +GND +Wire Wire Line + 2000 1600 3050 1600 +Wire Wire Line + 2600 2100 2350 2100 +Wire Wire Line + 2350 2100 2350 1600 +Connection ~ 2350 1600 +Wire Wire Line + 2900 2100 3750 2100 +Wire Wire Line + 3350 1800 3350 2150 +Wire Wire Line + 3300 2700 3300 2150 +Wire Wire Line + 3300 2150 3350 2150 +Connection ~ 3350 2100 +Wire Wire Line + 3300 3000 3300 3500 +Wire Wire Line + 4050 3500 4050 2300 +Wire Wire Line + 1700 1600 1350 1600 +Wire Wire Line + 4050 800 4050 1900 +Wire Wire Line + 4050 1250 3350 1250 +Wire Wire Line + 3350 1250 3350 1400 +Connection ~ 4050 1250 +Wire Wire Line + 5600 1550 6650 1550 +Wire Wire Line + 6200 2050 5950 2050 +Wire Wire Line + 5950 2050 5950 1550 +Connection ~ 5950 1550 +Wire Wire Line + 6500 2050 7350 2050 +Wire Wire Line + 6950 1750 6950 2100 +Wire Wire Line + 6900 2650 6900 2100 +Wire Wire Line + 6900 2100 6950 2100 +Connection ~ 6950 2050 +Wire Wire Line + 6900 2950 6900 3450 +Wire Wire Line + 7650 3450 7650 2250 +Wire Wire Line + 5300 1550 4950 1550 +Wire Wire Line + 7650 750 7650 1850 +Wire Wire Line + 7650 1200 6950 1200 +Wire Wire Line + 6950 1200 6950 1350 +Connection ~ 7650 1200 +Wire Wire Line + 1950 5350 3000 5350 +Wire Wire Line + 2550 5850 2300 5850 +Wire Wire Line + 2300 5850 2300 5350 +Connection ~ 2300 5350 +Wire Wire Line + 2850 5850 3700 5850 +Wire Wire Line + 3300 5550 3300 5900 +Wire Wire Line + 3250 6450 3250 5900 +Wire Wire Line + 3250 5900 3300 5900 +Connection ~ 3300 5850 +Wire Wire Line + 3250 6750 3250 7250 +Wire Wire Line + 4000 7250 4000 6050 +Wire Wire Line + 1650 5350 1300 5350 +Wire Wire Line + 4000 4550 4000 5650 +Wire Wire Line + 4000 5000 3300 5000 +Wire Wire Line + 3300 5000 3300 5150 +Connection ~ 4000 5000 +Wire Wire Line + 5550 5300 6600 5300 +Wire Wire Line + 6150 5800 5900 5800 +Wire Wire Line + 5900 5800 5900 5300 +Connection ~ 5900 5300 +Wire Wire Line + 6450 5800 7300 5800 +Wire Wire Line + 6900 5500 6900 5850 +Wire Wire Line + 6850 6400 6850 5850 +Wire Wire Line + 6850 5850 6900 5850 +Connection ~ 6900 5800 +Wire Wire Line + 6850 7250 6850 6700 +Wire Wire Line + 7600 7250 7600 6000 +Wire Wire Line + 5250 5300 4900 5300 +Wire Wire Line + 7600 4500 7600 5600 +Wire Wire Line + 7600 4950 6900 4950 +Wire Wire Line + 6900 4950 6900 5100 +Connection ~ 7600 4950 +Wire Wire Line + 3250 7250 9400 7250 +Connection ~ 4000 7250 +Connection ~ 6850 7250 +Wire Wire Line + 9400 7250 9400 3450 +Wire Wire Line + 4200 3450 9550 3450 +Connection ~ 7600 7250 +Connection ~ 7650 3450 +Wire Wire Line + 4200 3450 4200 3500 +Wire Wire Line + 4200 3500 3300 3500 +Connection ~ 6900 3450 +Connection ~ 4050 3500 +NoConn ~ 10150 3400 +NoConn ~ 10150 3800 +Wire Wire Line + 10150 3600 9550 3600 +Wire Wire Line + 9550 3600 9550 3450 +Connection ~ 9400 3450 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/L702/L702.sub b/library/SubcircuitLibrary/L702/L702.sub new file mode 100644 index 000000000..f0f13c42c --- /dev/null +++ b/library/SubcircuitLibrary/L702/L702.sub @@ -0,0 +1,27 @@ +* Subcircuit L702 +.subckt L702 /b4 /b3 ? /c4 /c3 /gnd /c2 /c1 ? /b2 /b1 +* c:\fossee\esim\library\subcircuitlibrary\l702\l702.cir +.include NPN.lib +r2 /b1 net-_q2-pad2_ 340 +r4 net-_q2-pad2_ net-_q2-pad3_ 7k +r6 net-_q2-pad3_ /gnd 500 +q2 /c1 net-_q2-pad2_ net-_q2-pad3_ Q2N2222 +q4 /c1 net-_q2-pad3_ /gnd Q2N2222 +r8 /b4 net-_q6-pad2_ 340 +r10 net-_q6-pad2_ net-_q6-pad3_ 7k +r12 net-_q6-pad3_ /gnd 500 +q6 /c4 net-_q6-pad2_ net-_q6-pad3_ Q2N2222 +q8 /c4 net-_q6-pad3_ /gnd Q2N2222 +r1 /b2 net-_q1-pad2_ 340 +r3 net-_q1-pad2_ net-_q1-pad3_ 7k +r5 net-_q1-pad3_ /gnd 500 +q1 /c2 net-_q1-pad2_ net-_q1-pad3_ Q2N2222 +q3 /c2 net-_q1-pad3_ /gnd Q2N2222 +r7 /b3 net-_q5-pad2_ 340 +r9 net-_q5-pad2_ net-_q5-pad3_ 7k +r11 net-_q5-pad3_ /gnd 500 +q5 /c3 net-_q5-pad2_ net-_q5-pad3_ Q2N2222 +q7 /c3 net-_q5-pad3_ /gnd Q2N2222 +* Control Statements + +.ends L702 \ No newline at end of file diff --git a/library/SubcircuitLibrary/L702/L702_Previous_Values.xml b/library/SubcircuitLibrary/L702/L702_Previous_Values.xml new file mode 100644 index 000000000..17402ef44 --- /dev/null +++ b/library/SubcircuitLibrary/L702/L702_Previous_Values.xml @@ -0,0 +1 @@ +C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec \ No newline at end of file diff --git a/library/SubcircuitLibrary/L702/NPN.lib b/library/SubcircuitLibrary/L702/NPN.lib new file mode 100644 index 000000000..be5f3073a --- /dev/null +++ b/library/SubcircuitLibrary/L702/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p ++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/L702/analysis b/library/SubcircuitLibrary/L702/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/SubcircuitLibrary/L702/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/library/SubcircuitLibrary/MC1723/MC1723-cache.lib b/library/SubcircuitLibrary/MC1723/MC1723-cache.lib new file mode 100644 index 000000000..0fdcdbaa5 --- /dev/null +++ b/library/SubcircuitLibrary/MC1723/MC1723-cache.lib @@ -0,0 +1,184 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# DC +# +DEF DC v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "DC" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 w +X - 2 0 -450 300 U 50 50 1 1 w +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_CP1 +# +DEF eSim_CP1 C 0 10 N N 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "eSim_CP1" 25 -100 50 H V L CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +ALIAS capacitor_polarised +$FPLIST + CP_* +$ENDFPLIST +DRAW +A 0 -150 128 1287 513 0 1 20 N -80 -50 80 -50 +P 2 0 1 20 -80 30 80 30 N +P 2 0 1 0 -70 90 -30 90 N +P 2 0 1 0 -50 70 -50 110 N +X ~ 1 0 150 110 D 50 50 1 1 P +X ~ 2 0 -150 130 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_Diode +# +DEF eSim_Diode D 0 40 N N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "eSim_Diode" 0 -100 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + TO-???* + *SingleDiode + *_Diode_* + *SingleDiode* + D_* +$ENDFPLIST +DRAW +T 0 -100 50 60 0 0 0 A Normal 0 C C +T 0 100 50 60 0 0 0 K Normal 0 C C +P 2 0 1 6 50 50 50 -50 N +P 3 0 1 0 -50 50 50 0 -50 -50 F +X A 1 -150 0 100 R 40 40 1 1 P +X K 2 150 0 100 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NJF +# +DEF eSim_NJF J 0 0 Y N 1 F N +F0 "J" -100 50 50 H V R CNN +F1 "eSim_NJF" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS jfet_n +DRAW +C 50 0 111 0 1 10 N +P 3 0 1 10 10 75 10 -75 10 -75 N +P 3 0 1 0 100 -100 100 -50 10 -50 N +P 3 0 1 0 100 100 100 55 10 55 N +P 4 0 1 0 0 0 -40 15 -40 -15 0 0 F +X D 1 100 200 100 D 50 50 1 1 P +X G 2 -200 0 210 R 50 50 1 1 P +X S 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_PNP +# +DEF eSim_PNP Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_PNP" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/MC1723/MC1723.bak b/library/SubcircuitLibrary/MC1723/MC1723.bak new file mode 100644 index 000000000..a9f2b7e19 --- /dev/null +++ b/library/SubcircuitLibrary/MC1723/MC1723.bak @@ -0,0 +1,771 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +EELAYER 25 0 +EELAYER END +$Descr A1 33110 23386 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_Diode D1 +U 1 1 6866D034 +P 5450 7100 +F 0 "D1" H 5450 7200 50 0000 C CNN +F 1 "eSim_Diode" H 5450 7000 50 0000 C CNN +F 2 "" H 5450 7100 60 0000 C CNN +F 3 "" H 5450 7100 60 0000 C CNN + 1 5450 7100 + 0 -1 -1 0 +$EndComp +$Comp +L resistor R1 +U 1 1 6866D12F +P 7650 5900 +F 0 "R1" H 7700 6030 50 0000 C CNN +F 1 "500" H 7700 5850 50 0000 C CNN +F 2 "" H 7700 5880 30 0000 C CNN +F 3 "" V 7700 5950 30 0000 C CNN + 1 7650 5900 + 0 1 1 0 +$EndComp +$Comp +L eSim_PNP Q1 +U 1 1 6866D1B5 +P 7800 7150 +F 0 "Q1" H 7700 7200 50 0000 R CNN +F 1 "eSim_PNP" H 7750 7300 50 0000 R CNN +F 2 "" H 8000 7250 29 0000 C CNN +F 3 "" H 7800 7150 60 0000 C CNN + 1 7800 7150 + -1 0 0 1 +$EndComp +$Comp +L resistor R2 +U 1 1 6866D242 +P 7650 8350 +F 0 "R2" H 7700 8480 50 0000 C CNN +F 1 "15k" H 7700 8300 50 0000 C CNN +F 2 "" H 7700 8330 30 0000 C CNN +F 3 "" V 7700 8400 30 0000 C CNN + 1 7650 8350 + 0 1 1 0 +$EndComp +$Comp +L eSim_NJF J1 +U 1 1 6866D35B +P 5700 12650 +F 0 "J1" H 5600 12700 50 0000 R CNN +F 1 "eSim_NJF" H 5650 12800 50 0000 R CNN +F 2 "" H 5900 12750 29 0000 C CNN +F 3 "" H 5700 12650 60 0000 C CNN + 1 5700 12650 + -1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q3 +U 1 1 6866D540 +P 10100 7150 +F 0 "Q3" H 10000 7200 50 0000 R CNN +F 1 "eSim_PNP" H 10050 7300 50 0000 R CNN +F 2 "" H 10300 7250 29 0000 C CNN +F 3 "" H 10100 7150 60 0000 C CNN + 1 10100 7150 + 1 0 0 1 +$EndComp +$Comp +L resistor R3 +U 1 1 6866D698 +P 10150 6050 +F 0 "R3" H 10200 6180 50 0000 C CNN +F 1 "25k" H 10200 6000 50 0000 C CNN +F 2 "" H 10200 6030 30 0000 C CNN +F 3 "" V 10200 6100 30 0000 C CNN + 1 10150 6050 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q2 +U 1 1 6866D973 +P 8400 15050 +F 0 "Q2" H 8300 15100 50 0000 R CNN +F 1 "eSim_NPN" H 8350 15200 50 0000 R CNN +F 2 "" H 8600 15150 29 0000 C CNN +F 3 "" H 8400 15050 60 0000 C CNN + 1 8400 15050 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q4 +U 1 1 6866DA95 +P 11200 9550 +F 0 "Q4" H 11100 9600 50 0000 R CNN +F 1 "eSim_NPN" H 11150 9700 50 0000 R CNN +F 2 "" H 11400 9650 29 0000 C CNN +F 3 "" H 11200 9550 60 0000 C CNN + 1 11200 9550 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q5 +U 1 1 6866DAFC +P 12500 10800 +F 0 "Q5" H 12400 10850 50 0000 R CNN +F 1 "eSim_NPN" H 12450 10950 50 0000 R CNN +F 2 "" H 12700 10900 29 0000 C CNN +F 3 "" H 12500 10800 60 0000 C CNN + 1 12500 10800 + 1 0 0 -1 +$EndComp +$Comp +L resistor R5 +U 1 1 6866DF63 +P 12550 12050 +F 0 "R5" H 12600 12180 50 0000 C CNN +F 1 "100" H 12600 12000 50 0000 C CNN +F 2 "" H 12600 12030 30 0000 C CNN +F 3 "" V 12600 12100 30 0000 C CNN + 1 12550 12050 + 0 1 1 0 +$EndComp +$Comp +L eSim_Diode D2 +U 1 1 6866E068 +P 12600 12750 +F 0 "D2" H 12600 12850 50 0000 C CNN +F 1 "eSim_Diode" H 12600 12650 50 0000 C CNN +F 2 "" H 12600 12750 60 0000 C CNN +F 3 "" H 12600 12750 60 0000 C CNN + 1 12600 12750 + 0 -1 -1 0 +$EndComp +$Comp +L resistor R6 +U 1 1 6866E0F8 +P 12550 14300 +F 0 "R6" H 12600 14430 50 0000 C CNN +F 1 "5.0k" H 12600 14250 50 0000 C CNN +F 2 "" H 12600 14280 30 0000 C CNN +F 3 "" V 12600 14350 30 0000 C CNN + 1 12550 14300 + 0 1 1 0 +$EndComp +$Comp +L resistor R4 +U 1 1 6866E39B +P 10500 14000 +F 0 "R4" H 10550 14130 50 0000 C CNN +F 1 "30k" H 10550 13950 50 0000 C CNN +F 2 "" H 10550 13980 30 0000 C CNN +F 3 "" V 10550 14050 30 0000 C CNN + 1 10500 14000 + 1 0 0 -1 +$EndComp +$Comp +L capacitor_polarised C1 +U 1 1 6866E601 +P 9150 13550 +F 0 "C1" H 9175 13650 50 0000 L CNN +F 1 "5.0p" H 9175 13450 50 0000 L CNN +F 2 "" H 9150 13550 50 0001 C CNN +F 3 "" H 9150 13550 50 0001 C CNN + 1 9150 13550 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5450 6950 5450 5500 +Wire Wire Line + 5450 5500 24150 5500 +Wire Wire Line + 7700 5500 7700 5800 +Wire Wire Line + 7700 6950 7700 6100 +Wire Wire Line + 7700 7350 7700 8250 +Wire Wire Line + 7700 8550 7700 8900 +Wire Wire Line + 7700 8900 5450 8900 +Wire Wire Line + 5450 7250 5450 9250 +Wire Wire Line + 5600 12450 5600 9250 +Wire Wire Line + 5600 9250 5450 9250 +Connection ~ 5450 8900 +Wire Wire Line + 5600 12850 5600 16350 +Wire Wire Line + 5600 16350 18650 16350 +Wire Wire Line + 18650 14900 18650 17150 +Wire Wire Line + 8000 7150 9900 7150 +Wire Wire Line + 8800 7150 8800 7800 +Wire Wire Line + 8800 7800 7700 7800 +Connection ~ 7700 7800 +Connection ~ 8800 7150 +Wire Wire Line + 10200 6950 10200 6250 +Wire Wire Line + 10200 5500 10200 5950 +Connection ~ 7700 5500 +Wire Wire Line + 5900 12650 6850 12650 +Wire Wire Line + 6850 12650 6850 16350 +Connection ~ 6850 16350 +Wire Wire Line + 8300 15250 8300 16350 +Connection ~ 8300 16350 +Wire Wire Line + 8300 9550 8300 14850 +Wire Wire Line + 8300 9550 11000 9550 +Wire Wire Line + 10200 7350 10200 9550 +Connection ~ 10200 9550 +Wire Wire Line + 11300 5500 11300 9350 +Connection ~ 10200 5500 +Wire Wire Line + 12300 10800 11300 10800 +Wire Wire Line + 11300 10800 11300 9750 +Wire Wire Line + 12600 11950 12600 11000 +Wire Wire Line + 12600 12250 12600 12600 +Wire Wire Line + 12600 12900 12600 14200 +Wire Wire Line + 8600 15050 9700 15050 +Wire Wire Line + 9700 15050 9700 14000 +Wire Wire Line + 9700 14000 10400 14000 +Wire Wire Line + 10400 14000 10400 13950 +Wire Wire Line + 10700 13950 12600 13950 +Connection ~ 12600 13950 +Wire Wire Line + 9150 13700 9150 15050 +Connection ~ 9150 15050 +Wire Wire Line + 9150 13400 9150 13000 +Wire Wire Line + 9150 13000 8300 13000 +Connection ~ 8300 13000 +Wire Wire Line + 12600 14500 12600 16350 +Connection ~ 12600 16350 +Wire Wire Line + 12600 12400 13450 12400 +Wire Wire Line + 13450 12400 13450 17700 +Connection ~ 12600 12400 +Wire Wire Line + 12600 5500 12600 10600 +Connection ~ 11300 5500 +$Comp +L resistor R8 +U 1 1 6866ED9A +P 14700 15200 +F 0 "R8" H 14750 15330 50 0000 C CNN +F 1 "300" H 14750 15150 50 0000 C CNN +F 2 "" H 14750 15180 30 0000 C CNN +F 3 "" V 14750 15250 30 0000 C CNN + 1 14700 15200 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q7 +U 1 1 6866EE4C +P 14850 13700 +F 0 "Q7" H 14750 13750 50 0000 R CNN +F 1 "eSim_NPN" H 14800 13850 50 0000 R CNN +F 2 "" H 15050 13800 29 0000 C CNN +F 3 "" H 14850 13700 60 0000 C CNN + 1 14850 13700 + -1 0 0 -1 +$EndComp +Wire Wire Line + 14750 15100 14750 13900 +Wire Wire Line + 14750 15400 14750 16350 +Connection ~ 14750 16350 +$Comp +L eSim_PNP Q6 +U 1 1 6866F0B6 +P 14650 7100 +F 0 "Q6" H 14550 7150 50 0000 R CNN +F 1 "eSim_PNP" H 14600 7250 50 0000 R CNN +F 2 "" H 14850 7200 29 0000 C CNN +F 3 "" H 14650 7100 60 0000 C CNN + 1 14650 7100 + 1 0 0 1 +$EndComp +Wire Wire Line + 14750 7300 14750 13500 +$Comp +L resistor R7 +U 1 1 6866F697 +P 14700 6100 +F 0 "R7" H 14750 6230 50 0000 C CNN +F 1 "1.0k" H 14750 6050 50 0000 C CNN +F 2 "" H 14750 6080 30 0000 C CNN +F 3 "" V 14750 6150 30 0000 C CNN + 1 14700 6100 + 0 1 1 0 +$EndComp +Wire Wire Line + 14750 6900 14750 6300 +Wire Wire Line + 14750 5500 14750 6000 +Connection ~ 12600 5500 +Wire Wire Line + 9500 7150 9500 7550 +Wire Wire Line + 9500 7550 18800 7550 +Wire Wire Line + 13200 7550 13200 7100 +Wire Wire Line + 13200 7100 14450 7100 +Connection ~ 9500 7150 +Wire Wire Line + 14750 11150 16100 11150 +Connection ~ 14750 11150 +$Comp +L eSim_NPN Q8 +U 1 1 6866FC42 +P 16300 11150 +F 0 "Q8" H 16200 11200 50 0000 R CNN +F 1 "eSim_NPN" H 16250 11300 50 0000 R CNN +F 2 "" H 16500 11250 29 0000 C CNN +F 3 "" H 16300 11150 60 0000 C CNN + 1 16300 11150 + 1 0 0 -1 +$EndComp +Wire Wire Line + 16400 11350 16400 14700 +Wire Wire Line + 15050 13700 18350 13700 +Connection ~ 16400 13700 +$Comp +L resistor R9 +U 1 1 6866FF68 +P 16350 14800 +F 0 "R9" H 16400 14930 50 0000 C CNN +F 1 "20k" H 16400 14750 50 0000 C CNN +F 2 "" H 16400 14780 30 0000 C CNN +F 3 "" V 16400 14850 30 0000 C CNN + 1 16350 14800 + 0 1 1 0 +$EndComp +Wire Wire Line + 16400 15000 16400 16350 +Connection ~ 16400 16350 +$Comp +L eSim_NPN Q10 +U 1 1 68670127 +P 18550 13700 +F 0 "Q10" H 18450 13750 50 0000 R CNN +F 1 "eSim_NPN" H 18500 13850 50 0000 R CNN +F 2 "" H 18750 13800 29 0000 C CNN +F 3 "" H 18550 13700 60 0000 C CNN + 1 18550 13700 + 1 0 0 -1 +$EndComp +Wire Wire Line + 18650 13900 18650 14600 +$Comp +L resistor R10 +U 1 1 68670483 +P 18600 14700 +F 0 "R10" H 18650 14830 50 0000 C CNN +F 1 "150" H 18650 14650 50 0000 C CNN +F 2 "" H 18650 14680 30 0000 C CNN +F 3 "" V 18650 14750 30 0000 C CNN + 1 18600 14700 + 0 1 1 0 +$EndComp +Connection ~ 18650 16350 +Wire Wire Line + 16400 5500 16400 10950 +Connection ~ 14750 5500 +$Comp +L eSim_NPN Q9 +U 1 1 68670B38 +P 18000 11100 +F 0 "Q9" H 17900 11150 50 0000 R CNN +F 1 "eSim_NPN" H 17950 11250 50 0000 R CNN +F 2 "" H 18200 11200 29 0000 C CNN +F 3 "" H 18000 11100 60 0000 C CNN + 1 18000 11100 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q12 +U 1 1 68670C29 +P 19550 11100 +F 0 "Q12" H 19450 11150 50 0000 R CNN +F 1 "eSim_NPN" H 19500 11250 50 0000 R CNN +F 2 "" H 19750 11200 29 0000 C CNN +F 3 "" H 19550 11100 60 0000 C CNN + 1 19550 11100 + -1 0 0 -1 +$EndComp +Wire Wire Line + 18100 11300 18100 11700 +Wire Wire Line + 18100 11700 19450 11700 +Wire Wire Line + 19450 11700 19450 11300 +Wire Wire Line + 18650 13500 18650 11700 +Connection ~ 18650 11700 +Wire Wire Line + 17800 11100 17350 11100 +Wire Wire Line + 17350 11100 17350 17450 +Wire Wire Line + 18100 7550 18100 10900 +Wire Wire Line + 18100 10050 11600 10050 +Wire Wire Line + 11600 10050 11600 10800 +Connection ~ 11600 10800 +$Comp +L eSim_PNP Q11 +U 1 1 686717D7 +P 19350 7350 +F 0 "Q11" H 19250 7400 50 0000 R CNN +F 1 "eSim_PNP" H 19300 7500 50 0000 R CNN +F 2 "" H 19550 7450 29 0000 C CNN +F 3 "" H 19350 7350 60 0000 C CNN + 1 19350 7350 + 1 0 0 1 +$EndComp +$Comp +L resistor R11 +U 1 1 6867192A +P 19400 6400 +F 0 "R11" H 19450 6530 50 0000 C CNN +F 1 "1.0k" H 19450 6350 50 0000 C CNN +F 2 "" H 19450 6380 30 0000 C CNN +F 3 "" V 19450 6450 30 0000 C CNN + 1 19400 6400 + 0 1 1 0 +$EndComp +Wire Wire Line + 19450 7150 19450 6600 +Wire Wire Line + 19450 5500 19450 6300 +Connection ~ 16400 5500 +Wire Wire Line + 19450 10900 19450 7550 +Wire Wire Line + 18800 7550 18800 7350 +Wire Wire Line + 18800 7350 19150 7350 +Connection ~ 13200 7550 +Connection ~ 18100 7550 +Connection ~ 18100 10050 +Wire Wire Line + 19750 11100 20250 11100 +Wire Wire Line + 20250 11100 20250 17000 +Wire Wire Line + 19450 9600 21350 9600 +Wire Wire Line + 21350 9600 21350 12600 +Connection ~ 19450 9600 +$Comp +L eSim_NPN Q13 +U 1 1 686728F4 +P 21450 12800 +F 0 "Q13" H 21350 12850 50 0000 R CNN +F 1 "eSim_NPN" H 21400 12950 50 0000 R CNN +F 2 "" H 21650 12900 29 0000 C CNN +F 3 "" H 21450 12800 60 0000 C CNN + 1 21450 12800 + -1 0 0 -1 +$EndComp +Wire Wire Line + 21350 13000 21350 14250 +Wire Wire Line + 21350 14250 23200 14250 +Wire Wire Line + 21650 12800 22750 12800 +Wire Wire Line + 21350 12250 23100 12250 +Connection ~ 21350 12250 +Wire Wire Line + 19450 8550 23850 8550 +Connection ~ 19450 8550 +$Comp +L eSim_NPN Q14 +U 1 1 6867315E +P 24050 8550 +F 0 "Q14" H 23950 8600 50 0000 R CNN +F 1 "eSim_NPN" H 24000 8700 50 0000 R CNN +F 2 "" H 24250 8650 29 0000 C CNN +F 3 "" H 24050 8550 60 0000 C CNN + 1 24050 8550 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q15 +U 1 1 68673385 +P 25000 9250 +F 0 "Q15" H 24900 9300 50 0000 R CNN +F 1 "eSim_NPN" H 24950 9400 50 0000 R CNN +F 2 "" H 25200 9350 29 0000 C CNN +F 3 "" H 25000 9250 60 0000 C CNN + 1 25000 9250 + 1 0 0 -1 +$EndComp +Wire Wire Line + 24800 9250 24150 9250 +Wire Wire Line + 24150 9250 24150 8750 +Wire Wire Line + 24400 9250 24400 10000 +Connection ~ 24400 9250 +$Comp +L resistor R12 +U 1 1 68673627 +P 24350 10100 +F 0 "R12" H 24400 10230 50 0000 C CNN +F 1 "15k" H 24400 10050 50 0000 C CNN +F 2 "" H 24400 10080 30 0000 C CNN +F 3 "" V 24400 10150 30 0000 C CNN + 1 24350 10100 + 0 1 1 0 +$EndComp +Wire Wire Line + 24400 10300 24400 10800 +Wire Wire Line + 24400 10800 26100 10800 +Wire Wire Line + 25100 9450 25100 10800 +Connection ~ 25100 10800 +Wire Wire Line + 25100 9900 25750 9900 +Wire Wire Line + 25750 9900 25750 9700 +Connection ~ 25100 9900 +$Comp +L eSim_Diode D3 +U 1 1 6867389F +P 25750 9550 +F 0 "D3" H 25750 9650 50 0000 C CNN +F 1 "eSim_Diode" H 25750 9450 50 0000 C CNN +F 2 "" H 25750 9550 60 0000 C CNN +F 3 "" H 25750 9550 60 0000 C CNN + 1 25750 9550 + 0 1 1 0 +$EndComp +Wire Wire Line + 25750 9400 25750 9100 +Wire Wire Line + 24150 5100 24150 8350 +Connection ~ 19450 5500 +Connection ~ 24150 5500 +Wire Wire Line + 25100 9050 25100 8250 +Wire Wire Line + 25100 8250 25150 8250 +$Comp +L PORT U1 +U 6 1 68674B11 +P 13200 17700 +F 0 "U1" H 13250 17800 30 0000 C CNN +F 1 "PORT" H 13200 17700 30 0000 C CNN +F 2 "" H 13200 17700 60 0000 C CNN +F 3 "" H 13200 17700 60 0000 C CNN + 6 13200 17700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 68674F10 +P 17100 17450 +F 0 "U1" H 17150 17550 30 0000 C CNN +F 1 "PORT" H 17100 17450 30 0000 C CNN +F 2 "" H 17100 17450 60 0000 C CNN +F 3 "" H 17100 17450 60 0000 C CNN + 5 17100 17450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 6867522F +P 18400 17150 +F 0 "U1" H 18450 17250 30 0000 C CNN +F 1 "PORT" H 18400 17150 30 0000 C CNN +F 2 "" H 18400 17150 60 0000 C CNN +F 3 "" H 18400 17150 60 0000 C CNN + 7 18400 17150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 68675409 +P 20000 17000 +F 0 "U1" H 20050 17100 30 0000 C CNN +F 1 "PORT" H 20000 17000 30 0000 C CNN +F 2 "" H 20000 17000 60 0000 C CNN +F 3 "" H 20000 17000 60 0000 C CNN + 4 20000 17000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 6867580E +P 23450 14250 +F 0 "U1" H 23500 14350 30 0000 C CNN +F 1 "PORT" H 23450 14250 30 0000 C CNN +F 2 "" H 23450 14250 60 0000 C CNN +F 3 "" H 23450 14250 60 0000 C CNN + 3 23450 14250 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 2 1 68675AF8 +P 23000 12800 +F 0 "U1" H 23050 12900 30 0000 C CNN +F 1 "PORT" H 23000 12800 30 0000 C CNN +F 2 "" H 23000 12800 60 0000 C CNN +F 3 "" H 23000 12800 60 0000 C CNN + 2 23000 12800 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 13 1 68675B85 +P 23350 12250 +F 0 "U1" H 23400 12350 30 0000 C CNN +F 1 "PORT" H 23350 12250 30 0000 C CNN +F 2 "" H 23350 12250 60 0000 C CNN +F 3 "" H 23350 12250 60 0000 C CNN + 13 23350 12250 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 10 1 68675CAE +P 26350 10800 +F 0 "U1" H 26400 10900 30 0000 C CNN +F 1 "PORT" H 26350 10800 30 0000 C CNN +F 2 "" H 26350 10800 60 0000 C CNN +F 3 "" H 26350 10800 60 0000 C CNN + 10 26350 10800 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 9 1 68675EF5 +P 26000 9100 +F 0 "U1" H 26050 9200 30 0000 C CNN +F 1 "PORT" H 26000 9100 30 0000 C CNN +F 2 "" H 26000 9100 60 0000 C CNN +F 3 "" H 26000 9100 60 0000 C CNN + 9 26000 9100 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 11 1 68675F94 +P 25400 8250 +F 0 "U1" H 25450 8350 30 0000 C CNN +F 1 "PORT" H 25400 8250 30 0000 C CNN +F 2 "" H 25400 8250 60 0000 C CNN +F 3 "" H 25400 8250 60 0000 C CNN + 11 25400 8250 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 12 1 68676039 +P 24400 5100 +F 0 "U1" H 24450 5200 30 0000 C CNN +F 1 "PORT" H 24400 5100 30 0000 C CNN +F 2 "" H 24400 5100 60 0000 C CNN +F 3 "" H 24400 5100 60 0000 C CNN + 12 24400 5100 + -1 0 0 1 +$EndComp +Text Label 24150 5350 0 60 ~ 0 +VCC +Text Label 25100 8550 0 60 ~ 0 +VC +Text Label 25750 9250 0 60 ~ 0 +VZ +Text Label 25950 10800 0 60 ~ 0 +VO +Text Label 22700 12250 0 60 ~ 0 +COMP +Text Label 22250 12800 0 60 ~ 0 +Curr_lim +Text Label 22500 14250 0 60 ~ 0 +Curr_sense +Text Label 20250 16300 0 60 ~ 0 +INV_IN +Text Label 17350 17050 0 60 ~ 0 +NON_INV_IN +Text Label 18650 16800 0 60 ~ 0 +VEE +Text Label 13450 17250 0 60 ~ 0 +VREF +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/MC1723/MC1723.cir b/library/SubcircuitLibrary/MC1723/MC1723.cir new file mode 100644 index 000000000..0f19af8fd --- /dev/null +++ b/library/SubcircuitLibrary/MC1723/MC1723.cir @@ -0,0 +1,44 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\MC1723\MC1723.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 07/04/25 01:37:30 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +D1 Net-_D1-Pad1_ /VCC eSim_Diode +R1 /VCC Net-_Q1-Pad3_ 500 +Q1 Net-_Q1-Pad1_ Net-_Q1-Pad1_ Net-_Q1-Pad3_ eSim_PNP +R2 Net-_Q1-Pad1_ Net-_D1-Pad1_ 15k +J1 Net-_D1-Pad1_ /VEE /VEE eSim_NJF +Q3 Net-_C1-Pad1_ Net-_Q1-Pad1_ Net-_Q3-Pad3_ eSim_PNP +R3 /VCC Net-_Q3-Pad3_ 25k +Q2 Net-_C1-Pad1_ Net-_C1-Pad2_ /VEE eSim_NPN +Q4 /VCC Net-_C1-Pad1_ Net-_Q1-Pad1_ eSim_NPN +Q5 /VCC Net-_Q1-Pad1_ Net-_Q5-Pad3_ eSim_NPN +R5 Net-_Q5-Pad3_ Net-_D2-Pad2_ 100 +D2 Net-_D2-Pad1_ Net-_D2-Pad2_ eSim_Diode +R6 Net-_D2-Pad1_ /VEE 5.0k +R4 Net-_C1-Pad2_ Net-_D2-Pad1_ 30k +C1 Net-_C1-Pad1_ Net-_C1-Pad2_ 5.0p +R8 Net-_Q7-Pad3_ /VEE 300 +Q7 Net-_Q6-Pad1_ Net-_Q10-Pad2_ Net-_Q7-Pad3_ eSim_NPN +Q6 Net-_Q6-Pad1_ Net-_Q1-Pad1_ Net-_Q6-Pad3_ eSim_PNP +R7 /VCC Net-_Q6-Pad3_ 1.0k +Q8 /VCC Net-_Q6-Pad1_ Net-_Q10-Pad2_ eSim_NPN +R9 Net-_Q10-Pad2_ /VEE 20k +Q10 Net-_Q10-Pad1_ Net-_Q10-Pad2_ Net-_Q10-Pad3_ eSim_NPN +R10 Net-_Q10-Pad3_ /VEE 150 +Q9 Net-_Q1-Pad1_ /NON_INV_IN Net-_Q10-Pad1_ eSim_NPN +Q12 /COMP /INV_IN Net-_Q10-Pad1_ eSim_NPN +Q11 /COMP Net-_Q1-Pad1_ Net-_Q11-Pad3_ eSim_PNP +R11 /VCC Net-_Q11-Pad3_ 1.0k +Q13 /COMP /Curr_lim /Curr_sense eSim_NPN +Q14 /VCC /COMP Net-_Q14-Pad3_ eSim_NPN +Q15 /VC Net-_Q14-Pad3_ /VO eSim_NPN +R12 Net-_Q14-Pad3_ /VO 15k +D3 /VZ /VO eSim_Diode +U1 /Curr_lim /Curr_sense /INV_IN /NON_INV_IN /VREF /VEE /VZ /VO /VC /VCC /COMP PORT +v1 Net-_D2-Pad2_ /VREF DC + +.end diff --git a/library/SubcircuitLibrary/MC1723/MC1723.cir.out b/library/SubcircuitLibrary/MC1723/MC1723.cir.out new file mode 100644 index 000000000..6d61d06e9 --- /dev/null +++ b/library/SubcircuitLibrary/MC1723/MC1723.cir.out @@ -0,0 +1,49 @@ +* c:\fossee\esim\library\subcircuitlibrary\mc1723\mc1723.cir + +.include ZenerD1N750.lib +.include NPN.lib +.include NJF.lib +.include PNP.lib +d1 net-_d1-pad1_ /vcc D1N750 +r1 /vcc net-_q1-pad3_ 500 +q1 net-_q1-pad1_ net-_q1-pad1_ net-_q1-pad3_ Q2N2907A +r2 net-_q1-pad1_ net-_d1-pad1_ 15k +j1 net-_d1-pad1_ /vee /vee J2N3819 +q3 net-_c1-pad1_ net-_q1-pad1_ net-_q3-pad3_ Q2N2907A +r3 /vcc net-_q3-pad3_ 25k +q2 net-_c1-pad1_ net-_c1-pad2_ /vee Q2N2222 +q4 /vcc net-_c1-pad1_ net-_q1-pad1_ Q2N2222 +q5 /vcc net-_q1-pad1_ net-_q5-pad3_ Q2N2222 +r5 net-_q5-pad3_ net-_d2-pad2_ 100 +d2 net-_d2-pad1_ net-_d2-pad2_ D1N750 +r6 net-_d2-pad1_ /vee 5.0k +r4 net-_c1-pad2_ net-_d2-pad1_ 30k +c1 net-_c1-pad1_ net-_c1-pad2_ 5.0p +r8 net-_q7-pad3_ /vee 300 +q7 net-_q6-pad1_ net-_q10-pad2_ net-_q7-pad3_ Q2N2222 +q6 net-_q6-pad1_ net-_q1-pad1_ net-_q6-pad3_ Q2N2907A +r7 /vcc net-_q6-pad3_ 1.0k +q8 /vcc net-_q6-pad1_ net-_q10-pad2_ Q2N2222 +r9 net-_q10-pad2_ /vee 20k +q10 net-_q10-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222 +r10 net-_q10-pad3_ /vee 150 +q9 net-_q1-pad1_ /non_inv_in net-_q10-pad1_ Q2N2222 +q12 /comp /inv_in net-_q10-pad1_ Q2N2222 +q11 /comp net-_q1-pad1_ net-_q11-pad3_ Q2N2907A +r11 /vcc net-_q11-pad3_ 1.0k +q13 /comp /curr_lim /curr_sense Q2N2222 +q14 /vcc /comp net-_q14-pad3_ Q2N2222 +q15 /vc net-_q14-pad3_ /vo Q2N2222 +r12 net-_q14-pad3_ /vo 15k +d3 /vz /vo D1N750 +* u1 /curr_lim /curr_sense /inv_in /non_inv_in /vref /vee /vz /vo /vc /vcc /comp port +v1 net-_d2-pad2_ /vref dc 7 +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/MC1723/MC1723.pro b/library/SubcircuitLibrary/MC1723/MC1723.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/MC1723/MC1723.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/MC1723/MC1723.sch b/library/SubcircuitLibrary/MC1723/MC1723.sch new file mode 100644 index 000000000..162167f0a --- /dev/null +++ b/library/SubcircuitLibrary/MC1723/MC1723.sch @@ -0,0 +1,784 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +EELAYER 25 0 +EELAYER END +$Descr A1 33110 23386 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_Diode D1 +U 1 1 6866D034 +P 5450 7100 +F 0 "D1" H 5450 7200 50 0000 C CNN +F 1 "eSim_Diode" H 5450 7000 50 0000 C CNN +F 2 "" H 5450 7100 60 0000 C CNN +F 3 "" H 5450 7100 60 0000 C CNN + 1 5450 7100 + 0 -1 -1 0 +$EndComp +$Comp +L resistor R1 +U 1 1 6866D12F +P 7650 5900 +F 0 "R1" H 7700 6030 50 0000 C CNN +F 1 "500" H 7700 5850 50 0000 C CNN +F 2 "" H 7700 5880 30 0000 C CNN +F 3 "" V 7700 5950 30 0000 C CNN + 1 7650 5900 + 0 1 1 0 +$EndComp +$Comp +L eSim_PNP Q1 +U 1 1 6866D1B5 +P 7800 7150 +F 0 "Q1" H 7700 7200 50 0000 R CNN +F 1 "eSim_PNP" H 7750 7300 50 0000 R CNN +F 2 "" H 8000 7250 29 0000 C CNN +F 3 "" H 7800 7150 60 0000 C CNN + 1 7800 7150 + -1 0 0 1 +$EndComp +$Comp +L resistor R2 +U 1 1 6866D242 +P 7650 8350 +F 0 "R2" H 7700 8480 50 0000 C CNN +F 1 "15k" H 7700 8300 50 0000 C CNN +F 2 "" H 7700 8330 30 0000 C CNN +F 3 "" V 7700 8400 30 0000 C CNN + 1 7650 8350 + 0 1 1 0 +$EndComp +$Comp +L eSim_NJF J1 +U 1 1 6866D35B +P 5700 12650 +F 0 "J1" H 5600 12700 50 0000 R CNN +F 1 "eSim_NJF" H 5650 12800 50 0000 R CNN +F 2 "" H 5900 12750 29 0000 C CNN +F 3 "" H 5700 12650 60 0000 C CNN + 1 5700 12650 + -1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q3 +U 1 1 6866D540 +P 10100 7150 +F 0 "Q3" H 10000 7200 50 0000 R CNN +F 1 "eSim_PNP" H 10050 7300 50 0000 R CNN +F 2 "" H 10300 7250 29 0000 C CNN +F 3 "" H 10100 7150 60 0000 C CNN + 1 10100 7150 + 1 0 0 1 +$EndComp +$Comp +L resistor R3 +U 1 1 6866D698 +P 10150 6050 +F 0 "R3" H 10200 6180 50 0000 C CNN +F 1 "25k" H 10200 6000 50 0000 C CNN +F 2 "" H 10200 6030 30 0000 C CNN +F 3 "" V 10200 6100 30 0000 C CNN + 1 10150 6050 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q2 +U 1 1 6866D973 +P 8400 15050 +F 0 "Q2" H 8300 15100 50 0000 R CNN +F 1 "eSim_NPN" H 8350 15200 50 0000 R CNN +F 2 "" H 8600 15150 29 0000 C CNN +F 3 "" H 8400 15050 60 0000 C CNN + 1 8400 15050 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q4 +U 1 1 6866DA95 +P 11200 9550 +F 0 "Q4" H 11100 9600 50 0000 R CNN +F 1 "eSim_NPN" H 11150 9700 50 0000 R CNN +F 2 "" H 11400 9650 29 0000 C CNN +F 3 "" H 11200 9550 60 0000 C CNN + 1 11200 9550 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q5 +U 1 1 6866DAFC +P 12500 10800 +F 0 "Q5" H 12400 10850 50 0000 R CNN +F 1 "eSim_NPN" H 12450 10950 50 0000 R CNN +F 2 "" H 12700 10900 29 0000 C CNN +F 3 "" H 12500 10800 60 0000 C CNN + 1 12500 10800 + 1 0 0 -1 +$EndComp +$Comp +L resistor R5 +U 1 1 6866DF63 +P 12550 12050 +F 0 "R5" H 12600 12180 50 0000 C CNN +F 1 "100" H 12600 12000 50 0000 C CNN +F 2 "" H 12600 12030 30 0000 C CNN +F 3 "" V 12600 12100 30 0000 C CNN + 1 12550 12050 + 0 1 1 0 +$EndComp +$Comp +L eSim_Diode D2 +U 1 1 6866E068 +P 12600 12750 +F 0 "D2" H 12600 12850 50 0000 C CNN +F 1 "eSim_Diode" H 12600 12650 50 0000 C CNN +F 2 "" H 12600 12750 60 0000 C CNN +F 3 "" H 12600 12750 60 0000 C CNN + 1 12600 12750 + 0 -1 -1 0 +$EndComp +$Comp +L resistor R6 +U 1 1 6866E0F8 +P 12550 14300 +F 0 "R6" H 12600 14430 50 0000 C CNN +F 1 "5.0k" H 12600 14250 50 0000 C CNN +F 2 "" H 12600 14280 30 0000 C CNN +F 3 "" V 12600 14350 30 0000 C CNN + 1 12550 14300 + 0 1 1 0 +$EndComp +$Comp +L resistor R4 +U 1 1 6866E39B +P 10500 14000 +F 0 "R4" H 10550 14130 50 0000 C CNN +F 1 "30k" H 10550 13950 50 0000 C CNN +F 2 "" H 10550 13980 30 0000 C CNN +F 3 "" V 10550 14050 30 0000 C CNN + 1 10500 14000 + 1 0 0 -1 +$EndComp +$Comp +L capacitor_polarised C1 +U 1 1 6866E601 +P 9150 13550 +F 0 "C1" H 9175 13650 50 0000 L CNN +F 1 "5.0p" H 9175 13450 50 0000 L CNN +F 2 "" H 9150 13550 50 0001 C CNN +F 3 "" H 9150 13550 50 0001 C CNN + 1 9150 13550 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5450 6950 5450 5500 +Wire Wire Line + 5450 5500 24150 5500 +Wire Wire Line + 7700 5500 7700 5800 +Wire Wire Line + 7700 6950 7700 6100 +Wire Wire Line + 7700 7350 7700 8250 +Wire Wire Line + 7700 8550 7700 8900 +Wire Wire Line + 7700 8900 5450 8900 +Wire Wire Line + 5450 7250 5450 9250 +Wire Wire Line + 5600 12450 5600 9250 +Wire Wire Line + 5600 9250 5450 9250 +Connection ~ 5450 8900 +Wire Wire Line + 5600 12850 5600 16350 +Wire Wire Line + 5600 16350 18650 16350 +Wire Wire Line + 18650 14900 18650 17150 +Wire Wire Line + 8000 7150 9900 7150 +Wire Wire Line + 8800 7150 8800 7800 +Wire Wire Line + 8800 7800 7700 7800 +Connection ~ 7700 7800 +Connection ~ 8800 7150 +Wire Wire Line + 10200 6950 10200 6250 +Wire Wire Line + 10200 5500 10200 5950 +Connection ~ 7700 5500 +Wire Wire Line + 5900 12650 6850 12650 +Wire Wire Line + 6850 12650 6850 16350 +Connection ~ 6850 16350 +Wire Wire Line + 8300 15250 8300 16350 +Connection ~ 8300 16350 +Wire Wire Line + 8300 9550 8300 14850 +Wire Wire Line + 8300 9550 11000 9550 +Wire Wire Line + 10200 7350 10200 9550 +Connection ~ 10200 9550 +Wire Wire Line + 11300 5500 11300 9350 +Connection ~ 10200 5500 +Wire Wire Line + 12300 10800 11300 10800 +Wire Wire Line + 11300 10800 11300 9750 +Wire Wire Line + 12600 11950 12600 11000 +Wire Wire Line + 12600 12250 12600 12600 +Wire Wire Line + 12600 12900 12600 14200 +Wire Wire Line + 8600 15050 9700 15050 +Wire Wire Line + 9700 15050 9700 14000 +Wire Wire Line + 9700 14000 10400 14000 +Wire Wire Line + 10400 14000 10400 13950 +Wire Wire Line + 10700 13950 12600 13950 +Connection ~ 12600 13950 +Wire Wire Line + 9150 13700 9150 15050 +Connection ~ 9150 15050 +Wire Wire Line + 9150 13400 9150 13000 +Wire Wire Line + 9150 13000 8300 13000 +Connection ~ 8300 13000 +Wire Wire Line + 12600 14500 12600 16350 +Connection ~ 12600 16350 +Wire Wire Line + 12600 12400 13450 12400 +Connection ~ 12600 12400 +Wire Wire Line + 12600 5500 12600 10600 +Connection ~ 11300 5500 +$Comp +L resistor R8 +U 1 1 6866ED9A +P 14700 15200 +F 0 "R8" H 14750 15330 50 0000 C CNN +F 1 "300" H 14750 15150 50 0000 C CNN +F 2 "" H 14750 15180 30 0000 C CNN +F 3 "" V 14750 15250 30 0000 C CNN + 1 14700 15200 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q7 +U 1 1 6866EE4C +P 14850 13700 +F 0 "Q7" H 14750 13750 50 0000 R CNN +F 1 "eSim_NPN" H 14800 13850 50 0000 R CNN +F 2 "" H 15050 13800 29 0000 C CNN +F 3 "" H 14850 13700 60 0000 C CNN + 1 14850 13700 + -1 0 0 -1 +$EndComp +Wire Wire Line + 14750 15100 14750 13900 +Wire Wire Line + 14750 15400 14750 16350 +Connection ~ 14750 16350 +$Comp +L eSim_PNP Q6 +U 1 1 6866F0B6 +P 14650 7100 +F 0 "Q6" H 14550 7150 50 0000 R CNN +F 1 "eSim_PNP" H 14600 7250 50 0000 R CNN +F 2 "" H 14850 7200 29 0000 C CNN +F 3 "" H 14650 7100 60 0000 C CNN + 1 14650 7100 + 1 0 0 1 +$EndComp +Wire Wire Line + 14750 7300 14750 13500 +$Comp +L resistor R7 +U 1 1 6866F697 +P 14700 6100 +F 0 "R7" H 14750 6230 50 0000 C CNN +F 1 "1.0k" H 14750 6050 50 0000 C CNN +F 2 "" H 14750 6080 30 0000 C CNN +F 3 "" V 14750 6150 30 0000 C CNN + 1 14700 6100 + 0 1 1 0 +$EndComp +Wire Wire Line + 14750 6900 14750 6300 +Wire Wire Line + 14750 5500 14750 6000 +Connection ~ 12600 5500 +Wire Wire Line + 9500 7150 9500 7550 +Wire Wire Line + 9500 7550 18800 7550 +Wire Wire Line + 13200 7550 13200 7100 +Wire Wire Line + 13200 7100 14450 7100 +Connection ~ 9500 7150 +Wire Wire Line + 14750 11150 16100 11150 +Connection ~ 14750 11150 +$Comp +L eSim_NPN Q8 +U 1 1 6866FC42 +P 16300 11150 +F 0 "Q8" H 16200 11200 50 0000 R CNN +F 1 "eSim_NPN" H 16250 11300 50 0000 R CNN +F 2 "" H 16500 11250 29 0000 C CNN +F 3 "" H 16300 11150 60 0000 C CNN + 1 16300 11150 + 1 0 0 -1 +$EndComp +Wire Wire Line + 16400 11350 16400 14700 +Wire Wire Line + 15050 13700 18350 13700 +Connection ~ 16400 13700 +$Comp +L resistor R9 +U 1 1 6866FF68 +P 16350 14800 +F 0 "R9" H 16400 14930 50 0000 C CNN +F 1 "20k" H 16400 14750 50 0000 C CNN +F 2 "" H 16400 14780 30 0000 C CNN +F 3 "" V 16400 14850 30 0000 C CNN + 1 16350 14800 + 0 1 1 0 +$EndComp +Wire Wire Line + 16400 15000 16400 16350 +Connection ~ 16400 16350 +$Comp +L eSim_NPN Q10 +U 1 1 68670127 +P 18550 13700 +F 0 "Q10" H 18450 13750 50 0000 R CNN +F 1 "eSim_NPN" H 18500 13850 50 0000 R CNN +F 2 "" H 18750 13800 29 0000 C CNN +F 3 "" H 18550 13700 60 0000 C CNN + 1 18550 13700 + 1 0 0 -1 +$EndComp +Wire Wire Line + 18650 13900 18650 14600 +$Comp +L resistor R10 +U 1 1 68670483 +P 18600 14700 +F 0 "R10" H 18650 14830 50 0000 C CNN +F 1 "150" H 18650 14650 50 0000 C CNN +F 2 "" H 18650 14680 30 0000 C CNN +F 3 "" V 18650 14750 30 0000 C CNN + 1 18600 14700 + 0 1 1 0 +$EndComp +Connection ~ 18650 16350 +Wire Wire Line + 16400 5500 16400 10950 +Connection ~ 14750 5500 +$Comp +L eSim_NPN Q9 +U 1 1 68670B38 +P 18000 11100 +F 0 "Q9" H 17900 11150 50 0000 R CNN +F 1 "eSim_NPN" H 17950 11250 50 0000 R CNN +F 2 "" H 18200 11200 29 0000 C CNN +F 3 "" H 18000 11100 60 0000 C CNN + 1 18000 11100 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q12 +U 1 1 68670C29 +P 19550 11100 +F 0 "Q12" H 19450 11150 50 0000 R CNN +F 1 "eSim_NPN" H 19500 11250 50 0000 R CNN +F 2 "" H 19750 11200 29 0000 C CNN +F 3 "" H 19550 11100 60 0000 C CNN + 1 19550 11100 + -1 0 0 -1 +$EndComp +Wire Wire Line + 18100 11300 18100 11700 +Wire Wire Line + 18100 11700 19450 11700 +Wire Wire Line + 19450 11700 19450 11300 +Wire Wire Line + 18650 13500 18650 11700 +Connection ~ 18650 11700 +Wire Wire Line + 17800 11100 17350 11100 +Wire Wire Line + 17350 11100 17350 17450 +Wire Wire Line + 18100 7550 18100 10900 +Wire Wire Line + 18100 10050 11600 10050 +Wire Wire Line + 11600 10050 11600 10800 +Connection ~ 11600 10800 +$Comp +L eSim_PNP Q11 +U 1 1 686717D7 +P 19350 7350 +F 0 "Q11" H 19250 7400 50 0000 R CNN +F 1 "eSim_PNP" H 19300 7500 50 0000 R CNN +F 2 "" H 19550 7450 29 0000 C CNN +F 3 "" H 19350 7350 60 0000 C CNN + 1 19350 7350 + 1 0 0 1 +$EndComp +$Comp +L resistor R11 +U 1 1 6867192A +P 19400 6400 +F 0 "R11" H 19450 6530 50 0000 C CNN +F 1 "1.0k" H 19450 6350 50 0000 C CNN +F 2 "" H 19450 6380 30 0000 C CNN +F 3 "" V 19450 6450 30 0000 C CNN + 1 19400 6400 + 0 1 1 0 +$EndComp +Wire Wire Line + 19450 7150 19450 6600 +Wire Wire Line + 19450 5500 19450 6300 +Connection ~ 16400 5500 +Wire Wire Line + 19450 10900 19450 7550 +Wire Wire Line + 18800 7550 18800 7350 +Wire Wire Line + 18800 7350 19150 7350 +Connection ~ 13200 7550 +Connection ~ 18100 7550 +Connection ~ 18100 10050 +Wire Wire Line + 19750 11100 20250 11100 +Wire Wire Line + 20250 11100 20250 17000 +Wire Wire Line + 19450 9600 21350 9600 +Wire Wire Line + 21350 9600 21350 12600 +Connection ~ 19450 9600 +$Comp +L eSim_NPN Q13 +U 1 1 686728F4 +P 21450 12800 +F 0 "Q13" H 21350 12850 50 0000 R CNN +F 1 "eSim_NPN" H 21400 12950 50 0000 R CNN +F 2 "" H 21650 12900 29 0000 C CNN +F 3 "" H 21450 12800 60 0000 C CNN + 1 21450 12800 + -1 0 0 -1 +$EndComp +Wire Wire Line + 21350 13000 21350 14250 +Wire Wire Line + 21350 14250 23200 14250 +Wire Wire Line + 21650 12800 22750 12800 +Wire Wire Line + 21350 12250 23100 12250 +Connection ~ 21350 12250 +Wire Wire Line + 19450 8550 23850 8550 +Connection ~ 19450 8550 +$Comp +L eSim_NPN Q14 +U 1 1 6867315E +P 24050 8550 +F 0 "Q14" H 23950 8600 50 0000 R CNN +F 1 "eSim_NPN" H 24000 8700 50 0000 R CNN +F 2 "" H 24250 8650 29 0000 C CNN +F 3 "" H 24050 8550 60 0000 C CNN + 1 24050 8550 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q15 +U 1 1 68673385 +P 25000 9250 +F 0 "Q15" H 24900 9300 50 0000 R CNN +F 1 "eSim_NPN" H 24950 9400 50 0000 R CNN +F 2 "" H 25200 9350 29 0000 C CNN +F 3 "" H 25000 9250 60 0000 C CNN + 1 25000 9250 + 1 0 0 -1 +$EndComp +Wire Wire Line + 24800 9250 24150 9250 +Wire Wire Line + 24150 9250 24150 8750 +Wire Wire Line + 24400 9250 24400 10000 +Connection ~ 24400 9250 +$Comp +L resistor R12 +U 1 1 68673627 +P 24350 10100 +F 0 "R12" H 24400 10230 50 0000 C CNN +F 1 "15k" H 24400 10050 50 0000 C CNN +F 2 "" H 24400 10080 30 0000 C CNN +F 3 "" V 24400 10150 30 0000 C CNN + 1 24350 10100 + 0 1 1 0 +$EndComp +Wire Wire Line + 24400 10300 24400 10800 +Wire Wire Line + 24400 10800 26100 10800 +Wire Wire Line + 25100 9450 25100 10800 +Connection ~ 25100 10800 +Wire Wire Line + 25100 9900 25750 9900 +Wire Wire Line + 25750 9900 25750 9700 +Connection ~ 25100 9900 +$Comp +L eSim_Diode D3 +U 1 1 6867389F +P 25750 9550 +F 0 "D3" H 25750 9650 50 0000 C CNN +F 1 "eSim_Diode" H 25750 9450 50 0000 C CNN +F 2 "" H 25750 9550 60 0000 C CNN +F 3 "" H 25750 9550 60 0000 C CNN + 1 25750 9550 + 0 1 1 0 +$EndComp +Wire Wire Line + 25750 9400 25750 9100 +Wire Wire Line + 24150 5100 24150 8350 +Connection ~ 19450 5500 +Connection ~ 24150 5500 +Wire Wire Line + 25100 9050 25100 8250 +Wire Wire Line + 25100 8250 25150 8250 +$Comp +L PORT U1 +U 6 1 68674B11 +P 13200 17700 +F 0 "U1" H 13250 17800 30 0000 C CNN +F 1 "PORT" H 13200 17700 30 0000 C CNN +F 2 "" H 13200 17700 60 0000 C CNN +F 3 "" H 13200 17700 60 0000 C CNN + 6 13200 17700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 68674F10 +P 17100 17450 +F 0 "U1" H 17150 17550 30 0000 C CNN +F 1 "PORT" H 17100 17450 30 0000 C CNN +F 2 "" H 17100 17450 60 0000 C CNN +F 3 "" H 17100 17450 60 0000 C CNN + 5 17100 17450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 6867522F +P 18400 17150 +F 0 "U1" H 18450 17250 30 0000 C CNN +F 1 "PORT" H 18400 17150 30 0000 C CNN +F 2 "" H 18400 17150 60 0000 C CNN +F 3 "" H 18400 17150 60 0000 C CNN + 7 18400 17150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 68675409 +P 20000 17000 +F 0 "U1" H 20050 17100 30 0000 C CNN +F 1 "PORT" H 20000 17000 30 0000 C CNN +F 2 "" H 20000 17000 60 0000 C CNN +F 3 "" H 20000 17000 60 0000 C CNN + 4 20000 17000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 6867580E +P 23450 14250 +F 0 "U1" H 23500 14350 30 0000 C CNN +F 1 "PORT" H 23450 14250 30 0000 C CNN +F 2 "" H 23450 14250 60 0000 C CNN +F 3 "" H 23450 14250 60 0000 C CNN + 3 23450 14250 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 2 1 68675AF8 +P 23000 12800 +F 0 "U1" H 23050 12900 30 0000 C CNN +F 1 "PORT" H 23000 12800 30 0000 C CNN +F 2 "" H 23000 12800 60 0000 C CNN +F 3 "" H 23000 12800 60 0000 C CNN + 2 23000 12800 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 13 1 68675B85 +P 23350 12250 +F 0 "U1" H 23400 12350 30 0000 C CNN +F 1 "PORT" H 23350 12250 30 0000 C CNN +F 2 "" H 23350 12250 60 0000 C CNN +F 3 "" H 23350 12250 60 0000 C CNN + 13 23350 12250 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 10 1 68675CAE +P 26350 10800 +F 0 "U1" H 26400 10900 30 0000 C CNN +F 1 "PORT" H 26350 10800 30 0000 C CNN +F 2 "" H 26350 10800 60 0000 C CNN +F 3 "" H 26350 10800 60 0000 C CNN + 10 26350 10800 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 9 1 68675EF5 +P 26000 9100 +F 0 "U1" H 26050 9200 30 0000 C CNN +F 1 "PORT" H 26000 9100 30 0000 C CNN +F 2 "" H 26000 9100 60 0000 C CNN +F 3 "" H 26000 9100 60 0000 C CNN + 9 26000 9100 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 11 1 68675F94 +P 25400 8250 +F 0 "U1" H 25450 8350 30 0000 C CNN +F 1 "PORT" H 25400 8250 30 0000 C CNN +F 2 "" H 25400 8250 60 0000 C CNN +F 3 "" H 25400 8250 60 0000 C CNN + 11 25400 8250 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 12 1 68676039 +P 24400 5100 +F 0 "U1" H 24450 5200 30 0000 C CNN +F 1 "PORT" H 24400 5100 30 0000 C CNN +F 2 "" H 24400 5100 60 0000 C CNN +F 3 "" H 24400 5100 60 0000 C CNN + 12 24400 5100 + -1 0 0 1 +$EndComp +Text Label 24150 5350 0 60 ~ 0 +VCC +Text Label 25100 8550 0 60 ~ 0 +VC +Text Label 25750 9250 0 60 ~ 0 +VZ +Text Label 25950 10800 0 60 ~ 0 +VO +Text Label 22700 12250 0 60 ~ 0 +COMP +Text Label 22250 12800 0 60 ~ 0 +Curr_lim +Text Label 22500 14250 0 60 ~ 0 +Curr_sense +Text Label 20250 16300 0 60 ~ 0 +INV_IN +Text Label 17350 17050 0 60 ~ 0 +NON_INV_IN +Text Label 18650 16800 0 60 ~ 0 +VEE +Text Label 13450 17250 0 60 ~ 0 +VREF +$Comp +L DC v1 +U 1 1 6867CB7E +P 13450 15750 +F 0 "v1" H 13250 15850 60 0000 C CNN +F 1 "DC" H 13250 15700 60 0000 C CNN +F 2 "R1" H 13150 15750 60 0000 C CNN +F 3 "" H 13450 15750 60 0000 C CNN + 1 13450 15750 + 1 0 0 -1 +$EndComp +Wire Wire Line + 13450 16200 13450 17700 +Wire Wire Line + 13450 12400 13450 15300 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/MC1723/MC1723.sub b/library/SubcircuitLibrary/MC1723/MC1723.sub new file mode 100644 index 000000000..083f3dd2c --- /dev/null +++ b/library/SubcircuitLibrary/MC1723/MC1723.sub @@ -0,0 +1,43 @@ +* Subcircuit MC1723 +.subckt MC1723 /curr_lim /curr_sense /inv_in /non_inv_in /vref /vee /vz /vo /vc /vcc /comp +* c:\fossee\esim\library\subcircuitlibrary\mc1723\mc1723.cir +.include ZenerD1N750.lib +.include NPN.lib +.include NJF.lib +.include PNP.lib +d1 net-_d1-pad1_ /vcc D1N750 +r1 /vcc net-_q1-pad3_ 500 +q1 net-_q1-pad1_ net-_q1-pad1_ net-_q1-pad3_ Q2N2907A +r2 net-_q1-pad1_ net-_d1-pad1_ 15k +j1 net-_d1-pad1_ /vee /vee J2N3819 +q3 net-_c1-pad1_ net-_q1-pad1_ net-_q3-pad3_ Q2N2907A +r3 /vcc net-_q3-pad3_ 25k +q2 net-_c1-pad1_ net-_c1-pad2_ /vee Q2N2222 +q4 /vcc net-_c1-pad1_ net-_q1-pad1_ Q2N2222 +q5 /vcc net-_q1-pad1_ net-_q5-pad3_ Q2N2222 +r5 net-_q5-pad3_ net-_d2-pad2_ 100 +d2 net-_d2-pad1_ net-_d2-pad2_ D1N750 +r6 net-_d2-pad1_ /vee 5.0k +r4 net-_c1-pad2_ net-_d2-pad1_ 30k +c1 net-_c1-pad1_ net-_c1-pad2_ 5.0p +r8 net-_q7-pad3_ /vee 300 +q7 net-_q6-pad1_ net-_q10-pad2_ net-_q7-pad3_ Q2N2222 +q6 net-_q6-pad1_ net-_q1-pad1_ net-_q6-pad3_ Q2N2907A +r7 /vcc net-_q6-pad3_ 1.0k +q8 /vcc net-_q6-pad1_ net-_q10-pad2_ Q2N2222 +r9 net-_q10-pad2_ /vee 20k +q10 net-_q10-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222 +r10 net-_q10-pad3_ /vee 150 +q9 net-_q1-pad1_ /non_inv_in net-_q10-pad1_ Q2N2222 +q12 /comp /inv_in net-_q10-pad1_ Q2N2222 +q11 /comp net-_q1-pad1_ net-_q11-pad3_ Q2N2907A +r11 /vcc net-_q11-pad3_ 1.0k +q13 /comp /curr_lim /curr_sense Q2N2222 +q14 /vcc /comp net-_q14-pad3_ Q2N2222 +q15 /vc net-_q14-pad3_ /vo Q2N2222 +r12 net-_q14-pad3_ /vo 15k +d3 /vz /vo D1N750 +v1 net-_d2-pad2_ /vref dc 7 +* Control Statements + +.ends MC1723 \ No newline at end of file diff --git a/library/SubcircuitLibrary/MC1723/MC1723_Previous_Values.xml b/library/SubcircuitLibrary/MC1723/MC1723_Previous_Values.xml new file mode 100644 index 000000000..26178a282 --- /dev/null +++ b/library/SubcircuitLibrary/MC1723/MC1723_Previous_Values.xml @@ -0,0 +1 @@ +dc7C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\ZenerD1N750.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\JFET\NJF.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\ZenerD1N750.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\ZenerD1N750.libtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec \ No newline at end of file diff --git a/library/SubcircuitLibrary/MC1723/NJF.lib b/library/SubcircuitLibrary/MC1723/NJF.lib new file mode 100644 index 000000000..dbb2cbae5 --- /dev/null +++ b/library/SubcircuitLibrary/MC1723/NJF.lib @@ -0,0 +1,4 @@ +.model J2N3819 NJF(Beta=1.304m Betatce=-.5 Rd=1 Rs=1 Lambda=2.25m Vto=-3 ++ Vtotc=-2.5m Is=33.57f Isr=322.4f N=1 Nr=2 Xti=3 Alpha=311.7u ++ Vk=243.6 Cgd=1.6p M=.3622 Pb=1 Fc=.5 Cgs=2.414p Kf=9.882E-18 ++ Af=1) diff --git a/library/SubcircuitLibrary/MC1723/NPN.lib b/library/SubcircuitLibrary/MC1723/NPN.lib new file mode 100644 index 000000000..be5f3073a --- /dev/null +++ b/library/SubcircuitLibrary/MC1723/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p ++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/MC1723/PNP.lib b/library/SubcircuitLibrary/MC1723/PNP.lib new file mode 100644 index 000000000..7edda0eab --- /dev/null +++ b/library/SubcircuitLibrary/MC1723/PNP.lib @@ -0,0 +1,4 @@ +.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 ++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 ++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 ++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/library/SubcircuitLibrary/MC1723/ZenerD1N750.lib b/library/SubcircuitLibrary/MC1723/ZenerD1N750.lib new file mode 100644 index 000000000..890c37fe2 --- /dev/null +++ b/library/SubcircuitLibrary/MC1723/ZenerD1N750.lib @@ -0,0 +1,3 @@ +.model D1N750 D( Is=880.5E-18 Rs=.25 Ikf=0 N=1 Xti=3 Eg=1.11 Cjo=175p M=.5516 ++ Vj=.75 Fc=.5 Isr=1.859n Nr=2 Bv=8.1 Ibv=20.245m Nbv=1.6989 Ibvl=1.9556m ++ Nbvl=14.976 Tbv1=-21.277u) diff --git a/library/SubcircuitLibrary/MC1723/analysis b/library/SubcircuitLibrary/MC1723/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/SubcircuitLibrary/MC1723/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/library/SubcircuitLibrary/MCT7800/BC547B.lib b/library/SubcircuitLibrary/MCT7800/BC547B.lib new file mode 100644 index 000000000..723537a7a --- /dev/null +++ b/library/SubcircuitLibrary/MCT7800/BC547B.lib @@ -0,0 +1 @@ +.model BC547B NPN(IS=1.8E-14 BF=400 NF=0.9955 VAF=80 IKF=0.14 ISE=5E-14 NE=1.46 BR=35.5 NR=1.005 VAR=12.5 IKR=0.03 ISC=1.72E-13 NC=1.27 RB=0.56 RE=0.6 RC=0.25 CJE=1.3E-11 TF=6.4E-10 CJC=4E-12 VJC=0.54 TR=5.072E-8) diff --git a/library/SubcircuitLibrary/MCT7800/MCT7800-cache.lib b/library/SubcircuitLibrary/MCT7800/MCT7800-cache.lib new file mode 100644 index 000000000..da3f9bc42 --- /dev/null +++ b/library/SubcircuitLibrary/MCT7800/MCT7800-cache.lib @@ -0,0 +1,147 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_CP1 +# +DEF eSim_CP1 C 0 10 N N 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "eSim_CP1" 25 -100 50 H V L CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +ALIAS capacitor_polarised +$FPLIST + CP_* +$ENDFPLIST +DRAW +A 0 -150 128 1287 513 0 1 20 N -80 -50 80 -50 +P 2 0 1 20 -80 30 80 30 N +P 2 0 1 0 -70 90 -30 90 N +P 2 0 1 0 -50 70 -50 110 N +X ~ 1 0 150 110 D 50 50 1 1 P +X ~ 2 0 -150 130 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_Diode +# +DEF eSim_Diode D 0 40 N N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "eSim_Diode" 0 -100 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + TO-???* + *SingleDiode + *_Diode_* + *SingleDiode* + D_* +$ENDFPLIST +DRAW +T 0 -100 50 60 0 0 0 A Normal 0 C C +T 0 100 50 60 0 0 0 K Normal 0 C C +P 2 0 1 6 50 50 50 -50 N +P 3 0 1 0 -50 50 50 0 -50 -50 F +X A 1 -150 0 100 R 40 40 1 1 P +X K 2 150 0 100 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_PNP +# +DEF eSim_PNP Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_PNP" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/MCT7800/MCT7800.bak b/library/SubcircuitLibrary/MCT7800/MCT7800.bak new file mode 100644 index 000000000..4f9aa4962 --- /dev/null +++ b/library/SubcircuitLibrary/MCT7800/MCT7800.bak @@ -0,0 +1,793 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L resistor R1 +U 1 1 683733D3 +P 1950 2400 +F 0 "R1" H 2000 2530 50 0000 C CNN +F 1 "100" H 2000 2350 50 0000 C CNN +F 2 "" H 2000 2380 30 0000 C CNN +F 3 "" V 2000 2450 30 0000 C CNN + 1 1950 2400 + 0 1 1 0 +$EndComp +$Comp +L resistor R2 +U 1 1 6837345D +P 3000 2150 +F 0 "R2" H 3050 2280 50 0000 C CNN +F 1 "500" H 3050 2100 50 0000 C CNN +F 2 "" H 3050 2130 30 0000 C CNN +F 3 "" V 3050 2200 30 0000 C CNN + 1 3000 2150 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q1 +U 1 1 683734A6 +P 2950 3200 +F 0 "Q1" H 2850 3250 50 0000 R CNN +F 1 "eSim_NPN" H 2900 3350 50 0000 R CNN +F 2 "" H 3150 3300 29 0000 C CNN +F 3 "" H 2950 3200 60 0000 C CNN + 1 2950 3200 + 1 0 0 -1 +$EndComp +$Comp +L resistor R3 +U 1 1 6837359D +P 3000 3900 +F 0 "R3" H 3050 4030 50 0000 C CNN +F 1 "3.3K" H 3050 3850 50 0000 C CNN +F 2 "" H 3050 3880 30 0000 C CNN +F 3 "" V 3050 3950 30 0000 C CNN + 1 3000 3900 + 0 1 1 0 +$EndComp +$Comp +L resistor R4 +U 1 1 683735FC +P 3000 5200 +F 0 "R4" H 3050 5330 50 0000 C CNN +F 1 "2.7K" H 3050 5150 50 0000 C CNN +F 2 "" H 3050 5180 30 0000 C CNN +F 3 "" V 3050 5250 30 0000 C CNN + 1 3000 5200 + 0 1 1 0 +$EndComp +$Comp +L resistor R5 +U 1 1 68373671 +P 3000 6350 +F 0 "R5" H 3050 6480 50 0000 C CNN +F 1 "500" H 3050 6300 50 0000 C CNN +F 2 "" H 3050 6330 30 0000 C CNN +F 3 "" V 3050 6400 30 0000 C CNN + 1 3000 6350 + 0 1 1 0 +$EndComp +$Comp +L eSim_Diode D1 +U 1 1 683737CF +P 2000 4450 +F 0 "D1" H 2000 4550 50 0000 C CNN +F 1 "eSim_Diode" H 2000 4350 50 0000 C CNN +F 2 "" H 2000 4450 60 0000 C CNN +F 3 "" H 2000 4450 60 0000 C CNN + 1 2000 4450 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_PNP Q8 +U 1 1 68373CF4 +P 5600 1750 +F 0 "Q8" H 5500 1800 50 0000 R CNN +F 1 "eSim_PNP" H 5550 1900 50 0000 R CNN +F 2 "" H 5800 1850 29 0000 C CNN +F 3 "" H 5600 1750 60 0000 C CNN + 1 5600 1750 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q12 +U 1 1 68373DC1 +P 6800 1750 +F 0 "Q12" H 6700 1800 50 0000 R CNN +F 1 "eSim_PNP" H 6750 1900 50 0000 R CNN +F 2 "" H 7000 1850 29 0000 C CNN +F 3 "" H 6800 1750 60 0000 C CNN + 1 6800 1750 + 1 0 0 1 +$EndComp +$Comp +L resistor R13 +U 1 1 68373E8C +P 6850 1200 +F 0 "R13" H 6900 1330 50 0000 C CNN +F 1 "100K" H 6900 1150 50 0000 C CNN +F 2 "" H 6900 1180 30 0000 C CNN +F 3 "" V 6900 1250 30 0000 C CNN + 1 6850 1200 + 0 1 1 0 +$EndComp +$Comp +L resistor R8 +U 1 1 68373EF9 +P 5450 1200 +F 0 "R8" H 5500 1330 50 0000 C CNN +F 1 "100" H 5500 1150 50 0000 C CNN +F 2 "" H 5500 1180 30 0000 C CNN +F 3 "" V 5500 1250 30 0000 C CNN + 1 5450 1200 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q2 +U 1 1 683742CA +P 4250 4400 +F 0 "Q2" H 4150 4450 50 0000 R CNN +F 1 "eSim_NPN" H 4200 4550 50 0000 R CNN +F 2 "" H 4450 4500 29 0000 C CNN +F 3 "" H 4250 4400 60 0000 C CNN + 1 4250 4400 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q10 +U 1 1 6837491E +P 6350 2550 +F 0 "Q10" H 6250 2600 50 0000 R CNN +F 1 "eSim_NPN" H 6300 2700 50 0000 R CNN +F 2 "" H 6550 2650 29 0000 C CNN +F 3 "" H 6350 2550 60 0000 C CNN + 1 6350 2550 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q3 +U 1 1 68374F77 +P 4450 6450 +F 0 "Q3" H 4350 6500 50 0000 R CNN +F 1 "eSim_NPN" H 4400 6600 50 0000 R CNN +F 2 "" H 4650 6550 29 0000 C CNN +F 3 "" H 4450 6450 60 0000 C CNN + 1 4450 6450 + -1 0 0 -1 +$EndComp +$Comp +L resistor R6 +U 1 1 683753C8 +P 4300 5600 +F 0 "R6" H 4350 5730 50 0000 C CNN +F 1 "1.4K" H 4350 5550 50 0000 C CNN +F 2 "" H 4350 5580 30 0000 C CNN +F 3 "" V 4350 5650 30 0000 C CNN + 1 4300 5600 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q7 +U 1 1 683756E3 +P 5400 6450 +F 0 "Q7" H 5300 6500 50 0000 R CNN +F 1 "eSim_NPN" H 5350 6600 50 0000 R CNN +F 2 "" H 5600 6550 29 0000 C CNN +F 3 "" H 5400 6450 60 0000 C CNN + 1 5400 6450 + 1 0 0 -1 +$EndComp +$Comp +L resistor R7 +U 1 1 68375756 +P 4850 6900 +F 0 "R7" H 4900 7030 50 0000 C CNN +F 1 "6.0K" H 4900 6850 50 0000 C CNN +F 2 "" H 4900 6880 30 0000 C CNN +F 3 "" V 4900 6950 30 0000 C CNN + 1 4850 6900 + 0 1 1 0 +$EndComp +$Comp +L resistor R11 +U 1 1 683757BF +P 5450 6950 +F 0 "R11" H 5500 7080 50 0000 C CNN +F 1 "1.0K" H 5500 6900 50 0000 C CNN +F 2 "" H 5500 6930 30 0000 C CNN +F 3 "" V 5500 7000 30 0000 C CNN + 1 5450 6950 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q4 +U 1 1 68375D06 +P 4650 6000 +F 0 "Q4" H 4550 6050 50 0000 R CNN +F 1 "eSim_NPN" H 4600 6150 50 0000 R CNN +F 2 "" H 4850 6100 29 0000 C CNN +F 3 "" H 4650 6000 60 0000 C CNN + 1 4650 6000 + 1 0 0 -1 +$EndComp +$Comp +L resistor R10 +U 1 1 68376041 +P 5450 5600 +F 0 "R10" H 5500 5730 50 0000 C CNN +F 1 "28K" H 5500 5550 50 0000 C CNN +F 2 "" H 5500 5580 30 0000 C CNN +F 3 "" V 5500 5650 30 0000 C CNN + 1 5450 5600 + 0 1 1 0 +$EndComp +$Comp +L resistor R9 +U 1 1 68376321 +P 5450 5050 +F 0 "R9" H 5500 5180 50 0000 C CNN +F 1 "6.0K" H 5500 5000 50 0000 C CNN +F 2 "" H 5500 5030 30 0000 C CNN +F 3 "" V 5500 5100 30 0000 C CNN + 1 5450 5050 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q6 +U 1 1 683771FE +P 5150 4550 +F 0 "Q6" H 5050 4600 50 0000 R CNN +F 1 "eSim_NPN" H 5100 4700 50 0000 R CNN +F 2 "" H 5350 4650 29 0000 C CNN +F 3 "" H 5150 4550 60 0000 C CNN + 1 5150 4550 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q5 +U 1 1 68377293 +P 5150 3500 +F 0 "Q5" H 5050 3550 50 0000 R CNN +F 1 "eSim_NPN" H 5100 3650 50 0000 R CNN +F 2 "" H 5350 3600 29 0000 C CNN +F 3 "" H 5150 3500 60 0000 C CNN + 1 5150 3500 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q9 +U 1 1 6837732F +P 5600 4000 +F 0 "Q9" H 5500 4050 50 0000 R CNN +F 1 "eSim_NPN" H 5550 4150 50 0000 R CNN +F 2 "" H 5800 4100 29 0000 C CNN +F 3 "" H 5600 4000 60 0000 C CNN + 1 5600 4000 + -1 0 0 -1 +$EndComp +$Comp +L capacitor_polarised C1 +U 1 1 68378529 +P 6050 5900 +F 0 "C1" H 6075 6000 50 0000 L CNN +F 1 "30p" H 6075 5800 50 0000 L CNN +F 2 "" H 6050 5900 50 0001 C CNN +F 3 "" H 6050 5900 50 0001 C CNN + 1 6050 5900 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_NPN Q11 +U 1 1 68378606 +P 6400 6200 +F 0 "Q11" H 6300 6250 50 0000 R CNN +F 1 "eSim_NPN" H 6350 6350 50 0000 R CNN +F 2 "" H 6600 6300 29 0000 C CNN +F 3 "" H 6400 6200 60 0000 C CNN + 1 6400 6200 + 1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q14 +U 1 1 68378E51 +P 7100 5200 +F 0 "Q14" H 7000 5250 50 0000 R CNN +F 1 "eSim_PNP" H 7050 5350 50 0000 R CNN +F 2 "" H 7300 5300 29 0000 C CNN +F 3 "" H 7100 5200 60 0000 C CNN + 1 7100 5200 + 1 0 0 1 +$EndComp +$Comp +L resistor R14 +U 1 1 68378EF1 +P 6850 4650 +F 0 "R14" H 6900 4780 50 0000 C CNN +F 1 "2.0K" H 6900 4600 50 0000 C CNN +F 2 "" H 6900 4630 30 0000 C CNN +F 3 "" V 6900 4700 30 0000 C CNN + 1 6850 4650 + 0 1 1 0 +$EndComp +$Comp +L resistor R12 +U 1 1 68379769 +P 6250 6950 +F 0 "R12" H 6300 7080 50 0000 C CNN +F 1 "5.0K" H 6300 6900 50 0000 C CNN +F 2 "" H 6300 6930 30 0000 C CNN +F 3 "" V 6300 7000 30 0000 C CNN + 1 6250 6950 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q13 +U 1 1 68379995 +P 6800 6550 +F 0 "Q13" H 6700 6600 50 0000 R CNN +F 1 "eSim_NPN" H 6750 6700 50 0000 R CNN +F 2 "" H 7000 6650 29 0000 C CNN +F 3 "" H 6800 6550 60 0000 C CNN + 1 6800 6550 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q16 +U 1 1 6837A706 +P 8550 2300 +F 0 "Q16" H 8450 2350 50 0000 R CNN +F 1 "eSim_NPN" H 8500 2450 50 0000 R CNN +F 2 "" H 8750 2400 29 0000 C CNN +F 3 "" H 8550 2300 60 0000 C CNN + 1 8550 2300 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q17 +U 1 1 6837A79F +P 10000 2650 +F 0 "Q17" H 9900 2700 50 0000 R CNN +F 1 "eSim_NPN" H 9950 2800 50 0000 R CNN +F 2 "" H 10200 2750 29 0000 C CNN +F 3 "" H 10000 2650 60 0000 C CNN + 1 10000 2650 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D2 +U 1 1 6837A926 +P 8000 1850 +F 0 "D2" H 8000 1950 50 0000 C CNN +F 1 "eSim_Diode" H 8000 1750 50 0000 C CNN +F 2 "" H 8000 1850 60 0000 C CNN +F 3 "" H 8000 1850 60 0000 C CNN + 1 8000 1850 + 0 -1 -1 0 +$EndComp +$Comp +L resistor R15 +U 1 1 6837AA35 +P 7950 1250 +F 0 "R15" H 8000 1380 50 0000 C CNN +F 1 "10K" H 8000 1200 50 0000 C CNN +F 2 "" H 8000 1230 30 0000 C CNN +F 3 "" V 8000 1300 30 0000 C CNN + 1 7950 1250 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q15 +U 1 1 6837AE59 +P 7750 2950 +F 0 "Q15" H 7650 3000 50 0000 R CNN +F 1 "eSim_NPN" H 7700 3100 50 0000 R CNN +F 2 "" H 7950 3050 29 0000 C CNN +F 3 "" H 7750 2950 60 0000 C CNN + 1 7750 2950 + -1 0 0 -1 +$EndComp +$Comp +L resistor R16 +U 1 1 6837B14E +P 8600 3150 +F 0 "R16" H 8650 3280 50 0000 C CNN +F 1 "200" H 8650 3100 50 0000 C CNN +F 2 "" H 8650 3130 30 0000 C CNN +F 3 "" V 8650 3200 30 0000 C CNN + 1 8600 3150 + 0 1 1 0 +$EndComp +$Comp +L resistor R20 +U 1 1 6837B3E1 +P 10150 3250 +F 0 "R20" H 10200 3380 50 0000 C CNN +F 1 "0.3" H 10200 3200 50 0000 C CNN +F 2 "" H 10200 3230 30 0000 C CNN +F 3 "" V 10200 3300 30 0000 C CNN + 1 10150 3250 + 0 -1 -1 0 +$EndComp +$Comp +L resistor R19 +U 1 1 6837B589 +P 9300 3000 +F 0 "R19" H 9350 3130 50 0000 C CNN +F 1 "240" H 9350 2950 50 0000 C CNN +F 2 "" H 9350 2980 30 0000 C CNN +F 3 "" V 9350 3050 30 0000 C CNN + 1 9300 3000 + 1 0 0 -1 +$EndComp +$Comp +L resistor R17 +U 1 1 6837D366 +P 9200 4250 +F 0 "R17" H 9250 4380 50 0000 C CNN +F 1 "0.25K" H 9250 4200 50 0000 C CNN +F 2 "" H 9250 4230 30 0000 C CNN +F 3 "" V 9250 4300 30 0000 C CNN + 1 9200 4250 + 0 1 1 0 +$EndComp +$Comp +L resistor R18 +U 1 1 6837D3FF +P 9200 5550 +F 0 "R18" H 9250 5680 50 0000 C CNN +F 1 "5.0K" H 9250 5500 50 0000 C CNN +F 2 "" H 9250 5530 30 0000 C CNN +F 3 "" V 9250 5600 30 0000 C CNN + 1 9200 5550 + 0 1 1 0 +$EndComp +Wire Wire Line + 2000 2300 2000 1400 +Wire Wire Line + 2000 1400 4450 1400 +Wire Wire Line + 2750 3200 2000 3200 +Wire Wire Line + 2000 2600 2000 4300 +Wire Wire Line + 3050 3000 3050 2350 +Wire Wire Line + 3050 1400 3050 2050 +Wire Wire Line + 3050 3800 3050 3400 +Wire Wire Line + 3050 4100 3050 5100 +Wire Wire Line + 3050 5400 3050 6250 +Connection ~ 2000 3200 +Wire Wire Line + 3050 6550 3050 6750 +Wire Wire Line + 2000 6750 2000 4600 +Connection ~ 3050 6750 +Wire Wire Line + 5500 1100 5500 1000 +Wire Wire Line + 5500 1400 5500 1550 +Wire Wire Line + 6900 1550 6900 1400 +Wire Wire Line + 6900 1000 6900 1100 +Wire Wire Line + 5800 1750 6600 1750 +Wire Wire Line + 4350 2950 4350 4200 +Wire Wire Line + 5500 2950 5500 1950 +Wire Wire Line + 6200 1750 6200 2150 +Wire Wire Line + 6200 2150 5500 2150 +Connection ~ 5500 2150 +Connection ~ 6200 1750 +Wire Wire Line + 4050 4400 3050 4400 +Connection ~ 3050 4400 +Wire Wire Line + 6450 2350 6450 2250 +Wire Wire Line + 6450 2250 6900 2250 +Connection ~ 6900 2250 +Wire Wire Line + 3550 2550 3550 5850 +Wire Wire Line + 3550 5850 3050 5850 +Connection ~ 3050 5850 +Wire Wire Line + 3700 6750 3700 2750 +Connection ~ 3700 6750 +Wire Wire Line + 4350 6650 4350 7400 +Wire Wire Line + 4350 5800 4350 6250 +Wire Wire Line + 4350 4600 4350 5500 +Wire Wire Line + 4650 6450 5200 6450 +Wire Wire Line + 4900 6800 4900 6450 +Connection ~ 4900 6450 +Wire Wire Line + 5500 6650 5500 6850 +Wire Wire Line + 5500 7400 5500 7150 +Wire Wire Line + 4900 7100 4900 7400 +Wire Wire Line + 4750 6200 4750 6400 +Wire Wire Line + 4750 6400 4800 6400 +Wire Wire Line + 4800 6400 4800 6450 +Connection ~ 4800 6450 +Wire Wire Line + 4450 6000 4350 6000 +Connection ~ 4350 6000 +Wire Wire Line + 5500 6250 5500 5800 +Wire Wire Line + 5500 5250 5500 5500 +Wire Wire Line + 4350 5350 5500 5350 +Connection ~ 4350 5350 +Wire Wire Line + 4750 5800 4750 5350 +Connection ~ 4750 5350 +Connection ~ 5500 5350 +Wire Wire Line + 5500 4950 5500 4200 +Wire Wire Line + 5350 4550 5500 4550 +Connection ~ 5500 4550 +Wire Wire Line + 5050 4350 5050 3700 +Wire Wire Line + 4350 2950 5500 2950 +Wire Wire Line + 5050 2950 5050 3300 +Connection ~ 5050 2950 +Wire Wire Line + 3550 2550 6150 2550 +Wire Wire Line + 3700 2750 6450 2750 +Wire Wire Line + 5350 3500 10500 3500 +Wire Wire Line + 5500 3800 5500 3500 +Connection ~ 5500 3500 +Wire Wire Line + 5800 4000 8550 4000 +Wire Wire Line + 8550 4000 8550 5100 +Wire Wire Line + 8550 5100 9250 5100 +Wire Wire Line + 5900 5900 5500 5900 +Connection ~ 5500 5900 +Wire Wire Line + 6200 6200 5650 6200 +Wire Wire Line + 5650 6200 5650 6100 +Wire Wire Line + 5650 6100 5500 6100 +Connection ~ 5500 6100 +Wire Wire Line + 6200 5900 6400 5900 +Wire Wire Line + 6400 5900 6400 5800 +Wire Wire Line + 6400 5800 6900 5800 +Wire Wire Line + 6500 6000 6500 5800 +Connection ~ 6500 5800 +Wire Wire Line + 6900 4850 6900 6350 +Connection ~ 6900 5200 +Wire Wire Line + 6900 1950 6900 4550 +Wire Wire Line + 7200 5000 7200 4300 +Wire Wire Line + 7200 4300 6900 4300 +Connection ~ 6900 4300 +Wire Wire Line + 7200 5400 7550 5400 +Wire Wire Line + 7550 5400 7550 6400 +Wire Wire Line + 6500 6400 6500 6700 +Wire Wire Line + 6300 6700 6550 6700 +Wire Wire Line + 6300 6700 6300 6850 +Connection ~ 6900 5800 +Wire Wire Line + 6600 6550 6550 6550 +Wire Wire Line + 6550 6550 6550 6700 +Connection ~ 6500 6700 +Wire Wire Line + 6900 7400 6900 6750 +Wire Wire Line + 6300 7400 6300 7150 +Wire Wire Line + 4450 1400 4450 1000 +Wire Wire Line + 4450 1000 9750 1000 +Connection ~ 3050 1400 +Connection ~ 5500 1000 +Wire Wire Line + 9750 1000 9750 1050 +Connection ~ 6900 1000 +Wire Wire Line + 8350 2300 7200 2300 +Wire Wire Line + 7200 2300 7200 2100 +Wire Wire Line + 7200 2100 6900 2100 +Connection ~ 6900 2100 +Wire Wire Line + 7650 3150 7650 3500 +Connection ~ 7650 3500 +Wire Wire Line + 9200 2950 7950 2950 +Wire Wire Line + 8000 2000 8000 2850 +Wire Wire Line + 8000 2850 8100 2850 +Wire Wire Line + 8100 2850 8100 2950 +Connection ~ 8100 2950 +Wire Wire Line + 8000 1450 8000 1700 +Wire Wire Line + 8000 1150 8000 1000 +Connection ~ 8000 1000 +Wire Wire Line + 8650 2100 8650 1000 +Connection ~ 8650 1000 +Wire Wire Line + 8650 2500 8650 3050 +Wire Wire Line + 8650 3350 8650 3500 +Connection ~ 8650 3500 +Wire Wire Line + 10100 2850 10100 3050 +Wire Wire Line + 10100 3350 10100 3500 +Connection ~ 10100 3500 +Wire Wire Line + 9800 2650 8650 2650 +Connection ~ 8650 2650 +Wire Wire Line + 9500 2950 10100 2950 +Connection ~ 10100 2950 +Wire Wire Line + 10100 2450 10100 1050 +Wire Wire Line + 9750 1050 10400 1050 +Connection ~ 10100 1050 +Wire Wire Line + 9250 4450 9250 5450 +Connection ~ 9250 5100 +Wire Wire Line + 9250 6400 9250 5750 +Wire Wire Line + 9250 4150 9250 3500 +Connection ~ 9250 3500 +Wire Wire Line + 5050 4750 5050 5350 +Connection ~ 5050 5350 +Wire Wire Line + 2000 6750 4100 6750 +Wire Wire Line + 4100 6750 4100 6950 +Wire Wire Line + 4100 6950 4350 6950 +Wire Wire Line + 4350 7400 7250 7400 +Connection ~ 4350 6950 +Connection ~ 4900 7400 +Connection ~ 5500 7400 +Connection ~ 6300 7400 +Wire Wire Line + 7250 7400 7250 6400 +Wire Wire Line + 7250 6400 10250 6400 +Connection ~ 6900 7400 +Connection ~ 7550 6400 +Connection ~ 9250 6400 +$Comp +L PORT U1 +U 2 1 683804D4 +P 10500 6400 +F 0 "U1" H 10550 6500 30 0000 C CNN +F 1 "PORT" H 10500 6400 30 0000 C CNN +F 2 "" H 10500 6400 60 0000 C CNN +F 3 "" H 10500 6400 60 0000 C CNN + 2 10500 6400 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 1 1 6838073F +P 10650 1050 +F 0 "U1" H 10700 1150 30 0000 C CNN +F 1 "PORT" H 10650 1050 30 0000 C CNN +F 2 "" H 10650 1050 60 0000 C CNN +F 3 "" H 10650 1050 60 0000 C CNN + 1 10650 1050 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 3 1 6838098E +P 10750 3500 +F 0 "U1" H 10800 3600 30 0000 C CNN +F 1 "PORT" H 10750 3500 30 0000 C CNN +F 2 "" H 10750 3500 60 0000 C CNN +F 3 "" H 10750 3500 60 0000 C CNN + 3 10750 3500 + -1 0 0 1 +$EndComp +Wire Wire Line + 7650 2750 7650 2300 +Connection ~ 7650 2300 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/MCT7800/MCT7800.cir b/library/SubcircuitLibrary/MCT7800/MCT7800.cir new file mode 100644 index 000000000..ee2afa7dd --- /dev/null +++ b/library/SubcircuitLibrary/MCT7800/MCT7800.cir @@ -0,0 +1,51 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\MCT7800\MCT7800.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 05/28/25 23:41:19 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +R1 Net-_Q16-Pad1_ Net-_D1-Pad2_ 100 +R2 Net-_Q16-Pad1_ Net-_Q1-Pad1_ 500 +Q1 Net-_Q1-Pad1_ Net-_D1-Pad2_ Net-_Q1-Pad3_ eSim_NPN +R3 Net-_Q1-Pad3_ Net-_Q2-Pad2_ 3.3K +R4 Net-_Q2-Pad2_ Net-_Q10-Pad2_ 2.7K +R5 Net-_Q10-Pad2_ Net-_D1-Pad1_ 500 +D1 Net-_D1-Pad1_ Net-_D1-Pad2_ eSim_Diode +Q8 Net-_Q12-Pad2_ Net-_Q12-Pad2_ Net-_Q8-Pad3_ eSim_PNP +Q12 Net-_Q10-Pad1_ Net-_Q12-Pad2_ Net-_Q12-Pad3_ eSim_PNP +R13 Net-_Q16-Pad1_ Net-_Q12-Pad3_ 100K +R8 Net-_Q16-Pad1_ Net-_Q8-Pad3_ 100 +Q2 Net-_Q12-Pad2_ Net-_Q2-Pad2_ Net-_Q2-Pad3_ eSim_NPN +Q10 Net-_Q10-Pad1_ Net-_Q10-Pad2_ Net-_D1-Pad1_ eSim_NPN +Q3 Net-_Q3-Pad1_ Net-_Q3-Pad2_ Net-_D1-Pad1_ eSim_NPN +R6 Net-_Q2-Pad3_ Net-_Q3-Pad1_ 1.4K +Q7 Net-_C1-Pad1_ Net-_Q3-Pad2_ Net-_Q7-Pad3_ eSim_NPN +R7 Net-_Q3-Pad2_ Net-_D1-Pad1_ 6.0K +R11 Net-_Q7-Pad3_ Net-_D1-Pad1_ 1.0K +Q4 Net-_Q2-Pad3_ Net-_Q3-Pad1_ Net-_Q3-Pad2_ eSim_NPN +R10 Net-_Q2-Pad3_ Net-_C1-Pad1_ 28K +R9 Net-_Q6-Pad2_ Net-_Q2-Pad3_ 6.0K +Q6 Net-_Q5-Pad3_ Net-_Q6-Pad2_ Net-_Q2-Pad3_ eSim_NPN +Q5 Net-_Q12-Pad2_ Net-_Q15-Pad3_ Net-_Q5-Pad3_ eSim_NPN +Q9 Net-_Q15-Pad3_ Net-_Q9-Pad2_ Net-_Q6-Pad2_ eSim_NPN +C1 Net-_C1-Pad1_ Net-_C1-Pad2_ 30p +Q11 Net-_C1-Pad2_ Net-_C1-Pad1_ Net-_Q11-Pad3_ eSim_NPN +Q14 Net-_D1-Pad1_ Net-_C1-Pad2_ Net-_Q10-Pad1_ eSim_PNP +R14 Net-_Q10-Pad1_ Net-_C1-Pad2_ 2.0K +R12 Net-_Q11-Pad3_ Net-_D1-Pad1_ 5.0K +Q13 Net-_C1-Pad2_ Net-_Q11-Pad3_ Net-_D1-Pad1_ eSim_NPN +Q16 Net-_Q16-Pad1_ Net-_Q10-Pad1_ Net-_Q16-Pad3_ eSim_NPN +Q17 Net-_Q16-Pad1_ Net-_Q16-Pad3_ Net-_Q17-Pad3_ eSim_NPN +D2 Net-_D2-Pad1_ Net-_D2-Pad2_ eSim_Diode +R15 Net-_Q16-Pad1_ Net-_D2-Pad2_ 10K +Q15 Net-_Q10-Pad1_ Net-_D2-Pad1_ Net-_Q15-Pad3_ eSim_NPN +R16 Net-_Q16-Pad3_ Net-_Q15-Pad3_ 200 +R20 Net-_Q15-Pad3_ Net-_Q17-Pad3_ 0.3 +R19 Net-_D2-Pad1_ Net-_Q17-Pad3_ 240 +R17 Net-_Q15-Pad3_ Net-_Q9-Pad2_ 0.25K +R18 Net-_Q9-Pad2_ Net-_D1-Pad1_ 5.0K +U1 Net-_Q16-Pad1_ Net-_D1-Pad1_ Net-_Q15-Pad3_ PORT + +.end diff --git a/library/SubcircuitLibrary/MCT7800/MCT7800.cir.out b/library/SubcircuitLibrary/MCT7800/MCT7800.cir.out new file mode 100644 index 000000000..ad2f477ab --- /dev/null +++ b/library/SubcircuitLibrary/MCT7800/MCT7800.cir.out @@ -0,0 +1,55 @@ +* c:\fossee\esim\library\subcircuitlibrary\mct7800\mct7800.cir + +.include BC547B.lib +.include PNP.lib +.include ZenerD1N750.lib +r1 net-_q16-pad1_ net-_d1-pad2_ 100 +r2 net-_q16-pad1_ net-_q1-pad1_ 500 +q1 net-_q1-pad1_ net-_d1-pad2_ net-_q1-pad3_ BC547B +r3 net-_q1-pad3_ net-_q2-pad2_ 3.3k +r4 net-_q2-pad2_ net-_q10-pad2_ 2.7k +r5 net-_q10-pad2_ net-_d1-pad1_ 500 +d1 net-_d1-pad1_ net-_d1-pad2_ D1N750 +q8 net-_q12-pad2_ net-_q12-pad2_ net-_q8-pad3_ Q2N2907A +q12 net-_q10-pad1_ net-_q12-pad2_ net-_q12-pad3_ Q2N2907A +r13 net-_q16-pad1_ net-_q12-pad3_ 100k +r8 net-_q16-pad1_ net-_q8-pad3_ 100 +q2 net-_q12-pad2_ net-_q2-pad2_ net-_q2-pad3_ BC547B +q10 net-_q10-pad1_ net-_q10-pad2_ net-_d1-pad1_ BC547B +q3 net-_q3-pad1_ net-_q3-pad2_ net-_d1-pad1_ BC547B +r6 net-_q2-pad3_ net-_q3-pad1_ 1.4k +q7 net-_c1-pad1_ net-_q3-pad2_ net-_q7-pad3_ BC547B +r7 net-_q3-pad2_ net-_d1-pad1_ 6.0k +r11 net-_q7-pad3_ net-_d1-pad1_ 1.0k +q4 net-_q2-pad3_ net-_q3-pad1_ net-_q3-pad2_ BC547B +r10 net-_q2-pad3_ net-_c1-pad1_ 28k +r9 net-_q6-pad2_ net-_q2-pad3_ 6.0k +q6 net-_q5-pad3_ net-_q6-pad2_ net-_q2-pad3_ BC547B +q5 net-_q12-pad2_ net-_q15-pad3_ net-_q5-pad3_ BC547B +q9 net-_q15-pad3_ net-_q9-pad2_ net-_q6-pad2_ BC547B +c1 net-_c1-pad1_ net-_c1-pad2_ 30p +q11 net-_c1-pad2_ net-_c1-pad1_ net-_q11-pad3_ BC547B +q14 net-_d1-pad1_ net-_c1-pad2_ net-_q10-pad1_ Q2N2907A +r14 net-_q10-pad1_ net-_c1-pad2_ 2.0k +r12 net-_q11-pad3_ net-_d1-pad1_ 5.0k +q13 net-_c1-pad2_ net-_q11-pad3_ net-_d1-pad1_ BC547B +q16 net-_q16-pad1_ net-_q10-pad1_ net-_q16-pad3_ BC547B +q17 net-_q16-pad1_ net-_q16-pad3_ net-_q17-pad3_ BC547B +d2 net-_d2-pad1_ net-_d2-pad2_ D1N750 +r15 net-_q16-pad1_ net-_d2-pad2_ 10k +q15 net-_q10-pad1_ net-_d2-pad1_ net-_q15-pad3_ BC547B +r16 net-_q16-pad3_ net-_q15-pad3_ 200 +r20 net-_q15-pad3_ net-_q17-pad3_ 0.3 +r19 net-_d2-pad1_ net-_q17-pad3_ 240 +r17 net-_q15-pad3_ net-_q9-pad2_ 0.25k +r18 net-_q9-pad2_ net-_d1-pad1_ 5.0k +* u1 net-_q16-pad1_ net-_d1-pad1_ net-_q15-pad3_ port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/MCT7800/MCT7800.pro b/library/SubcircuitLibrary/MCT7800/MCT7800.pro new file mode 100644 index 000000000..9591dc820 --- /dev/null +++ b/library/SubcircuitLibrary/MCT7800/MCT7800.pro @@ -0,0 +1,83 @@ +update=07/01/25 20:35:23 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts +[schematic_editor] +version=1 +PageLayoutDescrFile= +PlotDirectoryName= +SubpartIdSeparator=0 +SubpartFirstId=65 +NetFmtName= +SpiceForceRefPrefix=0 +SpiceUseNetNumbers=0 +LabSize=60 diff --git a/library/SubcircuitLibrary/MCT7800/MCT7800.sch b/library/SubcircuitLibrary/MCT7800/MCT7800.sch new file mode 100644 index 000000000..4467b8444 --- /dev/null +++ b/library/SubcircuitLibrary/MCT7800/MCT7800.sch @@ -0,0 +1,794 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:MCT7800-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L resistor R1 +U 1 1 683733D3 +P 1400 2350 +F 0 "R1" H 1450 2480 50 0000 C CNN +F 1 "100" H 1450 2300 50 0000 C CNN +F 2 "" H 1450 2330 30 0000 C CNN +F 3 "" V 1450 2400 30 0000 C CNN + 1 1400 2350 + 0 1 1 0 +$EndComp +$Comp +L resistor R2 +U 1 1 6837345D +P 2450 2100 +F 0 "R2" H 2500 2230 50 0000 C CNN +F 1 "500" H 2500 2050 50 0000 C CNN +F 2 "" H 2500 2080 30 0000 C CNN +F 3 "" V 2500 2150 30 0000 C CNN + 1 2450 2100 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q1 +U 1 1 683734A6 +P 2400 3150 +F 0 "Q1" H 2300 3200 50 0000 R CNN +F 1 "eSim_NPN" H 2350 3300 50 0000 R CNN +F 2 "" H 2600 3250 29 0000 C CNN +F 3 "" H 2400 3150 60 0000 C CNN + 1 2400 3150 + 1 0 0 -1 +$EndComp +$Comp +L resistor R3 +U 1 1 6837359D +P 2450 3850 +F 0 "R3" H 2500 3980 50 0000 C CNN +F 1 "3.3K" H 2500 3800 50 0000 C CNN +F 2 "" H 2500 3830 30 0000 C CNN +F 3 "" V 2500 3900 30 0000 C CNN + 1 2450 3850 + 0 1 1 0 +$EndComp +$Comp +L resistor R4 +U 1 1 683735FC +P 2450 5150 +F 0 "R4" H 2500 5280 50 0000 C CNN +F 1 "2.7K" H 2500 5100 50 0000 C CNN +F 2 "" H 2500 5130 30 0000 C CNN +F 3 "" V 2500 5200 30 0000 C CNN + 1 2450 5150 + 0 1 1 0 +$EndComp +$Comp +L resistor R5 +U 1 1 68373671 +P 2450 6300 +F 0 "R5" H 2500 6430 50 0000 C CNN +F 1 "500" H 2500 6250 50 0000 C CNN +F 2 "" H 2500 6280 30 0000 C CNN +F 3 "" V 2500 6350 30 0000 C CNN + 1 2450 6300 + 0 1 1 0 +$EndComp +$Comp +L eSim_Diode D1 +U 1 1 683737CF +P 1450 4400 +F 0 "D1" H 1450 4500 50 0000 C CNN +F 1 "eSim_Diode" H 1450 4300 50 0000 C CNN +F 2 "" H 1450 4400 60 0000 C CNN +F 3 "" H 1450 4400 60 0000 C CNN + 1 1450 4400 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_PNP Q8 +U 1 1 68373CF4 +P 5050 1700 +F 0 "Q8" H 4950 1750 50 0000 R CNN +F 1 "eSim_PNP" H 5000 1850 50 0000 R CNN +F 2 "" H 5250 1800 29 0000 C CNN +F 3 "" H 5050 1700 60 0000 C CNN + 1 5050 1700 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q12 +U 1 1 68373DC1 +P 6250 1700 +F 0 "Q12" H 6150 1750 50 0000 R CNN +F 1 "eSim_PNP" H 6200 1850 50 0000 R CNN +F 2 "" H 6450 1800 29 0000 C CNN +F 3 "" H 6250 1700 60 0000 C CNN + 1 6250 1700 + 1 0 0 1 +$EndComp +$Comp +L resistor R13 +U 1 1 68373E8C +P 6300 1150 +F 0 "R13" H 6350 1280 50 0000 C CNN +F 1 "100K" H 6350 1100 50 0000 C CNN +F 2 "" H 6350 1130 30 0000 C CNN +F 3 "" V 6350 1200 30 0000 C CNN + 1 6300 1150 + 0 1 1 0 +$EndComp +$Comp +L resistor R8 +U 1 1 68373EF9 +P 4900 1150 +F 0 "R8" H 4950 1280 50 0000 C CNN +F 1 "100" H 4950 1100 50 0000 C CNN +F 2 "" H 4950 1130 30 0000 C CNN +F 3 "" V 4950 1200 30 0000 C CNN + 1 4900 1150 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q2 +U 1 1 683742CA +P 3700 4350 +F 0 "Q2" H 3600 4400 50 0000 R CNN +F 1 "eSim_NPN" H 3650 4500 50 0000 R CNN +F 2 "" H 3900 4450 29 0000 C CNN +F 3 "" H 3700 4350 60 0000 C CNN + 1 3700 4350 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q10 +U 1 1 6837491E +P 5800 2500 +F 0 "Q10" H 5700 2550 50 0000 R CNN +F 1 "eSim_NPN" H 5750 2650 50 0000 R CNN +F 2 "" H 6000 2600 29 0000 C CNN +F 3 "" H 5800 2500 60 0000 C CNN + 1 5800 2500 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q3 +U 1 1 68374F77 +P 3900 6400 +F 0 "Q3" H 3800 6450 50 0000 R CNN +F 1 "eSim_NPN" H 3850 6550 50 0000 R CNN +F 2 "" H 4100 6500 29 0000 C CNN +F 3 "" H 3900 6400 60 0000 C CNN + 1 3900 6400 + -1 0 0 -1 +$EndComp +$Comp +L resistor R6 +U 1 1 683753C8 +P 3750 5550 +F 0 "R6" H 3800 5680 50 0000 C CNN +F 1 "1.4K" H 3800 5500 50 0000 C CNN +F 2 "" H 3800 5530 30 0000 C CNN +F 3 "" V 3800 5600 30 0000 C CNN + 1 3750 5550 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q7 +U 1 1 683756E3 +P 4850 6400 +F 0 "Q7" H 4750 6450 50 0000 R CNN +F 1 "eSim_NPN" H 4800 6550 50 0000 R CNN +F 2 "" H 5050 6500 29 0000 C CNN +F 3 "" H 4850 6400 60 0000 C CNN + 1 4850 6400 + 1 0 0 -1 +$EndComp +$Comp +L resistor R7 +U 1 1 68375756 +P 4300 6850 +F 0 "R7" H 4350 6980 50 0000 C CNN +F 1 "6.0K" H 4350 6800 50 0000 C CNN +F 2 "" H 4350 6830 30 0000 C CNN +F 3 "" V 4350 6900 30 0000 C CNN + 1 4300 6850 + 0 1 1 0 +$EndComp +$Comp +L resistor R11 +U 1 1 683757BF +P 4900 6900 +F 0 "R11" H 4950 7030 50 0000 C CNN +F 1 "1.0K" H 4950 6850 50 0000 C CNN +F 2 "" H 4950 6880 30 0000 C CNN +F 3 "" V 4950 6950 30 0000 C CNN + 1 4900 6900 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q4 +U 1 1 68375D06 +P 4100 5950 +F 0 "Q4" H 4000 6000 50 0000 R CNN +F 1 "eSim_NPN" H 4050 6100 50 0000 R CNN +F 2 "" H 4300 6050 29 0000 C CNN +F 3 "" H 4100 5950 60 0000 C CNN + 1 4100 5950 + 1 0 0 -1 +$EndComp +$Comp +L resistor R10 +U 1 1 68376041 +P 4900 5550 +F 0 "R10" H 4950 5680 50 0000 C CNN +F 1 "28K" H 4950 5500 50 0000 C CNN +F 2 "" H 4950 5530 30 0000 C CNN +F 3 "" V 4950 5600 30 0000 C CNN + 1 4900 5550 + 0 1 1 0 +$EndComp +$Comp +L resistor R9 +U 1 1 68376321 +P 4900 5000 +F 0 "R9" H 4950 5130 50 0000 C CNN +F 1 "6.0K" H 4950 4950 50 0000 C CNN +F 2 "" H 4950 4980 30 0000 C CNN +F 3 "" V 4950 5050 30 0000 C CNN + 1 4900 5000 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q6 +U 1 1 683771FE +P 4600 4500 +F 0 "Q6" H 4500 4550 50 0000 R CNN +F 1 "eSim_NPN" H 4550 4650 50 0000 R CNN +F 2 "" H 4800 4600 29 0000 C CNN +F 3 "" H 4600 4500 60 0000 C CNN + 1 4600 4500 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q5 +U 1 1 68377293 +P 4600 3450 +F 0 "Q5" H 4500 3500 50 0000 R CNN +F 1 "eSim_NPN" H 4550 3600 50 0000 R CNN +F 2 "" H 4800 3550 29 0000 C CNN +F 3 "" H 4600 3450 60 0000 C CNN + 1 4600 3450 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q9 +U 1 1 6837732F +P 5050 3950 +F 0 "Q9" H 4950 4000 50 0000 R CNN +F 1 "eSim_NPN" H 5000 4100 50 0000 R CNN +F 2 "" H 5250 4050 29 0000 C CNN +F 3 "" H 5050 3950 60 0000 C CNN + 1 5050 3950 + -1 0 0 -1 +$EndComp +$Comp +L capacitor_polarised C1 +U 1 1 68378529 +P 5500 5850 +F 0 "C1" H 5525 5950 50 0000 L CNN +F 1 "30p" H 5525 5750 50 0000 L CNN +F 2 "" H 5500 5850 50 0001 C CNN +F 3 "" H 5500 5850 50 0001 C CNN + 1 5500 5850 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_NPN Q11 +U 1 1 68378606 +P 5850 6150 +F 0 "Q11" H 5750 6200 50 0000 R CNN +F 1 "eSim_NPN" H 5800 6300 50 0000 R CNN +F 2 "" H 6050 6250 29 0000 C CNN +F 3 "" H 5850 6150 60 0000 C CNN + 1 5850 6150 + 1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q14 +U 1 1 68378E51 +P 6550 5150 +F 0 "Q14" H 6450 5200 50 0000 R CNN +F 1 "eSim_PNP" H 6500 5300 50 0000 R CNN +F 2 "" H 6750 5250 29 0000 C CNN +F 3 "" H 6550 5150 60 0000 C CNN + 1 6550 5150 + 1 0 0 1 +$EndComp +$Comp +L resistor R14 +U 1 1 68378EF1 +P 6300 4600 +F 0 "R14" H 6350 4730 50 0000 C CNN +F 1 "2.0K" H 6350 4550 50 0000 C CNN +F 2 "" H 6350 4580 30 0000 C CNN +F 3 "" V 6350 4650 30 0000 C CNN + 1 6300 4600 + 0 1 1 0 +$EndComp +$Comp +L resistor R12 +U 1 1 68379769 +P 5700 6900 +F 0 "R12" H 5750 7030 50 0000 C CNN +F 1 "5.0K" H 5750 6850 50 0000 C CNN +F 2 "" H 5750 6880 30 0000 C CNN +F 3 "" V 5750 6950 30 0000 C CNN + 1 5700 6900 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q13 +U 1 1 68379995 +P 6250 6500 +F 0 "Q13" H 6150 6550 50 0000 R CNN +F 1 "eSim_NPN" H 6200 6650 50 0000 R CNN +F 2 "" H 6450 6600 29 0000 C CNN +F 3 "" H 6250 6500 60 0000 C CNN + 1 6250 6500 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q16 +U 1 1 6837A706 +P 8000 2250 +F 0 "Q16" H 7900 2300 50 0000 R CNN +F 1 "eSim_NPN" H 7950 2400 50 0000 R CNN +F 2 "" H 8200 2350 29 0000 C CNN +F 3 "" H 8000 2250 60 0000 C CNN + 1 8000 2250 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q17 +U 1 1 6837A79F +P 9450 2600 +F 0 "Q17" H 9350 2650 50 0000 R CNN +F 1 "eSim_NPN" H 9400 2750 50 0000 R CNN +F 2 "" H 9650 2700 29 0000 C CNN +F 3 "" H 9450 2600 60 0000 C CNN + 1 9450 2600 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D2 +U 1 1 6837A926 +P 7450 1800 +F 0 "D2" H 7450 1900 50 0000 C CNN +F 1 "eSim_Diode" H 7450 1700 50 0000 C CNN +F 2 "" H 7450 1800 60 0000 C CNN +F 3 "" H 7450 1800 60 0000 C CNN + 1 7450 1800 + 0 -1 -1 0 +$EndComp +$Comp +L resistor R15 +U 1 1 6837AA35 +P 7400 1200 +F 0 "R15" H 7450 1330 50 0000 C CNN +F 1 "10K" H 7450 1150 50 0000 C CNN +F 2 "" H 7450 1180 30 0000 C CNN +F 3 "" V 7450 1250 30 0000 C CNN + 1 7400 1200 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q15 +U 1 1 6837AE59 +P 7200 2900 +F 0 "Q15" H 7100 2950 50 0000 R CNN +F 1 "eSim_NPN" H 7150 3050 50 0000 R CNN +F 2 "" H 7400 3000 29 0000 C CNN +F 3 "" H 7200 2900 60 0000 C CNN + 1 7200 2900 + -1 0 0 -1 +$EndComp +$Comp +L resistor R16 +U 1 1 6837B14E +P 8050 3100 +F 0 "R16" H 8100 3230 50 0000 C CNN +F 1 "200" H 8100 3050 50 0000 C CNN +F 2 "" H 8100 3080 30 0000 C CNN +F 3 "" V 8100 3150 30 0000 C CNN + 1 8050 3100 + 0 1 1 0 +$EndComp +$Comp +L resistor R20 +U 1 1 6837B3E1 +P 9600 3200 +F 0 "R20" H 9650 3330 50 0000 C CNN +F 1 "0.3" H 9650 3150 50 0000 C CNN +F 2 "" H 9650 3180 30 0000 C CNN +F 3 "" V 9650 3250 30 0000 C CNN + 1 9600 3200 + 0 -1 -1 0 +$EndComp +$Comp +L resistor R19 +U 1 1 6837B589 +P 8750 2950 +F 0 "R19" H 8800 3080 50 0000 C CNN +F 1 "240" H 8800 2900 50 0000 C CNN +F 2 "" H 8800 2930 30 0000 C CNN +F 3 "" V 8800 3000 30 0000 C CNN + 1 8750 2950 + 1 0 0 -1 +$EndComp +$Comp +L resistor R17 +U 1 1 6837D366 +P 8650 4200 +F 0 "R17" H 8700 4330 50 0000 C CNN +F 1 "0.25K" H 8700 4150 50 0000 C CNN +F 2 "" H 8700 4180 30 0000 C CNN +F 3 "" V 8700 4250 30 0000 C CNN + 1 8650 4200 + 0 1 1 0 +$EndComp +$Comp +L resistor R18 +U 1 1 6837D3FF +P 8650 5500 +F 0 "R18" H 8700 5630 50 0000 C CNN +F 1 "5.0K" H 8700 5450 50 0000 C CNN +F 2 "" H 8700 5480 30 0000 C CNN +F 3 "" V 8700 5550 30 0000 C CNN + 1 8650 5500 + 0 1 1 0 +$EndComp +Wire Wire Line + 1450 2250 1450 1350 +Wire Wire Line + 1450 1350 3900 1350 +Wire Wire Line + 2200 3150 1450 3150 +Wire Wire Line + 1450 2550 1450 4250 +Wire Wire Line + 2500 2950 2500 2300 +Wire Wire Line + 2500 1350 2500 2000 +Wire Wire Line + 2500 3750 2500 3350 +Wire Wire Line + 2500 4050 2500 5050 +Wire Wire Line + 2500 5350 2500 6200 +Connection ~ 1450 3150 +Wire Wire Line + 2500 6500 2500 6700 +Wire Wire Line + 1450 6700 1450 4550 +Connection ~ 2500 6700 +Wire Wire Line + 4950 1050 4950 950 +Wire Wire Line + 4950 1350 4950 1500 +Wire Wire Line + 6350 1500 6350 1350 +Wire Wire Line + 6350 950 6350 1050 +Wire Wire Line + 5250 1700 6050 1700 +Wire Wire Line + 3800 2900 3800 4150 +Wire Wire Line + 4950 2900 4950 1900 +Wire Wire Line + 5650 1700 5650 2100 +Wire Wire Line + 5650 2100 4950 2100 +Connection ~ 4950 2100 +Connection ~ 5650 1700 +Wire Wire Line + 3500 4350 2500 4350 +Connection ~ 2500 4350 +Wire Wire Line + 5900 2300 5900 2200 +Wire Wire Line + 5900 2200 6350 2200 +Connection ~ 6350 2200 +Wire Wire Line + 3000 2500 3000 5800 +Wire Wire Line + 3000 5800 2500 5800 +Connection ~ 2500 5800 +Wire Wire Line + 3150 6700 3150 2700 +Connection ~ 3150 6700 +Wire Wire Line + 3800 6600 3800 7350 +Wire Wire Line + 3800 5750 3800 6200 +Wire Wire Line + 3800 4550 3800 5450 +Wire Wire Line + 4100 6400 4650 6400 +Wire Wire Line + 4350 6750 4350 6400 +Connection ~ 4350 6400 +Wire Wire Line + 4950 6600 4950 6800 +Wire Wire Line + 4950 7350 4950 7100 +Wire Wire Line + 4350 7050 4350 7350 +Wire Wire Line + 4200 6150 4200 6350 +Wire Wire Line + 4200 6350 4250 6350 +Wire Wire Line + 4250 6350 4250 6400 +Connection ~ 4250 6400 +Wire Wire Line + 3900 5950 3800 5950 +Connection ~ 3800 5950 +Wire Wire Line + 4950 6200 4950 5750 +Wire Wire Line + 4950 5200 4950 5450 +Wire Wire Line + 3800 5300 4950 5300 +Connection ~ 3800 5300 +Wire Wire Line + 4200 5750 4200 5300 +Connection ~ 4200 5300 +Connection ~ 4950 5300 +Wire Wire Line + 4950 4900 4950 4150 +Wire Wire Line + 4800 4500 4950 4500 +Connection ~ 4950 4500 +Wire Wire Line + 4500 4300 4500 3650 +Wire Wire Line + 3800 2900 4950 2900 +Wire Wire Line + 4500 2900 4500 3250 +Connection ~ 4500 2900 +Wire Wire Line + 3000 2500 5600 2500 +Wire Wire Line + 3150 2700 5900 2700 +Wire Wire Line + 4800 3450 9950 3450 +Wire Wire Line + 4950 3750 4950 3450 +Connection ~ 4950 3450 +Wire Wire Line + 5250 3950 8000 3950 +Wire Wire Line + 8000 3950 8000 5050 +Wire Wire Line + 8000 5050 8700 5050 +Wire Wire Line + 5350 5850 4950 5850 +Connection ~ 4950 5850 +Wire Wire Line + 5650 6150 5100 6150 +Wire Wire Line + 5100 6150 5100 6050 +Wire Wire Line + 5100 6050 4950 6050 +Connection ~ 4950 6050 +Wire Wire Line + 5650 5850 5850 5850 +Wire Wire Line + 5850 5850 5850 5750 +Wire Wire Line + 5850 5750 6350 5750 +Wire Wire Line + 5950 5950 5950 5750 +Connection ~ 5950 5750 +Wire Wire Line + 6350 4800 6350 6300 +Connection ~ 6350 5150 +Wire Wire Line + 6350 1900 6350 4500 +Wire Wire Line + 6650 4950 6650 4250 +Wire Wire Line + 6650 4250 6350 4250 +Connection ~ 6350 4250 +Wire Wire Line + 6650 5350 7000 5350 +Wire Wire Line + 7000 5350 7000 6350 +Wire Wire Line + 5950 6350 5950 6650 +Wire Wire Line + 5750 6650 6000 6650 +Wire Wire Line + 5750 6650 5750 6800 +Connection ~ 6350 5750 +Wire Wire Line + 6050 6500 6000 6500 +Wire Wire Line + 6000 6500 6000 6650 +Connection ~ 5950 6650 +Wire Wire Line + 6350 7350 6350 6700 +Wire Wire Line + 5750 7350 5750 7100 +Wire Wire Line + 3900 1350 3900 950 +Wire Wire Line + 3900 950 9200 950 +Connection ~ 2500 1350 +Connection ~ 4950 950 +Wire Wire Line + 9200 950 9200 1000 +Connection ~ 6350 950 +Wire Wire Line + 7800 2250 6650 2250 +Wire Wire Line + 6650 2250 6650 2050 +Wire Wire Line + 6650 2050 6350 2050 +Connection ~ 6350 2050 +Wire Wire Line + 7100 3100 7100 3450 +Connection ~ 7100 3450 +Wire Wire Line + 8650 2900 7400 2900 +Wire Wire Line + 7450 1950 7450 2800 +Wire Wire Line + 7450 2800 7550 2800 +Wire Wire Line + 7550 2800 7550 2900 +Connection ~ 7550 2900 +Wire Wire Line + 7450 1400 7450 1650 +Wire Wire Line + 7450 1100 7450 950 +Connection ~ 7450 950 +Wire Wire Line + 8100 2050 8100 950 +Connection ~ 8100 950 +Wire Wire Line + 8100 2450 8100 3000 +Wire Wire Line + 8100 3300 8100 3450 +Connection ~ 8100 3450 +Wire Wire Line + 9550 2800 9550 3000 +Wire Wire Line + 9550 3300 9550 3450 +Connection ~ 9550 3450 +Wire Wire Line + 9250 2600 8100 2600 +Connection ~ 8100 2600 +Wire Wire Line + 8950 2900 9550 2900 +Connection ~ 9550 2900 +Wire Wire Line + 9550 2400 9550 1000 +Wire Wire Line + 9200 1000 9850 1000 +Connection ~ 9550 1000 +Wire Wire Line + 8700 4400 8700 5400 +Connection ~ 8700 5050 +Wire Wire Line + 8700 6350 8700 5700 +Wire Wire Line + 8700 4100 8700 3450 +Connection ~ 8700 3450 +Wire Wire Line + 4500 4700 4500 5300 +Connection ~ 4500 5300 +Wire Wire Line + 1450 6700 3550 6700 +Wire Wire Line + 3550 6700 3550 6900 +Wire Wire Line + 3550 6900 3800 6900 +Wire Wire Line + 3800 7350 6700 7350 +Connection ~ 3800 6900 +Connection ~ 4350 7350 +Connection ~ 4950 7350 +Connection ~ 5750 7350 +Wire Wire Line + 6700 7350 6700 6350 +Wire Wire Line + 6700 6350 9700 6350 +Connection ~ 6350 7350 +Connection ~ 7000 6350 +Connection ~ 8700 6350 +$Comp +L PORT U1 +U 2 1 683804D4 +P 9950 6350 +F 0 "U1" H 10000 6450 30 0000 C CNN +F 1 "PORT" H 9950 6350 30 0000 C CNN +F 2 "" H 9950 6350 60 0000 C CNN +F 3 "" H 9950 6350 60 0000 C CNN + 2 9950 6350 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 1 1 6838073F +P 10100 1000 +F 0 "U1" H 10150 1100 30 0000 C CNN +F 1 "PORT" H 10100 1000 30 0000 C CNN +F 2 "" H 10100 1000 60 0000 C CNN +F 3 "" H 10100 1000 60 0000 C CNN + 1 10100 1000 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 3 1 6838098E +P 10200 3450 +F 0 "U1" H 10250 3550 30 0000 C CNN +F 1 "PORT" H 10200 3450 30 0000 C CNN +F 2 "" H 10200 3450 60 0000 C CNN +F 3 "" H 10200 3450 60 0000 C CNN + 3 10200 3450 + -1 0 0 1 +$EndComp +Wire Wire Line + 7100 2700 7100 2250 +Connection ~ 7100 2250 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/MCT7800/MCT7800.sub b/library/SubcircuitLibrary/MCT7800/MCT7800.sub new file mode 100644 index 000000000..539a1707d --- /dev/null +++ b/library/SubcircuitLibrary/MCT7800/MCT7800.sub @@ -0,0 +1,49 @@ +* Subcircuit MCT7800 +.subckt MCT7800 net-_q16-pad1_ net-_d1-pad1_ net-_q15-pad3_ +* c:\fossee\esim\library\subcircuitlibrary\mct7800\mct7800.cir +.include BC547B.lib +.include PNP.lib +.include ZenerD1N750.lib +r1 net-_q16-pad1_ net-_d1-pad2_ 100 +r2 net-_q16-pad1_ net-_q1-pad1_ 500 +q1 net-_q1-pad1_ net-_d1-pad2_ net-_q1-pad3_ BC547B +r3 net-_q1-pad3_ net-_q2-pad2_ 3.3k +r4 net-_q2-pad2_ net-_q10-pad2_ 2.7k +r5 net-_q10-pad2_ net-_d1-pad1_ 500 +d1 net-_d1-pad1_ net-_d1-pad2_ D1N750 +q8 net-_q12-pad2_ net-_q12-pad2_ net-_q8-pad3_ Q2N2907A +q12 net-_q10-pad1_ net-_q12-pad2_ net-_q12-pad3_ Q2N2907A +r13 net-_q16-pad1_ net-_q12-pad3_ 100k +r8 net-_q16-pad1_ net-_q8-pad3_ 100 +q2 net-_q12-pad2_ net-_q2-pad2_ net-_q2-pad3_ BC547B +q10 net-_q10-pad1_ net-_q10-pad2_ net-_d1-pad1_ BC547B +q3 net-_q3-pad1_ net-_q3-pad2_ net-_d1-pad1_ BC547B +r6 net-_q2-pad3_ net-_q3-pad1_ 1.4k +q7 net-_c1-pad1_ net-_q3-pad2_ net-_q7-pad3_ BC547B +r7 net-_q3-pad2_ net-_d1-pad1_ 6.0k +r11 net-_q7-pad3_ net-_d1-pad1_ 1.0k +q4 net-_q2-pad3_ net-_q3-pad1_ net-_q3-pad2_ BC547B +r10 net-_q2-pad3_ net-_c1-pad1_ 28k +r9 net-_q6-pad2_ net-_q2-pad3_ 6.0k +q6 net-_q5-pad3_ net-_q6-pad2_ net-_q2-pad3_ BC547B +q5 net-_q12-pad2_ net-_q15-pad3_ net-_q5-pad3_ BC547B +q9 net-_q15-pad3_ net-_q9-pad2_ net-_q6-pad2_ BC547B +c1 net-_c1-pad1_ net-_c1-pad2_ 30p +q11 net-_c1-pad2_ net-_c1-pad1_ net-_q11-pad3_ BC547B +q14 net-_d1-pad1_ net-_c1-pad2_ net-_q10-pad1_ Q2N2907A +r14 net-_q10-pad1_ net-_c1-pad2_ 2.0k +r12 net-_q11-pad3_ net-_d1-pad1_ 5.0k +q13 net-_c1-pad2_ net-_q11-pad3_ net-_d1-pad1_ BC547B +q16 net-_q16-pad1_ net-_q10-pad1_ net-_q16-pad3_ BC547B +q17 net-_q16-pad1_ net-_q16-pad3_ net-_q17-pad3_ BC547B +d2 net-_d2-pad1_ net-_d2-pad2_ D1N750 +r15 net-_q16-pad1_ net-_d2-pad2_ 10k +q15 net-_q10-pad1_ net-_d2-pad1_ net-_q15-pad3_ BC547B +r16 net-_q16-pad3_ net-_q15-pad3_ 200 +r20 net-_q15-pad3_ net-_q17-pad3_ 0.3 +r19 net-_d2-pad1_ net-_q17-pad3_ 240 +r17 net-_q15-pad3_ net-_q9-pad2_ 0.25k +r18 net-_q9-pad2_ net-_d1-pad1_ 5.0k +* Control Statements + +.ends MCT7800 \ No newline at end of file diff --git a/library/SubcircuitLibrary/MCT7800/MCT7800_Previous_Values.xml b/library/SubcircuitLibrary/MCT7800/MCT7800_Previous_Values.xml new file mode 100644 index 000000000..e86a9aceb --- /dev/null +++ b/library/SubcircuitLibrary/MCT7800/MCT7800_Previous_Values.xml @@ -0,0 +1 @@ +truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperessecsecsecC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\BC547B.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\ZenerD1N750.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\BC547B.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\BC547B.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\BC547B.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\BC547B.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\BC547B.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\BC547B.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\BC547B.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\BC547B.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\BC547B.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\BC547B.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\BC547B.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\BC547B.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\ZenerD1N750.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\BC547B.lib \ No newline at end of file diff --git a/library/SubcircuitLibrary/MCT7800/PNP.lib b/library/SubcircuitLibrary/MCT7800/PNP.lib new file mode 100644 index 000000000..7edda0eab --- /dev/null +++ b/library/SubcircuitLibrary/MCT7800/PNP.lib @@ -0,0 +1,4 @@ +.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 ++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 ++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 ++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/library/SubcircuitLibrary/MCT7800/ZenerD1N750.lib b/library/SubcircuitLibrary/MCT7800/ZenerD1N750.lib new file mode 100644 index 000000000..890c37fe2 --- /dev/null +++ b/library/SubcircuitLibrary/MCT7800/ZenerD1N750.lib @@ -0,0 +1,3 @@ +.model D1N750 D( Is=880.5E-18 Rs=.25 Ikf=0 N=1 Xti=3 Eg=1.11 Cjo=175p M=.5516 ++ Vj=.75 Fc=.5 Isr=1.859n Nr=2 Bv=8.1 Ibv=20.245m Nbv=1.6989 Ibvl=1.9556m ++ Nbvl=14.976 Tbv1=-21.277u) diff --git a/library/SubcircuitLibrary/MCT7800/analysis b/library/SubcircuitLibrary/MCT7800/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/SubcircuitLibrary/MCT7800/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/library/SubcircuitLibrary/MMC4011/MMC4011-cache.lib b/library/SubcircuitLibrary/MMC4011/MMC4011-cache.lib new file mode 100644 index 000000000..348446c2e --- /dev/null +++ b/library/SubcircuitLibrary/MMC4011/MMC4011-cache.lib @@ -0,0 +1,100 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_MOS_N +# +DEF eSim_MOS_N M 0 0 Y N 1 F N +F0 "M" 0 -150 50 H V R CNN +F1 "eSim_MOS_N" 100 -50 50 H V R CNN +F2 "" 300 -300 29 H V C CNN +F3 "" 100 -200 60 H V C CNN +ALIAS mosfet_n +DRAW +C 150 -200 111 0 1 10 N +P 2 0 1 10 130 -290 130 -250 N +P 2 0 1 0 130 -270 200 -270 N +P 2 0 1 10 130 -220 130 -180 N +P 2 0 1 0 130 -200 200 -200 N +P 2 0 1 10 130 -150 130 -110 N +P 2 0 1 0 130 -130 200 -130 N +P 2 0 1 0 200 -300 200 -270 N +P 2 0 1 0 200 -130 200 -100 N +P 3 0 1 10 110 -275 110 -125 110 -125 N +P 3 0 1 0 200 -200 300 -200 300 -250 N +P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F +X D 1 200 0 100 D 50 50 1 1 P +X G 2 -100 -200 210 R 50 50 1 1 P +X S 3 200 -400 100 U 50 50 1 1 P +X B 4 300 -350 98 U 47 47 1 1 P +ENDDRAW +ENDDEF +# +# eSim_MOS_P +# +DEF eSim_MOS_P M 0 0 Y N 1 F N +F0 "M" -50 50 50 H V R CNN +F1 "eSim_MOS_P" 50 150 50 H V R CNN +F2 "" 250 100 29 H V C CNN +F3 "" 50 0 60 H V C CNN +ALIAS mosfet_p +DRAW +C 100 0 111 0 1 10 N +P 2 0 1 0 80 -70 150 -70 N +P 2 0 1 10 80 -50 80 -90 N +P 2 0 1 0 80 0 150 0 N +P 2 0 1 10 80 20 80 -20 N +P 2 0 1 0 80 70 150 70 N +P 2 0 1 10 80 90 80 50 N +P 2 0 1 0 150 -70 150 -100 N +P 2 0 1 0 150 100 150 70 N +P 3 0 1 10 60 75 60 -75 60 -75 N +P 3 0 1 0 150 0 250 0 250 -50 N +P 4 0 1 0 140 0 100 -15 100 15 140 0 F +X D 1 150 200 100 D 50 50 1 1 P +X G 2 -150 0 210 R 50 50 1 1 P +X S 3 150 -200 100 U 50 50 1 1 P +X B 4 250 -150 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/MMC4011/MMC4011.bak b/library/SubcircuitLibrary/MMC4011/MMC4011.bak new file mode 100644 index 000000000..427130294 --- /dev/null +++ b/library/SubcircuitLibrary/MMC4011/MMC4011.bak @@ -0,0 +1,57 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:MMC4011-cache +EELAYER 25 0 +EELAYER END +$Descr A1 33110 23386 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/MMC4011/MMC4011.cir b/library/SubcircuitLibrary/MMC4011/MMC4011.cir new file mode 100644 index 000000000..ad9556e1d --- /dev/null +++ b/library/SubcircuitLibrary/MMC4011/MMC4011.cir @@ -0,0 +1,51 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\MMC4011\MMC4011.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/20/25 01:25:37 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +M2 Net-_M1-Pad1_ /A /VDD /VDD eSim_MOS_P +M1 Net-_M1-Pad1_ /A /VSS /VSS eSim_MOS_N +M6 Net-_M11-Pad2_ /B /VDD /VDD eSim_MOS_P +M5 Net-_M11-Pad2_ /B /VSS /VSS eSim_MOS_N +M9 Net-_M11-Pad1_ Net-_M1-Pad1_ /VSS /VSS eSim_MOS_N +M12 Net-_M12-Pad1_ Net-_M1-Pad1_ /VDD /VDD eSim_MOS_P +M13 Net-_M11-Pad1_ Net-_M11-Pad2_ Net-_M12-Pad1_ /VDD eSim_MOS_P +M11 Net-_M11-Pad1_ Net-_M11-Pad2_ /VSS /VSS eSim_MOS_N +M18 /J Net-_M11-Pad1_ /VDD /VDD eSim_MOS_P +U1 /A /B /J /K /C /D /VSS /E /F /L /M /G /H /VDD PORT +M17 /J Net-_M11-Pad1_ /VSS /VSS eSim_MOS_N +M22 Net-_M21-Pad1_ /C /VDD /VDD eSim_MOS_P +M21 Net-_M21-Pad1_ /C /VSS /VSS eSim_MOS_N +M26 Net-_M25-Pad1_ /D /VDD /VDD eSim_MOS_P +M25 Net-_M25-Pad1_ /D /VSS /VSS eSim_MOS_N +M29 Net-_M29-Pad1_ Net-_M21-Pad1_ /VSS /VSS eSim_MOS_N +M32 Net-_M32-Pad1_ Net-_M21-Pad1_ /VDD /VDD eSim_MOS_P +M33 Net-_M29-Pad1_ Net-_M25-Pad1_ Net-_M32-Pad1_ /VDD eSim_MOS_P +M31 Net-_M29-Pad1_ Net-_M25-Pad1_ /VSS /VSS eSim_MOS_N +M38 /K Net-_M29-Pad1_ /VDD /VDD eSim_MOS_P +M37 /K Net-_M29-Pad1_ /VSS /VSS eSim_MOS_N +M4 Net-_M10-Pad2_ /E /VDD /VDD eSim_MOS_P +M3 Net-_M10-Pad2_ /E /VSS /VSS eSim_MOS_N +M8 Net-_M14-Pad2_ /F /VDD /VDD eSim_MOS_P +M7 Net-_M14-Pad2_ /F /VSS /VSS eSim_MOS_N +M10 Net-_M10-Pad1_ Net-_M10-Pad2_ /VSS /VSS eSim_MOS_N +M15 Net-_M15-Pad1_ Net-_M10-Pad2_ /VDD /VDD eSim_MOS_P +M16 Net-_M10-Pad1_ Net-_M14-Pad2_ Net-_M15-Pad1_ /VDD eSim_MOS_P +M14 Net-_M10-Pad1_ Net-_M14-Pad2_ /VSS /VSS eSim_MOS_N +M20 /L Net-_M10-Pad1_ /VDD /VDD eSim_MOS_P +M19 /L Net-_M10-Pad1_ /VSS /VSS eSim_MOS_N +M24 Net-_M23-Pad1_ /G /VDD /VDD eSim_MOS_P +M23 Net-_M23-Pad1_ /G /VSS /VSS eSim_MOS_N +M28 Net-_M27-Pad1_ /H /VDD /VDD eSim_MOS_P +M27 Net-_M27-Pad1_ /H /VSS /VSS eSim_MOS_N +M30 Net-_M30-Pad1_ Net-_M23-Pad1_ /VSS /VSS eSim_MOS_N +M35 Net-_M35-Pad1_ Net-_M23-Pad1_ /VDD /VDD eSim_MOS_P +M36 Net-_M30-Pad1_ Net-_M27-Pad1_ Net-_M35-Pad1_ /VDD eSim_MOS_P +M34 Net-_M30-Pad1_ Net-_M27-Pad1_ /VSS /VSS eSim_MOS_N +M40 /M Net-_M30-Pad1_ /VDD /VDD eSim_MOS_P +M39 /M Net-_M30-Pad1_ /VSS /VSS eSim_MOS_N + +.end diff --git a/library/SubcircuitLibrary/MMC4011/MMC4011.cir.out b/library/SubcircuitLibrary/MMC4011/MMC4011.cir.out new file mode 100644 index 000000000..f29417319 --- /dev/null +++ b/library/SubcircuitLibrary/MMC4011/MMC4011.cir.out @@ -0,0 +1,54 @@ +* c:\fossee\esim\library\subcircuitlibrary\mmc4011\mmc4011.cir + +.include PMOS-5um.lib +.include NMOS-5um.lib +m2 net-_m1-pad1_ /a /vdd /vdd mos_p W=40u L=5u M=1 +m1 net-_m1-pad1_ /a /vss /vss mos_n W=100u L=100u M=1 +m6 net-_m11-pad2_ /b /vdd /vdd mos_p W=100u L=100u M=1 +m5 net-_m11-pad2_ /b /vss /vss mos_n W=100u L=100u M=1 +m9 net-_m11-pad1_ net-_m1-pad1_ /vss /vss mos_n W=100u L=100u M=1 +m12 net-_m12-pad1_ net-_m1-pad1_ /vdd /vdd mos_p W=100u L=100u M=1 +m13 net-_m11-pad1_ net-_m11-pad2_ net-_m12-pad1_ /vdd mos_p W=100u L=100u M=1 +m11 net-_m11-pad1_ net-_m11-pad2_ /vss /vss mos_n W=100u L=100u M=1 +m18 /j net-_m11-pad1_ /vdd /vdd mos_p W=100u L=100u M=1 +* u1 /a /b /j /k /c /d /vss /e /f /l /m /g /h /vdd port +m17 /j net-_m11-pad1_ /vss /vss mos_n W=100u L=100u M=1 +m22 net-_m21-pad1_ /c /vdd /vdd mos_p W=100u L=100u M=1 +m21 net-_m21-pad1_ /c /vss /vss mos_n W=100u L=100u M=1 +m26 net-_m25-pad1_ /d /vdd /vdd mos_p W=100u L=100u M=1 +m25 net-_m25-pad1_ /d /vss /vss mos_n W=100u L=100u M=1 +m29 net-_m29-pad1_ net-_m21-pad1_ /vss /vss mos_n W=100u L=100u M=1 +m32 net-_m32-pad1_ net-_m21-pad1_ /vdd /vdd mos_p W=100u L=100u M=1 +m33 net-_m29-pad1_ net-_m25-pad1_ net-_m32-pad1_ /vdd mos_p W=100u L=100u M=1 +m31 net-_m29-pad1_ net-_m25-pad1_ /vss /vss mos_n W=100u L=100u M=1 +m38 /k net-_m29-pad1_ /vdd /vdd mos_p W=100u L=100u M=1 +m37 /k net-_m29-pad1_ /vss /vss mos_n W=100u L=100u M=1 +m4 net-_m10-pad2_ /e /vdd /vdd mos_p W=100u L=100u M=1 +m3 net-_m10-pad2_ /e /vss /vss mos_n W=100u L=100u M=1 +m8 net-_m14-pad2_ /f /vdd /vdd mos_p W=100u L=100u M=1 +m7 net-_m14-pad2_ /f /vss /vss mos_n W=100u L=100u M=1 +m10 net-_m10-pad1_ net-_m10-pad2_ /vss /vss mos_n W=100u L=100u M=1 +m15 net-_m15-pad1_ net-_m10-pad2_ /vdd /vdd mos_p W=100u L=100u M=1 +m16 net-_m10-pad1_ net-_m14-pad2_ net-_m15-pad1_ /vdd mos_p W=100u L=100u M=1 +m14 net-_m10-pad1_ net-_m14-pad2_ /vss /vss mos_n W=100u L=100u M=1 +m20 /l net-_m10-pad1_ /vdd /vdd mos_p W=100u L=100u M=1 +m19 /l net-_m10-pad1_ /vss /vss mos_n W=100u L=100u M=1 +m24 net-_m23-pad1_ /g /vdd /vdd mos_p W=100u L=100u M=1 +m23 net-_m23-pad1_ /g /vss /vss mos_n W=100u L=100u M=1 +m28 net-_m27-pad1_ /h /vdd /vdd mos_p W=100u L=100u M=1 +m27 net-_m27-pad1_ /h /vss /vss mos_n W=100u L=100u M=1 +m30 net-_m30-pad1_ net-_m23-pad1_ /vss /vss mos_n W=100u L=100u M=1 +m35 net-_m35-pad1_ net-_m23-pad1_ /vdd /vdd mos_p W=100u L=100u M=1 +m36 net-_m30-pad1_ net-_m27-pad1_ net-_m35-pad1_ /vdd mos_p W=100u L=100u M=1 +m34 net-_m30-pad1_ net-_m27-pad1_ /vss /vss mos_n W=100u L=100u M=1 +m40 /m net-_m30-pad1_ /vdd /vdd mos_p W=100u L=100u M=1 +m39 /m net-_m30-pad1_ /vss /vss mos_n W=100u L=100u M=1 +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/MMC4011/MMC4011.pro b/library/SubcircuitLibrary/MMC4011/MMC4011.pro new file mode 100644 index 000000000..8fc830805 --- /dev/null +++ b/library/SubcircuitLibrary/MMC4011/MMC4011.pro @@ -0,0 +1,83 @@ +update=07/02/25 13:40:37 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts +[schematic_editor] +version=1 +PageLayoutDescrFile= +PlotDirectoryName= +SubpartIdSeparator=0 +SubpartFirstId=65 +NetFmtName= +SpiceForceRefPrefix=0 +SpiceUseNetNumbers=0 +LabSize=60 diff --git a/library/SubcircuitLibrary/MMC4011/MMC4011.sch b/library/SubcircuitLibrary/MMC4011/MMC4011.sch new file mode 100644 index 000000000..c4134d371 --- /dev/null +++ b/library/SubcircuitLibrary/MMC4011/MMC4011.sch @@ -0,0 +1,1314 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:MMC4011-cache +LIBS:SINGLE-cache +EELAYER 25 0 +EELAYER END +$Descr A1 33110 23386 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_MOS_P M2 +U 1 1 68545DED +P 6100 5800 +F 0 "M2" H 6050 5850 50 0000 R CNN +F 1 "eSim_MOS_P" H 6150 5950 50 0000 R CNN +F 2 "" H 6350 5900 29 0000 C CNN +F 3 "" H 6150 5800 60 0000 C CNN + 1 6100 5800 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M1 +U 1 1 68545DEE +P 6050 6650 +F 0 "M1" H 6050 6500 50 0000 R CNN +F 1 "eSim_MOS_N" H 6150 6600 50 0000 R CNN +F 2 "" H 6350 6350 29 0000 C CNN +F 3 "" H 6150 6450 60 0000 C CNN + 1 6050 6650 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M6 +U 1 1 68545DEF +P 7800 6550 +F 0 "M6" H 7750 6600 50 0000 R CNN +F 1 "eSim_MOS_P" H 7850 6700 50 0000 R CNN +F 2 "" H 8050 6650 29 0000 C CNN +F 3 "" H 7850 6550 60 0000 C CNN + 1 7800 6550 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M5 +U 1 1 68545DF0 +P 7750 7200 +F 0 "M5" H 7750 7050 50 0000 R CNN +F 1 "eSim_MOS_N" H 7850 7150 50 0000 R CNN +F 2 "" H 8050 6900 29 0000 C CNN +F 3 "" H 7850 7000 60 0000 C CNN + 1 7750 7200 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_N M9 +U 1 1 68545DF1 +P 9200 7900 +F 0 "M9" H 9200 7750 50 0000 R CNN +F 1 "eSim_MOS_N" H 9300 7850 50 0000 R CNN +F 2 "" H 9500 7600 29 0000 C CNN +F 3 "" H 9300 7700 60 0000 C CNN + 1 9200 7900 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M12 +U 1 1 68545DF2 +P 10800 6000 +F 0 "M12" H 10750 6050 50 0000 R CNN +F 1 "eSim_MOS_P" H 10850 6150 50 0000 R CNN +F 2 "" H 11050 6100 29 0000 C CNN +F 3 "" H 10850 6000 60 0000 C CNN + 1 10800 6000 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_P M13 +U 1 1 68545DF3 +P 10800 6750 +F 0 "M13" H 10750 6800 50 0000 R CNN +F 1 "eSim_MOS_P" H 10850 6900 50 0000 R CNN +F 2 "" H 11050 6850 29 0000 C CNN +F 3 "" H 10850 6750 60 0000 C CNN + 1 10800 6750 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M11 +U 1 1 68545DF4 +P 10500 7900 +F 0 "M11" H 10500 7750 50 0000 R CNN +F 1 "eSim_MOS_N" H 10600 7850 50 0000 R CNN +F 2 "" H 10800 7600 29 0000 C CNN +F 3 "" H 10600 7700 60 0000 C CNN + 1 10500 7900 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M18 +U 1 1 68545DF5 +P 12200 6700 +F 0 "M18" H 12150 6750 50 0000 R CNN +F 1 "eSim_MOS_P" H 12250 6850 50 0000 R CNN +F 2 "" H 12450 6800 29 0000 C CNN +F 3 "" H 12250 6700 60 0000 C CNN + 1 12200 6700 + 1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 1 1 68545DF6 +P 4200 6200 +F 0 "U1" H 4250 6300 30 0000 C CNN +F 1 "PORT" H 4200 6200 30 0000 C CNN +F 2 "" H 4200 6200 60 0000 C CNN +F 3 "" H 4200 6200 60 0000 C CNN + 1 4200 6200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 68545DF7 +P 4350 7800 +F 0 "U1" H 4400 7900 30 0000 C CNN +F 1 "PORT" H 4350 7800 30 0000 C CNN +F 2 "" H 4350 7800 60 0000 C CNN +F 3 "" H 4350 7800 60 0000 C CNN + 2 4350 7800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 68545DF8 +P 13950 7100 +F 0 "U1" H 14000 7200 30 0000 C CNN +F 1 "PORT" H 13950 7100 30 0000 C CNN +F 2 "" H 13950 7100 60 0000 C CNN +F 3 "" H 13950 7100 60 0000 C CNN + 3 13950 7100 + -1 0 0 1 +$EndComp +Text Label 4600 6250 0 60 ~ 0 +A +Text Label 4800 7800 0 60 ~ 0 +B +Text Label 13350 7100 0 60 ~ 0 +J +$Comp +L eSim_MOS_N M17 +U 1 1 68545DFB +P 12150 7300 +F 0 "M17" H 12150 7150 50 0000 R CNN +F 1 "eSim_MOS_N" H 12250 7250 50 0000 R CNN +F 2 "" H 12450 7000 29 0000 C CNN +F 3 "" H 12250 7100 60 0000 C CNN + 1 12150 7300 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M22 +U 1 1 6854613A +P 19050 5600 +F 0 "M22" H 19000 5650 50 0000 R CNN +F 1 "eSim_MOS_P" H 19100 5750 50 0000 R CNN +F 2 "" H 19300 5700 29 0000 C CNN +F 3 "" H 19100 5600 60 0000 C CNN + 1 19050 5600 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M21 +U 1 1 68546140 +P 19000 6450 +F 0 "M21" H 19000 6300 50 0000 R CNN +F 1 "eSim_MOS_N" H 19100 6400 50 0000 R CNN +F 2 "" H 19300 6150 29 0000 C CNN +F 3 "" H 19100 6250 60 0000 C CNN + 1 19000 6450 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M26 +U 1 1 6854614F +P 20750 6350 +F 0 "M26" H 20700 6400 50 0000 R CNN +F 1 "eSim_MOS_P" H 20800 6500 50 0000 R CNN +F 2 "" H 21000 6450 29 0000 C CNN +F 3 "" H 20800 6350 60 0000 C CNN + 1 20750 6350 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M25 +U 1 1 68546155 +P 20700 7000 +F 0 "M25" H 20700 6850 50 0000 R CNN +F 1 "eSim_MOS_N" H 20800 6950 50 0000 R CNN +F 2 "" H 21000 6700 29 0000 C CNN +F 3 "" H 20800 6800 60 0000 C CNN + 1 20700 7000 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_N M29 +U 1 1 6854616C +P 22150 7700 +F 0 "M29" H 22150 7550 50 0000 R CNN +F 1 "eSim_MOS_N" H 22250 7650 50 0000 R CNN +F 2 "" H 22450 7400 29 0000 C CNN +F 3 "" H 22250 7500 60 0000 C CNN + 1 22150 7700 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M32 +U 1 1 6854617C +P 23750 5800 +F 0 "M32" H 23700 5850 50 0000 R CNN +F 1 "eSim_MOS_P" H 23800 5950 50 0000 R CNN +F 2 "" H 24000 5900 29 0000 C CNN +F 3 "" H 23800 5800 60 0000 C CNN + 1 23750 5800 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_P M33 +U 1 1 68546182 +P 23750 6550 +F 0 "M33" H 23700 6600 50 0000 R CNN +F 1 "eSim_MOS_P" H 23800 6700 50 0000 R CNN +F 2 "" H 24000 6650 29 0000 C CNN +F 3 "" H 23800 6550 60 0000 C CNN + 1 23750 6550 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M31 +U 1 1 68546196 +P 23450 7700 +F 0 "M31" H 23450 7550 50 0000 R CNN +F 1 "eSim_MOS_N" H 23550 7650 50 0000 R CNN +F 2 "" H 23750 7400 29 0000 C CNN +F 3 "" H 23550 7500 60 0000 C CNN + 1 23450 7700 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M38 +U 1 1 685461A7 +P 25150 6500 +F 0 "M38" H 25100 6550 50 0000 R CNN +F 1 "eSim_MOS_P" H 25200 6650 50 0000 R CNN +F 2 "" H 25400 6600 29 0000 C CNN +F 3 "" H 25200 6500 60 0000 C CNN + 1 25150 6500 + 1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 5 1 685461BE +P 17150 6000 +F 0 "U1" H 17200 6100 30 0000 C CNN +F 1 "PORT" H 17150 6000 30 0000 C CNN +F 2 "" H 17150 6000 60 0000 C CNN +F 3 "" H 17150 6000 60 0000 C CNN + 5 17150 6000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 685461C4 +P 17300 7600 +F 0 "U1" H 17350 7700 30 0000 C CNN +F 1 "PORT" H 17300 7600 30 0000 C CNN +F 2 "" H 17300 7600 60 0000 C CNN +F 3 "" H 17300 7600 60 0000 C CNN + 6 17300 7600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 685461CA +P 26900 6900 +F 0 "U1" H 26950 7000 30 0000 C CNN +F 1 "PORT" H 26900 6900 30 0000 C CNN +F 2 "" H 26900 6900 60 0000 C CNN +F 3 "" H 26900 6900 60 0000 C CNN + 4 26900 6900 + -1 0 0 1 +$EndComp +Text Label 17550 6050 0 60 ~ 0 +C +Text Label 17750 7600 0 60 ~ 0 +D +Text Label 26300 6900 0 60 ~ 0 +K +Text Label 30850 7550 0 60 ~ 0 +VDD +$Comp +L eSim_MOS_N M37 +U 1 1 685461EC +P 25100 7100 +F 0 "M37" H 25100 6950 50 0000 R CNN +F 1 "eSim_MOS_N" H 25200 7050 50 0000 R CNN +F 2 "" H 25400 6800 29 0000 C CNN +F 3 "" H 25200 6900 60 0000 C CNN + 1 25100 7100 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M4 +U 1 1 685463F0 +P 6400 13050 +F 0 "M4" H 6350 13100 50 0000 R CNN +F 1 "eSim_MOS_P" H 6450 13200 50 0000 R CNN +F 2 "" H 6650 13150 29 0000 C CNN +F 3 "" H 6450 13050 60 0000 C CNN + 1 6400 13050 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M3 +U 1 1 685463F6 +P 6350 13900 +F 0 "M3" H 6350 13750 50 0000 R CNN +F 1 "eSim_MOS_N" H 6450 13850 50 0000 R CNN +F 2 "" H 6650 13600 29 0000 C CNN +F 3 "" H 6450 13700 60 0000 C CNN + 1 6350 13900 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M8 +U 1 1 68546405 +P 8100 13800 +F 0 "M8" H 8050 13850 50 0000 R CNN +F 1 "eSim_MOS_P" H 8150 13950 50 0000 R CNN +F 2 "" H 8350 13900 29 0000 C CNN +F 3 "" H 8150 13800 60 0000 C CNN + 1 8100 13800 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M7 +U 1 1 6854640B +P 8050 14450 +F 0 "M7" H 8050 14300 50 0000 R CNN +F 1 "eSim_MOS_N" H 8150 14400 50 0000 R CNN +F 2 "" H 8350 14150 29 0000 C CNN +F 3 "" H 8150 14250 60 0000 C CNN + 1 8050 14450 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_N M10 +U 1 1 68546422 +P 9500 15150 +F 0 "M10" H 9500 15000 50 0000 R CNN +F 1 "eSim_MOS_N" H 9600 15100 50 0000 R CNN +F 2 "" H 9800 14850 29 0000 C CNN +F 3 "" H 9600 14950 60 0000 C CNN + 1 9500 15150 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M15 +U 1 1 68546432 +P 11100 13250 +F 0 "M15" H 11050 13300 50 0000 R CNN +F 1 "eSim_MOS_P" H 11150 13400 50 0000 R CNN +F 2 "" H 11350 13350 29 0000 C CNN +F 3 "" H 11150 13250 60 0000 C CNN + 1 11100 13250 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_P M16 +U 1 1 68546438 +P 11100 14000 +F 0 "M16" H 11050 14050 50 0000 R CNN +F 1 "eSim_MOS_P" H 11150 14150 50 0000 R CNN +F 2 "" H 11350 14100 29 0000 C CNN +F 3 "" H 11150 14000 60 0000 C CNN + 1 11100 14000 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M14 +U 1 1 6854644C +P 10800 15150 +F 0 "M14" H 10800 15000 50 0000 R CNN +F 1 "eSim_MOS_N" H 10900 15100 50 0000 R CNN +F 2 "" H 11100 14850 29 0000 C CNN +F 3 "" H 10900 14950 60 0000 C CNN + 1 10800 15150 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M20 +U 1 1 6854645D +P 12500 13950 +F 0 "M20" H 12450 14000 50 0000 R CNN +F 1 "eSim_MOS_P" H 12550 14100 50 0000 R CNN +F 2 "" H 12750 14050 29 0000 C CNN +F 3 "" H 12550 13950 60 0000 C CNN + 1 12500 13950 + 1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 8 1 68546474 +P 4500 13450 +F 0 "U1" H 4550 13550 30 0000 C CNN +F 1 "PORT" H 4500 13450 30 0000 C CNN +F 2 "" H 4500 13450 60 0000 C CNN +F 3 "" H 4500 13450 60 0000 C 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0000 C CNN +F 2 "" H 31500 7550 60 0000 C CNN +F 3 "" H 31500 7550 60 0000 C CNN + 14 31500 7550 + -1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/MMC4011/MMC4011.sub b/library/SubcircuitLibrary/MMC4011/MMC4011.sub new file mode 100644 index 000000000..0b4f34efa --- /dev/null +++ b/library/SubcircuitLibrary/MMC4011/MMC4011.sub @@ -0,0 +1,48 @@ +* Subcircuit MMC4011 +.subckt MMC4011 /a /b /j /k /c /d /vss /e /f /l /m /g /h /vdd +* c:\fossee\esim\library\subcircuitlibrary\mmc4011\mmc4011.cir +.include PMOS-5um.lib +.include NMOS-5um.lib +m2 net-_m1-pad1_ /a /vdd /vdd mos_p W=40u L=5u M=8 +m1 net-_m1-pad1_ /a /vss /vss mos_n W=20u L=5u M=4 +m6 net-_m11-pad2_ /b /vdd /vdd mos_p W=40u L=5u M=8 +m5 net-_m11-pad2_ /b /vss /vss mos_n W=20u L=5u M=4 +m9 net-_m11-pad1_ net-_m1-pad1_ /vss /vss mos_n W=20u L=5u M=4 +m12 net-_m12-pad1_ net-_m1-pad1_ /vdd /vdd mos_p W=40u L=5u M=8 +m13 net-_m11-pad1_ net-_m11-pad2_ net-_m12-pad1_ /vdd mos_p W=40u L=5u M=8 +m11 net-_m11-pad1_ net-_m11-pad2_ /vss /vss mos_n W=20u L=5u M=4 +m18 /j net-_m11-pad1_ /vdd /vdd mos_p W=40u L=5u M=8 +m17 /j net-_m11-pad1_ /vss /vss mos_n W=20u L=5u M=4 +m22 net-_m21-pad1_ /c /vdd /vdd mos_p W=40u L=5u M=8 +m21 net-_m21-pad1_ /c /vss /vss mos_n W=20u L=5u M=4 +m26 net-_m25-pad1_ /d /vdd /vdd mos_p W=40u L=5u M=8 +m25 net-_m25-pad1_ /d /vss /vss mos_n W=20u L=5u M=4 +m29 net-_m29-pad1_ net-_m21-pad1_ /vss /vss mos_n W=20u L=5u M=4 +m32 net-_m32-pad1_ net-_m21-pad1_ /vdd /vdd mos_p W=40u L=5u M=8 +m33 net-_m29-pad1_ net-_m25-pad1_ net-_m32-pad1_ /vdd mos_p W=40u L=5u M=8 +m31 net-_m29-pad1_ net-_m25-pad1_ /vss /vss mos_n W=20u L=5u M=4 +m38 /k net-_m29-pad1_ /vdd /vdd mos_p W=40u L=5u M=8 +m37 /k net-_m29-pad1_ /vss /vss mos_n W=20u L=5u M=4 +m4 net-_m10-pad2_ /e /vdd /vdd mos_p W=40u L=5u M=8 +m3 net-_m10-pad2_ /e /vss /vss mos_n W=20u L=5u M=4 +m8 net-_m14-pad2_ /f /vdd /vdd mos_p W=40u L=5u M=8 +m7 net-_m14-pad2_ /f /vss /vss mos_n W=20u L=5u M=4 +m10 net-_m10-pad1_ net-_m10-pad2_ /vss /vss mos_n W=20u L=5u M=4 +m15 net-_m15-pad1_ net-_m10-pad2_ /vdd /vdd mos_p W=40u L=5u M=8 +m16 net-_m10-pad1_ net-_m14-pad2_ net-_m15-pad1_ /vdd mos_p W=40u L=5u M=8 +m14 net-_m10-pad1_ net-_m14-pad2_ /vss /vss mos_n W=20u L=5u M=4 +m20 /l net-_m10-pad1_ /vdd /vdd mos_p W=40u L=5u M=8 +m19 /l net-_m10-pad1_ /vss /vss mos_n W=20u L=5u M=4 +m24 net-_m23-pad1_ /g /vdd /vdd mos_p W=40u L=5u M=8 +m23 net-_m23-pad1_ /g /vss /vss mos_n W=20u L=5u M=4 +m28 net-_m27-pad1_ /h /vdd /vdd mos_p W=40u L=5u M=8 +m27 net-_m27-pad1_ /h /vss /vss mos_n W=20u L=5u M=4 +m30 net-_m30-pad1_ net-_m23-pad1_ /vss /vss mos_n W=20u L=5u M=4 +m35 net-_m35-pad1_ net-_m23-pad1_ /vdd /vdd mos_p W=40u L=5u M=8 +m36 net-_m30-pad1_ net-_m27-pad1_ net-_m35-pad1_ /vdd mos_p W=40u L=5u M=8 +m34 net-_m30-pad1_ net-_m27-pad1_ /vss /vss mos_n W=20u L=5u M=4 +m40 /m net-_m30-pad1_ /vdd /vdd mos_p W=40u L=5u M=8 +m39 /m net-_m30-pad1_ /vss /vss mos_n W=20u L=5u M=4 +* Control Statements + +.ends MMC4011 \ No newline at end of file diff --git a/library/SubcircuitLibrary/MMC4011/MMC4011_Previous_Values.xml b/library/SubcircuitLibrary/MMC4011/MMC4011_Previous_Values.xml new file mode 100644 index 000000000..c736c70cf --- /dev/null +++ b/library/SubcircuitLibrary/MMC4011/MMC4011_Previous_Values.xml @@ -0,0 +1 @@ +truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperessecsecsecC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.lib40u5u8C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.lib20u5u4C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.lib40u5u8C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.lib20u5u4C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.lib20u5u4C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.lib40u5u8C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.lib40u5u8C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.lib20u5u4C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.lib40u5u8C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.lib20u5u4C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.lib40u5u8C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.lib20u5u4C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.lib40u5u8C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.lib20u5u4C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.lib20u5u4C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.lib40u5u8C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.lib40u5u8C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.lib20u5u4C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.lib40u5u8C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.lib20u5u4C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.lib40u5u8C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.lib20u5u4C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.lib20u5u4C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.lib20u5u4C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.lib20u5u4C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.lib40u5u8C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.lib40u5u8C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.lib20u5u4C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.lib40u5u8C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.lib20u5u4C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.lib40u5u8C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.lib20u5u4C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.lib40u5u8C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.lib20u5u4C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.lib20u5u4C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.lib40u5u8C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.lib40u5u8C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.lib20u5u4C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.lib40u5u8C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.lib20u5u4 \ No newline at end of file diff --git a/library/SubcircuitLibrary/MMC4011/NMOS-5um.lib b/library/SubcircuitLibrary/MMC4011/NMOS-5um.lib new file mode 100644 index 000000000..a237e1fe3 --- /dev/null +++ b/library/SubcircuitLibrary/MMC4011/NMOS-5um.lib @@ -0,0 +1,5 @@ +* 5um technology + +.model mos_n NMOS( Cgso=0.4n Tox=85n Vto=1 phi=0.7 ++ Level=1 ++ Mj=.5 UO=750 Cgdo=0.4n Gamma=1.4 LAMBDA=0.01 LD=0.7u JS=1u CJ=0.4m CJSW=0.8n MJSW=0.5 PB=0.7 CGBO=0.2n ) diff --git a/library/SubcircuitLibrary/MMC4011/PMOS-5um.lib b/library/SubcircuitLibrary/MMC4011/PMOS-5um.lib new file mode 100644 index 000000000..9c3ed9760 --- /dev/null +++ b/library/SubcircuitLibrary/MMC4011/PMOS-5um.lib @@ -0,0 +1,5 @@ +*5um technology + +.model mos_p PMOS( Cgso=0.4n Tox=85n Vto=-1 phi=0.65 ++ Level=1 ++ Mj=.5 UO=250 Cgdo=0.4n Gamma=0.65 LAMBDA=0.03 LD=0.6u JS=1u CJ=0.18m CJSW=0.6n MJSW=0.5 PB=0.7 CGBO=0.2n ) diff --git a/library/SubcircuitLibrary/MMC4011/analysis b/library/SubcircuitLibrary/MMC4011/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/SubcircuitLibrary/MMC4011/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74S163/3_and-cache.lib b/library/SubcircuitLibrary/SN74S163/3_and-cache.lib new file mode 100644 index 000000000..0a3ccf7f9 --- /dev/null +++ b/library/SubcircuitLibrary/SN74S163/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74S163/3_and.cir b/library/SubcircuitLibrary/SN74S163/3_and.cir new file mode 100644 index 000000000..15f8954df --- /dev/null +++ b/library/SubcircuitLibrary/SN74S163/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/library/SubcircuitLibrary/SN74S163/3_and.cir.out b/library/SubcircuitLibrary/SN74S163/3_and.cir.out new file mode 100644 index 000000000..e3c966454 --- /dev/null +++ b/library/SubcircuitLibrary/SN74S163/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN74S163/3_and.pro b/library/SubcircuitLibrary/SN74S163/3_and.pro new file mode 100644 index 000000000..a4cdec482 --- /dev/null +++ b/library/SubcircuitLibrary/SN74S163/3_and.pro @@ -0,0 +1,43 @@ +update=05/31/19 15:26:09 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_User +LibName9=eSim_Sources +LibName10=eSim_Subckt diff --git a/library/SubcircuitLibrary/SN74S163/3_and.sch b/library/SubcircuitLibrary/SN74S163/3_and.sch new file mode 100644 index 000000000..c853bf49d --- /dev/null +++ b/library/SubcircuitLibrary/SN74S163/3_and.sch @@ -0,0 +1,130 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:3_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +Text Notes 3500 2600 0 60 ~ 12 +in1 +Text Notes 3450 2800 0 60 ~ 12 +in2\n +Text Notes 3500 3100 0 60 ~ 12 +in3 +Text Notes 6100 2850 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN74S163/3_and.sub b/library/SubcircuitLibrary/SN74S163/3_and.sub new file mode 100644 index 000000000..b949ae4fb --- /dev/null +++ b/library/SubcircuitLibrary/SN74S163/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74S163/3_and_Previous_Values.xml b/library/SubcircuitLibrary/SN74S163/3_and_Previous_Values.xml new file mode 100644 index 000000000..abc5faaae --- /dev/null +++ b/library/SubcircuitLibrary/SN74S163/3_and_Previous_Values.xml @@ -0,0 +1 @@ +d_andd_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74S163/4_OR-cache.lib b/library/SubcircuitLibrary/SN74S163/4_OR-cache.lib new file mode 100644 index 000000000..a3c1c9728 --- /dev/null +++ b/library/SubcircuitLibrary/SN74S163/4_OR-cache.lib @@ -0,0 +1,63 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74S163/4_OR.cir b/library/SubcircuitLibrary/SN74S163/4_OR.cir new file mode 100644 index 000000000..7adbf177d --- /dev/null +++ b/library/SubcircuitLibrary/SN74S163/4_OR.cir @@ -0,0 +1,14 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\4_OR\4_OR.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/28/19 22:47:12 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_or +U3 Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U3-Pad3_ d_or +U4 Net-_U2-Pad3_ Net-_U3-Pad3_ Net-_U1-Pad5_ d_or +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT + +.end diff --git a/library/SubcircuitLibrary/SN74S163/4_OR.cir.out b/library/SubcircuitLibrary/SN74S163/4_OR.cir.out new file mode 100644 index 000000000..4388b9757 --- /dev/null +++ b/library/SubcircuitLibrary/SN74S163/4_OR.cir.out @@ -0,0 +1,24 @@ +* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or +* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or +* u4 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4 +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN74S163/4_OR.pro b/library/SubcircuitLibrary/SN74S163/4_OR.pro new file mode 100644 index 000000000..a19bf4252 --- /dev/null +++ b/library/SubcircuitLibrary/SN74S163/4_OR.pro @@ -0,0 +1,44 @@ +update=06/01/19 12:36:09 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=power +LibName2=eSim_Analog +LibName3=eSim_Devices +LibName4=eSim_Digital +LibName5=eSim_Hybrid +LibName6=eSim_Miscellaneous +LibName7=eSim_Plot +LibName8=eSim_Power +LibName9=eSim_User +LibName10=eSim_Sources +LibName11=eSim_Subckt diff --git a/library/SubcircuitLibrary/SN74S163/4_OR.sch b/library/SubcircuitLibrary/SN74S163/4_OR.sch new file mode 100644 index 000000000..2f28896cb --- /dev/null +++ b/library/SubcircuitLibrary/SN74S163/4_OR.sch @@ -0,0 +1,150 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_or U2 +U 1 1 5C9D00E1 +P 4300 2950 +F 0 "U2" H 4300 2950 60 0000 C CNN +F 1 "d_or" H 4300 3050 60 0000 C CNN +F 2 "" H 4300 2950 60 0000 C CNN +F 3 "" H 4300 2950 60 0000 C CNN + 1 4300 2950 + 1 0 0 -1 +$EndComp +$Comp +L d_or U3 +U 1 1 5C9D011F +P 4300 3350 +F 0 "U3" H 4300 3350 60 0000 C CNN +F 1 "d_or" H 4300 3450 60 0000 C CNN +F 2 "" H 4300 3350 60 0000 C CNN +F 3 "" H 4300 3350 60 0000 C CNN + 1 4300 3350 + 1 0 0 -1 +$EndComp +$Comp +L d_or U4 +U 1 1 5C9D0141 +P 5250 3150 +F 0 "U4" H 5250 3150 60 0000 C CNN +F 1 "d_or" H 5250 3250 60 0000 C CNN +F 2 "" H 5250 3150 60 0000 C CNN +F 3 "" H 5250 3150 60 0000 C CNN + 1 5250 3150 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4800 3050 4800 2900 +Wire Wire Line + 4800 2900 4750 2900 +Wire Wire Line + 4800 3150 4800 3300 +Wire Wire Line + 4800 3300 4750 3300 +Wire Wire Line + 3350 2850 3850 2850 +Wire Wire Line + 3850 2950 3600 2950 +Wire Wire Line + 3850 3250 3350 3250 +Wire Wire Line + 3600 2950 3600 3000 +Wire Wire Line + 3600 3000 3350 3000 +Wire Wire Line + 3850 3350 3850 3400 +Wire Wire Line + 3850 3400 3350 3400 +Wire Wire Line + 5700 3100 6200 3100 +$Comp +L PORT U1 +U 1 1 5C9D01F4 +P 3100 2850 +F 0 "U1" H 3150 2950 30 0000 C CNN +F 1 "PORT" H 3100 2850 30 0000 C CNN +F 2 "" H 3100 2850 60 0000 C CNN +F 3 "" H 3100 2850 60 0000 C CNN + 1 3100 2850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9D022F +P 3100 3000 +F 0 "U1" H 3150 3100 30 0000 C CNN +F 1 "PORT" H 3100 3000 30 0000 C CNN +F 2 "" H 3100 3000 60 0000 C CNN +F 3 "" H 3100 3000 60 0000 C CNN + 2 3100 3000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9D0271 +P 3100 3250 +F 0 "U1" H 3150 3350 30 0000 C CNN +F 1 "PORT" H 3100 3250 30 0000 C CNN +F 2 "" H 3100 3250 60 0000 C CNN +F 3 "" H 3100 3250 60 0000 C CNN + 3 3100 3250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9D0299 +P 3100 3400 +F 0 "U1" H 3150 3500 30 0000 C CNN +F 1 "PORT" H 3100 3400 30 0000 C CNN +F 2 "" H 3100 3400 60 0000 C CNN +F 3 "" H 3100 3400 60 0000 C CNN + 4 3100 3400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9D02C2 +P 6450 3100 +F 0 "U1" H 6500 3200 30 0000 C CNN +F 1 "PORT" H 6450 3100 30 0000 C CNN +F 2 "" H 6450 3100 60 0000 C CNN +F 3 "" H 6450 3100 60 0000 C CNN + 5 6450 3100 + -1 0 0 1 +$EndComp +Text Notes 3450 2850 0 60 ~ 12 +in1 +Text Notes 3450 3000 0 60 ~ 12 +in2 +Text Notes 3450 3250 0 60 ~ 12 +in3 +Text Notes 3450 3400 0 60 ~ 12 +in4 +Text Notes 5800 3100 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN74S163/4_OR.sub b/library/SubcircuitLibrary/SN74S163/4_OR.sub new file mode 100644 index 000000000..53fc8b332 --- /dev/null +++ b/library/SubcircuitLibrary/SN74S163/4_OR.sub @@ -0,0 +1,18 @@ +* Subcircuit 4_OR +.subckt 4_OR net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ +* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or +* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or +* u4 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4 +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 4_OR \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74S163/4_OR_Previous_Values.xml b/library/SubcircuitLibrary/SN74S163/4_OR_Previous_Values.xml new file mode 100644 index 000000000..0683d9eb6 --- /dev/null +++ b/library/SubcircuitLibrary/SN74S163/4_OR_Previous_Values.xml @@ -0,0 +1 @@ +d_ord_ord_ortruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74S163/SN74S163-cache.lib b/library/SubcircuitLibrary/SN74S163/SN74S163-cache.lib new file mode 100644 index 000000000..49ab4eb99 --- /dev/null +++ b/library/SubcircuitLibrary/SN74S163/SN74S163-cache.lib @@ -0,0 +1,186 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 4_OR +# +DEF 4_OR X 0 40 Y Y 1 F N +F0 "X" 150 -100 60 H V C CNN +F1 "4_OR" 150 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -800 0 650 226 -226 0 1 0 N -200 250 -200 -250 +A -73 134 444 -599 -176 0 1 0 N 150 -250 350 0 +A -30 -99 393 627 146 0 1 0 N 150 250 350 0 +P 2 0 1 0 -200 -250 150 -250 N +P 2 0 1 0 -200 250 150 250 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X in4 4 -350 -150 200 R 50 50 1 1 I +X out 5 550 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_buffer +# +DEF d_buffer U 0 40 Y Y 1 F N +F0 "U" 0 -50 60 H V C CNN +F1 "d_buffer" 0 50 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 4 0 1 0 -300 200 -300 -200 450 0 -300 200 N +X IN 1 -500 0 200 R 50 50 1 1 I +X OUT 2 650 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_dff +# +DEF d_dff U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_dff" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S 350 450 -350 -400 0 1 0 N +X Din 1 -550 350 200 R 50 50 1 1 I +X Clk 2 -550 -300 200 R 50 50 1 1 I C +X Set 3 0 650 200 D 50 50 1 1 I +X Reset 4 0 -600 200 U 50 50 1 1 I +X Dout 5 550 350 200 L 50 50 1 1 O +X Ndout 6 550 -300 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nor +# +DEF d_nor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nor" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_xnor +# +DEF d_xnor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_xnor" 50 100 47 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -350 50 180 -337 337 0 1 0 N -200 -50 -200 150 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 150 -50 -200 -50 N +P 2 0 1 0 150 150 -200 150 N +X IN1 1 -450 100 215 R 50 43 1 1 I +X IN2 2 -450 0 215 R 50 43 1 1 I +X OUT 3 450 50 200 L 50 43 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74S163/SN74S163.bak b/library/SubcircuitLibrary/SN74S163/SN74S163.bak new file mode 100644 index 000000000..26bc695e7 --- /dev/null +++ b/library/SubcircuitLibrary/SN74S163/SN74S163.bak @@ -0,0 +1,1054 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:SN74S163-cache +EELAYER 25 0 +EELAYER END +$Descr A1 33110 23386 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_dff U40 +U 1 1 686BBBA3 +P 22500 9800 +F 0 "U40" H 22500 9800 60 0000 C CNN +F 1 "d_dff" H 22500 9950 60 0000 C CNN +F 2 "" H 22500 9800 60 0000 C CNN +F 3 "" H 22500 9800 60 0000 C CNN + 1 22500 9800 + 1 0 0 -1 +$EndComp +$Comp +L d_dff U43 +U 1 1 686BBBDB +P 22750 12300 +F 0 "U43" H 22750 12300 60 0000 C CNN +F 1 "d_dff" H 22750 12450 60 0000 C CNN +F 2 "" H 22750 12300 60 0000 C CNN +F 3 "" H 22750 12300 60 0000 C CNN + 1 22750 12300 + 1 0 0 -1 +$EndComp +$Comp +L d_dff U41 +U 1 1 686BBDFE +P 22500 14950 +F 0 "U41" H 22500 14950 60 0000 C CNN +F 1 "d_dff" H 22500 15100 60 0000 C CNN +F 2 "" H 22500 14950 60 0000 C CNN +F 3 "" H 22500 14950 60 0000 C CNN + 1 22500 14950 + 1 0 0 -1 +$EndComp +$Comp +L d_dff U42 +U 1 1 686BBE5B +P 22700 17400 +F 0 "U42" H 22700 17400 60 0000 C CNN +F 1 "d_dff" H 22700 17550 60 0000 C CNN +F 2 "" H 22700 17400 60 0000 C CNN +F 3 "" H 22700 17400 60 0000 C CNN + 1 22700 17400 + 1 0 0 -1 +$EndComp +$Comp +L d_buffer U11 +U 1 1 686BBEDA +P 8450 3500 +F 0 "U11" H 8450 3450 60 0000 C CNN +F 1 "d_buffer" H 8450 3550 60 0000 C CNN +F 2 "" H 8450 3500 60 0000 C CNN +F 3 "" H 8450 3500 60 0000 C CNN + 1 8450 3500 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U15 +U 1 1 686BBF3F +P 11000 3500 +F 0 "U15" H 11000 3400 60 0000 C CNN +F 1 "d_inverter" H 11000 3650 60 0000 C CNN +F 2 "" H 11050 3450 60 0000 C CNN +F 3 "" H 11050 3450 60 0000 C CNN + 1 11000 3500 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U36 +U 1 1 686BC0CC +P 21450 10100 +F 0 "U36" H 21450 10000 60 0000 C CNN +F 1 "d_inverter" H 21450 10250 60 0000 C CNN +F 2 "" H 21500 10050 60 0000 C CNN +F 3 "" H 21500 10050 60 0000 C CNN + 1 21450 10100 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U39 +U 1 1 686BC107 +P 21800 12600 +F 0 "U39" H 21800 12500 60 0000 C CNN +F 1 "d_inverter" H 21800 12750 60 0000 C CNN +F 2 "" H 21850 12550 60 0000 C CNN +F 3 "" H 21850 12550 60 0000 C CNN + 1 21800 12600 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U37 +U 1 1 686BC174 +P 21550 15250 +F 0 "U37" H 21550 15150 60 0000 C CNN +F 1 "d_inverter" H 21550 15400 60 0000 C CNN +F 2 "" H 21600 15200 60 0000 C CNN +F 3 "" H 21600 15200 60 0000 C CNN + 1 21550 15250 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U38 +U 1 1 686BC277 +P 21750 17700 +F 0 "U38" H 21750 17600 60 0000 C CNN +F 1 "d_inverter" H 21750 17850 60 0000 C CNN +F 2 "" H 21800 17650 60 0000 C CNN +F 3 "" H 21800 17650 60 0000 C CNN + 1 21750 17700 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U16 +U 1 1 686BC368 +P 12900 7000 +F 0 "U16" H 12900 7000 60 0000 C CNN +F 1 "d_nor" H 12950 7100 60 0000 C CNN +F 2 "" H 12900 7000 60 0000 C CNN +F 3 "" H 12900 7000 60 0000 C CNN + 1 12900 7000 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U17 +U 1 1 686BC49C +P 12950 8550 +F 0 "U17" H 12950 8550 60 0000 C CNN +F 1 "d_nor" H 13000 8650 60 0000 C CNN +F 2 "" H 12950 8550 60 0000 C CNN +F 3 "" H 12950 8550 60 0000 C CNN + 1 12950 8550 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U6 +U 1 1 686BC5A5 +P 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0000 C CNN +F 3 "" H 26300 14700 60 0000 C CNN + 12 26300 14700 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 11 1 686CA19D +P 26900 17000 +F 0 "U1" H 26950 17100 30 0000 C CNN +F 1 "PORT" H 26900 17000 30 0000 C CNN +F 2 "" H 26900 17000 60 0000 C CNN +F 3 "" H 26900 17000 60 0000 C CNN + 11 26900 17000 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 15 1 686CA4A2 +P 27600 19200 +F 0 "U1" H 27650 19300 30 0000 C CNN +F 1 "PORT" H 27600 19200 30 0000 C CNN +F 2 "" H 27600 19200 60 0000 C CNN +F 3 "" H 27600 19200 60 0000 C CNN + 15 27600 19200 + -1 0 0 1 +$EndComp +NoConn ~ 22500 10400 +NoConn ~ 22500 9150 +NoConn ~ 22750 11650 +NoConn ~ 22750 12900 +NoConn ~ 22500 14300 +NoConn ~ 22500 15550 +NoConn ~ 22700 16750 +NoConn ~ 22700 18000 +Text Label 5650 3500 0 60 ~ 0 +CLK +Text Label 5700 6900 0 60 ~ 0 +LOAD_BAR +Text Label 2700 8650 0 60 ~ 0 +CLR_BAR +Text Label 2900 9050 0 60 ~ 0 +DATA_A +Text Label 3150 11550 0 60 ~ 0 +DATA_B +Text Label 2750 14300 0 60 ~ 0 +DATA_C +Text Label 2550 16900 0 60 ~ 0 +DATA_D +Text Label 1100 18200 0 60 ~ 0 +ENP +Text Label 1100 18300 0 60 ~ 0 +ENT +Text Label 26550 19300 0 60 ~ 0 +RCO +Text Label 26250 17050 0 60 ~ 0 +QD +Text Label 25650 14600 0 60 ~ 0 +QC +Text Label 25250 11950 0 60 ~ 0 +QB +Text Label 25450 9450 0 60 ~ 0 +QA +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN74S163/SN74S163.cir b/library/SubcircuitLibrary/SN74S163/SN74S163.cir new file mode 100644 index 000000000..79445b0f4 --- /dev/null +++ b/library/SubcircuitLibrary/SN74S163/SN74S163.cir @@ -0,0 +1,56 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\SN74S163\SN74S163.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 07/08/25 18:43:59 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U40 Net-_U32-Pad3_ Net-_U36-Pad2_ ? ? /QA Net-_U18-Pad2_ d_dff +U43 Net-_U33-Pad3_ Net-_U39-Pad2_ ? ? /QB Net-_U19-Pad2_ d_dff +U41 Net-_U34-Pad3_ Net-_U37-Pad2_ ? ? /QC Net-_U20-Pad2_ d_dff +U42 Net-_U35-Pad3_ Net-_U38-Pad2_ ? ? /QD Net-_U21-Pad2_ d_dff +U11 /CLK Net-_U11-Pad2_ d_buffer +U15 Net-_U11-Pad2_ Net-_U15-Pad2_ d_inverter +U36 Net-_U15-Pad2_ Net-_U36-Pad2_ d_inverter +U39 Net-_U15-Pad2_ Net-_U39-Pad2_ d_inverter +U37 Net-_U15-Pad2_ Net-_U37-Pad2_ d_inverter +U38 Net-_U15-Pad2_ Net-_U38-Pad2_ d_inverter +U16 /LOAD_BAR Net-_U10-Pad2_ Net-_U16-Pad3_ d_nor +U17 Net-_U16-Pad3_ Net-_U10-Pad2_ Net-_U17-Pad3_ d_nor +U6 /CLR_BAR Net-_U10-Pad1_ d_inverter +U10 Net-_U10-Pad1_ Net-_U10-Pad2_ d_buffer +U30 Net-_U16-Pad3_ /DATA_D Net-_U30-Pad3_ d_and +U31 Net-_U17-Pad3_ Net-_U21-Pad3_ Net-_U31-Pad3_ d_and +U35 Net-_U30-Pad3_ Net-_U31-Pad3_ Net-_U35-Pad3_ d_or +U28 /DATA_C Net-_U16-Pad3_ Net-_U28-Pad3_ d_and +U29 Net-_U17-Pad3_ Net-_U20-Pad3_ Net-_U29-Pad3_ d_and +U34 Net-_U28-Pad3_ Net-_U29-Pad3_ Net-_U34-Pad3_ d_or +U26 /DATA_B Net-_U16-Pad3_ Net-_U26-Pad3_ d_and +U27 Net-_U17-Pad3_ Net-_U19-Pad3_ Net-_U27-Pad3_ d_and +U33 Net-_U26-Pad3_ Net-_U27-Pad3_ Net-_U33-Pad3_ d_or +U24 /DATA_A Net-_U16-Pad3_ Net-_U24-Pad3_ d_and +U25 Net-_U18-Pad3_ Net-_U17-Pad3_ Net-_U25-Pad3_ d_and +U32 Net-_U24-Pad3_ Net-_U25-Pad3_ Net-_U32-Pad3_ d_or +U18 Net-_U12-Pad2_ Net-_U18-Pad2_ Net-_U18-Pad3_ d_xnor +U19 Net-_U12-Pad3_ Net-_U19-Pad2_ Net-_U19-Pad3_ d_xnor +U20 Net-_U13-Pad3_ Net-_U20-Pad2_ Net-_U20-Pad3_ d_xnor +U21 Net-_U14-Pad3_ Net-_U21-Pad2_ Net-_U21-Pad3_ d_xnor +U2 /ENP /ENT Net-_U12-Pad2_ d_and +U3 Net-_U18-Pad2_ Net-_U3-Pad2_ d_buffer +U7 Net-_U3-Pad2_ Net-_U12-Pad1_ d_inverter +U12 Net-_U12-Pad1_ Net-_U12-Pad2_ Net-_U12-Pad3_ d_and +X2 Net-_U21-Pad2_ Net-_U20-Pad2_ Net-_U19-Pad2_ Net-_U18-Pad2_ Net-_U22-Pad1_ 4_OR +U23 Net-_U22-Pad3_ /RCO d_inverter +U22 Net-_U22-Pad1_ Net-_U22-Pad2_ Net-_U22-Pad3_ d_or +U4 /ENT Net-_U4-Pad2_ d_buffer +U9 Net-_U4-Pad2_ Net-_U22-Pad2_ d_inverter +U13 Net-_U13-Pad1_ Net-_U12-Pad2_ Net-_U13-Pad3_ d_and +U14 Net-_U14-Pad1_ Net-_U12-Pad2_ Net-_U14-Pad3_ d_and +U5 Net-_U18-Pad2_ Net-_U19-Pad2_ Net-_U13-Pad1_ d_nor +U8 Net-_U45-Pad3_ Net-_U14-Pad1_ d_inverter +U1 /CLR_BAR /CLK /DATA_A /DATA_B /DATA_C /DATA_D /ENP /LOAD_BAR /ENT /QD /QC /QB /QA /RCO PORT +U44 Net-_U20-Pad2_ Net-_U19-Pad2_ Net-_U44-Pad3_ d_or +U45 Net-_U44-Pad3_ Net-_U18-Pad2_ Net-_U45-Pad3_ d_or + +.end diff --git a/library/SubcircuitLibrary/SN74S163/SN74S163.cir.out b/library/SubcircuitLibrary/SN74S163/SN74S163.cir.out new file mode 100644 index 000000000..4f98243d4 --- /dev/null +++ b/library/SubcircuitLibrary/SN74S163/SN74S163.cir.out @@ -0,0 +1,190 @@ +* c:\fossee\esim\library\subcircuitlibrary\sn74s163\sn74s163.cir + +.include 4_OR.sub +* u40 net-_u32-pad3_ net-_u36-pad2_ ? ? /qa net-_u18-pad2_ d_dff +* u43 net-_u33-pad3_ net-_u39-pad2_ ? ? /qb net-_u19-pad2_ d_dff +* u41 net-_u34-pad3_ net-_u37-pad2_ ? ? /qc net-_u20-pad2_ d_dff +* u42 net-_u35-pad3_ net-_u38-pad2_ ? ? /qd net-_u21-pad2_ d_dff +* u11 /clk net-_u11-pad2_ d_buffer +* u15 net-_u11-pad2_ net-_u15-pad2_ d_inverter +* u36 net-_u15-pad2_ net-_u36-pad2_ d_inverter +* u39 net-_u15-pad2_ net-_u39-pad2_ d_inverter +* u37 net-_u15-pad2_ net-_u37-pad2_ d_inverter +* u38 net-_u15-pad2_ net-_u38-pad2_ d_inverter +* u16 /load_bar net-_u10-pad2_ net-_u16-pad3_ d_nor +* u17 net-_u16-pad3_ net-_u10-pad2_ net-_u17-pad3_ d_nor +* u6 /clr_bar net-_u10-pad1_ d_inverter +* u10 net-_u10-pad1_ net-_u10-pad2_ d_buffer +* u30 net-_u16-pad3_ /data_d net-_u30-pad3_ d_and +* u31 net-_u17-pad3_ net-_u21-pad3_ net-_u31-pad3_ d_and +* u35 net-_u30-pad3_ net-_u31-pad3_ net-_u35-pad3_ d_or +* u28 /data_c net-_u16-pad3_ net-_u28-pad3_ d_and +* u29 net-_u17-pad3_ net-_u20-pad3_ net-_u29-pad3_ d_and +* u34 net-_u28-pad3_ net-_u29-pad3_ net-_u34-pad3_ d_or +* u26 /data_b net-_u16-pad3_ net-_u26-pad3_ d_and +* u27 net-_u17-pad3_ net-_u19-pad3_ net-_u27-pad3_ d_and +* u33 net-_u26-pad3_ net-_u27-pad3_ net-_u33-pad3_ d_or +* u24 /data_a net-_u16-pad3_ net-_u24-pad3_ d_and +* u25 net-_u18-pad3_ net-_u17-pad3_ net-_u25-pad3_ d_and +* u32 net-_u24-pad3_ net-_u25-pad3_ net-_u32-pad3_ d_or +* u18 net-_u12-pad2_ net-_u18-pad2_ net-_u18-pad3_ d_xnor +* u19 net-_u12-pad3_ net-_u19-pad2_ net-_u19-pad3_ d_xnor +* u20 net-_u13-pad3_ net-_u20-pad2_ net-_u20-pad3_ d_xnor +* u21 net-_u14-pad3_ net-_u21-pad2_ net-_u21-pad3_ d_xnor +* u2 /enp /ent net-_u12-pad2_ d_and +* u3 net-_u18-pad2_ net-_u3-pad2_ d_buffer +* u7 net-_u3-pad2_ net-_u12-pad1_ d_inverter +* u12 net-_u12-pad1_ net-_u12-pad2_ net-_u12-pad3_ d_and +x2 net-_u21-pad2_ net-_u20-pad2_ net-_u19-pad2_ net-_u18-pad2_ net-_u22-pad1_ 4_OR +* u23 net-_u22-pad3_ /rco d_inverter +* u22 net-_u22-pad1_ net-_u22-pad2_ net-_u22-pad3_ d_or +* u4 /ent net-_u4-pad2_ d_buffer +* u9 net-_u4-pad2_ net-_u22-pad2_ d_inverter +* u13 net-_u13-pad1_ net-_u12-pad2_ net-_u13-pad3_ d_and +* u14 net-_u14-pad1_ net-_u12-pad2_ net-_u14-pad3_ d_and +* u5 net-_u18-pad2_ net-_u19-pad2_ net-_u13-pad1_ d_nor +* u8 net-_u45-pad3_ net-_u14-pad1_ d_inverter +* u1 /clr_bar /clk /data_a /data_b /data_c /data_d /enp /load_bar /ent /qd /qc /qb /qa /rco port +* u44 net-_u20-pad2_ net-_u19-pad2_ net-_u44-pad3_ d_or +* u45 net-_u44-pad3_ net-_u18-pad2_ net-_u45-pad3_ d_or +a1 net-_u32-pad3_ net-_u36-pad2_ ? ? /qa net-_u18-pad2_ u40 +a2 net-_u33-pad3_ net-_u39-pad2_ ? ? /qb net-_u19-pad2_ u43 +a3 net-_u34-pad3_ net-_u37-pad2_ ? ? /qc net-_u20-pad2_ u41 +a4 net-_u35-pad3_ net-_u38-pad2_ ? ? /qd net-_u21-pad2_ u42 +a5 /clk net-_u11-pad2_ u11 +a6 net-_u11-pad2_ net-_u15-pad2_ u15 +a7 net-_u15-pad2_ net-_u36-pad2_ u36 +a8 net-_u15-pad2_ net-_u39-pad2_ u39 +a9 net-_u15-pad2_ net-_u37-pad2_ u37 +a10 net-_u15-pad2_ net-_u38-pad2_ u38 +a11 [/load_bar net-_u10-pad2_ ] net-_u16-pad3_ u16 +a12 [net-_u16-pad3_ net-_u10-pad2_ ] net-_u17-pad3_ u17 +a13 /clr_bar net-_u10-pad1_ u6 +a14 net-_u10-pad1_ net-_u10-pad2_ u10 +a15 [net-_u16-pad3_ /data_d ] net-_u30-pad3_ u30 +a16 [net-_u17-pad3_ net-_u21-pad3_ ] net-_u31-pad3_ u31 +a17 [net-_u30-pad3_ net-_u31-pad3_ ] net-_u35-pad3_ u35 +a18 [/data_c net-_u16-pad3_ ] net-_u28-pad3_ u28 +a19 [net-_u17-pad3_ net-_u20-pad3_ ] net-_u29-pad3_ u29 +a20 [net-_u28-pad3_ net-_u29-pad3_ ] net-_u34-pad3_ u34 +a21 [/data_b net-_u16-pad3_ ] net-_u26-pad3_ u26 +a22 [net-_u17-pad3_ net-_u19-pad3_ ] net-_u27-pad3_ u27 +a23 [net-_u26-pad3_ net-_u27-pad3_ ] net-_u33-pad3_ u33 +a24 [/data_a net-_u16-pad3_ ] net-_u24-pad3_ u24 +a25 [net-_u18-pad3_ net-_u17-pad3_ ] net-_u25-pad3_ u25 +a26 [net-_u24-pad3_ net-_u25-pad3_ ] net-_u32-pad3_ u32 +a27 [net-_u12-pad2_ net-_u18-pad2_ ] net-_u18-pad3_ u18 +a28 [net-_u12-pad3_ net-_u19-pad2_ ] net-_u19-pad3_ u19 +a29 [net-_u13-pad3_ net-_u20-pad2_ ] net-_u20-pad3_ u20 +a30 [net-_u14-pad3_ net-_u21-pad2_ ] net-_u21-pad3_ u21 +a31 [/enp /ent ] net-_u12-pad2_ u2 +a32 net-_u18-pad2_ net-_u3-pad2_ u3 +a33 net-_u3-pad2_ net-_u12-pad1_ u7 +a34 [net-_u12-pad1_ net-_u12-pad2_ ] net-_u12-pad3_ u12 +a35 net-_u22-pad3_ /rco u23 +a36 [net-_u22-pad1_ net-_u22-pad2_ ] net-_u22-pad3_ u22 +a37 /ent net-_u4-pad2_ u4 +a38 net-_u4-pad2_ net-_u22-pad2_ u9 +a39 [net-_u13-pad1_ net-_u12-pad2_ ] net-_u13-pad3_ u13 +a40 [net-_u14-pad1_ net-_u12-pad2_ ] net-_u14-pad3_ u14 +a41 [net-_u18-pad2_ net-_u19-pad2_ ] net-_u13-pad1_ u5 +a42 net-_u45-pad3_ net-_u14-pad1_ u8 +a43 [net-_u20-pad2_ net-_u19-pad2_ ] net-_u44-pad3_ u44 +a44 [net-_u44-pad3_ net-_u18-pad2_ ] net-_u45-pad3_ u45 +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u40 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u43 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u41 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u42 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u11 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u36 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u39 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u37 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u38 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u16 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u17 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u10 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u30 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u31 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u35 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u28 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u29 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u34 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u26 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u27 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u33 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u24 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u25 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u32 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xnor, NgSpice Name: d_xnor +.model u18 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xnor, NgSpice Name: d_xnor +.model u19 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xnor, NgSpice Name: d_xnor +.model u20 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xnor, NgSpice Name: d_xnor +.model u21 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u3 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u12 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u23 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u22 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u4 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u13 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u14 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u5 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u44 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u45 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN74S163/SN74S163.pro b/library/SubcircuitLibrary/SN74S163/SN74S163.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/SN74S163/SN74S163.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/SN74S163/SN74S163.sch b/library/SubcircuitLibrary/SN74S163/SN74S163.sch new file mode 100644 index 000000000..033bb96eb --- /dev/null +++ b/library/SubcircuitLibrary/SN74S163/SN74S163.sch @@ -0,0 +1,1077 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:SN74S163-cache +EELAYER 25 0 +EELAYER END +$Descr A1 33110 23386 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_dff U40 +U 1 1 686BBBA3 +P 22500 9800 +F 0 "U40" H 22500 9800 60 0000 C CNN +F 1 "d_dff" H 22500 9950 60 0000 C CNN +F 2 "" H 22500 9800 60 0000 C CNN +F 3 "" H 22500 9800 60 0000 C CNN + 1 22500 9800 + 1 0 0 -1 +$EndComp +$Comp +L d_dff U43 +U 1 1 686BBBDB +P 22750 12300 +F 0 "U43" H 22750 12300 60 0000 C CNN +F 1 "d_dff" H 22750 12450 60 0000 C CNN +F 2 "" H 22750 12300 60 0000 C CNN +F 3 "" H 22750 12300 60 0000 C CNN + 1 22750 12300 + 1 0 0 -1 +$EndComp +$Comp +L d_dff U41 +U 1 1 686BBDFE +P 22500 14950 +F 0 "U41" H 22500 14950 60 0000 C CNN +F 1 "d_dff" H 22500 15100 60 0000 C CNN +F 2 "" H 22500 14950 60 0000 C CNN +F 3 "" H 22500 14950 60 0000 C CNN + 1 22500 14950 + 1 0 0 -1 +$EndComp +$Comp +L d_dff U42 +U 1 1 686BBE5B +P 22700 17400 +F 0 "U42" H 22700 17400 60 0000 C CNN +F 1 "d_dff" H 22700 17550 60 0000 C CNN +F 2 "" H 22700 17400 60 0000 C CNN +F 3 "" H 22700 17400 60 0000 C CNN + 1 22700 17400 + 1 0 0 -1 +$EndComp +$Comp +L d_buffer U11 +U 1 1 686BBEDA +P 8450 3500 +F 0 "U11" H 8450 3450 60 0000 C CNN +F 1 "d_buffer" H 8450 3550 60 0000 C CNN +F 2 "" H 8450 3500 60 0000 C CNN +F 3 "" H 8450 3500 60 0000 C CNN + 1 8450 3500 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U15 +U 1 1 686BBF3F +P 11000 3500 +F 0 "U15" H 11000 3400 60 0000 C CNN +F 1 "d_inverter" H 11000 3650 60 0000 C CNN +F 2 "" H 11050 3450 60 0000 C CNN +F 3 "" H 11050 3450 60 0000 C CNN + 1 11000 3500 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U36 +U 1 1 686BC0CC +P 21450 10100 +F 0 "U36" H 21450 10000 60 0000 C CNN +F 1 "d_inverter" H 21450 10250 60 0000 C CNN +F 2 "" H 21500 10050 60 0000 C CNN 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686BD435 +P 19050 14750 +F 0 "U34" H 19050 14750 60 0000 C CNN +F 1 "d_or" H 19050 14850 60 0000 C CNN +F 2 "" H 19050 14750 60 0000 C CNN +F 3 "" H 19050 14750 60 0000 C CNN + 1 19050 14750 + 1 0 0 -1 +$EndComp +$Comp +L d_and U26 +U 1 1 686BD748 +P 17200 11650 +F 0 "U26" H 17200 11650 60 0000 C CNN +F 1 "d_and" H 17250 11750 60 0000 C CNN +F 2 "" H 17200 11650 60 0000 C CNN +F 3 "" H 17200 11650 60 0000 C CNN + 1 17200 11650 + 1 0 0 -1 +$EndComp +$Comp +L d_and U27 +U 1 1 686BD74E +P 17200 12600 +F 0 "U27" H 17200 12600 60 0000 C CNN +F 1 "d_and" H 17250 12700 60 0000 C CNN +F 2 "" H 17200 12600 60 0000 C CNN +F 3 "" H 17200 12600 60 0000 C CNN + 1 17200 12600 + 1 0 0 -1 +$EndComp +$Comp +L d_or U33 +U 1 1 686BD754 +P 19000 12000 +F 0 "U33" H 19000 12000 60 0000 C CNN +F 1 "d_or" H 19000 12100 60 0000 C CNN +F 2 "" H 19000 12000 60 0000 C CNN +F 3 "" H 19000 12000 60 0000 C CNN + 1 19000 12000 + 1 0 0 -1 +$EndComp +$Comp +L d_and U24 +U 1 1 686BD75E +P 17150 9150 +F 0 "U24" H 17150 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17650 +Wire Wire Line + 4500 17250 5300 17250 +Connection ~ 4500 17250 +Wire Wire Line + 4400 17350 5300 17350 +Connection ~ 4400 17350 +Wire Wire Line + 4100 17450 5650 17450 +Connection ~ 4100 17450 +Wire Wire Line + 6100 14950 4100 14950 +Connection ~ 4100 14950 +Wire Wire Line + 6100 15050 4400 15050 +Connection ~ 4400 15050 +Wire Wire Line + 7000 15000 9550 15000 +Wire Wire Line + 9550 15100 9550 15150 +Wire Wire Line + 9550 15150 8800 15150 +Connection ~ 8800 15150 +Wire Wire Line + 10450 15050 13050 15050 +Wire Wire Line + 13050 15050 13050 15200 +Wire Wire Line + 10550 17600 13150 17600 +Wire Wire Line + 13150 17600 13150 17750 +Wire Wire Line + 16350 19300 27350 19300 +Wire Wire Line + 27350 19300 27350 19200 +Wire Wire Line + 19500 14700 21950 14700 +Wire Wire Line + 21950 14700 21950 14600 +Wire Wire Line + 22200 11950 19450 11950 +Wire Wire Line + 21950 9450 19400 9450 +Wire Wire Line + 23050 9450 25650 9450 +Wire Wire Line + 23300 11950 25800 11950 +Wire Wire Line + 25800 11950 25800 12000 +Wire Wire Line + 23050 14600 26050 14600 +Wire Wire Line + 26050 14600 26050 14700 +Wire Wire Line + 23250 17050 26650 17050 +Wire Wire Line + 26650 17050 26650 17000 +Wire Wire Line + 6450 8650 2550 8650 +Wire Wire Line + 2550 8650 2550 8000 +$Comp +L PORT U1 +U 2 1 686C751C +P 5250 3550 +F 0 "U1" H 5300 3650 30 0000 C CNN +F 1 "PORT" H 5250 3550 30 0000 C CNN +F 2 "" H 5250 3550 60 0000 C CNN +F 3 "" H 5250 3550 60 0000 C CNN + 2 5250 3550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 686C77B9 +P 5250 6800 +F 0 "U1" H 5300 6900 30 0000 C CNN +F 1 "PORT" H 5250 6800 30 0000 C CNN +F 2 "" H 5250 6800 60 0000 C CNN +F 3 "" H 5250 6800 60 0000 C CNN + 9 5250 6800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 686C7AE2 +P 2300 8000 +F 0 "U1" H 2350 8100 30 0000 C CNN +F 1 "PORT" H 2300 8000 30 0000 C CNN +F 2 "" H 2300 8000 60 0000 C CNN +F 3 "" H 2300 8000 60 0000 C CNN + 1 2300 8000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 686C7C5F +P 2450 9200 +F 0 "U1" H 2500 9300 30 0000 C CNN +F 1 "PORT" H 2450 9200 30 0000 C CNN +F 2 "" H 2450 9200 60 0000 C CNN +F 3 "" H 2450 9200 60 0000 C CNN + 3 2450 9200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 686C80EA +P 2700 11550 +F 0 "U1" H 2750 11650 30 0000 C CNN +F 1 "PORT" H 2700 11550 30 0000 C CNN +F 2 "" H 2700 11550 60 0000 C CNN +F 3 "" H 2700 11550 60 0000 C CNN + 4 2700 11550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 686C836C +P 2100 14250 +F 0 "U1" H 2150 14350 30 0000 C CNN +F 1 "PORT" H 2100 14250 30 0000 C CNN +F 2 "" H 2100 14250 60 0000 C CNN +F 3 "" H 2100 14250 60 0000 C CNN + 5 2100 14250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 686C8561 +P 2000 16950 +F 0 "U1" H 2050 17050 30 0000 C CNN +F 1 "PORT" H 2000 16950 30 0000 C CNN +F 2 "" H 2000 16950 60 0000 C CNN +F 3 "" H 2000 16950 60 0000 C CNN + 6 2000 16950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 686C88BB +P 700 18200 +F 0 "U1" H 750 18300 30 0000 C CNN +F 1 "PORT" H 700 18200 30 0000 C CNN +F 2 "" H 700 18200 60 0000 C CNN +F 3 "" H 700 18200 60 0000 C CNN + 7 700 18200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 686C8B9A +P 650 18450 +F 0 "U1" H 700 18550 30 0000 C CNN +F 1 "PORT" H 650 18450 30 0000 C CNN +F 2 "" H 650 18450 60 0000 C CNN +F 3 "" H 650 18450 60 0000 C CNN + 10 650 18450 + 1 0 0 -1 +$EndComp +Wire Wire Line + 950 18300 950 18450 +Wire Wire Line + 950 18450 900 18450 +$Comp +L PORT U1 +U 14 1 686C9983 +P 25900 9450 +F 0 "U1" H 25950 9550 30 0000 C CNN +F 1 "PORT" H 25900 9450 30 0000 C CNN +F 2 "" H 25900 9450 60 0000 C CNN +F 3 "" H 25900 9450 60 0000 C CNN + 14 25900 9450 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 13 1 686C9BA4 +P 26050 12000 +F 0 "U1" H 26100 12100 30 0000 C CNN +F 1 "PORT" H 26050 12000 30 0000 C CNN +F 2 "" H 26050 12000 60 0000 C CNN +F 3 "" H 26050 12000 60 0000 C CNN + 13 26050 12000 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 12 1 686C9EBC +P 26300 14700 +F 0 "U1" H 26350 14800 30 0000 C CNN +F 1 "PORT" H 26300 14700 30 0000 C CNN +F 2 "" H 26300 14700 60 0000 C CNN +F 3 "" H 26300 14700 60 0000 C CNN + 12 26300 14700 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 11 1 686CA19D +P 26900 17000 +F 0 "U1" H 26950 17100 30 0000 C CNN +F 1 "PORT" H 26900 17000 30 0000 C CNN +F 2 "" H 26900 17000 60 0000 C CNN +F 3 "" H 26900 17000 60 0000 C CNN + 11 26900 17000 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 15 1 686CA4A2 +P 27600 19200 +F 0 "U1" H 27650 19300 30 0000 C CNN +F 1 "PORT" H 27600 19200 30 0000 C CNN +F 2 "" H 27600 19200 60 0000 C CNN +F 3 "" H 27600 19200 60 0000 C CNN + 15 27600 19200 + -1 0 0 1 +$EndComp +NoConn ~ 22500 10400 +NoConn ~ 22500 9150 +NoConn ~ 22750 11650 +NoConn ~ 22750 12900 +NoConn ~ 22500 14300 +NoConn ~ 22500 15550 +NoConn ~ 22700 16750 +NoConn ~ 22700 18000 +Text Label 5650 3500 0 60 ~ 0 +CLK +Text Label 5700 6900 0 60 ~ 0 +LOAD_BAR +Text Label 2700 8650 0 60 ~ 0 +CLR_BAR +Text Label 2900 9050 0 60 ~ 0 +DATA_A +Text Label 3150 11550 0 60 ~ 0 +DATA_B +Text Label 2750 14300 0 60 ~ 0 +DATA_C +Text Label 2550 16900 0 60 ~ 0 +DATA_D +Text Label 1100 18200 0 60 ~ 0 +ENP +Text Label 1100 18300 0 60 ~ 0 +ENT +Text Label 26550 19300 0 60 ~ 0 +RCO +Text Label 26250 17050 0 60 ~ 0 +QD +Text Label 25650 14600 0 60 ~ 0 +QC +Text Label 25250 11950 0 60 ~ 0 +QB +Text Label 25450 9450 0 60 ~ 0 +QA +Wire Wire Line + 23550 18600 12600 18600 +Wire Wire Line + 12600 17850 12600 19150 +Connection ~ 12600 18600 +$Comp +L d_or U44 +U 1 1 686DA9AB +P 5750 17350 +F 0 "U44" H 5750 17350 60 0000 C CNN +F 1 "d_or" H 5750 17450 60 0000 C CNN +F 2 "" H 5750 17350 60 0000 C CNN +F 3 "" H 5750 17350 60 0000 C CNN + 1 5750 17350 + 1 0 0 -1 +$EndComp +$Comp +L d_or U45 +U 1 1 686DADD1 +P 6500 17650 +F 0 "U45" H 6500 17650 60 0000 C CNN +F 1 "d_or" H 6500 17750 60 0000 C CNN +F 2 "" H 6500 17650 60 0000 C CNN +F 3 "" H 6500 17650 60 0000 C CNN + 1 6500 17650 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6050 17550 6050 17450 +Wire Wire Line + 6050 17450 6200 17450 +Wire Wire Line + 6200 17450 6200 17300 +Wire Wire Line + 5650 17450 5650 17650 +Wire Wire Line + 5650 17650 6050 17650 +Wire Wire Line + 6950 17350 6950 17600 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN74S163/SN74S163.sub b/library/SubcircuitLibrary/SN74S163/SN74S163.sub new file mode 100644 index 000000000..72e71624c --- /dev/null +++ b/library/SubcircuitLibrary/SN74S163/SN74S163.sub @@ -0,0 +1,184 @@ +* Subcircuit SN74S163 +.subckt SN74S163 /clr_bar /clk /data_a /data_b /data_c /data_d /enp /load_bar /ent /qd /qc /qb /qa /rco +* c:\fossee\esim\library\subcircuitlibrary\sn74s163\sn74s163.cir +.include 4_OR.sub +* u40 net-_u32-pad3_ net-_u36-pad2_ ? ? /qa net-_u18-pad2_ d_dff +* u43 net-_u33-pad3_ net-_u39-pad2_ ? ? /qb net-_u19-pad2_ d_dff +* u41 net-_u34-pad3_ net-_u37-pad2_ ? ? /qc net-_u20-pad2_ d_dff +* u42 net-_u35-pad3_ net-_u38-pad2_ ? ? /qd net-_u21-pad2_ d_dff +* u11 /clk net-_u11-pad2_ d_buffer +* u15 net-_u11-pad2_ net-_u15-pad2_ d_inverter +* u36 net-_u15-pad2_ net-_u36-pad2_ d_inverter +* u39 net-_u15-pad2_ net-_u39-pad2_ d_inverter +* u37 net-_u15-pad2_ net-_u37-pad2_ d_inverter +* u38 net-_u15-pad2_ net-_u38-pad2_ d_inverter +* u16 /load_bar net-_u10-pad2_ net-_u16-pad3_ d_nor +* u17 net-_u16-pad3_ net-_u10-pad2_ net-_u17-pad3_ d_nor +* u6 /clr_bar net-_u10-pad1_ d_inverter +* u10 net-_u10-pad1_ net-_u10-pad2_ d_buffer +* u30 net-_u16-pad3_ /data_d net-_u30-pad3_ d_and +* u31 net-_u17-pad3_ net-_u21-pad3_ net-_u31-pad3_ d_and +* u35 net-_u30-pad3_ net-_u31-pad3_ net-_u35-pad3_ d_or +* u28 /data_c net-_u16-pad3_ net-_u28-pad3_ d_and +* u29 net-_u17-pad3_ net-_u20-pad3_ net-_u29-pad3_ d_and +* u34 net-_u28-pad3_ net-_u29-pad3_ net-_u34-pad3_ d_or +* u26 /data_b net-_u16-pad3_ net-_u26-pad3_ d_and +* u27 net-_u17-pad3_ net-_u19-pad3_ net-_u27-pad3_ d_and +* u33 net-_u26-pad3_ net-_u27-pad3_ net-_u33-pad3_ d_or +* u24 /data_a net-_u16-pad3_ net-_u24-pad3_ d_and +* u25 net-_u18-pad3_ net-_u17-pad3_ net-_u25-pad3_ d_and +* u32 net-_u24-pad3_ net-_u25-pad3_ net-_u32-pad3_ d_or +* u18 net-_u12-pad2_ net-_u18-pad2_ net-_u18-pad3_ d_xnor +* u19 net-_u12-pad3_ net-_u19-pad2_ net-_u19-pad3_ d_xnor +* u20 net-_u13-pad3_ net-_u20-pad2_ net-_u20-pad3_ d_xnor +* u21 net-_u14-pad3_ net-_u21-pad2_ net-_u21-pad3_ d_xnor +* u2 /enp /ent net-_u12-pad2_ d_and +* u3 net-_u18-pad2_ net-_u3-pad2_ d_buffer +* u7 net-_u3-pad2_ net-_u12-pad1_ d_inverter +* u12 net-_u12-pad1_ net-_u12-pad2_ net-_u12-pad3_ d_and +x2 net-_u21-pad2_ net-_u20-pad2_ net-_u19-pad2_ net-_u18-pad2_ net-_u22-pad1_ 4_OR +* u23 net-_u22-pad3_ /rco d_inverter +* u22 net-_u22-pad1_ net-_u22-pad2_ net-_u22-pad3_ d_or +* u4 /ent net-_u4-pad2_ d_buffer +* u9 net-_u4-pad2_ net-_u22-pad2_ d_inverter +* u13 net-_u13-pad1_ net-_u12-pad2_ net-_u13-pad3_ d_and +* u14 net-_u14-pad1_ net-_u12-pad2_ net-_u14-pad3_ d_and +* u5 net-_u18-pad2_ net-_u19-pad2_ net-_u13-pad1_ d_nor +* u8 net-_u45-pad3_ net-_u14-pad1_ d_inverter +* u44 net-_u20-pad2_ net-_u19-pad2_ net-_u44-pad3_ d_or +* u45 net-_u44-pad3_ net-_u18-pad2_ net-_u45-pad3_ d_or +a1 net-_u32-pad3_ net-_u36-pad2_ ? ? /qa net-_u18-pad2_ u40 +a2 net-_u33-pad3_ net-_u39-pad2_ ? ? /qb net-_u19-pad2_ u43 +a3 net-_u34-pad3_ net-_u37-pad2_ ? ? /qc net-_u20-pad2_ u41 +a4 net-_u35-pad3_ net-_u38-pad2_ ? ? /qd net-_u21-pad2_ u42 +a5 /clk net-_u11-pad2_ u11 +a6 net-_u11-pad2_ net-_u15-pad2_ u15 +a7 net-_u15-pad2_ net-_u36-pad2_ u36 +a8 net-_u15-pad2_ net-_u39-pad2_ u39 +a9 net-_u15-pad2_ net-_u37-pad2_ u37 +a10 net-_u15-pad2_ net-_u38-pad2_ u38 +a11 [/load_bar net-_u10-pad2_ ] net-_u16-pad3_ u16 +a12 [net-_u16-pad3_ net-_u10-pad2_ ] net-_u17-pad3_ u17 +a13 /clr_bar net-_u10-pad1_ u6 +a14 net-_u10-pad1_ net-_u10-pad2_ u10 +a15 [net-_u16-pad3_ /data_d ] net-_u30-pad3_ u30 +a16 [net-_u17-pad3_ net-_u21-pad3_ ] net-_u31-pad3_ u31 +a17 [net-_u30-pad3_ net-_u31-pad3_ ] net-_u35-pad3_ u35 +a18 [/data_c net-_u16-pad3_ ] net-_u28-pad3_ u28 +a19 [net-_u17-pad3_ net-_u20-pad3_ ] net-_u29-pad3_ u29 +a20 [net-_u28-pad3_ net-_u29-pad3_ ] net-_u34-pad3_ u34 +a21 [/data_b net-_u16-pad3_ ] net-_u26-pad3_ u26 +a22 [net-_u17-pad3_ net-_u19-pad3_ ] net-_u27-pad3_ u27 +a23 [net-_u26-pad3_ net-_u27-pad3_ ] net-_u33-pad3_ u33 +a24 [/data_a net-_u16-pad3_ ] net-_u24-pad3_ u24 +a25 [net-_u18-pad3_ net-_u17-pad3_ ] net-_u25-pad3_ u25 +a26 [net-_u24-pad3_ net-_u25-pad3_ ] net-_u32-pad3_ u32 +a27 [net-_u12-pad2_ net-_u18-pad2_ ] net-_u18-pad3_ u18 +a28 [net-_u12-pad3_ net-_u19-pad2_ ] net-_u19-pad3_ u19 +a29 [net-_u13-pad3_ net-_u20-pad2_ ] net-_u20-pad3_ u20 +a30 [net-_u14-pad3_ net-_u21-pad2_ ] net-_u21-pad3_ u21 +a31 [/enp /ent ] net-_u12-pad2_ u2 +a32 net-_u18-pad2_ net-_u3-pad2_ u3 +a33 net-_u3-pad2_ net-_u12-pad1_ u7 +a34 [net-_u12-pad1_ net-_u12-pad2_ ] net-_u12-pad3_ u12 +a35 net-_u22-pad3_ /rco u23 +a36 [net-_u22-pad1_ net-_u22-pad2_ ] net-_u22-pad3_ u22 +a37 /ent net-_u4-pad2_ u4 +a38 net-_u4-pad2_ net-_u22-pad2_ u9 +a39 [net-_u13-pad1_ net-_u12-pad2_ ] net-_u13-pad3_ u13 +a40 [net-_u14-pad1_ net-_u12-pad2_ ] net-_u14-pad3_ u14 +a41 [net-_u18-pad2_ net-_u19-pad2_ ] net-_u13-pad1_ u5 +a42 net-_u45-pad3_ net-_u14-pad1_ u8 +a43 [net-_u20-pad2_ net-_u19-pad2_ ] net-_u44-pad3_ u44 +a44 [net-_u44-pad3_ net-_u18-pad2_ ] net-_u45-pad3_ u45 +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u40 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u43 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u41 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u42 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u11 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u36 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u39 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u37 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u38 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u16 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u17 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u10 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u30 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u31 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u35 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u28 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u29 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u34 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u26 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u27 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u33 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u24 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u25 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u32 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xnor, NgSpice Name: d_xnor +.model u18 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xnor, NgSpice Name: d_xnor +.model u19 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xnor, NgSpice Name: d_xnor +.model u20 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xnor, NgSpice Name: d_xnor +.model u21 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u3 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u12 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u23 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u22 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u4 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u13 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u14 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u5 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u44 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u45 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends SN74S163 \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74S163/SN74S163_Previous_Values.xml b/library/SubcircuitLibrary/SN74S163/SN74S163_Previous_Values.xml new file mode 100644 index 000000000..93a2738e2 --- /dev/null +++ b/library/SubcircuitLibrary/SN74S163/SN74S163_Previous_Values.xml @@ -0,0 +1 @@ +d_dffd_dffd_dffd_dffd_bufferd_inverterd_inverterd_inverterd_inverterd_inverterd_nord_nord_inverterd_bufferd_andd_andd_ord_andd_andd_ord_andd_andd_ord_andd_andd_ord_xnord_xnord_xnord_xnord_andd_bufferd_inverterd_andd_inverterd_ord_bufferd_inverterd_andd_andd_nord_inverterd_ord_orC:\FOSSEE\eSim\library\SubcircuitLibrary\4_ORtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74S163/analysis b/library/SubcircuitLibrary/SN74S163/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/SubcircuitLibrary/SN74S163/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/library/kicadLibrary/kicad_eSim-Library/eSim_Subckt.lib b/library/kicadLibrary/kicad_eSim-Library/eSim_Subckt.lib index e69de29bb..6afee64dc 100644 --- a/library/kicadLibrary/kicad_eSim-Library/eSim_Subckt.lib +++ b/library/kicadLibrary/kicad_eSim-Library/eSim_Subckt.lib @@ -0,0 +1,1402 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 10bitDAC +# +DEF 10bitDAC X 0 40 Y Y 1 F N +F0 "X" 0 50 60 H V C CNN +F1 "10bitDAC" -50 -50 60 H V C CNN +F2 "" 0 50 60 H I C CNN +F3 "" 0 50 60 H I C CNN +DRAW +S -500 500 400 -600 0 1 0 N +X D0 1 -700 -500 200 R 50 50 1 1 I +X D1 2 -700 -400 200 R 50 50 1 1 I +X D2 3 -700 -300 200 R 50 50 1 1 I +X D3 4 -700 -200 200 R 50 50 1 1 I +X D4 5 -700 -100 200 R 50 50 1 1 I +X D5 6 -700 0 200 R 50 50 1 1 I +X D6 7 -700 100 200 R 50 50 1 1 I +X D7 8 -700 200 200 R 50 50 1 1 I +X D8 9 -700 300 200 R 50 50 1 1 I +X D9 10 -700 400 200 R 50 50 1 1 I +X AnalogOut 11 600 350 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 2BITMUL +# +DEF 2BITMUL X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "2BITMUL" 0 0 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -300 400 300 -400 0 1 0 N +X A0 1 -500 300 200 R 50 50 1 1 I +X A1 2 -500 150 200 R 50 50 1 1 I +X B0 3 -500 -50 200 R 50 50 1 1 I +X B1 4 -500 -250 200 R 50 50 1 1 I +X M0 5 500 250 200 L 50 50 1 1 O +X M1 6 500 100 200 L 50 50 1 1 O +X M2 7 500 -50 200 L 50 50 1 1 O +X M3 8 500 -250 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 100 -50 60 H V C CNN +F1 "3_and" 150 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 150 50 158 716 -716 0 1 0 N 200 200 200 -100 +P 2 0 1 0 -150 200 200 200 N +P 3 0 1 0 -150 200 -150 -100 200 -100 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X out 4 500 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 4_OR +# +DEF 4_OR X 0 40 Y Y 1 F N +F0 "X" 150 -100 60 H V C CNN +F1 "4_OR" 150 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -800 0 650 226 -226 0 1 0 N -200 250 -200 -250 +A -73 134 444 -599 -176 0 1 0 N 150 -250 350 0 +A -30 -99 393 627 146 0 1 0 N 150 250 350 0 +P 2 0 1 0 -200 -250 150 -250 N +P 2 0 1 0 -200 250 150 250 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X in4 4 -350 -150 200 R 50 50 1 1 I +X out 5 550 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 4_and +# +DEF 4_and X 0 40 Y Y 1 F N +F0 "X" 50 -50 60 H V C CNN +F1 "4_and" 100 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 100 0 206 760 -760 0 1 0 N 150 200 150 -200 +P 2 0 1 0 -200 200 150 200 N +P 4 0 1 0 -200 200 -200 -200 50 -200 150 -200 N +X in1 1 -400 150 200 R 50 50 1 1 I +X in2 2 -400 50 200 R 50 50 1 1 I +X in3 3 -400 -50 200 R 50 50 1 1 I +X in4 4 -400 -150 200 R 50 50 1 1 I +X out 5 500 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 556 +# +DEF 556 X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "556" 0 0 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -300 400 250 -550 0 1 0 N +X dis1 1 -500 150 200 R 50 50 1 1 I +X thr1 2 -500 -150 200 R 50 50 1 1 I +X cv1 3 -150 -750 200 U 50 50 1 1 I +X rst1 4 -200 600 200 D 50 50 1 1 I +X out1 5 -500 0 200 R 50 50 1 1 O +X trig1 6 -500 -300 200 R 50 50 1 1 I +X gnd 7 0 -750 200 U 50 50 1 1 I +X trig2 8 450 -300 200 L 50 50 1 1 I +X out2 9 450 0 200 L 50 50 1 1 O +X rst2 10 100 600 200 D 50 50 1 1 I +X cv2 11 150 -750 200 U 50 50 1 1 I +X thr2 12 450 -150 200 L 50 50 1 1 I +X dis2 13 450 150 200 L 50 50 1 1 I +X vcc 14 -50 600 200 D 50 50 1 1 I +ENDDRAW +ENDDEF +# +# 5_and +# +DEF 5_and X 0 40 Y Y 1 F N +F0 "X" 50 -100 60 H V C CNN +F1 "5_and" 100 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 100 0 255 787 -787 0 1 0 N 150 250 150 -250 +P 2 0 1 0 -250 250 150 250 N +P 3 0 1 0 -250 250 -250 -250 150 -250 N +X in1 1 -450 200 200 R 50 50 1 1 I +X in2 2 -450 100 200 R 50 50 1 1 I +X in3 3 -450 0 200 R 50 50 1 1 I +X in4 4 -450 -100 200 R 50 50 1 1 I +X in5 5 -450 -200 200 R 50 50 1 1 I +X out 6 550 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 74HCT4040 +# +DEF 74HCT4040 X 0 40 Y Y 1 F N +F0 "X" 0 100 60 H V C CNN +F1 "74HCT4040" 0 250 60 H V C CNN +F2 "" 0 100 60 H I C CNN +F3 "" 0 100 60 H I C CNN +DRAW +S -550 850 550 -450 0 1 0 N +X Q11 1 -750 750 200 R 50 50 1 1 O +X Q5 2 -750 600 200 R 50 50 1 1 O +X Q4 3 -750 450 200 R 50 50 1 1 O +X Q6 4 -750 300 200 R 50 50 1 1 O +X Q3 5 -750 150 200 R 50 50 1 1 O +X Q2 6 -750 0 200 R 50 50 1 1 O +X Q1 7 -750 -150 200 R 50 50 1 1 O +X GND 8 -750 -300 200 R 50 50 1 1 I N +X Q0 9 750 -300 200 L 50 50 1 1 O +X CP_Bar 10 750 -150 200 L 50 50 1 1 I +X MR 11 750 0 200 L 50 50 1 1 I +X Q8 12 750 150 200 L 50 50 1 1 O +X Q7 13 750 300 200 L 50 50 1 1 O +X Q9 14 750 450 200 L 50 50 1 1 O +X Q10 15 750 600 200 L 50 50 1 1 O +X VCC 16 750 750 200 L 50 50 1 1 I N +ENDDRAW +ENDDEF +# +# 74LS93 +# +DEF 74LS93 X 0 40 Y Y 1 F N +F0 "X" 150 -400 60 H V C CNN +F1 "74LS93" 100 100 60 H V C CNN +F2 "" 100 100 60 H I C CNN +F3 "" 100 100 60 H I C CNN +DRAW +S -250 50 500 -750 0 1 0 N +S 300 -1150 300 -1150 0 1 0 N +X CP1_bar 1 -450 -50 200 R 50 50 1 1 I +X MR1 2 -450 -150 200 R 50 50 1 1 I +X MR2 3 -450 -250 200 R 50 50 1 1 I +X NC 4 -450 -350 200 R 50 50 1 1 N +X VCC 5 -450 -450 200 R 50 50 1 1 I +X NC 6 -450 -550 200 R 50 50 1 1 N +X NC 7 -450 -650 200 R 50 50 1 1 N +X Q2 8 700 -650 200 L 50 50 1 1 O +X Q1 9 700 -550 200 L 50 50 1 1 O +X GND 10 700 -450 200 L 50 50 1 1 I +X Q3 11 700 -350 200 L 50 50 1 1 O +X Q0 12 700 -250 200 L 50 50 1 1 O +X NC 13 700 -150 200 L 50 50 1 1 N +X CP0_bar 14 700 -50 200 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# 93L14 +# +DEF 93L14 X 0 40 Y Y 1 F N +F0 "X" -50 -1000 60 H V C CNN +F1 "93L14" -50 200 60 H V C CNN +F2 "" -50 200 60 H I C CNN +F3 "" -50 200 60 H I C CNN +DRAW +S -300 150 200 -950 0 1 0 N +S 200 -300 200 -250 0 1 0 N +X E_Bar 1 -500 100 200 R 50 50 1 1 I +X S0_bar 2 -500 -150 200 R 50 50 1 1 I +X D0 3 -500 -250 200 R 50 50 1 1 I +X D1 4 -500 -450 200 R 50 50 1 1 I +X S2_bar 5 -500 -550 200 R 50 50 1 1 I +X D2 6 -500 -650 200 R 50 50 1 1 I +X D3 7 -500 -850 200 R 50 50 1 1 I +X MR_Bar 9 -500 0 200 R 50 50 1 1 I +X Q3 10 400 -650 200 L 50 50 1 1 O +X S3_bar 11 -500 -750 200 R 50 50 1 1 I +X Q2 12 400 -450 200 L 50 50 1 1 O +X Q1 13 400 -250 200 L 50 50 1 1 O +X S1_bar 14 -500 -350 200 R 50 50 1 1 I +X Q0 15 400 -50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# AOI +# +DEF AOI X 0 40 Y Y 1 F N +F0 "X" 0 100 60 H V C CNN +F1 "AOI" 0 0 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -200 300 200 -300 0 1 0 N +S 200 -300 200 -300 0 1 0 N +X A 1 -400 200 200 R 50 50 1 1 I +X B 2 -400 100 200 R 50 50 1 1 I +X E 3 0 -500 200 U 50 50 1 1 O +X VSS 7 -400 -100 200 R 50 50 1 1 I +X I 10 0 500 200 D 50 50 1 1 I +X C 12 400 100 200 L 50 50 1 1 I +X D 13 400 200 200 L 50 50 1 1 I +X VDD 14 400 -100 200 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# BAT54A +# +DEF BAT54A X 0 40 Y Y 1 F N +F0 "X" 150 -150 60 H V C CNN +F1 "BAT54A" 150 0 60 H V C CNN +F2 "" 150 0 60 H I C CNN +F3 "" 150 0 60 H I C CNN +DRAW +S -350 250 600 -200 0 1 0 N +X AN1 1 -550 50 200 R 50 50 1 1 I +X AN2 2 800 50 200 L 50 50 1 1 I +X K 3 150 450 200 D 50 50 1 1 O +ENDDRAW +ENDDEF +# +# CD4017B +# +DEF CD4017B X 0 40 Y Y 1 F N +F0 "X" 100 300 60 H V C CNN +F1 "CD4017B" 50 -700 60 H V C CNN +F2 "" 50 -700 60 H I C CNN +F3 "" 50 -700 60 H I C CNN +DRAW +S -350 400 350 -750 0 1 0 N +X NO_5 1 -550 300 200 R 50 50 1 1 O +X NO_1 2 -550 200 200 R 50 50 1 1 O +X NO_0 3 -550 100 200 R 50 50 1 1 O +X NO_2 4 -550 0 200 R 50 50 1 1 O +X NO_6 5 -550 -100 200 R 50 50 1 1 O +X NO_7 6 -550 -200 200 R 50 50 1 1 O +X NO_3 7 -550 -300 200 R 50 50 1 1 O +X NO_8 9 -550 -400 200 R 50 50 1 1 O +X NO_4 10 -550 -500 200 R 50 50 1 1 O +X NO_9 11 -550 -600 200 R 50 50 1 1 O +X CAR_OUT 12 550 -500 200 L 50 50 1 1 O +X CLK_INHIB 13 550 -300 200 L 50 50 1 1 I +X CLK 14 550 -100 200 L 50 50 1 1 I +X RESET 15 550 100 200 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# CD4022B +# +DEF CD4022B X 0 40 Y Y 1 F N +F0 "X" 0 350 60 H V C CNN +F1 "CD4022B" 0 0 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -550 900 600 -200 0 1 0 N +S -550 1000 -550 1000 0 1 0 N +X NO_1 1 -750 800 200 R 50 50 1 1 O +X No_0 2 -750 650 200 R 50 50 1 1 O +X NO_2 3 -750 500 200 R 50 50 1 1 O +X NO_5 4 -750 350 200 R 50 50 1 1 O +X NO_6 5 -750 200 200 R 50 50 1 1 O +X NC 6 -750 50 200 R 50 50 1 1 O +X NO_3 7 -750 -100 200 R 50 50 1 1 O +X NC 9 800 -100 200 L 50 50 1 1 O +X NO_7 10 800 50 200 L 50 50 1 1 O +X NO_4 11 800 200 200 L 50 50 1 1 O +X CARRY_OUT 12 800 350 200 L 50 50 1 1 O +X CLK_INHIB 13 800 500 200 L 50 50 1 1 I +X CLK 14 800 650 200 L 50 50 1 1 I +X RESET 15 800 800 200 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# CD4030B +# +DEF CD4030B X 0 40 Y Y 1 F N +F0 "X" 0 100 60 H V C CNN +F1 "CD4030B" -50 500 60 H V C CNN +F2 "" 0 -400 60 H I C CNN +F3 "" 0 -400 60 H I C CNN +DRAW +S -350 550 350 -500 0 1 0 N +X A 1 -550 450 200 R 50 50 1 1 I +X B 2 -550 300 200 R 50 50 1 1 I +X J 3 -550 150 200 R 50 50 1 1 O +X K 4 -550 0 200 R 50 50 1 1 O +X C 5 -550 -150 200 R 50 50 1 1 I +X D 6 -550 -300 200 R 50 50 1 1 I +X VSS 7 -550 -450 200 R 50 50 1 1 I +X E 8 550 -450 200 L 50 50 1 1 I +X F 9 550 -300 200 L 50 50 1 1 I +X L 10 550 -150 200 L 50 50 1 1 O +X M 11 550 0 200 L 50 50 1 1 O +X G 12 550 150 200 L 50 50 1 1 I +X H 13 550 300 200 L 50 50 1 1 I +X VDD 14 550 450 200 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# CD4078B +# +DEF CD4078B X 0 40 Y Y 1 F N +F0 "X" 0 250 60 H V C CNN +F1 "CD4078B" 0 100 60 H V C CNN +F2 "" 0 100 60 H I C CNN +F3 "" 0 100 60 H I C CNN +DRAW +S -350 700 350 -450 0 1 0 N +S 400 -700 400 -700 0 1 0 N +X K 1 -550 550 200 R 50 50 1 1 O +X A 2 -550 400 200 R 50 50 1 1 I +X B 3 -550 250 200 R 50 50 1 1 I +X C 4 -550 100 200 R 50 50 1 1 I +X D 5 -550 -50 200 R 50 50 1 1 I +X NC 6 -550 -200 200 R 50 50 1 1 I +X VSS 7 -550 -350 200 R 50 50 1 1 I +X NC 8 550 -350 200 L 50 50 1 1 I +X E 9 550 -200 200 L 50 50 1 1 I +X F 10 550 -50 200 L 50 50 1 1 I +X G 11 550 100 200 L 50 50 1 1 I +X H 12 550 250 200 L 50 50 1 1 I +X J 13 550 400 200 L 50 50 1 1 I +X VDD 14 550 550 200 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# CD4085B +# +DEF CD4085B X 0 40 Y Y 1 F N +F0 "X" 0 150 60 H V C CNN +F1 "CD4085B" 0 450 60 H V C CNN +F2 "" 0 450 60 H I C CNN +F3 "" 0 450 60 H I C CNN +DRAW +S -450 750 450 -350 0 1 0 N +X A1 1 -650 650 200 R 50 50 1 1 I +X B1 2 -650 500 200 R 50 50 1 1 I +X E1 3 -650 350 200 R 50 50 1 1 O +X E2 4 -650 200 200 R 50 50 1 1 O +X A2 5 -650 50 200 R 50 50 1 1 I +X B2 6 -650 -100 200 R 50 50 1 1 I +X VSS 7 -650 -250 200 R 50 50 1 1 I +X C2 8 650 -250 200 L 50 50 1 1 I +X D2 9 650 -100 200 L 50 50 1 1 I +X INHIB1 10 650 50 200 L 50 50 1 1 I +X INHIB2 11 650 200 200 L 50 50 1 1 I +X C1 12 650 350 200 L 50 50 1 1 I +X D1 13 650 500 200 L 50 50 1 1 I +X VDD 14 650 650 200 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# CD74HC4050 +# +DEF CD74HC4050 X 0 40 Y Y 1 F N +F0 "X" 0 300 60 H V C CNN +F1 "CD74HC4050" 0 -600 60 H V C CNN +F2 "" 0 -600 60 H I C CNN +F3 "" 0 -600 60 H I C CNN +DRAW +S -350 450 350 -650 0 1 0 N +X 1Y 2 -550 300 200 R 50 50 1 1 O +X 1A 3 -550 150 200 R 50 50 1 1 I +X 2Y 4 -550 0 200 R 50 50 1 1 O +X 2A 5 -550 -150 200 R 50 50 1 1 I +X 3Y 6 -550 -300 200 R 50 50 1 1 O +X 3A 7 -550 -450 200 R 50 50 1 1 I +X 4A 9 550 -450 200 L 50 50 1 1 I +X 4Y 10 550 -300 200 L 50 50 1 1 O +X 5A 11 550 -150 200 L 50 50 1 1 I +X 5Y 12 550 0 200 L 50 50 1 1 O +X 6A 14 550 150 200 L 50 50 1 1 I +X 6Y 15 550 300 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# CMOS_NAND +# +DEF CMOS_NAND X 0 40 Y Y 1 F N +F0 "X" -100 -150 60 H V C CNN +F1 "CMOS_NAND" 0 -50 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A 150 -50 381 668 -668 0 1 0 N 300 300 300 -400 +C 550 0 50 0 1 0 N +P 2 0 1 0 -350 300 300 300 N +P 3 0 1 0 -350 300 -350 -400 300 -400 N +X in1 1 -550 250 200 R 50 50 1 1 I +X in2 2 -550 -300 200 R 50 50 1 1 I +X out 3 800 0 279 L 79 79 1 1 I +ENDDRAW +ENDDEF +# +# Clock_pulse_generator +# +DEF Clock_pulse_generator X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "Clock_pulse_generator" 0 -100 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -550 200 600 -300 0 1 0 N +X Vdd 1 -750 100 200 R 50 50 1 1 I +X R 2 -750 -50 200 R 50 50 1 1 I +X C 3 -750 -200 200 R 50 50 1 1 I +X Clkout 4 800 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# DSR_Latch +# +DEF DSR_Latch X 0 40 Y Y 1 F N +F0 "X" -50 -350 60 H V C CNN +F1 "DSR_Latch" -50 200 60 H V C CNN +F2 "" -50 200 60 H I C CNN +F3 "" -50 200 60 H I C CNN +DRAW +S -300 150 200 -300 0 1 0 N +S 200 -300 200 -250 0 1 0 N +X E_Bar 1 -500 100 200 R 50 50 1 1 I +X S0_bar 2 -500 -150 200 R 50 50 1 1 I +X D0 3 -500 -250 200 R 50 50 1 1 I +X MR_Bar 9 -500 0 200 R 50 50 1 1 I +X Q0 15 400 -50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# EXOR_S +# +DEF EXOR_S X 0 40 Y Y 1 F N +F0 "X" 0 100 60 H V C CNN +F1 "EXOR_S" 0 0 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -550 450 500 -350 0 1 0 N +X A 1 -750 300 200 R 50 50 1 1 I +X B 2 -750 -100 200 R 50 50 1 1 I +X O 3 700 50 200 L 50 50 1 1 O +X VSS 7 0 -550 200 U 50 50 1 1 I +X VCC 14 0 650 200 D 50 50 1 1 I +ENDDRAW +ENDDEF +# +# HEX +# +DEF HEX X 0 40 Y Y 1 F N +F0 "X" 0 100 60 H V C CNN +F1 "HEX" 0 -50 60 H V C CNN +F2 "" 0 -50 60 H I C CNN +F3 "" 0 -50 60 H I C CNN +DRAW +S -250 150 250 -200 0 1 0 N +S 250 -200 250 -200 0 1 0 N +X A 1 -450 0 200 R 50 50 1 1 I +X Y 2 450 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# IC733 +# +DEF IC733 X 0 40 Y Y 1 F N +F0 "X" -150 -800 60 H V C CNN +F1 "IC733" -150 400 60 H V C CNN +F2 "" 0 450 60 H I C CNN +F3 "" 0 450 60 H I C CNN +DRAW +S -450 350 150 -750 0 1 0 N +X IN2 1 -650 250 200 R 50 50 1 1 I +X NC 2 -650 100 200 R 50 50 1 1 I +X G2B 3 -650 -50 200 R 50 50 1 1 I +X G1B 4 -650 -200 200 R 50 50 1 1 I +X V- 5 -650 -350 200 R 50 50 1 1 I +X NC 6 -650 -500 200 R 50 50 1 1 I +X OUT2 7 -650 -650 200 R 50 50 1 1 O +X OUT1 8 350 -650 200 L 50 50 1 1 O +X NC 9 350 -500 200 L 50 50 1 1 I +X V+ 10 350 -350 200 L 50 50 1 1 I +X G1A 11 350 -200 200 L 50 50 1 1 I +X G2A 12 350 -50 200 L 50 50 1 1 I +X NC 13 350 100 200 L 50 50 1 1 I +X IN1 14 350 250 200 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# ICL7611 +# +DEF ICL7611 X 0 40 Y Y 1 F N +F0 "X" 0 -50 60 H V C CNN +F1 "ICL7611" 0 -350 60 H V C CNN +F2 "" 0 -50 60 H I C CNN +F3 "" 0 -50 60 H I C CNN +DRAW +S -300 100 -300 100 0 1 0 N +S -250 250 250 -300 0 1 0 N +S 250 -250 250 -250 0 1 0 N +X BAL 1 -450 200 200 R 50 50 1 1 I +X -IN 2 -450 50 200 R 50 50 1 1 I +X +IN 3 -450 -100 200 R 50 50 1 1 I +X V- 4 -450 -250 200 R 50 50 1 1 I +X BAL 5 450 -250 200 L 50 50 1 1 I +X OUT 6 450 -100 200 L 50 50 1 1 O +X V+ 7 450 50 200 L 50 50 1 1 I +X Iq_SET 8 450 200 200 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# ICL8212 +# +DEF ICL8212 X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "ICL8212" 0 -350 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -450 450 500 -500 0 1 0 N +X HYST 2 -650 250 200 R 50 50 1 1 O +X THRES 3 -650 0 200 R 50 50 1 1 I +X OUT 4 -650 -200 200 R 50 50 1 1 O +X GND 5 700 -100 200 L 50 50 1 1 I +X V+ 8 700 150 200 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# IC_4002 +# +DEF IC_4002 X 0 40 Y Y 1 F N +F0 "X" 0 150 60 H V C CNN +F1 "IC_4002" 0 0 60 H V C CNN +F2 "" 50 -150 60 H V C CNN +F3 "" 50 -150 60 H V C CNN +DRAW +S -250 350 250 -400 0 1 0 N +X 1Y 1 -450 250 200 R 50 50 1 1 O +X 1A 2 -450 150 200 R 50 50 1 1 I +X 1B 3 -450 50 200 R 50 50 1 1 I +X 1C 4 -450 -50 200 R 50 50 1 1 I +X 1D 5 -450 -150 200 R 50 50 1 1 I +X NC 6 -450 -250 200 R 50 50 1 1 I +X GND 7 -450 -350 200 R 50 50 1 1 I +X NC 8 450 -350 200 L 50 50 1 1 I +X 2A 9 450 -250 200 L 50 50 1 1 I +X 2B 10 450 -150 200 L 50 50 1 1 I +X 2C 11 450 -50 200 L 50 50 1 1 I +X 2D 12 450 50 200 L 50 50 1 1 I +X 2Y 13 450 150 200 L 50 50 1 1 O +X VCC 14 450 250 200 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# IC_4012 +# +DEF IC_4012 X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "IC_4012" 0 200 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -300 400 350 -400 0 1 0 N +X Q1 1 -500 300 200 R 50 50 1 1 O +X A1 2 -500 200 200 R 50 50 1 1 I +X B1 3 -500 100 200 R 50 50 1 1 I +X C1 4 -500 0 200 R 50 50 1 1 I +X D1 5 -500 -100 200 R 50 50 1 1 I +X NC 6 -500 -200 200 R 50 50 1 1 N +X VSS 7 -500 -300 200 R 50 50 1 1 I +X NC 8 550 -300 200 L 50 50 1 1 N +X A2 9 550 -200 200 L 50 50 1 1 I +X B2 10 550 -100 200 L 50 50 1 1 I +X C2 11 550 0 200 L 50 50 1 1 I +X D2 12 550 100 200 L 50 50 1 1 I +X Q2 13 550 200 200 L 50 50 1 1 O +X VDD 14 550 300 200 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# IC_4017 +# +DEF IC_4017 X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "IC_4017" 0 0 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -350 850 400 -850 0 1 0 N +X 1 1 600 650 200 L 50 50 1 1 O +X 2 2 600 500 200 L 50 50 1 1 O +X 3 3 600 350 200 L 50 50 1 1 O +X 4 4 600 200 200 L 50 50 1 1 O +X 5 5 600 50 200 L 50 50 1 1 O +X 6 6 600 -100 200 L 50 50 1 1 O +X 7 7 600 -250 200 L 50 50 1 1 O +X 8 8 600 -400 200 L 50 50 1 1 O +X 9 9 600 -600 200 L 50 50 1 1 O +X 10 10 600 -750 200 L 50 50 1 1 O +X RST 11 -550 -400 200 R 50 50 1 1 I +X CLK 12 -550 350 200 R 50 50 1 1 I +ENDDRAW +ENDDEF +# +# IC_4023 +# +DEF IC_4023 X 0 40 Y Y 1 F N +F0 "X" 0 -100 60 H V C CNN +F1 "IC_4023" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -300 450 300 -450 0 1 0 N +X A1 1 -500 300 200 R 50 50 1 1 I +X B1 2 -500 200 200 R 50 50 1 1 I +X A2 3 -500 100 200 R 50 50 1 1 I +X B2 4 -500 0 200 R 50 50 1 1 I +X C2 5 -500 -100 200 R 50 50 1 1 I +X Q2 6 -500 -200 200 R 50 50 1 1 O +X Vss 7 -500 -300 200 R 50 50 1 1 I +X C1 8 500 -300 200 L 50 50 1 1 I +X Q1 9 500 -200 200 L 50 50 1 1 O +X Q3 10 500 -100 200 L 50 50 1 1 O +X C3 11 500 0 200 L 50 50 1 1 I +X B3 12 500 100 200 L 50 50 1 1 I +X A3 13 500 200 200 L 50 50 1 1 I +X Vdd 14 500 300 200 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# IC_4028 +# +DEF IC_4028 X 0 40 Y Y 1 F N +F0 "X" 0 -100 60 H V C CNN +F1 "IC_4028" 0 50 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -300 450 300 -450 0 1 0 N +X Q4 1 -500 350 200 R 50 50 1 1 O +X Q2 2 -500 250 200 R 50 50 1 1 O +X Q0 3 -500 150 200 R 50 50 1 1 O +X Q7 4 -500 50 200 R 50 50 1 1 O +X Q9 5 -500 -50 200 R 50 50 1 1 O +X Q5 6 -500 -150 200 R 50 50 1 1 O +X Q6 7 -500 -250 200 R 50 50 1 1 O +X Vss 8 -500 -350 200 R 50 50 1 1 I +X Q8 9 500 -350 200 L 50 50 1 1 O +X A0 10 500 -250 200 L 50 50 1 1 I +X A3 11 500 -150 200 L 50 50 1 1 I +X A2 12 500 -50 200 L 50 50 1 1 I +X A1 13 500 50 200 L 50 50 1 1 I +X Q1 14 500 150 200 L 50 50 1 1 O +X Q3 15 500 250 200 L 50 50 1 1 O +X Vdd 16 500 350 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# IC_4073 +# +DEF IC_4073 X 0 40 Y Y 1 F N +F0 "X" 0 -100 60 H V C CNN +F1 "IC_4073" 0 50 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -300 400 300 -400 0 1 0 N +X A1 1 -500 300 200 R 50 50 1 1 I +X B1 2 -500 200 200 R 50 50 1 1 I +X A2 3 -500 100 200 R 50 50 1 1 I +X B2 4 -500 0 200 R 50 50 1 1 I +X C2 5 -500 -100 200 R 50 50 1 1 I +X Q2 6 -500 -200 200 R 50 50 1 1 O +X Vss 7 -500 -300 200 R 50 50 1 1 I +X C1 8 500 -300 200 L 50 50 1 1 I +X Q1 9 500 -200 200 L 50 50 1 1 O +X Q3 10 500 -100 200 L 50 50 1 1 O +X A3 11 500 0 200 L 50 50 1 1 I +X B3 12 500 100 200 L 50 50 1 1 I +X C3 13 500 200 200 L 50 50 1 1 I +X Vdd 14 500 300 200 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# IC_74153 +# +DEF IC_74153 X 0 40 Y Y 1 F N +F0 "X" 100 50 60 H V C CNN +F1 "IC_74153" 100 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +T 0 100 -200 60 0 0 0 4:1 Normal 0 C C +T 0 100 -100 60 0 0 0 DUAL Normal 0 C C +T 0 100 -300 60 0 0 0 MUX Normal 0 C C +S -200 500 350 -550 0 1 0 N +X a0 1 -400 350 200 R 50 50 1 1 I +X a1 2 -400 250 200 R 50 50 1 1 I +X a2 3 -400 150 200 R 50 50 1 1 I +X a3 4 -400 50 200 R 50 50 1 1 I +X EA 5 0 700 200 D 50 50 1 1 I I +X b0 6 -400 -150 200 R 50 50 1 1 I +X b1 7 -400 -250 200 R 50 50 1 1 I +X b2 8 -400 -350 200 R 50 50 1 1 I +X b3 9 -400 -450 200 R 50 50 1 1 I +X EB 10 200 700 200 D 50 50 1 1 I I +X s1 11 50 -750 200 U 50 50 1 1 I +X s0 12 150 -750 200 U 50 50 1 1 I +X ya 13 550 250 200 L 50 50 1 1 O +X yb 14 550 -300 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# IC_74154 +# +DEF IC_74154 X 0 40 Y Y 1 F N +F0 "X" 0 -200 60 H V C CNN +F1 "IC_74154" 50 -50 60 H V C CNN +F2 "" 0 50 60 H V C CNN +F3 "" 0 50 60 H V C CNN +DRAW +T 0 0 400 60 0 0 0 4:16~ Normal 0 C C +T 0 0 250 60 0 0 0 decoder Normal 0 C C +S -350 700 400 -700 0 0 0 N +X ~Y0 1 -550 550 200 R 50 50 1 1 O I +X ~Y1 2 -550 450 200 R 50 50 1 1 O I +X ~Y2 3 -550 350 200 R 50 50 1 1 O I +X ~Y3 4 -550 250 200 R 50 50 1 1 O I +X ~Y4 5 -550 150 200 R 50 50 1 1 O I +X ~Y5 6 -550 50 200 R 50 50 1 1 O I +X ~Y6 7 -550 -50 200 R 50 50 1 1 O I +X ~Y7 8 -550 -150 200 R 50 50 1 1 O I +X ~Y8 9 -550 -250 200 R 50 50 1 1 O I +X ~Y9 10 -550 -350 200 R 50 50 1 1 O I +X A3 20 600 150 200 L 50 50 1 1 I +X ~Y10 11 -550 -450 200 R 50 50 1 1 O I +X A2 21 600 250 200 L 50 50 1 1 I +X GND 12 -550 -550 200 R 50 50 1 1 I +X A1 22 600 350 200 L 50 50 1 1 I +X ~Y11 13 600 -550 200 L 50 50 1 1 O I +X A0 23 600 450 200 L 50 50 1 1 I +X ~Y12 14 600 -450 200 L 50 50 1 1 O I +X Vcc 24 600 550 200 L 50 50 1 1 I +X ~Y13 15 600 -350 200 L 50 50 1 1 O I +X ~Y14 16 600 -250 200 L 50 50 1 1 O I +X ~Y15 17 600 -150 200 L 50 50 1 1 O I +X ~E0 18 600 -50 200 L 50 50 1 1 I I +X ~E1 19 600 50 200 L 50 50 1 1 I I +ENDDRAW +ENDDEF +# +# IC_74157 +# +DEF IC_74157 X 0 40 Y Y 1 F N +F0 "X" 50 -50 60 H V C CNN +F1 "IC_74157" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +T 0 50 -300 60 0 0 0 2:1 Normal 0 C C +T 0 50 -400 60 0 0 0 MUX Normal 0 C C +T 0 50 -200 60 0 0 0 QUAD Normal 0 C C +S -350 550 400 -650 0 1 0 N +X a0 1 -550 450 200 R 50 50 1 1 I +X a1 2 -550 300 200 R 50 50 1 1 I +X b0 3 -550 200 200 R 50 50 1 1 I +X b1 4 -550 100 200 R 50 50 1 1 I +X c0 5 -550 0 200 R 50 50 1 1 I +X c1 6 -550 -100 200 R 50 50 1 1 I +X d0 7 -550 -200 200 R 50 50 1 1 I +X d1 8 -550 -300 200 R 50 50 1 1 I +X EN 9 -550 -550 200 R 50 50 1 1 I I +X S 10 -550 -450 200 R 50 50 1 1 I +X Yd 11 600 0 200 L 50 50 1 1 O +X Ya 12 600 300 200 L 50 50 1 1 O +X Yb 13 600 200 200 L 50 50 1 1 O +X Yc 14 600 100 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# IC_7485 +# +DEF IC_7485 X 0 40 Y Y 1 F N +F0 "X" -50 -100 60 H V C CNN +F1 "IC_7485" -50 50 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +T 0 0 550 60 0 0 0 4~BIT~comparator Normal 0 C C +S -350 450 400 -400 0 1 0 N +X AB(in) 3 600 -300 200 L 50 50 1 1 I +X A3 4 -550 100 200 R 50 50 1 1 I +X B3 5 -550 -350 200 R 50 50 1 1 I +X A2 6 -550 200 200 R 50 50 1 1 I +X B2 7 -550 -250 200 R 50 50 1 1 I +X A1 8 -550 300 200 R 50 50 1 1 I +X B1 9 -550 -150 200 R 50 50 1 1 I +X A0 10 -550 400 200 R 50 50 1 1 I +X B0 11 -550 -50 200 R 50 50 1 1 I +X A>B(out) 12 600 350 200 L 50 50 1 1 O +X A=B(out) 13 600 250 200 L 50 50 1 1 O +X A