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Cortex-A78 r0p0 has atomic errata that needs runtime workaround #1000

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Sonicadvance1 opened this issue May 1, 2021 · 0 comments
Open

Cortex-A78 r0p0 has atomic errata that needs runtime workaround #1000

Sonicadvance1 opened this issue May 1, 2021 · 0 comments
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2212

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@Sonicadvance1
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Sonicadvance1 commented May 1, 2021 •
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Needs a DMB ST in front of every atomic load acquire instruction that doesn't have release semantics.
r1p0 and r1p1 doesn't need this as TZ will workaround it for us.

Need to check SoCs and upcoming SoCs to see if any manage to ship r0p0
@skmp skmp added this to the 2212 milestone Aug 10, 2022
@skmp skmp moved this to 🆕 Unplanned in Next Project Milestone Aug 18, 2022
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