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Author: ECEDong

Diff for: asy_FIFO.v

@@ -0,0 +1,141 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2023/06/28 08:05:32
+// Design Name: 
+// Module Name: asy_FIFO
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module asy_FIFO(
+    wr_clk,
+    rd_clk,
+    wr_rstn,
+    rd_rstn,
+    wr_en,
+    rd_en,
+    wr_data,
+    rd_data,
+    fifo_empty,
+    fifo_full
+    );
+    parameter width = 8;
+    parameter depth = 8;
+    parameter addr = $clog2(depth);
+    
+    input wr_clk,rd_clk,wr_rstn,rd_rstn,wr_en,rd_en;
+    input [width-1:0] wr_data;
+    output reg [width-1:0] rd_data;
+    output reg fifo_empty,fifo_full;
+
+    //Define a FIFO, width/depth
+    reg [width-1:0] fifo [depth-1:0];//depth-1
+
+    // binary pointer
+    reg [addr:0] wr_pt;
+    reg [addr:0] rd_pt;
+
+    // gray code pointer
+    wire [addr:0] wr_ptg;
+    wire [addr:0] rd_ptg;
+    // synchronizer: 2 flip flop
+    reg [addr:0] wr_ptgr;//after one ff
+    reg [addr:0] rd_ptgr;
+    reg [addr:0] wr_ptgrr;//after two ff
+    reg [addr:0] rd_ptgrr;
+
+    //binary to gray
+    assign wr_ptg=wr_pt^(wr_pt>>>1);//why >>> but not >>?
+    assign rd_ptg=rd_pt^(rd_pt>>>1);
+
+    //sychronize by two flip flop
+    always@(posedge wr_clk, negedge wr_rstn)begin
+        if(!wr_rstn)begin
+            wr_ptgr<=0; wr_ptgrr<=0;
+        end
+        else begin
+            wr_ptgr<=wr_ptg;  // one ff
+            wr_ptgrr<=wr_ptgr;// two ff
+        end
+    end
+    
+    always@(posedge rd_clk, negedge rd_rstn)begin
+        if(!rd_rstn)begin
+            rd_ptgr<=0; rd_ptgrr<=0;
+        end
+        else begin
+            rd_ptgr<=rd_ptg;  // one ff
+            rd_ptgrr<=rd_ptgr;// two ff
+        end
+    end
+
+    //determine full or empty
+    always@(posedge wr_clk, negedge wr_rstn)begin
+        if(!wr_rstn)begin
+            fifo_full<=0;
+        end
+        else if(wr_ptg[addr]==rd_ptgrr[addr]&&wr_ptg[addr-1]!=rd_ptgrr[addr-1]//
+        &&wr_ptg[addr-2]!=rd_ptgrr[addr-2]&&wr_ptg[addr-3]==rd_ptgrr[addr-3]) begin//need change if length/addr change
+            fifo_full<=1;
+        end
+        else begin
+            fifo_full<=0;
+        end
+    end
+
+    always@(posedge rd_clk, negedge rd_rstn)begin
+        if(!rd_rstn)begin
+            fifo_empty<=0;
+        end
+        else if(rd_pt==wr_ptgrr) begin//rd_pt==wr_ptgrr和rd_pt[addr-1:0]==wr_ptgrr[addr-1:0]有什么区�?//need change if length/addr change
+            fifo_empty<=1;
+        end
+        else begin
+            fifo_empty<=0;
+        end
+    end
+
+    //write data
+    always@(posedge wr_clk, negedge wr_rstn)begin
+        if(!wr_rstn) begin
+            wr_pt<=0;
+        end
+        else if(!fifo_full&&wr_en)begin
+            fifo[wr_pt]<=wr_data;
+            wr_pt<=wr_pt+1;
+        end
+        else begin
+            wr_pt<=wr_pt;
+        end
+    end
+
+    //read data
+    always@(posedge rd_clk, negedge rd_rstn)begin
+        if(!rd_rstn) begin
+            rd_pt<=0;
+        end
+        else if(!fifo_empty&&rd_en)begin
+            fifo[rd_pt]<=rd_data;
+            rd_pt<=rd_pt+1;
+        end
+        else begin
+            rd_pt<=rd_pt;
+        end
+    end
+
+
+
+endmodule

Diff for: synchronous_FIFO.v

@@ -0,0 +1,116 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2023/06/27 21:31:44
+// Design Name: 
+// Module Name: synchronous_FIFO
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+// use a counter to determine whether the FIFO is full or empty
+
+module syn_fifo(clk, rstn, wr_en, rd_en, wr_data, rd_data, fifo_full, fifo_empty);
+
+    //参数定义
+    parameter   width = 8;
+    parameter   depth = 8;
+    parameter   addr  = 3;
+
+    //输入信号
+    input   clk;    //时钟信号
+    input   rstn;   //下降沿复位
+    input   wr_en;  //写入使能
+    input   rd_en;  //读取使能
+
+    //数据信号
+    input   [width - 1 : 0] wr_data;    //写数据
+    output  [width - 1 : 0] rd_data;    //读数据
+
+    reg [width - 1 : 0] rd_data;
+
+    //空满判断信号
+    output  fifo_full;
+    output  fifo_empty;
+
+    //定义一个计数器，用于判断空满
+    reg [$clog2(depth): 0] cnt;
+
+    //定义读写地址
+    reg [depth - 1 : 0] wr_ptr;
+    reg [depth - 1 : 0] rd_ptr;
+
+    //定义一个宽度为为width，深度为depth的fifo
+    reg [width - 1 : 0] fifo [depth - 1 : 0];
+    
+
+    //写地址操作
+    always @ (posedge clk or negedge rstn) begin
+        if(!rstn)
+            wr_ptr <= 0;
+        else if(wr_en && !fifo_full)    //写使能，且fifo未写满
+            wr_ptr <= wr_ptr + 1;
+        else
+            wr_ptr <= wr_ptr;
+    end
+   
+    //读地址操作
+    always @ (posedge clk or negedge rstn) begin
+        if(!rstn)
+            rd_ptr <= 0;
+        else if(rd_en && !fifo_empty)   //读使能，且fifo不为空
+            rd_ptr <= rd_ptr + 1;
+        else
+            rd_ptr <= rd_ptr;
+    end
+
+    //写数据
+    integer i;
+
+    always @ (posedge clk or negedge rstn) begin
+        if(!rstn) begin //复位清空fifo
+            for(i = 0; i < depth; i = i + 1)
+                fifo[i] <= 0;
+        end
+        else if(wr_en)  //写使能时将数据写入fifo
+            fifo[wr_ptr] <= wr_data;
+        else    //否则保持
+            fifo[wr_ptr] <= fifo[wr_ptr];
+    end
+
+    //读数据
+    always @ (posedge clk or negedge rstn) begin
+        if(!rstn)
+            rd_data <= 0;
+        else if (rd_en)
+            rd_data <= fifo[rd_ptr];    //从fifo中读取数据
+        else
+            rd_data <= rd_data;
+    end
+
+    //辅助计数，用于判断空满
+    always @ (posedge clk or negedge rstn) begin
+        if(!rstn)
+            cnt <= 0;
+        else if (wr_en && !rd_en && !fifo_full) //有效的只写入
+            cnt <= cnt + 1;
+        else if (!wr_en && rd_en && !fifo_empty) //有效的只读取
+            cnt <= cnt - 1;
+        else 
+            cnt <= cnt;
+    end
+
+    //空满判断
+    assign fifo_full = (cnt == depth)? 1 : 0;
+    assign fifo_empty = (cnt == 0) ? 1 : 0;
+endmodule