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Datadog Syncup Service
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Merge branch 'upstream-master'
2 parents 78abca0 + 456c71d commit 0837b95

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Diff for: ‎make/ModuleWrapper.gmk

+1-1
Original file line numberDiff line numberDiff line change
@@ -51,7 +51,7 @@ ifeq ($(MAKEFILE_PREFIX), Lib)
5151
# which static library files to include. The variable $(MODULE)_INCLUDED_LIBS is
5252
# added to for each call to SetupJdkLibrary. The file module-included-libs.txt is then
5353
# read in StaticLibs.gmk.
54-
ifneq ($($(MODULE)_JDK_LIBS), )
54+
ifneq ($($(MODULE)_INCLUDED_LIBS), )
5555
LIBLIST := $(SUPPORT_OUTPUTDIR)/modules_static-libs/$(MODULE)/module-included-libs.txt
5656

5757
$(LIBLIST): $(TARGETS)

Diff for: ‎make/autoconf/util.m4

+1-1
Original file line numberDiff line numberDiff line change
@@ -575,7 +575,7 @@ AC_DEFUN([UTIL_CHECK_TYPE_directory],
575575
576576
if test "[x]ARG_CHECK_FOR_FILES" != "x:"; then
577577
for file in ARG_CHECK_FOR_FILES; do
578-
found_files=$($ECHO $(ls $1/$file 2> /dev/null))
578+
found_files=$($ECHO $($LS -d $1/$file 2> /dev/null))
579579
if test "x$found_files" = x; then
580580
FAILURE="Directory $1 does not contain $file"
581581
break

Diff for: ‎make/test/BuildMicrobenchmark.gmk

+1
Original file line numberDiff line numberDiff line change
@@ -89,6 +89,7 @@ $(eval $(call SetupJavaCompilation, BUILD_JDK_MICROBENCHMARK, \
8989
SRC := $(MICROBENCHMARK_SRC), \
9090
BIN := $(MICROBENCHMARK_CLASSES), \
9191
JAVAC_FLAGS := \
92+
--add-exports java.base/jdk.internal.classfile.components=ALL-UNNAMED \
9293
--add-exports java.base/jdk.internal.classfile.impl=ALL-UNNAMED \
9394
--add-exports java.base/jdk.internal.event=ALL-UNNAMED \
9495
--add-exports java.base/jdk.internal.foreign=ALL-UNNAMED \

Diff for: ‎src/hotspot/cpu/aarch64/c2_MacroAssembler_aarch64.cpp

+4-4
Original file line numberDiff line numberDiff line change
@@ -206,8 +206,8 @@ void C2_MacroAssembler::fast_lock(Register objectReg, Register boxReg, Register
206206
// Handle existing monitor.
207207
bind(object_has_monitor);
208208

209-
// Try to CAS owner (no owner => current thread's _lock_id).
210-
ldr(rscratch2, Address(rthread, JavaThread::lock_id_offset()));
209+
// Try to CAS owner (no owner => current thread's _monitor_owner_id).
210+
ldr(rscratch2, Address(rthread, JavaThread::monitor_owner_id_offset()));
211211
add(tmp, disp_hdr, (in_bytes(ObjectMonitor::owner_offset())-markWord::monitor_value));
212212
cmpxchg(tmp, zr, rscratch2, Assembler::xword, /*acquire*/ true,
213213
/*release*/ true, /*weak*/ false, tmp3Reg); // Sets flags for result
@@ -469,8 +469,8 @@ void C2_MacroAssembler::fast_lock_lightweight(Register obj, Register box, Regist
469469
// Compute owner address.
470470
lea(t2_owner_addr, owner_address);
471471

472-
// Try to CAS owner (no owner => current thread's _lock_id).
473-
ldr(rscratch2, Address(rthread, JavaThread::lock_id_offset()));
472+
// Try to CAS owner (no owner => current thread's _monitor_owner_id).
473+
ldr(rscratch2, Address(rthread, JavaThread::monitor_owner_id_offset()));
474474
cmpxchg(t2_owner_addr, zr, rscratch2, Assembler::xword, /*acquire*/ true,
475475
/*release*/ false, /*weak*/ false, t3_owner);
476476
br(Assembler::EQ, monitor_locked);

Diff for: ‎src/hotspot/cpu/aarch64/macroAssembler_aarch64.cpp

+1-1
Original file line numberDiff line numberDiff line change
@@ -5305,7 +5305,7 @@ MacroAssembler::KlassDecodeMode MacroAssembler::klass_decode_mode() {
53055305
if (operand_valid_for_logical_immediate(
53065306
/*is32*/false, (uint64_t)CompressedKlassPointers::base())) {
53075307
const size_t range = CompressedKlassPointers::klass_range_end() - CompressedKlassPointers::base();
5308-
const uint64_t range_mask = (1ULL << log2i(range)) - 1;
5308+
const uint64_t range_mask = right_n_bits(ceil_log2(range));
53095309
if (((uint64_t)CompressedKlassPointers::base() & range_mask) == 0) {
53105310
return (_klass_decode_mode = KlassDecodeXor);
53115311
}

Diff for: ‎src/hotspot/cpu/ppc/assembler_ppc.hpp

+21
Original file line numberDiff line numberDiff line change
@@ -506,13 +506,18 @@ class Assembler : public AbstractAssembler {
506506
LFSU_OPCODE = (49u << OPCODE_SHIFT | 00u << 1),
507507
LFSX_OPCODE = (31u << OPCODE_SHIFT | 535u << 1),
508508

509+
LFIWAX_OPCODE = (31u << OPCODE_SHIFT | 855u << 1),
510+
LFIWZX_OPCODE = (31u << OPCODE_SHIFT | 887u << 1),
511+
509512
STFD_OPCODE = (54u << OPCODE_SHIFT | 00u << 1),
510513
STFDU_OPCODE = (55u << OPCODE_SHIFT | 00u << 1),
511514
STFDX_OPCODE = (31u << OPCODE_SHIFT | 727u << 1),
512515
STFS_OPCODE = (52u << OPCODE_SHIFT | 00u << 1),
513516
STFSU_OPCODE = (53u << OPCODE_SHIFT | 00u << 1),
514517
STFSX_OPCODE = (31u << OPCODE_SHIFT | 663u << 1),
515518

519+
STFIWX_OPCODE = (31u << OPCODE_SHIFT | 983u << 1),
520+
516521
FSQRT_OPCODE = (63u << OPCODE_SHIFT | 22u << 1), // A-FORM
517522
FSQRTS_OPCODE = (59u << OPCODE_SHIFT | 22u << 1), // A-FORM
518523

@@ -555,6 +560,10 @@ class Assembler : public AbstractAssembler {
555560
XVDIVSP_OPCODE = (60u << OPCODE_SHIFT | 88u << 3),
556561
XXBRD_OPCODE = (60u << OPCODE_SHIFT | 475u << 2 | 23u << 16), // XX2-FORM
557562
XXBRW_OPCODE = (60u << OPCODE_SHIFT | 475u << 2 | 15u << 16), // XX2-FORM
563+
XVCVHPSP_OPCODE= (60u << OPCODE_SHIFT | 475u << 2 | 24u << 16), // XX2-FORM
564+
XVCVSPHP_OPCODE= (60u << OPCODE_SHIFT | 475u << 2 | 25u << 16), // XX2-FORM
565+
XSCVHPDP_OPCODE= (60u << OPCODE_SHIFT | 347u << 2 | 16u << 16), // XX2-FORM
566+
XSCVDPHP_OPCODE= (60u << OPCODE_SHIFT | 347u << 2 | 17u << 16), // XX2-FORM
558567
XXPERM_OPCODE = (60u << OPCODE_SHIFT | 26u << 3),
559568
XXSEL_OPCODE = (60u << OPCODE_SHIFT | 3u << 4),
560569
XXSPLTIB_OPCODE= (60u << OPCODE_SHIFT | 360u << 1),
@@ -2076,6 +2085,9 @@ class Assembler : public AbstractAssembler {
20762085
inline void lfdu( FloatRegister d, int si16, Register a);
20772086
inline void lfdx( FloatRegister d, Register a, Register b);
20782087

2088+
inline void lfiwax(FloatRegister d, Register a, Register b);
2089+
inline void lfiwzx(FloatRegister d, Register a, Register b);
2090+
20792091
// PPC 1, section 4.6.3 Floating-Point Store Instructions
20802092
inline void stfs( FloatRegister s, int si16, Register a);
20812093
inline void stfsu( FloatRegister s, int si16, Register a);
@@ -2084,6 +2096,8 @@ class Assembler : public AbstractAssembler {
20842096
inline void stfdu( FloatRegister s, int si16, Register a);
20852097
inline void stfdx( FloatRegister s, Register a, Register b);
20862098

2099+
inline void stfiwx(FloatRegister s, Register a, Register b);
2100+
20872101
// PPC 1, section 4.6.4 Floating-Point Move Instructions
20882102
inline void fmr( FloatRegister d, FloatRegister b);
20892103
inline void fmr_( FloatRegister d, FloatRegister b);
@@ -2348,6 +2362,10 @@ class Assembler : public AbstractAssembler {
23482362
inline void xxleqv( VectorSRegister d, VectorSRegister a, VectorSRegister b);
23492363
inline void xxbrd( VectorSRegister d, VectorSRegister b);
23502364
inline void xxbrw( VectorSRegister d, VectorSRegister b);
2365+
inline void xvcvhpsp( VectorSRegister d, VectorSRegister b);
2366+
inline void xvcvsphp( VectorSRegister d, VectorSRegister b);
2367+
inline void xscvhpdp( VectorSRegister d, VectorSRegister b);
2368+
inline void xscvdphp( VectorSRegister d, VectorSRegister b);
23512369
inline void xxland( VectorSRegister d, VectorSRegister a, VectorSRegister b);
23522370
inline void xxsel( VectorSRegister d, VectorSRegister a, VectorSRegister b, VectorSRegister c);
23532371
inline void xxspltib( VectorSRegister d, int ui8);
@@ -2474,10 +2492,13 @@ class Assembler : public AbstractAssembler {
24742492
inline void lfsx( FloatRegister d, Register b);
24752493
inline void lfd( FloatRegister d, int si16);
24762494
inline void lfdx( FloatRegister d, Register b);
2495+
inline void lfiwax(FloatRegister d, Register b);
2496+
inline void lfiwzx(FloatRegister d, Register b);
24772497
inline void stfs( FloatRegister s, int si16);
24782498
inline void stfsx( FloatRegister s, Register b);
24792499
inline void stfd( FloatRegister s, int si16);
24802500
inline void stfdx( FloatRegister s, Register b);
2501+
inline void stfiwx(FloatRegister s, Register b);
24812502
inline void lvebx( VectorRegister d, Register s2);
24822503
inline void lvehx( VectorRegister d, Register s2);
24832504
inline void lvewx( VectorRegister d, Register s2);

Diff for: ‎src/hotspot/cpu/ppc/assembler_ppc.inline.hpp

+14
Original file line numberDiff line numberDiff line change
@@ -741,6 +741,9 @@ inline void Assembler::lfd( FloatRegister d, int si16, Register a) { emit_int3
741741
inline void Assembler::lfdu(FloatRegister d, int si16, Register a) { emit_int32( LFDU_OPCODE | frt(d) | ra(a) | simm(si16,16)); }
742742
inline void Assembler::lfdx(FloatRegister d, Register a, Register b) { emit_int32( LFDX_OPCODE | frt(d) | ra0mem(a) | rb(b)); }
743743

744+
inline void Assembler::lfiwax(FloatRegister d, Register a, Register b) { emit_int32( LFIWAX_OPCODE | frt(d) | ra0mem(a) |rb(b)); }
745+
inline void Assembler::lfiwzx(FloatRegister d, Register a, Register b) { emit_int32( LFIWZX_OPCODE | frt(d) | ra0mem(a) |rb(b)); }
746+
744747
// PPC 1, section 4.6.3 Floating-Point Store Instructions
745748
// Use ra0mem instead of ra in some instructions below.
746749
inline void Assembler::stfs( FloatRegister s, int si16, Register a) { emit_int32( STFS_OPCODE | frs(s) | ra0mem(a) | simm(si16,16)); }
@@ -750,6 +753,8 @@ inline void Assembler::stfd( FloatRegister s, int si16, Register a) { emit_int3
750753
inline void Assembler::stfdu(FloatRegister s, int si16, Register a) { emit_int32( STFDU_OPCODE | frs(s) | ra(a) | simm(si16,16)); }
751754
inline void Assembler::stfdx(FloatRegister s, Register a, Register b){ emit_int32( STFDX_OPCODE | frs(s) | ra0mem(a) | rb(b)); }
752755

756+
inline void Assembler::stfiwx(FloatRegister s, Register a, Register b) { emit_int32( STFIWX_OPCODE | frs(s) | ra0mem(a) |rb(b)); }
757+
753758
// PPC 1, section 4.6.4 Floating-Point Move Instructions
754759
inline void Assembler::fmr( FloatRegister d, FloatRegister b) { emit_int32( FMR_OPCODE | frt(d) | frb(b) | rc(0)); }
755760
inline void Assembler::fmr_(FloatRegister d, FloatRegister b) { emit_int32( FMR_OPCODE | frt(d) | frb(b) | rc(1)); }
@@ -871,6 +876,10 @@ inline void Assembler::xxlxor( VectorSRegister d, VectorSRegister a, VectorSReg
871876
inline void Assembler::xxleqv( VectorSRegister d, VectorSRegister a, VectorSRegister b) { emit_int32( XXLEQV_OPCODE | vsrt(d) | vsra(a) | vsrb(b)); }
872877
inline void Assembler::xxbrd( VectorSRegister d, VectorSRegister b) { emit_int32( XXBRD_OPCODE | vsrt(d) | vsrb(b) ); }
873878
inline void Assembler::xxbrw( VectorSRegister d, VectorSRegister b) { emit_int32( XXBRW_OPCODE | vsrt(d) | vsrb(b) ); }
879+
inline void Assembler::xvcvhpsp(VectorSRegister d, VectorSRegister b) { emit_int32( XVCVHPSP_OPCODE | vsrt(d) | vsrb(b) ); }
880+
inline void Assembler::xvcvsphp(VectorSRegister d, VectorSRegister b) { emit_int32( XVCVSPHP_OPCODE | vsrt(d) | vsrb(b) ); }
881+
inline void Assembler::xscvhpdp(VectorSRegister d, VectorSRegister b) { emit_int32( XSCVHPDP_OPCODE | vsrt(d) | vsrb(b) ); }
882+
inline void Assembler::xscvdphp(VectorSRegister d, VectorSRegister b) { emit_int32( XSCVDPHP_OPCODE | vsrt(d) | vsrb(b) ); }
874883
inline void Assembler::xvdivsp( VectorSRegister d, VectorSRegister a, VectorSRegister b) { emit_int32( XVDIVSP_OPCODE | vsrt(d) | vsra(a) | vsrb(b)); }
875884
inline void Assembler::xvdivdp( VectorSRegister d, VectorSRegister a, VectorSRegister b) { emit_int32( XVDIVDP_OPCODE | vsrt(d) | vsra(a) | vsrb(b)); }
876885
inline void Assembler::xvabssp( VectorSRegister d, VectorSRegister b) { emit_int32( XVABSSP_OPCODE | vsrt(d) | vsrb(b)); }
@@ -1150,12 +1159,17 @@ inline void Assembler::lfsx(FloatRegister d, Register b) { emit_int32( LFSX_OPCO
11501159
inline void Assembler::lfd( FloatRegister d, int si16) { emit_int32( LFD_OPCODE | frt(d) | simm(si16,16)); }
11511160
inline void Assembler::lfdx(FloatRegister d, Register b) { emit_int32( LFDX_OPCODE | frt(d) | rb(b)); }
11521161

1162+
inline void Assembler::lfiwax(FloatRegister d, Register b) { emit_int32( LFIWAX_OPCODE | frt(d) | rb(b)); }
1163+
inline void Assembler::lfiwzx(FloatRegister d, Register b) { emit_int32( LFIWZX_OPCODE | frt(d) | rb(b)); }
1164+
11531165
// ra0 version
11541166
inline void Assembler::stfs( FloatRegister s, int si16) { emit_int32( STFS_OPCODE | frs(s) | simm(si16, 16)); }
11551167
inline void Assembler::stfsx(FloatRegister s, Register b) { emit_int32( STFSX_OPCODE | frs(s) | rb(b)); }
11561168
inline void Assembler::stfd( FloatRegister s, int si16) { emit_int32( STFD_OPCODE | frs(s) | simm(si16, 16)); }
11571169
inline void Assembler::stfdx(FloatRegister s, Register b) { emit_int32( STFDX_OPCODE | frs(s) | rb(b)); }
11581170

1171+
inline void Assembler::stfiwx(FloatRegister s, Register b) { emit_int32( STFIWX_OPCODE | frs(s) |rb(b)); }
1172+
11591173
// ra0 version
11601174
inline void Assembler::lvebx( VectorRegister d, Register s2) { emit_int32( LVEBX_OPCODE | vrt(d) | rb(s2)); }
11611175
inline void Assembler::lvehx( VectorRegister d, Register s2) { emit_int32( LVEHX_OPCODE | vrt(d) | rb(s2)); }

Diff for: ‎src/hotspot/cpu/ppc/c1_LIRAssembler_ppc.cpp

+9-1
Original file line numberDiff line numberDiff line change
@@ -1713,7 +1713,7 @@ void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr
17131713
}
17141714

17151715

1716-
void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr thread, LIR_Opr dest, LIR_Op* op) {
1716+
void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr tmp, LIR_Opr dest, LIR_Op* op) {
17171717
switch (code) {
17181718
case lir_sqrt: {
17191719
__ fsqrt(dest->as_double_reg(), value->as_double_reg());
@@ -1723,6 +1723,14 @@ void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr thread, L
17231723
__ fabs(dest->as_double_reg(), value->as_double_reg());
17241724
break;
17251725
}
1726+
case lir_f2hf: {
1727+
__ f2hf(dest.as_register(), value.as_float_reg(), tmp.as_float_reg());
1728+
break;
1729+
}
1730+
case lir_hf2f: {
1731+
__ hf2f(dest->as_float_reg(), value.as_register());
1732+
break;
1733+
}
17261734
default: {
17271735
ShouldNotReachHere();
17281736
break;

Diff for: ‎src/hotspot/cpu/ppc/c1_LIRGenerator_ppc.cpp

+19
Original file line numberDiff line numberDiff line change
@@ -690,6 +690,25 @@ void LIRGenerator::do_MathIntrinsic(Intrinsic* x) {
690690
__ abs(value.result(), dst, LIR_OprFact::illegalOpr);
691691
break;
692692
}
693+
case vmIntrinsics::_floatToFloat16: {
694+
assert(x->number_of_arguments() == 1, "wrong type");
695+
LIRItem value(x->argument_at(0), this);
696+
value.load_item();
697+
LIR_Opr dst = rlock_result(x);
698+
LIR_Opr tmp = new_register(T_FLOAT);
699+
// f2hf treats tmp as live_in. Workaround: initialize to some value.
700+
__ move(LIR_OprFact::floatConst(-0.0), tmp); // just to satisfy LinearScan
701+
__ f2hf(value.result(), dst, tmp);
702+
break;
703+
}
704+
case vmIntrinsics::_float16ToFloat: {
705+
assert(x->number_of_arguments() == 1, "wrong type");
706+
LIRItem value(x->argument_at(0), this);
707+
value.load_item();
708+
LIR_Opr dst = rlock_result(x);
709+
__ hf2f(value.result(), dst, LIR_OprFact::illegalOpr);
710+
break;
711+
}
693712
case vmIntrinsics::_dsqrt:
694713
case vmIntrinsics::_dsqrt_strict: {
695714
if (VM_Version::has_fsqrt()) {

Diff for: ‎src/hotspot/cpu/ppc/macroAssembler_ppc.cpp

+4-4
Original file line numberDiff line numberDiff line change
@@ -2664,10 +2664,10 @@ void MacroAssembler::compiler_fast_lock_object(ConditionRegister flag, Register
26642664
// Handle existing monitor.
26652665
bind(object_has_monitor);
26662666

2667-
// Try to CAS owner (no owner => current thread's _lock_id).
2667+
// Try to CAS owner (no owner => current thread's _monitor_owner_id).
26682668
addi(temp, displaced_header, in_bytes(ObjectMonitor::owner_offset()) - markWord::monitor_value);
26692669
Register thread_id = displaced_header;
2670-
ld(thread_id, in_bytes(JavaThread::lock_id_offset()), R16_thread);
2670+
ld(thread_id, in_bytes(JavaThread::monitor_owner_id_offset()), R16_thread);
26712671
cmpxchgd(/*flag=*/flag,
26722672
/*current_value=*/current_header,
26732673
/*compare_value=*/(intptr_t)0,
@@ -2944,9 +2944,9 @@ void MacroAssembler::compiler_fast_lock_lightweight_object(ConditionRegister fla
29442944
addi(owner_addr, monitor, in_bytes(ObjectMonitor::owner_offset()));
29452945
}
29462946

2947-
// Try to CAS owner (no owner => current thread's _lock_id).
2947+
// Try to CAS owner (no owner => current thread's _monitor_owner_id).
29482948
assert_different_registers(thread_id, monitor, owner_addr, box, R0);
2949-
ld(thread_id, in_bytes(JavaThread::lock_id_offset()), R16_thread);
2949+
ld(thread_id, in_bytes(JavaThread::monitor_owner_id_offset()), R16_thread);
29502950
cmpxchgd(/*flag=*/CCR0,
29512951
/*current_value=*/R0,
29522952
/*compare_value=*/(intptr_t)0,

Diff for: ‎src/hotspot/cpu/ppc/macroAssembler_ppc.hpp

+3
Original file line numberDiff line numberDiff line change
@@ -186,6 +186,9 @@ class MacroAssembler: public Assembler {
186186
void inline set_cmpu3(Register dst, bool treat_unordered_like_less);
187187
// Branch-free implementation to convert !=0 to 1.
188188
void inline normalize_bool(Register dst, Register temp = R0, bool is_64bit = false);
189+
// Convert between half precision float encoded into a short and a float in a FloatRegister.
190+
void inline f2hf(Register dst, FloatRegister src, FloatRegister tmp);
191+
void inline hf2f(FloatRegister dst, Register src);
189192

190193
inline void pd_patch_instruction(address branch, address target, const char* file, int line);
191194
NOT_PRODUCT(static void pd_print_patched_instruction(address branch);)

Diff for: ‎src/hotspot/cpu/ppc/macroAssembler_ppc.inline.hpp

+14
Original file line numberDiff line numberDiff line change
@@ -297,6 +297,20 @@ inline void MacroAssembler::normalize_bool(Register dst, Register temp, bool is_
297297
}
298298
}
299299

300+
inline void MacroAssembler::f2hf(Register dst, FloatRegister src, FloatRegister tmp) {
301+
// Single precision values in FloatRegisters use double precision format on PPC64.
302+
xscvdphp(tmp->to_vsr(), src->to_vsr());
303+
mffprd(dst, tmp);
304+
// Make it a proper short (sign-extended).
305+
extsh(dst, dst);
306+
}
307+
308+
inline void MacroAssembler::hf2f(FloatRegister dst, Register src) {
309+
mtfprd(dst, src);
310+
// Single precision values in FloatRegisters use double precision format on PPC64.
311+
xscvhpdp(dst->to_vsr(), dst->to_vsr());
312+
}
313+
300314
// Convenience bc_far versions
301315
inline void MacroAssembler::blt_far(ConditionRegister crx, Label& L, int optimize) { MacroAssembler::bc_far(bcondCRbiIs1, bi0(crx, less), L, optimize); }
302316
inline void MacroAssembler::bgt_far(ConditionRegister crx, Label& L, int optimize) { MacroAssembler::bc_far(bcondCRbiIs1, bi0(crx, greater), L, optimize); }

Diff for: ‎src/hotspot/cpu/ppc/ppc.ad

+31
Original file line numberDiff line numberDiff line change
@@ -2077,6 +2077,9 @@ bool Matcher::match_rule_supported(int opcode) {
20772077
case Op_PopCountI:
20782078
case Op_PopCountL:
20792079
return (UsePopCountInstruction && VM_Version::has_popcntw());
2080+
case Op_ConvF2HF:
2081+
case Op_ConvHF2F:
2082+
return VM_Version::supports_float16();
20802083

20812084
case Op_AddVB:
20822085
case Op_AddVS:
@@ -11245,6 +11248,34 @@ instruct convF2D_reg(regD dst, regF src) %{
1124511248
ins_pipe(pipe_class_default);
1124611249
%}
1124711250

11251+
instruct convF2HF_reg_reg(iRegIdst dst, regF src, regF tmp) %{
11252+
match(Set dst (ConvF2HF src));
11253+
effect(TEMP tmp);
11254+
ins_cost(3 * DEFAULT_COST);
11255+
size(12);
11256+
format %{ "xscvdphp $tmp, $src\t# convert to half precision\n\t"
11257+
"mffprd $dst, $tmp\t# move result from $tmp to $dst\n\t"
11258+
"extsh $dst, $dst\t# make it a proper short"
11259+
%}
11260+
ins_encode %{
11261+
__ f2hf($dst$$Register, $src$$FloatRegister, $tmp$$FloatRegister);
11262+
%}
11263+
ins_pipe(pipe_class_default);
11264+
%}
11265+
11266+
instruct convHF2F_reg_reg(regF dst, iRegIsrc src) %{
11267+
match(Set dst (ConvHF2F src));
11268+
ins_cost(2 * DEFAULT_COST);
11269+
size(8);
11270+
format %{ "mtfprd $dst, $src\t# move source from $src to $dst\n\t"
11271+
"xscvhpdp $dst, $dst\t# convert from half precision"
11272+
%}
11273+
ins_encode %{
11274+
__ hf2f($dst$$FloatRegister, $src$$Register);
11275+
%}
11276+
ins_pipe(pipe_class_default);
11277+
%}
11278+
1124811279
//----------Control Flow Instructions------------------------------------------
1124911280
// Compare Instructions
1125011281

Diff for: ‎src/hotspot/cpu/ppc/stubGenerator_ppc.cpp

+24
Original file line numberDiff line numberDiff line change
@@ -3451,6 +3451,24 @@ class StubGenerator: public StubCodeGenerator {
34513451
return start;
34523452
}
34533453

3454+
address generate_floatToFloat16() {
3455+
__ align(CodeEntryAlignment);
3456+
StubCodeMark mark(this, "StubRoutines", "floatToFloat16");
3457+
address start = __ function_entry();
3458+
__ f2hf(R3_RET, F1_ARG1, F0);
3459+
__ blr();
3460+
return start;
3461+
}
3462+
3463+
address generate_float16ToFloat() {
3464+
__ align(CodeEntryAlignment);
3465+
StubCodeMark mark(this, "StubRoutines", "float16ToFloat");
3466+
address start = __ function_entry();
3467+
__ hf2f(F1_RET, R3_ARG1);
3468+
__ blr();
3469+
return start;
3470+
}
3471+
34543472
address generate_method_entry_barrier() {
34553473
__ align(CodeEntryAlignment);
34563474
StubCodeMark mark(this, "StubRoutines", "nmethod_entry_barrier");
@@ -4678,6 +4696,12 @@ address generate_lookup_secondary_supers_table_stub(u1 super_klass_index) {
46784696
StubRoutines::_crc32c_table_addr = StubRoutines::ppc::generate_crc_constants(REVERSE_CRC32C_POLY);
46794697
StubRoutines::_updateBytesCRC32C = generate_CRC32_updateBytes(true);
46804698
}
4699+
4700+
if (VM_Version::supports_float16()) {
4701+
// For results consistency both intrinsics should be enabled.
4702+
StubRoutines::_hf2f = generate_float16ToFloat();
4703+
StubRoutines::_f2hf = generate_floatToFloat16();
4704+
}
46814705
}
46824706

46834707
void generate_continuation_stubs() {

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