diff --git a/cubenode/pin-descriptions.md b/cubenode/pin-descriptions.md
index e9e6712..7c30e86 100644
--- a/cubenode/pin-descriptions.md
+++ b/cubenode/pin-descriptions.md
@@ -6,5 +6,5 @@ Depending on the CubeNode version, the IMU may not be available.&#x20;
 
 <figure><img src="../.gitbook/assets/CubeNode Pin descriptions.jpg" alt=""><figcaption></figcaption></figure>
 
-<table><thead><tr><th width="137">Pin Number</th><th width="108">Pin Type</th><th width="134">Pin Name</th><th width="157">Function</th><th>Additional Functions</th></tr></thead><tbody><tr><td>1</td><td>I/O</td><td>CAN1_L</td><td>CAN1_L</td><td></td></tr><tr><td>2</td><td>I/O</td><td>CAN1_H</td><td>CAN1_H</td><td></td></tr><tr><td>3</td><td>I/O</td><td>PE1</td><td>UART8_TX</td><td>EVENTOUT</td></tr><tr><td>4</td><td>I/O</td><td>PE0</td><td>UART8_RX</td><td>EVENTOUT</td></tr><tr><td>5</td><td>I/O</td><td>PB8</td><td>I2C1_SCL</td><td>TIM16_CH1,TIM4_CH3,UART4_RX,EVENTOUT</td></tr><tr><td>6</td><td>I/O</td><td>PB7</td><td>I2C1_SDA</td><td>TIM17_CH1N,TIM4_CH2,USART1_RX,EVENTOUT</td></tr><tr><td>7</td><td>I/O</td><td>PC10</td><td>SPI3_SCK</td><td>USART3_TX,UART4_TX,EVENTOUT</td></tr><tr><td>8</td><td>I/O</td><td>PC11</td><td>SPI3_MISO</td><td>USART3_RX,UART4_RX,EVENTOUT</td></tr><tr><td>9</td><td>I/O</td><td>PC12</td><td>SPI3_MOSI</td><td>UART5_TX,EVENTOUT</td></tr><tr><td>10</td><td>I/O</td><td>PA10/PA8</td><td>SPI3_CS</td><td>TIM1_CH1,I2C3_SCL,EVENTOUT</td></tr><tr><td>11</td><td></td><td></td><td><strong>Reserved Don’t Use</strong></td><td></td></tr><tr><td>12</td><td></td><td></td><td><strong>Reserved Don’t Use</strong></td><td></td></tr><tr><td>13</td><td>P</td><td>VDD_3V3</td><td>VDD_3V3</td><td></td></tr><tr><td>14</td><td>I/O</td><td>CAN2_L</td><td>CAN2_L</td><td></td></tr><tr><td>15</td><td>I/O</td><td>CAN2_H</td><td>CAN2_H</td><td></td></tr><tr><td>16</td><td>I/O</td><td>PA14</td><td>SWCLK</td><td></td></tr><tr><td>17</td><td>I/O</td><td>PA13</td><td>SWDIO</td><td></td></tr><tr><td>18</td><td>I</td><td>NRST</td><td>NRST</td><td></td></tr><tr><td>19</td><td>I</td><td>BOOT0</td><td>BOOT0</td><td></td></tr><tr><td>20</td><td>I/O</td><td>PE2</td><td>GPIO_PE2</td><td>SPI4_SCK,EVENTOUT</td></tr><tr><td>21</td><td>I/O</td><td>PE10</td><td>GPIO_PE10</td><td>TIM1_CH2N,EVENTOUT</td></tr><tr><td>22</td><td>I/O</td><td>PE8</td><td>UART7_TX</td><td>TIM1_CH1N,EVENTOUT</td></tr><tr><td>23</td><td>I/O</td><td>PE7</td><td>UART7_RX</td><td>EVENTOUT.</td></tr><tr><td>24</td><td>P</td><td>GND</td><td>GND</td><td></td></tr><tr><td>25</td><td>I/O</td><td>PF3</td><td>ADC3_INP5</td><td>EVENTOUT</td></tr><tr><td>26</td><td>I/O</td><td>PF5</td><td>ADC3_INP4</td><td>EVENTOUT</td></tr><tr><td>27</td><td>I/O</td><td>PC3_C</td><td>ADC3_INP1</td><td>EVENTOUT</td></tr><tr><td>28</td><td>I/O</td><td>PC2_C</td><td>ADC3_INP0</td><td>SPI2_MISO,ADC3_INN1,EVENTOUT</td></tr><tr><td>29</td><td>P</td><td>GND</td><td>GND</td><td></td></tr><tr><td>30</td><td>I/O</td><td>PC9</td><td>TIM8_CH4</td><td>TIM3_CH4,I2C3_SDA,EVENTOUT</td></tr><tr><td>31</td><td>I/O</td><td>PC8</td><td>TIM8_CH3</td><td>TIM3_CH3,EVENTOUT</td></tr><tr><td>32</td><td>I/O</td><td>PD15</td><td>TIM4_CH4</td><td>EVENTOUT</td></tr><tr><td>33</td><td>I/O</td><td>PD14</td><td>TIM4_CH3</td><td>EVENTOUT</td></tr><tr><td>34</td><td>I/O</td><td>PD13</td><td>TIM4_CH2</td><td>I2C4_SDA,EVENTOUT</td></tr><tr><td>35</td><td>I/O</td><td>PD12</td><td>TIM4_CH1</td><td>I2C4_SCL,EVENTOUT</td></tr><tr><td>36</td><td>P</td><td>GND</td><td>GND</td><td></td></tr><tr><td>37</td><td>I/O</td><td>PF4</td><td>ADC3_INP9</td><td>ADC3_INN5,ADC3_INP9,EVENTOUT</td></tr><tr><td>38</td><td>I/O</td><td>PF14</td><td>ADC2_INP6</td><td>I2C4_SCL,ADC2_INN2,ADC2_INP6,EVENTOUT</td></tr><tr><td>39</td><td>I/O</td><td>PF13</td><td>ADC2_INP2</td><td>EVENTOUT</td></tr><tr><td>40</td><td></td><td></td><td><strong>Reserved Don’t Use</strong></td><td></td></tr><tr><td>41</td><td></td><td></td><td><strong>Reserved Don’t Use</strong></td><td></td></tr><tr><td>42</td><td>P</td><td>GND</td><td>GND</td><td></td></tr><tr><td>43</td><td>I/O</td><td>PC7</td><td>TIM8_CH2</td><td>USART6_RX,TIM3_CH2,EVENTOUT</td></tr><tr><td>44</td><td>I/O</td><td>PC6</td><td>TIM8_CH1</td><td>USART6_TX,TIM3_CH1,EVENTOUT</td></tr><tr><td>45</td><td>I/O</td><td>PB1</td><td>TIM3_CH4</td><td>TIM1_CH3N,TIM8_CH3N,TIM8_CH3N,EVENTOUT</td></tr><tr><td>46</td><td>I/O</td><td>PB0</td><td>TIM3_CH3</td><td>TIM1_CH2N,TIM8_CH2N,ADC12_INN5,ADC12_INP9,EVENTOUT</td></tr><tr><td>47</td><td>I/O</td><td>PE6</td><td>TIM15_CH2</td><td>SPI4_MOSI,EVENTOUT</td></tr><tr><td>48</td><td></td><td></td><td><strong>Reserved Don’t Use</strong></td><td></td></tr><tr><td>49</td><td>P</td><td>GND</td><td>GND</td><td></td></tr><tr><td>50</td><td>I/O</td><td>PA5</td><td>ADC1_INP19</td><td>TIM2_CH1,TIM8_CH1N,SPI1_SCK,EVENTOUT</td></tr><tr><td>51</td><td>I/O</td><td>PA4</td><td>ADC1_INP18</td><td>DAC1_OUT1,EVENTOUT</td></tr><tr><td>52</td><td></td><td></td><td><strong>Reserved Don’t Use</strong></td><td></td></tr><tr><td>53</td><td>I/O</td><td>PC0</td><td>ADC1_INP10</td><td>EVENTOUT</td></tr><tr><td>54</td><td>P</td><td>GND</td><td>GND</td><td></td></tr><tr><td>55</td><td>I/O</td><td>PA3</td><td>TIM5_CH4</td><td>TIM2_CH4,TIM15_CH2,USART2_RX,ADC12_INP15,EVENTOUT</td></tr><tr><td>56</td><td></td><td></td><td><strong>Reserved Don’t Use</strong></td><td></td></tr><tr><td>57</td><td>I/O</td><td>PE5</td><td>TIM15_CH1</td><td>SPI4_MISO,EVENTOUT</td></tr><tr><td>58</td><td>I/O</td><td>PB10</td><td>TIM2_CH3</td><td>I2C2_SCL,SPI2_SCK,USART3_TX,EVENTOUT</td></tr><tr><td>59</td><td></td><td></td><td><strong>Reserved Don’t Use</strong></td><td></td></tr><tr><td>60</td><td>I/O</td><td>PA15</td><td>TIM2_CH1</td><td>EVENTOUT</td></tr><tr><td>61</td><td>P</td><td>GND</td><td>GND</td><td></td></tr><tr><td>62</td><td>I/O</td><td>PF12</td><td>ADC1_INP6</td><td>ADC1_INN2,EVENTOUT</td></tr><tr><td>63</td><td></td><td></td><td><strong>Reserved Don’t Use</strong></td><td></td></tr><tr><td>64</td><td>I/O</td><td>PA6</td><td>ADC1_INP3</td><td>TIM3_CH1,SPI1_MISO,TIM13_CH1,EVENTOUT</td></tr><tr><td>65</td><td>I/O</td><td>PF11</td><td>ADC1_INP2</td><td>ADC1_INP2,EVENTOUT</td></tr><tr><td>66</td><td>P</td><td>GND</td><td>GND</td><td></td></tr><tr><td>67</td><td></td><td></td><td><strong>Reserved Don’t Use</strong></td><td></td></tr><tr><td>68</td><td>I/O</td><td>PA0</td><td>TIM5_CH1</td><td>TIM2_CH1,UART4_TX,ADC1_INP16,EVENTOUT</td></tr><tr><td>69</td><td>I/O</td><td>PE14</td><td>TIM1_CH4</td><td>SPI4_MOSI,EVENTOUT</td></tr><tr><td>70</td><td>I/O</td><td>PE13</td><td>TIM1_CH3</td><td>SPI4_MISO,EVENTOUT</td></tr><tr><td>71</td><td>I/O</td><td>PE11</td><td>TIM1_CH2</td><td>EVENTOUT</td></tr><tr><td>72</td><td>I/O</td><td>PE9</td><td>TIM1_CH1</td><td>EVENTOUT</td></tr><tr><td>73</td><td>P</td><td>GND</td><td>GND</td><td></td></tr><tr><td>74</td><td>P</td><td>GND</td><td>GND</td><td></td></tr><tr><td>75</td><td>I/O</td><td>PA12</td><td>OTG_FS_DP</td><td>UART4_TX,EVENTOUT</td></tr><tr><td>76</td><td>I/O</td><td>PA11</td><td>OTG_FS_DM</td><td>TIM1_CH4,UART4_RX,EVENTOUT</td></tr><tr><td>77</td><td>P</td><td>PA9</td><td>VBUS</td><td></td></tr><tr><td>78</td><td>P</td><td>VDD_5V</td><td>VDD_5V</td><td></td></tr><tr><td>79</td><td>I/O</td><td>ETHERNET_TX-</td><td>ETHERNET_TX-</td><td></td></tr><tr><td>80</td><td>I/O</td><td>ETHERNET_TX+</td><td>ETHERNET_TX+</td><td></td></tr><tr><td>81</td><td>I/O</td><td>ETHERNET_RX-</td><td>ETHERNET_RX-</td><td></td></tr><tr><td>82</td><td>I/O</td><td>ETHERNET_RX+</td><td>ETHERNET_RX+</td><td></td></tr><tr><td>83-84</td><td>P</td><td>GND</td><td>GND</td><td></td></tr><tr><td>85-95</td><td></td><td></td><td><strong>Reserved Don’t Use</strong></td><td></td></tr><tr><td>96-97</td><td>P</td><td>GND</td><td>GND</td><td></td></tr><tr><td>98-100</td><td></td><td></td><td><strong>Reserved Don’t Use</strong></td><td></td></tr><tr><td>101</td><td>I/O</td><td>PB15</td><td>SDMMC2_D1</td><td>TIM1_CH3N,TIM12_CH2,TIM8_CH3N,USART1_RX,OTG_HS_DP,EVENTOUT</td></tr><tr><td>102</td><td>I/O</td><td>PB14</td><td>SDMMC2_D0</td><td>TIM1_CH2N,TIM12_CH1,TIM8,CH2N,USART1_TX,SPI2_MISO,OTG_HS_DM,EVENTOUT</td></tr><tr><td>103-105</td><td></td><td></td><td><strong>Reserved Don’t Use</strong></td><td></td></tr><tr><td>106</td><td>I/O</td><td>PB3</td><td>SDMMC2_D2</td><td>TIM2_CH2,SPI1_SCK,EVENTOUT</td></tr><tr><td>107</td><td>I/O</td><td>PB4</td><td>SDMMC2_D3</td><td>TIM3_CH1,SPI1_MISO,EVENTOUT</td></tr><tr><td>108-109</td><td></td><td></td><td><strong>Reserved Don’t Use</strong></td><td></td></tr><tr><td>110</td><td>I/O</td><td>PD6</td><td>SDMMC2_CK</td><td>USART2_RX,EVENTOUT</td></tr><tr><td>111</td><td>I/O</td><td>PD7</td><td>SDMMC2_CMD</td><td>SPI1_MOSI,EVENTOUT</td></tr></tbody></table>
+<table><thead><tr><th width="137">Pin Number</th><th width="108">Pin Type</th><th width="134">Pin Name</th><th width="157">Function</th><th>Additional Functions</th></tr></thead><tbody><tr><td>1</td><td>I/O</td><td>CAN1_L</td><td>CAN1_L</td><td></td></tr><tr><td>2</td><td>I/O</td><td>CAN1_H</td><td>CAN1_H</td><td></td></tr><tr><td>3</td><td>I/O</td><td>PE1</td><td>UART8_TX</td><td>EVENTOUT</td></tr><tr><td>4</td><td>I/O</td><td>PE0</td><td>UART8_RX</td><td>EVENTOUT</td></tr><tr><td>5</td><td>I/O</td><td>PB8</td><td>I2C1_SCL</td><td>TIM16_CH1,TIM4_CH3,UART4_RX,EVENTOUT</td></tr><tr><td>6</td><td>I/O</td><td>PB7</td><td>I2C1_SDA</td><td>TIM17_CH1N,TIM4_CH2,USART1_RX,EVENTOUT</td></tr><tr><td>7</td><td>I/O</td><td>PC10</td><td>SPI3_SCK</td><td>USART3_TX,UART4_TX,EVENTOUT</td></tr><tr><td>8</td><td>I/O</td><td>PC11</td><td>SPI3_MISO</td><td>USART3_RX,UART4_RX,EVENTOUT</td></tr><tr><td>9</td><td>I/O</td><td>PC12</td><td>SPI3_MOSI</td><td>UART5_TX,EVENTOUT</td></tr><tr><td>10</td><td>I/O</td><td>PA10/PA8</td><td>SPI3_CS</td><td>TIM1_CH1,I2C3_SCL,EVENTOUT</td></tr><tr><td>11</td><td></td><td></td><td><strong>Reserved Don’t Use</strong></td><td></td></tr><tr><td>12</td><td></td><td></td><td><strong>Reserved Don’t Use</strong></td><td></td></tr><tr><td>13</td><td>P</td><td>VDD_3V3</td><td>VDD_3V3</td><td></td></tr><tr><td>14</td><td>I/O</td><td>CAN2_L</td><td>CAN2_L</td><td></td></tr><tr><td>15</td><td>I/O</td><td>CAN2_H</td><td>CAN2_H</td><td></td></tr><tr><td>16</td><td>I/O</td><td>PA14</td><td>SWCLK</td><td></td></tr><tr><td>17</td><td>I/O</td><td>PA13</td><td>SWDIO</td><td></td></tr><tr><td>18</td><td>I</td><td>NRST</td><td>NRST</td><td></td></tr><tr><td>19</td><td>I</td><td>BOOT0</td><td>BOOT0</td><td></td></tr><tr><td>20</td><td>I/O</td><td>PE2</td><td>GPIO_PE2</td><td>SPI4_SCK,EVENTOUT</td></tr><tr><td>21</td><td>I/O</td><td>PE10</td><td>GPIO_PE10</td><td>TIM1_CH2N,EVENTOUT</td></tr><tr><td>22</td><td>I/O</td><td>PE8</td><td>UART7_TX</td><td>TIM1_CH1N,EVENTOUT</td></tr><tr><td>23</td><td>I/O</td><td>PE7</td><td>UART7_RX</td><td>EVENTOUT.</td></tr><tr><td>24</td><td>P</td><td>GND</td><td>GND</td><td></td></tr><tr><td>25</td><td>I/O</td><td>PF3</td><td>ADC3_INP5</td><td>EVENTOUT</td></tr><tr><td>26</td><td>I/O</td><td>PF5</td><td>ADC3_INP4</td><td>EVENTOUT</td></tr><tr><td>27</td><td>I/O</td><td>PC3_C</td><td>ADC3_INP1</td><td>EVENTOUT</td></tr><tr><td>28</td><td>I/O</td><td>PC2_C</td><td>ADC3_INP0</td><td>SPI2_MISO,ADC3_INN1,EVENTOUT</td></tr><tr><td>29</td><td>P</td><td>GND</td><td>GND</td><td></td></tr><tr><td>30</td><td>I/O</td><td>PC9</td><td>TIM8_CH4</td><td>TIM3_CH4,I2C3_SDA,EVENTOUT</td></tr><tr><td>31</td><td>I/O</td><td>PC8</td><td>TIM8_CH3</td><td>TIM3_CH3,EVENTOUT</td></tr><tr><td>32</td><td>I/O</td><td>PD15</td><td>TIM4_CH4</td><td>EVENTOUT</td></tr><tr><td>33</td><td>I/O</td><td>PD14</td><td>TIM4_CH3</td><td>EVENTOUT</td></tr><tr><td>34</td><td>I/O</td><td>PD13</td><td>TIM4_CH2</td><td>I2C4_SDA,EVENTOUT</td></tr><tr><td>35</td><td>I/O</td><td>PD12</td><td>TIM4_CH1</td><td>I2C4_SCL,EVENTOUT</td></tr><tr><td>36</td><td>P</td><td>GND</td><td>GND</td><td></td></tr><tr><td>37</td><td>I/O</td><td>PF4</td><td>ADC3_INP9</td><td>ADC3_INN5,ADC3_INP9,EVENTOUT</td></tr><tr><td>38</td><td>I/O</td><td>PF14</td><td>ADC2_INP6</td><td>I2C4_SCL,ADC2_INN2,ADC2_INP6,EVENTOUT</td></tr><tr><td>39</td><td>I/O</td><td>PF13</td><td>ADC2_INP2</td><td>EVENTOUT</td></tr><tr><td>40</td><td></td><td></td><td><strong>Reserved Don’t Use</strong></td><td></td></tr><tr><td>41</td><td></td><td></td><td><strong>Reserved Don’t Use</strong></td><td></td></tr><tr><td>42</td><td>P</td><td>GND</td><td>GND</td><td></td></tr><tr><td>43</td><td>I/O</td><td>PC7</td><td>TIM8_CH2</td><td>USART6_RX,TIM3_CH2,EVENTOUT</td></tr><tr><td>44</td><td>I/O</td><td>PC6</td><td>TIM8_CH1</td><td>USART6_TX,TIM3_CH1,EVENTOUT</td></tr><tr><td>45</td><td>I/O</td><td>PB1</td><td>TIM3_CH4</td><td>TIM1_CH3N,TIM8_CH3N,TIM8_CH3N,EVENTOUT</td></tr><tr><td>46</td><td>I/O</td><td>PB0</td><td>TIM3_CH3</td><td>TIM1_CH2N,TIM8_CH2N,ADC12_INN5,ADC12_INP9,EVENTOUT</td></tr><tr><td>47</td><td>I/O</td><td>PE6</td><td>TIM15_CH2</td><td>SPI4_MOSI,EVENTOUT</td></tr><tr><td>48</td><td></td><td></td><td><strong>Reserved Don’t Use</strong></td><td></td></tr><tr><td>49</td><td>P</td><td>GND</td><td>GND</td><td></td></tr><tr><td>50</td><td>I/O</td><td>PA5</td><td>ADC1_INP19</td><td>TIM2_CH1,TIM8_CH1N,SPI1_SCK,EVENTOUT</td></tr><tr><td>51</td><td>I/O</td><td>PA4</td><td>ADC1_INP18</td><td>DAC1_OUT1,EVENTOUT</td></tr><tr><td>52</td><td></td><td></td><td><strong>Reserved Don’t Use</strong></td><td></td></tr><tr><td>53</td><td>I/O</td><td>PC0</td><td>ADC1_INP10</td><td>EVENTOUT</td></tr><tr><td>54</td><td>P</td><td>GND</td><td>GND</td><td></td></tr><tr><td>55</td><td>I/O</td><td>PA3</td><td>TIM5_CH4</td><td>TIM2_CH4,TIM15_CH2,USART2_RX,ADC12_INP15,EVENTOUT</td></tr><tr><td>56</td><td></td><td></td><td><strong>Reserved Don’t Use</strong></td><td></td></tr><tr><td>57</td><td>I/O</td><td>PE5</td><td>TIM15_CH1</td><td>SPI4_MISO,EVENTOUT</td></tr><tr><td>58</td><td>I/O</td><td>PB10</td><td>TIM2_CH3</td><td>I2C2_SCL,SPI2_SCK,USART3_TX,EVENTOUT</td></tr><tr><td>59</td><td></td><td></td><td><strong>Reserved Don’t Use</strong></td><td></td></tr><tr><td>60</td><td>I/O</td><td>PA15</td><td>TIM2_CH1</td><td>EVENTOUT</td></tr><tr><td>61</td><td>P</td><td>GND</td><td>GND</td><td></td></tr><tr><td>62</td><td>I/O</td><td>PF12</td><td>ADC1_INP6</td><td>ADC1_INN2,EVENTOUT</td></tr><tr><td>63</td><td></td><td></td><td><strong>Reserved Don’t Use</strong></td><td></td></tr><tr><td>64</td><td>I/O</td><td>PA6</td><td>ADC1_INP3</td><td>TIM3_CH1,SPI1_MISO,TIM13_CH1,EVENTOUT</td></tr><tr><td>65</td><td>I/O</td><td>PF11</td><td>ADC1_INP2</td><td>ADC1_INP2,EVENTOUT</td></tr><tr><td>66</td><td>P</td><td>GND</td><td>GND</td><td></td></tr><tr><td>67</td><td></td><td></td><td><strong>Reserved Don’t Use</strong></td><td></td></tr><tr><td>68</td><td>I/O</td><td>PA0</td><td>TIM5_CH1</td><td>TIM2_CH1,UART4_TX,ADC1_INP16,EVENTOUT</td></tr><tr><td>69</td><td>I/O</td><td>PE14</td><td>TIM1_CH4</td><td>SPI4_MOSI,EVENTOUT</td></tr><tr><td>70</td><td>I/O</td><td>PE13</td><td>TIM1_CH3</td><td>SPI4_MISO,EVENTOUT</td></tr><tr><td>71</td><td>I/O</td><td>PE11</td><td>TIM1_CH2</td><td>EVENTOUT</td></tr><tr><td>72</td><td>I/O</td><td>PE9</td><td>TIM1_CH1</td><td>EVENTOUT</td></tr><tr><td>73</td><td>P</td><td>GND</td><td>GND</td><td></td></tr><tr><td>74</td><td>P</td><td>GND</td><td>GND</td><td></td></tr><tr><td>75</td><td>I/O</td><td>PA12</td><td>OTG_FS_DP</td><td>UART4_TX,EVENTOUT</td></tr><tr><td>76</td><td>I/O</td><td>PA11</td><td>OTG_FS_DM</td><td>TIM1_CH4,UART4_RX,EVENTOUT</td></tr><tr><td>77</td><td>P</td><td>PA9</td><td>VBUS</td><td></td></tr><tr><td>78</td><td>P</td><td>VDD_5V</td><td>VDD_5V</td><td></td></tr><tr><td>79</td><td>I/O</td><td>PB12</td><td>ETHERNET_TX-</td><td></td></tr><tr><td>80</td><td>I/O</td><td>PB13</td><td>ETHERNET_TX+</td><td></td></tr><tr><td>81</td><td>I/O</td><td>PC4</td><td>ETHERNET_RX-</td><td></td></tr><tr><td>82</td><td>I/O</td><td>PC5</td><td>ETHERNET_RX+</td><td></td></tr><tr><td>83-84</td><td>P</td><td>GND</td><td>GND</td><td></td></tr><tr><td>85-95</td><td></td><td></td><td><strong>Reserved Don’t Use</strong></td><td></td></tr><tr><td>96-97</td><td>P</td><td>GND</td><td>GND</td><td></td></tr><tr><td>98-100</td><td></td><td></td><td><strong>Reserved Don’t Use</strong></td><td></td></tr><tr><td>101</td><td>I/O</td><td>PB15</td><td>SDMMC2_D1</td><td>TIM1_CH3N,TIM12_CH2,TIM8_CH3N,USART1_RX,OTG_HS_DP,EVENTOUT</td></tr><tr><td>102</td><td>I/O</td><td>PB14</td><td>SDMMC2_D0</td><td>TIM1_CH2N,TIM12_CH1,TIM8,CH2N,USART1_TX,SPI2_MISO,OTG_HS_DM,EVENTOUT</td></tr><tr><td>103-105</td><td></td><td></td><td><strong>Reserved Don’t Use</strong></td><td></td></tr><tr><td>106</td><td>I/O</td><td>PB3</td><td>SDMMC2_D2</td><td>TIM2_CH2,SPI1_SCK,EVENTOUT</td></tr><tr><td>107</td><td>I/O</td><td>PB4</td><td>SDMMC2_D3</td><td>TIM3_CH1,SPI1_MISO,EVENTOUT</td></tr><tr><td>108-109</td><td></td><td></td><td><strong>Reserved Don’t Use</strong></td><td></td></tr><tr><td>110</td><td>I/O</td><td>PD6</td><td>SDMMC2_CK</td><td>USART2_RX,EVENTOUT</td></tr><tr><td>111</td><td>I/O</td><td>PD7</td><td>SDMMC2_CMD</td><td>SPI1_MOSI,EVENTOUT</td></tr></tbody></table>
 

Pin Number	Pin Type	Pin Name	Function	Additional Functions
1	I/O	CAN1_L	CAN1_L
2	I/O	CAN1_H	CAN1_H
3	I/O	PE1	UART8_TX	EVENTOUT
4	I/O	PE0	UART8_RX	EVENTOUT
5	I/O	PB8	I2C1_SCL	TIM16_CH1,TIM4_CH3,UART4_RX,EVENTOUT
6	I/O	PB7	I2C1_SDA	TIM17_CH1N,TIM4_CH2,USART1_RX,EVENTOUT
7	I/O	PC10	SPI3_SCK	USART3_TX,UART4_TX,EVENTOUT
8	I/O	PC11	SPI3_MISO	USART3_RX,UART4_RX,EVENTOUT
9	I/O	PC12	SPI3_MOSI	UART5_TX,EVENTOUT
10	I/O	PA10/PA8	SPI3_CS	TIM1_CH1,I2C3_SCL,EVENTOUT
11			Reserved Don’t Use
12			Reserved Don’t Use
13	P	VDD_3V3	VDD_3V3
14	I/O	CAN2_L	CAN2_L
15	I/O	CAN2_H	CAN2_H
16	I/O	PA14	SWCLK
17	I/O	PA13	SWDIO
18	I	NRST	NRST
19	I	BOOT0	BOOT0
20	I/O	PE2	GPIO_PE2	SPI4_SCK,EVENTOUT
21	I/O	PE10	GPIO_PE10	TIM1_CH2N,EVENTOUT
22	I/O	PE8	UART7_TX	TIM1_CH1N,EVENTOUT
23	I/O	PE7	UART7_RX	EVENTOUT.
24	P	GND	GND
25	I/O	PF3	ADC3_INP5	EVENTOUT
26	I/O	PF5	ADC3_INP4	EVENTOUT
27	I/O	PC3_C	ADC3_INP1	EVENTOUT
28	I/O	PC2_C	ADC3_INP0	SPI2_MISO,ADC3_INN1,EVENTOUT
29	P	GND	GND
30	I/O	PC9	TIM8_CH4	TIM3_CH4,I2C3_SDA,EVENTOUT
31	I/O	PC8	TIM8_CH3	TIM3_CH3,EVENTOUT
32	I/O	PD15	TIM4_CH4	EVENTOUT
33	I/O	PD14	TIM4_CH3	EVENTOUT
34	I/O	PD13	TIM4_CH2	I2C4_SDA,EVENTOUT
35	I/O	PD12	TIM4_CH1	I2C4_SCL,EVENTOUT
36	P	GND	GND
37	I/O	PF4	ADC3_INP9	ADC3_INN5,ADC3_INP9,EVENTOUT
38	I/O	PF14	ADC2_INP6	I2C4_SCL,ADC2_INN2,ADC2_INP6,EVENTOUT
39	I/O	PF13	ADC2_INP2	EVENTOUT
40			Reserved Don’t Use
41			Reserved Don’t Use
42	P	GND	GND
43	I/O	PC7	TIM8_CH2	USART6_RX,TIM3_CH2,EVENTOUT
44	I/O	PC6	TIM8_CH1	USART6_TX,TIM3_CH1,EVENTOUT
45	I/O	PB1	TIM3_CH4	TIM1_CH3N,TIM8_CH3N,TIM8_CH3N,EVENTOUT
46	I/O	PB0	TIM3_CH3	TIM1_CH2N,TIM8_CH2N,ADC12_INN5,ADC12_INP9,EVENTOUT
47	I/O	PE6	TIM15_CH2	SPI4_MOSI,EVENTOUT
48			Reserved Don’t Use
49	P	GND	GND
50	I/O	PA5	ADC1_INP19	TIM2_CH1,TIM8_CH1N,SPI1_SCK,EVENTOUT
51	I/O	PA4	ADC1_INP18	DAC1_OUT1,EVENTOUT
52			Reserved Don’t Use
53	I/O	PC0	ADC1_INP10	EVENTOUT
54	P	GND	GND
55	I/O	PA3	TIM5_CH4	TIM2_CH4,TIM15_CH2,USART2_RX,ADC12_INP15,EVENTOUT
56			Reserved Don’t Use
57	I/O	PE5	TIM15_CH1	SPI4_MISO,EVENTOUT
58	I/O	PB10	TIM2_CH3	I2C2_SCL,SPI2_SCK,USART3_TX,EVENTOUT
59			Reserved Don’t Use
60	I/O	PA15	TIM2_CH1	EVENTOUT
61	P	GND	GND
62	I/O	PF12	ADC1_INP6	ADC1_INN2,EVENTOUT
63			Reserved Don’t Use
64	I/O	PA6	ADC1_INP3	TIM3_CH1,SPI1_MISO,TIM13_CH1,EVENTOUT
65	I/O	PF11	ADC1_INP2	ADC1_INP2,EVENTOUT
66	P	GND	GND
67			Reserved Don’t Use
68	I/O	PA0	TIM5_CH1	TIM2_CH1,UART4_TX,ADC1_INP16,EVENTOUT
69	I/O	PE14	TIM1_CH4	SPI4_MOSI,EVENTOUT
70	I/O	PE13	TIM1_CH3	SPI4_MISO,EVENTOUT
71	I/O	PE11	TIM1_CH2	EVENTOUT
72	I/O	PE9	TIM1_CH1	EVENTOUT
73	P	GND	GND
74	P	GND	GND
75	I/O	PA12	OTG_FS_DP	UART4_TX,EVENTOUT
76	I/O	PA11	OTG_FS_DM	TIM1_CH4,UART4_RX,EVENTOUT
77	P	PA9	VBUS
78	P	VDD_5V	VDD_5V
79	I/O	ETHERNET_TX-	ETHERNET_TX-
80	I/O	ETHERNET_TX+	ETHERNET_TX+
81	I/O	ETHERNET_RX-	ETHERNET_RX-
82	I/O	ETHERNET_RX+	ETHERNET_RX+
83-84	P	GND	GND
85-95			Reserved Don’t Use
96-97	P	GND	GND
98-100			Reserved Don’t Use
101	I/O	PB15	SDMMC2_D1	TIM1_CH3N,TIM12_CH2,TIM8_CH3N,USART1_RX,OTG_HS_DP,EVENTOUT
102	I/O	PB14	SDMMC2_D0	TIM1_CH2N,TIM12_CH1,TIM8,CH2N,USART1_TX,SPI2_MISO,OTG_HS_DM,EVENTOUT
103-105			Reserved Don’t Use
106	I/O	PB3	SDMMC2_D2	TIM2_CH2,SPI1_SCK,EVENTOUT
107	I/O	PB4	SDMMC2_D3	TIM3_CH1,SPI1_MISO,EVENTOUT
108-109			Reserved Don’t Use
110	I/O	PD6	SDMMC2_CK	USART2_RX,EVENTOUT
111	I/O	PD7	SDMMC2_CMD	SPI1_MOSI,EVENTOUT