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‎DRAMPower/.gitignore

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drampower
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*.d
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*.o
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*.a
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test/libdrampowertest/library_test
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test/libdrampowertest/window_example
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*.gcno
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*.gcda
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traces/*
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traces.zip
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.sconf_temp/
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.sconsign.dblite
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*.swp
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*.swo
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cscope.*
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commands.trace
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coverage_report
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.DS_Store

‎DRAMPower/.gitlab-ci.yml

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before_script:
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- sudo apt-get install -y libxerces-c-dev wget unzip python
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default_test:
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script:
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- make test COVERAGE=1

‎DRAMPower/.travis.yml

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os:
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- linux
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- osx
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matrix:
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allow_failures:
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- os: osx
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language: cpp
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compiler:
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- gcc
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- clang
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install:
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- echo "No install."
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before_install:
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- if [[ "$TRAVIS_OS_NAME" == "linux" ]]; then sudo pip install cpp-coveralls; fi
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- if [[ "$TRAVIS_OS_NAME" == "linux" ]]; then sudo apt-get install -y libxerces-c-dev; fi
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- if [[ "$TRAVIS_OS_NAME" == "osx" ]]; then brew update ; fi
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- if [[ "$TRAVIS_OS_NAME" == "osx" ]]; then brew install xerces-c; fi
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script:
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- if [[ "$TRAVIS_OS_NAME" == "linux" && "$CXX" == "g++" ]]; then make test COVERAGE=1; fi
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- if [[ "$TRAVIS_OS_NAME" == "linux" && "$CXX" == "clang++" ]]; then make test; fi
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- if [[ "$TRAVIS_OS_NAME" == "osx" ]]; then make test; fi
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after_success:
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- if [[ "$TRAVIS_OS_NAME" == "linux" ]]; then coveralls --exclude lib --exclude tests --gcov-options '\-lp'; fi

‎DRAMPower/CMakeLists.txt

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# Copyright (c) 2020, Fraunhofer IESE
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met:
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#
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# 1. Redistributions of source code must retain the above copyright notice,
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# this list of conditions and the following disclaimer.
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#
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# 2. Redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution.
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#
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# 3. Neither the name of the copyright holder nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
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# OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Author: Matthias Jung
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cmake_minimum_required(VERSION 3.10)
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# Set the project name:
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project(DRAMPower)
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# Configuration:
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include_directories(
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src/
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src/libdrampower
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)
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# Build:
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add_library(DRAMPower
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src/libdrampower/LibDRAMPower.cc
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src/CommandAnalysis.cc
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src/MemArchitectureSpec.cc
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src/MemCommand.cc
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src/MemPowerSpec.cc
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src/MemTimingSpec.cc
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src/MemoryPowerModel.cc
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src/MemorySpecification.cc
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src/Parameter.cc
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src/Parametrisable.cc
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src/libdrampower/LibDRAMPower.cc
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src/CAHelpers.cc
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src/CmdHandlers.cc
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src/MemBankWiseParams.cc
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)

‎DRAMPower/ChangeLog

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Change Log:
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DRAMPower v4.0 - * DRAMPower can now be compiled as a library. This enables a user
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to access the tool through an API and log commands and their
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corresponding time stamps, removing the need to store large
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command traces on disk. In addition, cycle counting variables
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have been changed to int64 to support longer simulations.
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The library can be compiled without Xerces to remove an optional
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dependency and reduce the size of the binary.
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* Improved robustness. The latest build is automatically checked
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out on a test server, compiled, and tested to verify that the
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output matches an expected reference. The code is also compiled
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with a large number of warning flags enabled and treats all
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warnings as errors.
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* Bug fix: Fixed bug in io/termination energy calculation.
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* Bug fix: Fixed bug in calculation of auto precharge cycle.
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DRAMPower v3.1 - * Added IO and Termination Power measures from Micron's DRAM Power
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Calculator, for all supported DRAM generations. In the case of
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Wide IO DRAMs, these measures are already included in the provided
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current specifications. This feature enables support for multi-rank
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DRAM DIMMs (DDR2/3/4) and stacking of multiple Wide IO DRAM dies
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(equivalent to ranks). To indicate use of multi-rank DRAMs or
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multiple Wide IO DRAM dies/layers, the 'nbrOfRanks' parameter in
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the memory specification XMLs can be employed. Note: The DRAM
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command scheduler does not support multi-rank/multi-die DRAMs yet.
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Only the power estimation component of DRAMPower has been updated
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to support them. The current measures for dual-rank DRAMs only
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reflect those for the active rank and not the idle rank. The
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default state of the idle rank is assumed to be the same as the
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current memory state, for background power estimation. Hence,
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rank information in the command trace is not required.
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* Added warning messages: New warning messages are provided, to
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identify if the memory or bank state is inconsistent in the
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user-defined traces. Towards this, a state check is performed on
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every memory command issued.
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* Improved run-time options: Users can now point directly to the
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memory specification XML, instead of just the memory ID. Also,
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users can optionally include IO and termination power estimates
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(for both single and dual rank DRAMs) using '-r' flag in the
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command line options.
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* Bug fixes: (1) Refresh handler in the DRAM Command Scheduler was
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kept ON in the Self-Refresh mode, when it can be turned OFF. This
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bug has now been fixed. (2) Precharge All (PREA) always considered
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precharging of all banks. It has now been modified to consider
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precharging of the open/active banks alone.
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DRAMPower v3.0 - * Added support for LPDDR3 and DDR4 memories, besides the already
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supported DDR2/DDR3, LPDDR/LPDDR2 and WIDE IO DRAM memories.
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* Added DRAM Command Scheduler: To support users of DRAMPower
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without access to DRAM controllers, we have added a simple DRAM
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command scheduler that dynamically schedules DRAM commands as if
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it were a memory controller. The scheduler assumes closed-page
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policy, employs ASAP scheduling for DRAM commands (i.e. schedules
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commands as soon as timing constraints are met), performs FCFS
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scheduling on DRAM transactions and supports all the different
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DRAM generations supported by the power model. The generated DRAM
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command schedule is also analyzable for real-time applications.
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Users can also select speculative usage of power-down or
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self-refresh modes (if needed) for idle periods between
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transactions. It should be noted that using this command scheduler
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is optional and it can be (de-)selected during run-time and users
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can switch back to the previously used DRAM command interface as
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in the earlier versions.
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* Improved run-time options: Users can specify the memory and the
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trace file to be used by DRAMPower using command line options.
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Additionally, if the DRAM command scheduler is being used, the
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users can specify the degree of bank interleaving required, the
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request size and power-down or self-refresh options. Also, for
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DDR4 memories the bank group interleaving can be specified using
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command line options.
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* Bug fixes: (1) For command traces ending with a RD/WR/RDA/WRA
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command, the tool did not consider completion of operations when
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estimating the total trace energy. The missing cycles are now
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taken into account.
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(2) The IDD5 (REF current) specification for WIDE IO SDR memory
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specifications only included 2 banks for refreshes instead of all
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four. We would like to thank David Roberts from AMD for spotting
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the issue in our DATE'13 article. These measures have been updated.
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(3) When estimating precharge cycle for commands with
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auto-precharge, (RDA/WRA), the command analysis tool employed the
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last activation cycle in the entire DRAM instead of the particular
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DRAM bank. This bug has been fixed in this release.
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DRAMPower v2.1 - * Added support for variation-aware power estimation, for a
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selection of DDR3 memories manufactured using 50nm process
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technology, based on the Monte-Carlo analysis presented in our
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DAC'13 article.
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DRAMPower v2.0 - * Added support for LPDDR/LPDDR2 and WIDE IO DRAM memories, besides
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the already supported DDR2/DDR3 memories.
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* Faster analysis: The trace analysis component in DRAMPower v2.0
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triggers the evaluation only during memory state transitions
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(between active, precharged, active and precharged power-down,
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refresh, self-refresh and power-up states) and not on every clock
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cycle, as was the case till the last version. This optimization
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speeds up the power simulations using DRAMPower by several times
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over cycle-accurate analysis, resulting in fast power analysis,
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without affecting the accuracy of the trace analysis or the
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reported power and energy estimates.
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* Verification effort: Our power model was verified by the
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Microelectronic System Design group at TU Kaiserslautern using
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circuit-level SPICE simulations of a DRAM cross-section. As a
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result of this verification effort, a couple of power equations
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have been modified for Refresh and Self-refresh operations. The
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difference between the power and energy estimates reported by our
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updated model and the equivalent circuit-level simulations is
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< 2% for all memory operations of any granularity for all memories
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supported by DRAMPower.
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DRAMPower v1.2 - * Supports different power-down and self-refresh modes in DDR2 and
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DDR3 DRAM memories.
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* Bug fix: Refresh power consumption equation in DRAMPower v1,
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incorrectly subtracted IDD2n (precharge background current)
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instead of IDD3n (active background current) from IDD5 (total
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refresh current). This error has been rectified in this version.
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DRAMPower v1.0 - * Performs cycle-accurate memory command trace analysis and estimates
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power and energy consumption numbers for the trace.
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* It supports the basic memory operations like read, write, refresh,
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activate and (auto) precharge in DDR2 and DDR3 memories.

‎DRAMPower/Makefile

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#/*
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# * Copyright (c) 2012-2014, TU Delft
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# * Copyright (c) 2012-2014, TU Eindhoven
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# * Copyright (c) 2012-2014, TU Kaiserslautern
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# * All rights reserved.
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# *
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# * Redistribution and use in source and binary forms, with or without
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# * modification, are permitted provided that the following conditions are
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# * met:
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# *
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# * 1. Redistributions of source code must retain the above copyright
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# * notice, this list of conditions and the following disclaimer.
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# *
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# * 2. Redistributions in binary form must reproduce the above copyright
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# * notice, this list of conditions and the following disclaimer in the
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# * documentation and/or other materials provided with the distribution.
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# *
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# * 3. Neither the name of the copyright holder nor the names of its
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# * contributors may be used to endorse or promote products derived from
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# * this software without specific prior written permission.
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# *
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# * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
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# * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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# * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
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# * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
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# * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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# * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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# * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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# * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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# * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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# *
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# * Authors: Karthik Chandrasekar, Benny Akesson, Sven Goossens
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# *
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# */
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include common.mk
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CXX := g++
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# Name of the generated binary.
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BINARY := drampower
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LIBS := src/libdrampower.a src/libdrampowerxml.a
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# Identifies the source files and derives name of object files.
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CLISOURCES := src/TraceParser.cc $(wildcard src/cli/*.cc)
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LIBSOURCES := $(wildcard src/libdrampower/*.cc) \
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src/CommandAnalysis.cc \
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src/CAHelpers.cc \
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src/CmdHandlers.cc \
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src/MemArchitectureSpec.cc\
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src/MemCommand.cc\
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src/MemoryPowerModel.cc\
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src/MemorySpecification.cc\
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src/MemPowerSpec.cc\
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src/MemTimingSpec.cc\
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src/Parameter.cc\
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src/Parametrisable.cc\
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src/MemBankWiseParams.cc
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XMLPARSERSOURCES := $(wildcard src/xmlparser/*.cc)
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ALLSOURCES := $(wildcard src/cli/*.cc) $(wildcard src/*.cc) $(wildcard src/xmlparser/*.cc) $(wildcard src/libdrampower/*.cc)
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ALLHEADERS := $(wildcard src/*.h) $(wildcard src/xmlparser/*.h) $(wildcard src/libdrampower/*.h)
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CLIOBJECTS := ${CLISOURCES:.cc=.o}
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XMLPARSEROBJECTS := ${XMLPARSERSOURCES:.cc=.o}
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LIBOBJECTS := ${LIBSOURCES:.cc=.o}
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ALLOBJECTS := ${ALLSOURCES:.cc=.o}
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DEPENDENCIES := ${ALLSOURCES:.cc=.d}
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# Warning flags for deprecated files
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DEPWARNFLAGS := -W -pedantic-errors -Wextra -Werror \
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-Wformat -Wformat-nonliteral -Wpointer-arith \
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-Wcast-align -Wall -Werror
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# Sum up the flags.
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DEPCXXFLAGS := -O0 ${DEPWARNFLAGS} ${DBGCXXFLAGS} ${OPTCXXFLAGS} -std=c++0x
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# Linker flags.
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LDFLAGS := -Wall -lstdc++
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##########################################
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# Xerces settings
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##########################################
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XERCES_ROOT ?= /usr
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XERCES_INC := $(XERCES_ROOT)/include
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XERCES_LIB := $(XERCES_ROOT)/lib
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XERCES_LDFLAGS := -L$(XERCES_LIB) -lxerces-c
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##########################################
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# Targets
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##########################################
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all: ${BINARY} src/libdrampower.a parserlib traces
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$(BINARY): ${XMLPARSEROBJECTS} ${CLIOBJECTS} src/libdrampower.a
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$(CXX) ${CXXFLAGS} $(LDFLAGS) -o $@ $^ -Lsrc/ $(XERCES_LDFLAGS) -ldrampower
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# From .cpp to .o. Dependency files are generated here
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%.o: %.cc
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$(CXX) ${CXXFLAGS} -MMD -MF $(subst .o,.d,$@) -iquote src -o $@ -c $<
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src/libdrampower.a: ${LIBOBJECTS}
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ar -cvr src/libdrampower.a ${LIBOBJECTS}
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parserlib: ${XMLPARSEROBJECTS}
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ar -cvr src/libdrampowerxml.a ${XMLPARSEROBJECTS}
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clean:
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$(RM) $(ALLOBJECTS) $(DEPENDENCIES) $(BINARY) $(LIBS)
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$(MAKE) -C test/libdrampowertest clean
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$(RM) traces.zip
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coverageclean:
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$(RM) ${ALLSOURCES:.cc=.gcno} ${ALLSOURCES:.cc=.gcda}
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$(MAKE) -C test/libdrampowertest coverageclean
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pretty:
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uncrustify -c src/uncrustify.cfg $(ALLSOURCES) --no-backup
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uncrustify -c src/uncrustify.cfg $(ALLHEADERS) --no-backup
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test: traces
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python test/test.py -v
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traces.zip:
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wget --quiet --output-document=traces.zip https://github.com/Sv3n/DRAMPowerTraces/archive/master.zip
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traces: traces.zip
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unzip traces.zip && mkdir -p traces && mv DRAMPowerTraces-master/traces/* traces/ && rm -rf DRAMPowerTraces-master
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LCOV_OUTDIR = coverage_report
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coveragecheck: coveragecheckclean
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ifeq ($(CXX),g++)
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hash lcov 2>/dev/null || { echo >&2 "lcov could not be found. Aborting."; exit 1; }
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COVERAGE=1 $(MAKE) clean || { echo >&2 "make clean failed. Aborting."; exit 1; }
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COVERAGE=1 $(MAKE) || { echo >&2 "make failed. Aborting."; exit 1; }
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lcov --no-external -c -i -d . -o .coverage.base
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COVERAGE=1 $(MAKE) test || { echo >&2 "make test failed. Aborting."; exit 1; }
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lcov --no-external -c -d . -o .coverage.run
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lcov -d . -a .coverage.base -a .coverage.run -o .coverage.total
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genhtml -q --no-branch-coverage -o $(LCOV_OUTDIR) .coverage.total
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rm -f .coverage.base .coverage.run .coverage.total
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else
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@{ echo >&2 "The coveragecheck rule is not implemented for $(CXX). Aborting."; exit 1; }
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endif
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coveragecheckclean:
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rm -rf $(LCOV_OUTDIR)
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-include $(DEPENDENCIES)

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