[TLB & PTW - Rocketchip] Research the ptw and tlb microarchitecture and output the ppt.

[Jerryy959]

[Jerryy959]

https://carrv.github.io/2020/papers/CARRV2020_paper_11_Papadopoulos.pdf
This paper describes the TLB microarchitecture, valuable to understand.
Especially this figure,

You should combine this figure with rocketchip’s PTW code for understanding and reading.
Link this:
https://github.com/chipsalliance/rocket-chip/blob/master/src/main/scala/rocket/PTW.scala

Page Walker
Page Walker 是一个状态机，根据虚拟地址访问页表，访问规则与 RV 手册中相似，直到：

访问到 2MB 的节点，返回给 Last Level Page Walker，由 Last Level Page Walker 进行最后一级页表的访问
访问叶子节点，为大页（SuperPage），返回给一级 TLB
访问到非法节点，页表项的 v 位为 false 等
Page Walker 访存的结果会存到 Page Cache 中。 Page Walker 同时只能够处理一个请求，并且最多只访问前两级页表，访存能力较弱，原因在 Last Level Page Walker 节说明。

[Jerryy959]

TLB:
[1] TLB on Nutshell: https://oscpu.github.io/NutShell-doc/%E5%8A%9F%E8%83%BD%E9%83%A8%E4%BB%B6/tlb.html
[2] TLB on xiangshan: https://xiangshan-doc.readthedocs.io/zh-cn/latest/memory/mmu/mmu/

PTW:
[1] riscv-page-table-walk: https://www.francisz.cn/2021/02/20/riscv-page-table-walk/
[2] groups: https://groups.google.com/a/groups.riscv.org/g/sw-dev/c/nd4yruTpTj0
[3] PTW on xiangshan: https://xiangshan-doc.readthedocs.io/zh-cn/latest/memory/mmu/l2tlb/ 🌟

[Jerryy959]

Check out my keynote:
This will be reported at the next group meeting.

https://github.com/BOSC-Hvisor/Doc/blob/9a14dd1aa66bfa72a46d94fae880f441e2a9f508/Presentation/TLB_and_PTW.key

[Jerryy959]

TLB的工作原理：
https://pages.cs.wisc.edu/~remzi/OSTEP/Chinese/19.pdf

[Jerryy959]

虚拟存储器的讲解：
https://www.cnblogs.com/lyc-seu/p/16995924.html

[Jerryy959]

https://cgi.di.uoa.gr/~vkarakos/papers/fpl20_configurable_tlb_riscv-slides.pdf
https://www.kancloud.cn/wepeng/php/1172762
https://www.risc-v1.com/thread-1148-1-1.html