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‎.gitignore

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/tests/*.o
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/firmware/*.o
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/firmware/firmware.bin
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/firmware/firmware.elf
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/firmware/firmware.hex
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/firmware/firmware.map
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/dhrystone/dhry.bin
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/dhrystone/dhry.elf
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/dhrystone/dhry.hex
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/dhrystone/dhry.map
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/dhrystone/testbench.vvp
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/dhrystone/testbench.vcd
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/dhrystone/testbench_nola.vvp
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/dhrystone/testbench_nola.vcd
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/dhrystone/timing.vvp
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/dhrystone/timing.txt
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/dhrystone/*.d
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/dhrystone/*.o
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/riscv-gnu-toolchain-riscv32i
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/riscv-gnu-toolchain-riscv32ic
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/riscv-gnu-toolchain-riscv32im
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/riscv-gnu-toolchain-riscv32imc
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/testbench.vvp
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/testbench_wb.vvp
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/testbench_ez.vvp
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/testbench_sp.vvp
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/testbench_rvf.vvp
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/testbench_synth.vvp
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/testbench.gtkw
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/testbench.vcd
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/testbench.trace
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/testbench_verilator*
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/check.smt2
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/check.vcd
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/synth.log
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/synth.v
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.*.swp
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testbench_mod.vvp
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‎COL_IDCT.v

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module COL_IDCT( input clk,
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input signed [31:0] col_idct_ip[0:7],
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output signed [31:0] col_idct_op[0:8]
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);
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reg signed [31:0] x [0:8];
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reg signed [31:0] y [0:8];
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integer W1 = 2841;
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integer W2 = 2676;
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integer W3 = 2408;
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integer W5 = 1609;
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integer W6 = 1108;
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integer W7 = 565;
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assign col_idct_op [0:8] = y[0:8];
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always @(*)
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begin
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x[0] = col_idct_ip[0];
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x[1] = col_idct_ip[1];
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x[2] = col_idct_ip[2];
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x[3] = col_idct_ip[3];
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x[4] = col_idct_ip[4];
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x[5] = col_idct_ip[5];
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x[6] = col_idct_ip[6];
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x[7] = col_idct_ip[7];
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x[0] = (x[0] <<< 8) + 8192;
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x[8] = W7 * (x[4] + x[5]) + 4;
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x[4] = (x[8] + (W1 - W7) * x[4]) >>> 3;
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x[5] = (x[8] - (W1 + W7) * x[5]) >>> 3;
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x[8] = W3 * (x[6] + x[7]) + 4;
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x[6] = (x[8] - (W3 - W5) * x[6]) >>> 3;
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x[7] = (x[8] - (W3 + W5) * x[7]) >>> 3;
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x[8] = x[0] + x[1];
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x[0] = x[0]-x[1];
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x[1] = W6 * (x[3] + x[2]) + 4;
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x[2] = (x[1] - (W2 + W6) * x[2]) >>> 3;
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x[3] = (x[1] + (W2 - W6) * x[3]) >>> 3;
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x[1] = x[4] + x[6];
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x[4] = x[4]-x[6];
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x[6] = x[5] + x[7];
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x[5] = x[5]-x[7];
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x[7] = x[8] + x[3];
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x[8] = x[8]-x[3];
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x[3] = x[0] + x[2];
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x[0] = x[0]-x[2];
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x[2] = (181 * (x[4] + x[5]) + 128) >>> 8;
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x[4] = (181 * (x[4] - x[5]) + 128) >>> 8;
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y[0] = x[0];
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y[1] = x[1];
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y[2] = x[2];
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y[3] = x[3];
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y[4] = x[4];
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y[5] = x[5];
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y[6] = x[6];
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y[7] = x[7];
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y[8] = x[8];
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end
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endmodule

‎Makefile

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RISCV_GNU_TOOLCHAIN_GIT_REVISION = 411d134
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RISCV_GNU_TOOLCHAIN_INSTALL_PREFIX = /opt/riscv32
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# Give the user some easy overrides for local configuration quirks.
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# If you change one of these and it breaks, then you get to keep both pieces.
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SHELL = bash
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PYTHON = python3
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VERILATOR = verilator
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ICARUS_SUFFIX =
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IVERILOG = iverilog$(ICARUS_SUFFIX)
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VVP = vvp$(ICARUS_SUFFIX)
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TEST_OBJS = $(addsuffix .o,$(basename $(wildcard tests/*.S)))
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FIRMWARE_OBJS = firmware/start.o firmware/irq.o firmware/print.o firmware/hello.o firmware/sieve.o firmware/multest.o firmware/stats.o
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GCC_WARNS = -Werror -Wall -Wextra -Wshadow -Wundef -Wpointer-arith -Wcast-qual -Wcast-align -Wwrite-strings
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GCC_WARNS += -Wredundant-decls -Wstrict-prototypes -Wmissing-prototypes -pedantic # -Wconversion
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TOOLCHAIN_PREFIX = $(RISCV_GNU_TOOLCHAIN_INSTALL_PREFIX)i/bin/riscv32-unknown-elf-
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COMPRESSED_ISA = C
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# Add things like "export http_proxy=... https_proxy=..." here
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GIT_ENV = true
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test_mod: testbench_mod.vvp firmware/firmware.hex
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$(VVP) -N $<
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test: testbench.vvp firmware/firmware.hex
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$(VVP) -N $<
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test_vcd: testbench.vvp firmware/firmware.hex
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$(VVP) -N $< +vcd +trace +noerror
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test_rvf: testbench_rvf.vvp firmware/firmware.hex
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$(VVP) -N $< +vcd +trace +noerror
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test_wb: testbench_wb.vvp firmware/firmware.hex
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$(VVP) -N $<
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test_wb_vcd: testbench_wb.vvp firmware/firmware.hex
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$(VVP) -N $< +vcd +trace +noerror
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test_ez: testbench_ez.vvp
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$(VVP) -N $<
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test_ez_vcd: testbench_ez.vvp
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$(VVP) -N $< +vcd
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test_sp: testbench_sp.vvp firmware/firmware.hex
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$(VVP) -N $<
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test_axi: testbench.vvp firmware/firmware.hex
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$(VVP) -N $< +axi_test
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test_synth: testbench_synth.vvp firmware/firmware.hex
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$(VVP) -N $<
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test_verilator: testbench_verilator firmware/firmware.hex
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./testbench_verilator
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testbench.vvp: testbench.v picorv32.v
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$(IVERILOG) -o $@ $(subst C,-DCOMPRESSED_ISA,$(COMPRESSED_ISA)) $^
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chmod -x $@
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testbench_mod.vvp: testbench_mod.v axi4_mem_periph.v picorv32.v ROW_IDCT.v COL_IDCT.v
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$(IVERILOG) -o $@ $(subst C,-DCOMPRESSED_ISA,$(COMPRESSED_ISA)) $^
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chmod -x $@
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testbench_rvf.vvp: testbench.v picorv32.v rvfimon.v
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$(IVERILOG) -o $@ -D RISCV_FORMAL $(subst C,-DCOMPRESSED_ISA,$(COMPRESSED_ISA)) $^
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chmod -x $@
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testbench_wb.vvp: testbench_wb.v picorv32.v
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$(IVERILOG) -o $@ $(subst C,-DCOMPRESSED_ISA,$(COMPRESSED_ISA)) $^
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chmod -x $@
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testbench_ez.vvp: testbench_ez.v picorv32.v
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$(IVERILOG) -o $@ $(subst C,-DCOMPRESSED_ISA,$(COMPRESSED_ISA)) $^
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chmod -x $@
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testbench_sp.vvp: testbench.v picorv32.v
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$(IVERILOG) -o $@ $(subst C,-DCOMPRESSED_ISA,$(COMPRESSED_ISA)) -DSP_TEST $^
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chmod -x $@
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testbench_synth.vvp: testbench.v synth.v
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$(IVERILOG) -o $@ -DSYNTH_TEST $^
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chmod -x $@
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testbench_verilator: testbench_mod.v picorv32.v axi4_mem_periph.v testbench.cc
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$(VERILATOR) --cc --exe -Wno-lint -trace --top-module picorv32_wrapper testbench_mod.v picorv32.v axi4_mem_periph.v testbench.cc \
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$(subst C,-DCOMPRESSED_ISA,$(COMPRESSED_ISA)) --Mdir testbench_verilator_dir
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$(MAKE) -C testbench_verilator_dir -f Vpicorv32_wrapper.mk
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cp testbench_verilator_dir/Vpicorv32_wrapper testbench_verilator
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check: check-yices
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check-%: check.smt2
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yosys-smtbmc -s $(subst check-,,$@) -t 30 --dump-vcd check.vcd check.smt2
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yosys-smtbmc -s $(subst check-,,$@) -t 25 --dump-vcd check.vcd -i check.smt2
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check.smt2: picorv32.v
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yosys -v2 -p 'read_verilog -formal picorv32.v' \
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-p 'prep -top picorv32 -nordff' \
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-p 'assertpmux -noinit; opt -fast' \
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-p 'write_smt2 -wires check.smt2'
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synth.v: picorv32.v scripts/yosys/synth_sim.ys
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yosys -qv3 -l synth.log scripts/yosys/synth_sim.ys
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# Changing below to use 512k RAM
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firmware/firmware.hex: firmware/firmware.bin firmware/makehex.py
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$(PYTHON) firmware/makehex.py $< 524288 > $@
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firmware/firmware.bin: firmware/firmware.elf
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$(TOOLCHAIN_PREFIX)objcopy -O binary $< $@
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chmod -x $@
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firmware/firmware.elf: $(FIRMWARE_OBJS) $(TEST_OBJS) firmware/sections.lds firmware/nanojpeg.c
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$(TOOLCHAIN_PREFIX)gcc -Os -ffreestanding -nostdlib -o $@ \
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-Wl,-Bstatic,-T,firmware/sections.lds,-Map,firmware/firmware.map,--strip-debug \
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$(FIRMWARE_OBJS) $(TEST_OBJS) -lgcc
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chmod -x $@
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firmware/start.o: firmware/start.S
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$(TOOLCHAIN_PREFIX)gcc -c -march=rv32im$(subst C,c,$(COMPRESSED_ISA)) -o $@ $<
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firmware/%.o: firmware/%.c
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$(TOOLCHAIN_PREFIX)gcc -c -march=rv32i$(subst C,c,$(COMPRESSED_ISA)) -Os --std=c99 $(GCC_WARNS) -ffreestanding -nostdlib -o $@ $<
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tests/%.o: tests/%.S tests/riscv_test.h tests/test_macros.h
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$(TOOLCHAIN_PREFIX)gcc -c -march=rv32im -o $@ -DTEST_FUNC_NAME=$(notdir $(basename $<)) \
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-DTEST_FUNC_TXT='"$(notdir $(basename $<))"' -DTEST_FUNC_RET=$(notdir $(basename $<))_ret $<
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download-tools:
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sudo bash -c 'set -ex; mkdir -p /var/cache/distfiles; $(GIT_ENV); \
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$(foreach REPO,riscv-gnu-toolchain riscv-binutils-gdb riscv-gcc riscv-glibc riscv-newlib, \
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if ! test -d /var/cache/distfiles/$(REPO).git; then rm -rf /var/cache/distfiles/$(REPO).git.part; \
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git clone --bare https://github.com/riscv/$(REPO) /var/cache/distfiles/$(REPO).git.part; \
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mv /var/cache/distfiles/$(REPO).git.part /var/cache/distfiles/$(REPO).git; else \
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(cd /var/cache/distfiles/$(REPO).git; git fetch https://github.com/riscv/$(REPO)); fi;)'
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define build_tools_template
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build-$(1)-tools:
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@read -p "This will remove all existing data from $(RISCV_GNU_TOOLCHAIN_INSTALL_PREFIX)$(subst riscv32,,$(1)). Type YES to continue: " reply && [[ "$$$$reply" == [Yy][Ee][Ss] || "$$$$reply" == [Yy] ]]
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sudo bash -c "set -ex; rm -rf $(RISCV_GNU_TOOLCHAIN_INSTALL_PREFIX)$(subst riscv32,,$(1)); mkdir -p $(RISCV_GNU_TOOLCHAIN_INSTALL_PREFIX)$(subst riscv32,,$(1)); chown $$$${USER}: $(RISCV_GNU_TOOLCHAIN_INSTALL_PREFIX)$(subst riscv32,,$(1))"
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+$(MAKE) build-$(1)-tools-bh
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build-$(1)-tools-bh:
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+set -ex; $(GIT_ENV); \
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if [ -d /var/cache/distfiles/riscv-gnu-toolchain.git ]; then reference_riscv_gnu_toolchain="--reference /var/cache/distfiles/riscv-gnu-toolchain.git"; else reference_riscv_gnu_toolchain=""; fi; \
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if [ -d /var/cache/distfiles/riscv-binutils-gdb.git ]; then reference_riscv_binutils_gdb="--reference /var/cache/distfiles/riscv-binutils-gdb.git"; else reference_riscv_binutils_gdb=""; fi; \
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if [ -d /var/cache/distfiles/riscv-gcc.git ]; then reference_riscv_gcc="--reference /var/cache/distfiles/riscv-gcc.git"; else reference_riscv_gcc=""; fi; \
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if [ -d /var/cache/distfiles/riscv-glibc.git ]; then reference_riscv_glibc="--reference /var/cache/distfiles/riscv-glibc.git"; else reference_riscv_glibc=""; fi; \
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if [ -d /var/cache/distfiles/riscv-newlib.git ]; then reference_riscv_newlib="--reference /var/cache/distfiles/riscv-newlib.git"; else reference_riscv_newlib=""; fi; \
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rm -rf riscv-gnu-toolchain-$(1); git clone $$$$reference_riscv_gnu_toolchain https://github.com/riscv/riscv-gnu-toolchain riscv-gnu-toolchain-$(1); \
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cd riscv-gnu-toolchain-$(1); git checkout $(RISCV_GNU_TOOLCHAIN_GIT_REVISION); \
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git submodule update --init $$$$reference_riscv_binutils_gdb riscv-binutils; \
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git submodule update --init $$$$reference_riscv_binutils_gdb riscv-gdb; \
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git submodule update --init $$$$reference_riscv_gcc riscv-gcc; \
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git submodule update --init $$$$reference_riscv_glibc riscv-glibc; \
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git submodule update --init $$$$reference_riscv_newlib riscv-newlib; \
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mkdir build; cd build; ../configure --with-arch=$(2) --prefix=$(RISCV_GNU_TOOLCHAIN_INSTALL_PREFIX)$(subst riscv32,,$(1)); make
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.PHONY: build-$(1)-tools
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endef
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$(eval $(call build_tools_template,riscv32i,rv32i))
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$(eval $(call build_tools_template,riscv32ic,rv32ic))
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$(eval $(call build_tools_template,riscv32im,rv32im))
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$(eval $(call build_tools_template,riscv32imc,rv32imc))
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build-tools:
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@echo "This will remove all existing data from $(RISCV_GNU_TOOLCHAIN_INSTALL_PREFIX)i, $(RISCV_GNU_TOOLCHAIN_INSTALL_PREFIX)ic, $(RISCV_GNU_TOOLCHAIN_INSTALL_PREFIX)im, and $(RISCV_GNU_TOOLCHAIN_INSTALL_PREFIX)imc."
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@read -p "Type YES to continue: " reply && [[ "$$reply" == [Yy][Ee][Ss] || "$$reply" == [Yy] ]]
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sudo bash -c "set -ex; rm -rf $(RISCV_GNU_TOOLCHAIN_INSTALL_PREFIX){i,ic,im,imc}; mkdir -p $(RISCV_GNU_TOOLCHAIN_INSTALL_PREFIX){i,ic,im,imc}; chown $${USER}: $(RISCV_GNU_TOOLCHAIN_INSTALL_PREFIX){i,ic,im,imc}"
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+$(MAKE) build-riscv32i-tools-bh
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+$(MAKE) build-riscv32ic-tools-bh
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+$(MAKE) build-riscv32im-tools-bh
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+$(MAKE) build-riscv32imc-tools-bh
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toc:
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gawk '/^-+$$/ { y=tolower(x); gsub("[^a-z0-9]+", "-", y); gsub("-$$", "", y); printf("- [%s](#%s)\n", x, y); } { x=$$0; }' README.md
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clean:
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rm -rf riscv-gnu-toolchain-riscv32i riscv-gnu-toolchain-riscv32ic \
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riscv-gnu-toolchain-riscv32im riscv-gnu-toolchain-riscv32imc
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rm -vrf $(FIRMWARE_OBJS) $(TEST_OBJS) check.smt2 check.vcd synth.v synth.log \
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firmware/firmware.elf firmware/firmware.bin firmware/firmware.hex firmware/firmware.map \
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testbench.vvp testbench_sp.vvp testbench_synth.vvp testbench_ez.vvp \
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testbench_rvf.vvp testbench_wb.vvp testbench.vcd testbench.trace \
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testbench_verilator testbench_verilator_dir
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.PHONY: test test_vcd test_sp test_axi test_wb test_wb_vcd test_ez test_ez_vcd test_synth download-tools build-tools toc clean

‎README.md

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# Template project
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This is a template project for the course EE2003 at IIT Madras.
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*Note*: This is a forked repository of PicoRV32 - the original README is available at [[README_picorv32.md]].
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Acknowledgements:
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- [PicoRV32](https://github.com/YosysHQ/picorv32) - from C. Wolf (YosysHQ).
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- [NanoJPEG](https://keyj.emphy.de/nanojpeg/)
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## Problem statement
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This is a "starter" project that you can use in case you are unable to define a project of your own. It includes the code for the [nanojpeg](https://keyj.emphy.de/nanojpeg/) decoder, with some modifications so that it can be run under the constrained environment of the picorv processor.
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This means that you do not have access to things like File Input/Output, memory management (`malloc` etc.) or `printf` style statements that you can usually use for debugging.
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To get around these the code has the following additions:
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- A set of functions have been defined in `njmem.c` that can allocate memory for random use. It uses a very trivial form of memory allocation that only works because our program never needs to `free` memory and try to use it again later. A set of addresses starting at `0x40000000` are defined for use with the memory management.
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- A set of addresses starting from `0x30000000` are defined for reading from the file. You first need to run a pre-processing script (`firmware/jpg2hex.py`) to generate the file `firmware/jpg.hex` which will be mapped to this memory range. This is marked as a read-only memory, so you can only read from that range of addresses. Since the file size cannot be read this way, the script also puts the size of the file as an `int` in the first 4 bytes of the memory range.
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- Writing to the address `0x20000000` will result in dumping the appropriate byte into the file `output.dump`. This means that you can use this to do the equivalent of a `fwrite` function in C. However, the filename is always fixed as it cannot be changed from the C program.
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- There are also two functions defined in `hello.c` that can be used to read out the number of cycles from the CPU at any point. This can be used, for example, to find out the time taken by the `njDecode` function. More importantly, you can use a similar technique inside your code to get the time taken for other functions and find out which ones take the longest to run.
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You will need to read through the code changes in `axi4_mem_periph.v` and `hello.c` etc. in order to understand how all these work. You will need to understand them properly in order to make any changes or improvements in the code.
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## How to run
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### Step 1 - Generate a suitable input
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The code comes with sample data in `firmware/jpg.hex` - this corresponds to the input file `firmware/k8x8.jpg`. The hex file is generated as follows:
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```sh
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$ cd firmware
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$ python3 jpg2hex.py k8x8.jpg > jpg.hex
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```
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You can replace `k8x8.jpg` with some other JPEG file to try with that. Note that the system has an overall memory limitation so any file larger than about 100x100 will most likely run into problems.
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### Step 2.1 - Build and run with iverilog
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```sh
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$ make
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```
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Just typing the above command (while you are in the `nanojpeg` folder, not inside one of the subfolders) will take care of compiling and running with iverilog.
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**WARNING**: This is *horrendously* slow - it takes about 6-7 *minutes* to run on the default input file, which is just a single JPEG macroblock and the entire image is of size 8 pixels by 7 pixels.
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Therefore if you try this with another file (say `kitten.jpg`, which is 24x22 macroblocks in size), you can expect it to take more than 3000 minutes -- that is, more than 2 days to run. Please do not try this on the EE2003 server - if the system shows excessive load it will be restarted more than once a day as needed, so simulations will almost certainly not run to completion.
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### Step 2.2 - Build and run with verilator
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Fortunately, there is a *much* faster verilog simulator called `verilator`. This works by first converting the Verilog code into C++, compiling it, and running the resulting executable. This can actually finish simulating the entire `kitten.jpg` input in less than 1 minute. If you want to test any changes to your code, you are strongly advised to use this approach.
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To run this, you can just type
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```sh
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$ make test_verilator
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```
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This is already set up to take the exact same inputs and generate the same output.
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### Step 3 - understand the results
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When you run the code, you will see that it generates a file named `output.dump` in the main `nanojpeg` folder. You can rename this file as `output.ppm`, and then it should be possible to view this file. Note that you cannot view it on the server, you will need to download the file to your local machine and then view it.
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The default input will generate an image of a kitten that is 8x7 pixels in size -- in other words, if you recognize it as a kitten, you have a very good imagination. Instead, the actual output generated by running the converter on another PC is also available in the file `firmware/k8x8.ppm`.
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Note that there is currently a bug in the code that results in one extra byte being added to the output. This means that you cannot directly compare the two files to check for correctness. However, if you use the command
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```sh
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$ xxd output.dump
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```
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it will dump out the hex formatted output, and here you can see that it matches the original except for the last byte.
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## What to do next
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The present code not only runs the decoder, it also prints out the total number of clock cycles taken for the code to run. The fact that it is slow in simulation is not relevant, so do not try to speed that up. Instead, your goal should be to identify where the bottleneck is in the existing code, and to see if there are parts of it that can be accelerated in hardware.
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Converting the entire code to hardware is not just difficult, it is also probably a bad idea, since there is a lot of conditional logic which is well suited to software, but will result in very bad and irregularly structured hardware.
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On the other hand, certain blocks (in particular the DCT computations) are well suited to hardware implementation. So if you can create a module (similar to the seq_mult in assignment 1) that takes in appropriate inputs, does the computations in hardware and returns the results, there is a chance that you may speed things up.
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Why only a chance? Because the transfer of data into and out of the hardware module will require the CPU to do read/write or load/store operations. It is quite possible that depending on how this is done, it may end up taking longer in hardware than to just do the computations in software.
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You will need to *instrument* your code to find out where your changes will be most effective - that is, put in appropriate `get_num_cycles` calls in places where you can trace the time taken.
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## Alternative ideas
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This is, as explained at the beginning, just a *starter* project. You are welcome to build on this in any way you want, or even completely ignore it and do another project of your own. For such projects, you are of course expected to run the ideas past the course instructor to ensure that your project idea is feasible and reasonable for the requirements of the course.

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