forked from dotnet/runtime
-
Notifications
You must be signed in to change notification settings - Fork 0
/
Copy pathhwintrinsiccodegenxarch.cpp
3097 lines (2669 loc) · 107 KB
/
hwintrinsiccodegenxarch.cpp
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
// Licensed to the .NET Foundation under one or more agreements.
// The .NET Foundation licenses this file to you under the MIT license.
/*XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
XX XX
XX Intel hardware intrinsic Code Generator XX
XX XX
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
*/
#include "jitpch.h"
#ifdef _MSC_VER
#pragma hdrstop
#endif
#ifdef FEATURE_HW_INTRINSICS
#include "emit.h"
#include "codegen.h"
#include "sideeffects.h"
#include "lower.h"
#include "gcinfo.h"
#include "gcinfoencoder.h"
//------------------------------------------------------------------------
// assertIsContainableHWIntrinsicOp: Asserts that op is containable by node
//
// Arguments:
// lowering - The lowering phase from the compiler
// containingNode - The HWIntrinsic node that has the contained node
// containedNode - The node that is contained
//
static void assertIsContainableHWIntrinsicOp(Lowering* lowering,
GenTreeHWIntrinsic* containingNode,
GenTree* containedNode)
{
#if DEBUG
// The Lowering::IsContainableHWIntrinsicOp call is not quite right, since it follows pre-register allocation
// logic. However, this check is still important due to the various containment rules that SIMD intrinsics follow.
//
// We use isContainable to track the special HWIntrinsic node containment rules (for things like LoadAligned and
// LoadUnaligned) and we use the supportsRegOptional check to support general-purpose loads (both from stack
// spillage and for isUsedFromMemory contained nodes, in the case where the register allocator decided to not
// allocate a register in the first place).
GenTree* node = containedNode;
// Now that we are doing full memory containment safety checks, we can't properly check nodes that are not
// linked into an evaluation tree, like the special nodes we create in genHWIntrinsic.
// So, just say those are ok.
//
if (node->gtNext == nullptr)
{
return;
}
bool supportsRegOptional = false;
bool isContainable = lowering->IsContainableHWIntrinsicOp(containingNode, node, &supportsRegOptional);
assert(isContainable || supportsRegOptional);
#endif // DEBUG
}
//------------------------------------------------------------------------
// genIsTableDrivenHWIntrinsic:
//
// Arguments:
// category - category of a HW intrinsic
//
// Return Value:
// returns true if this category can be table-driven in CodeGen
//
static bool genIsTableDrivenHWIntrinsic(NamedIntrinsic intrinsicId, HWIntrinsicCategory category)
{
// TODO - make more categories to the table-driven framework
// HW_Category_Helper and HW_Flag_MultiIns/HW_Flag_SpecialCodeGen usually need manual codegen
const bool tableDrivenCategory =
(category != HW_Category_Special) && (category != HW_Category_Scalar) && (category != HW_Category_Helper);
const bool tableDrivenFlag =
!HWIntrinsicInfo::GeneratesMultipleIns(intrinsicId) && !HWIntrinsicInfo::HasSpecialCodegen(intrinsicId);
return tableDrivenCategory && tableDrivenFlag;
}
//------------------------------------------------------------------------
// AddEmbRoundingMode: Adds the embedded rounding mode to the insOpts
//
// Arguments:
// instOptions - The existing insOpts
// mode - The embedded rounding mode to add to instOptions
//
// Return Value:
// The modified insOpts
//
static insOpts AddEmbRoundingMode(insOpts instOptions, int8_t mode)
{
// The full rounding mode is a bitmask in the shape of:
// * RC: 2-bit rounding control
// * RS: 1-bit rounding select
// * P: 1-bit precision mask
// * 4-bit reserved
//
// The embedded rounding form assumes that P is 1, indicating
// that floating-point exceptions should not be raised and also
// assumes that RS is 0, indicating that MXCSR.RC is ignored.
//
// Given that the user is specifying a rounding mode and that
// .NET doesn't support raising IEEE 754 floating-point exceptions,
// we simplify the handling below to only consider the 2-bits of RC.
assert((instOptions & INS_OPTS_EVEX_b_MASK) == 0);
unsigned result = static_cast<unsigned>(instOptions);
switch (mode & 0x03)
{
case 0x01:
{
result |= INS_OPTS_EVEX_eb_er_rd;
break;
}
case 0x02:
{
result |= INS_OPTS_EVEX_er_ru;
break;
}
case 0x03:
{
result |= INS_OPTS_EVEX_er_rz;
break;
}
default:
{
break;
}
}
return static_cast<insOpts>(result);
}
//------------------------------------------------------------------------
// AddEmbMaskingMode: Adds the embedded masking mode to the insOpts
//
// Arguments:
// instOptions - The existing insOpts
// maskReg - The register to use for the embedded mask
// mergeWithZero - true if the mask merges with zero; otherwise, false
//
// Return Value:
// The modified insOpts
//
static insOpts AddEmbMaskingMode(insOpts instOptions, regNumber maskReg, bool mergeWithZero)
{
assert((instOptions & INS_OPTS_EVEX_aaa_MASK) == 0);
assert((instOptions & INS_OPTS_EVEX_z_MASK) == 0);
unsigned result = static_cast<unsigned>(instOptions);
unsigned em_k = (maskReg - KBASE) << 2;
unsigned em_z = mergeWithZero ? INS_OPTS_EVEX_em_zero : 0;
assert(emitter::isMaskReg(maskReg));
assert((em_k & INS_OPTS_EVEX_aaa_MASK) == em_k);
result |= em_k;
result |= em_z;
return static_cast<insOpts>(result);
}
//------------------------------------------------------------------------
// genHWIntrinsic: Generates the code for a given hardware intrinsic node.
//
// Arguments:
// node - The hardware intrinsic node
//
void CodeGen::genHWIntrinsic(GenTreeHWIntrinsic* node)
{
NamedIntrinsic intrinsicId = node->GetHWIntrinsicId();
CORINFO_InstructionSet isa = HWIntrinsicInfo::lookupIsa(intrinsicId);
HWIntrinsicCategory category = HWIntrinsicInfo::lookupCategory(intrinsicId);
size_t numArgs = node->GetOperandCount();
GenTree* embMaskOp = nullptr;
// We need to validate that other phases of the compiler haven't introduced unsupported intrinsics
assert(compiler->compIsaSupportedDebugOnly(isa));
assert(HWIntrinsicInfo::RequiresCodegen(intrinsicId));
bool isTableDriven = genIsTableDrivenHWIntrinsic(intrinsicId, category);
insOpts instOptions = INS_OPTS_NONE;
if (GetEmitter()->UseEvexEncoding())
{
if (numArgs == 3)
{
GenTree* op2 = node->Op(2);
if (op2->IsEmbMaskOp())
{
assert(intrinsicId == NI_AVX512F_BlendVariableMask);
assert(op2->isContained());
assert(op2->OperIsHWIntrinsic());
// We currently only support this for table driven intrinsics
assert(isTableDriven);
GenTree* op1 = node->Op(1);
GenTree* op3 = node->Op(3);
regNumber targetReg = node->GetRegNum();
regNumber mergeReg = op1->GetRegNum();
regNumber maskReg = op3->GetRegNum();
// TODO-AVX512-CQ: Ensure we can support embedded operations on RMW intrinsics
assert(!op2->isRMWHWIntrinsic(compiler));
bool mergeWithZero = op1->isContained();
if (mergeWithZero)
{
// We're merging with zero, so we the target register isn't RMW
assert(op1->IsVectorZero());
mergeWithZero = true;
}
else
{
// We're merging with a non-zero value, so the target register is RMW
emitAttr attr = emitActualTypeSize(Compiler::getSIMDTypeForSize(node->GetSimdSize()));
GetEmitter()->emitIns_Mov(INS_movaps, attr, targetReg, mergeReg, /* canSkip */ true);
}
// Update op2 to use the actual target register
op2->ClearContained();
op2->SetRegNum(targetReg);
// Fixup all the already initialized variables
node = op2->AsHWIntrinsic();
intrinsicId = node->GetHWIntrinsicId();
isa = HWIntrinsicInfo::lookupIsa(intrinsicId);
category = HWIntrinsicInfo::lookupCategory(intrinsicId);
numArgs = node->GetOperandCount();
// Add the embedded masking info to the insOpts
instOptions = AddEmbMaskingMode(instOptions, maskReg, mergeWithZero);
// We don't need to genProduceReg(node) since that will be handled by processing op2
// likewise, processing op2 will ensure its own registers are consumed
// Make sure we consume the registers that are getting specially handled
genConsumeReg(op1);
embMaskOp = op3;
}
}
if (HWIntrinsicInfo::IsEmbRoundingCompatible(intrinsicId))
{
assert(isTableDriven);
size_t expectedArgNum = HWIntrinsicInfo::EmbRoundingArgPos(intrinsicId);
if (numArgs == expectedArgNum)
{
GenTree* lastOp = node->Op(numArgs);
// Now that we've extracted the rounding mode, we'll remove the
// last operand, adjust the arg count, and continue. This allows
// us to reuse all the existing logic without having to add new
// specialized handling everywhere.
switch (numArgs)
{
case 3:
{
numArgs = 2;
node->ResetHWIntrinsicId(intrinsicId, compiler, node->Op(1), node->Op(2));
break;
}
default:
{
unreached();
}
}
if (lastOp->isContained())
{
assert(lastOp->IsCnsIntOrI());
int8_t mode = static_cast<int8_t>(lastOp->AsIntCon()->IconValue());
instOptions = AddEmbRoundingMode(instOptions, mode);
}
else
{
var_types baseType = node->GetSimdBaseType();
instruction ins = HWIntrinsicInfo::lookupIns(intrinsicId, baseType);
assert(ins != INS_invalid);
emitAttr simdSize = emitActualTypeSize(Compiler::getSIMDTypeForSize(node->GetSimdSize()));
assert(simdSize != 0);
genConsumeMultiOpOperands(node);
genConsumeRegs(lastOp);
switch (numArgs)
{
case 2:
{
auto emitSwCase = [&](int8_t i) {
insOpts newInstOptions = AddEmbRoundingMode(instOptions, i);
genHWIntrinsic_R_R_RM(node, ins, simdSize, newInstOptions);
};
regNumber baseReg = node->ExtractTempReg();
regNumber offsReg = node->GetSingleTempReg();
genHWIntrinsicJumpTableFallback(intrinsicId, lastOp->GetRegNum(), baseReg, offsReg,
emitSwCase);
break;
}
default:
{
unreached();
}
}
genProduceReg(node);
return;
}
}
}
}
if (isTableDriven)
{
regNumber targetReg = node->GetRegNum();
var_types baseType = node->GetSimdBaseType();
GenTree* op1 = nullptr;
GenTree* op2 = nullptr;
GenTree* op3 = nullptr;
GenTree* op4 = nullptr;
regNumber op1Reg = REG_NA;
regNumber op2Reg = REG_NA;
regNumber op3Reg = REG_NA;
regNumber op4Reg = REG_NA;
emitter* emit = GetEmitter();
assert(numArgs >= 0);
instruction ins = HWIntrinsicInfo::lookupIns(intrinsicId, baseType);
assert(ins != INS_invalid);
emitAttr simdSize = emitActualTypeSize(Compiler::getSIMDTypeForSize(node->GetSimdSize()));
assert(simdSize != 0);
int ival = HWIntrinsicInfo::lookupIval(compiler, intrinsicId, baseType);
switch (numArgs)
{
case 1:
{
op1 = node->Op(1);
if (node->OperIsMemoryLoad())
{
genConsumeAddress(op1);
// Until we improve the handling of addressing modes in the emitter, we'll create a
// temporary GT_IND to generate code with.
GenTreeIndir load = indirForm(node->TypeGet(), op1);
emit->emitInsLoadInd(ins, simdSize, node->GetRegNum(), &load);
}
else
{
genConsumeRegs(op1);
op1Reg = op1->GetRegNum();
if (ival != -1)
{
assert((ival >= 0) && (ival <= 127));
if (HWIntrinsicInfo::CopiesUpperBits(intrinsicId))
{
assert(!op1->isContained());
emit->emitIns_SIMD_R_R_R_I(ins, simdSize, targetReg, op1Reg, op1Reg,
static_cast<int8_t>(ival));
}
else
{
genHWIntrinsic_R_RM_I(node, ins, simdSize, static_cast<int8_t>(ival));
}
}
else if (HWIntrinsicInfo::CopiesUpperBits(intrinsicId))
{
assert(!op1->isContained());
emit->emitIns_SIMD_R_R_R(ins, simdSize, targetReg, op1Reg, op1Reg);
}
else
{
genHWIntrinsic_R_RM(node, ins, simdSize, targetReg, op1);
}
}
break;
}
case 2:
{
op1 = node->Op(1);
op2 = node->Op(2);
if (category == HW_Category_MemoryStore)
{
genConsumeAddress(op1);
genConsumeReg(op2);
// Until we improve the handling of addressing modes in the emitter, we'll create a
// temporary GT_STORE_IND to generate code with.
GenTreeStoreInd store = storeIndirForm(node->TypeGet(), op1, op2);
emit->emitInsStoreInd(ins, simdSize, &store);
break;
}
genConsumeRegs(op1);
genConsumeRegs(op2);
op1Reg = op1->GetRegNum();
op2Reg = op2->GetRegNum();
if ((op1Reg != targetReg) && (op2Reg == targetReg) && node->isRMWHWIntrinsic(compiler))
{
// We have "reg2 = reg1 op reg2" where "reg1 != reg2" on a RMW intrinsic.
//
// For non-commutative intrinsics, we should have ensured that op2 was marked
// delay free in order to prevent it from getting assigned the same register
// as target. However, for commutative intrinsics, we can just swap the operands
// in order to have "reg2 = reg2 op reg1" which will end up producing the right code.
noway_assert(node->OperIsCommutative());
op2Reg = op1Reg;
op1Reg = targetReg;
}
if (ival != -1)
{
assert((ival >= 0) && (ival <= 127));
genHWIntrinsic_R_R_RM_I(node, ins, simdSize, static_cast<int8_t>(ival));
}
else if (category == HW_Category_MemoryLoad)
{
// Get the address and the 'other' register.
GenTree* addr;
regNumber otherReg;
if (intrinsicId == NI_AVX_MaskLoad || intrinsicId == NI_AVX2_MaskLoad)
{
addr = op1;
otherReg = op2Reg;
}
else
{
addr = op2;
otherReg = op1Reg;
}
// Until we improve the handling of addressing modes in the emitter, we'll create a
// temporary GT_IND to generate code with.
GenTreeIndir load = indirForm(node->TypeGet(), addr);
assert(!node->isRMWHWIntrinsic(compiler));
inst_RV_RV_TT(ins, simdSize, targetReg, otherReg, &load, false, instOptions);
}
else if (HWIntrinsicInfo::isImmOp(intrinsicId, op2))
{
auto emitSwCase = [&](int8_t i) {
if (HWIntrinsicInfo::CopiesUpperBits(intrinsicId))
{
assert(!op1->isContained());
emit->emitIns_SIMD_R_R_R_I(ins, simdSize, targetReg, op1Reg, op1Reg, i);
}
else
{
genHWIntrinsic_R_RM_I(node, ins, simdSize, i);
}
};
if (op2->IsCnsIntOrI())
{
ssize_t ival = op2->AsIntCon()->IconValue();
assert((ival >= 0) && (ival <= 255));
emitSwCase((int8_t)ival);
}
else
{
// We emit a fallback case for the scenario when the imm-op is not a constant.
// This should
// normally happen when the intrinsic is called indirectly, such as via
// Reflection. However, it
// can also occur if the consumer calls it directly and just doesn't pass a
// constant value.
regNumber baseReg = node->ExtractTempReg();
regNumber offsReg = node->GetSingleTempReg();
genHWIntrinsicJumpTableFallback(intrinsicId, op2Reg, baseReg, offsReg, emitSwCase);
}
}
else if (node->TypeGet() == TYP_VOID)
{
genHWIntrinsic_R_RM(node, ins, simdSize, op1Reg, op2);
}
else
{
genHWIntrinsic_R_R_RM(node, ins, simdSize, instOptions);
}
break;
}
case 3:
{
op1 = node->Op(1);
op2 = node->Op(2);
op3 = node->Op(3);
genConsumeRegs(op1);
op1Reg = op1->GetRegNum();
genConsumeRegs(op2);
op2Reg = op2->GetRegNum();
genConsumeRegs(op3);
op3Reg = op3->GetRegNum();
assert(ival == -1);
if (HWIntrinsicInfo::isImmOp(intrinsicId, op3))
{
auto emitSwCase = [&](int8_t i) { genHWIntrinsic_R_R_RM_I(node, ins, simdSize, i); };
if (op3->IsCnsIntOrI())
{
ssize_t ival = op3->AsIntCon()->IconValue();
assert((ival >= 0) && (ival <= 255));
emitSwCase((int8_t)ival);
}
else
{
// We emit a fallback case for the scenario when the imm-op is not a constant. This should
// normally happen when the intrinsic is called indirectly, such as via Reflection. However, it
// can also occur if the consumer calls it directly and just doesn't pass a constant value.
regNumber baseReg = node->ExtractTempReg();
regNumber offsReg = node->GetSingleTempReg();
genHWIntrinsicJumpTableFallback(intrinsicId, op3Reg, baseReg, offsReg, emitSwCase);
}
}
else if (category == HW_Category_MemoryStore)
{
// The Mask instructions do not currently support containment of the address.
assert(!op2->isContained());
if (intrinsicId == NI_AVX_MaskStore || intrinsicId == NI_AVX2_MaskStore)
{
emit->emitIns_AR_R_R(ins, simdSize, op2Reg, op3Reg, op1Reg, 0);
}
else
{
assert(intrinsicId == NI_SSE2_MaskMove);
assert(targetReg == REG_NA);
// SSE2 MaskMove hardcodes the destination (op3) in DI/EDI/RDI
emit->emitIns_Mov(INS_mov, EA_PTRSIZE, REG_EDI, op3Reg, /* canSkip */ true);
emit->emitIns_R_R(ins, simdSize, op1Reg, op2Reg);
}
}
else
{
switch (intrinsicId)
{
case NI_SSE41_BlendVariable:
case NI_AVX_BlendVariable:
case NI_AVX2_BlendVariable:
case NI_AVX512F_BlendVariableMask:
{
genHWIntrinsic_R_R_RM_R(node, ins, simdSize);
break;
}
case NI_AVXVNNI_MultiplyWideningAndAdd:
case NI_AVXVNNI_MultiplyWideningAndAddSaturate:
{
assert(targetReg != REG_NA);
assert(op1Reg != REG_NA);
assert(op2Reg != REG_NA);
genHWIntrinsic_R_R_R_RM(ins, simdSize, targetReg, op1Reg, op2Reg, op3);
break;
}
default:
{
unreached();
break;
};
}
}
break;
}
case 4:
{
op1 = node->Op(1);
op2 = node->Op(2);
op3 = node->Op(3);
op4 = node->Op(4);
genConsumeRegs(op1);
op1Reg = op1->GetRegNum();
genConsumeRegs(op2);
op2Reg = op2->GetRegNum();
genConsumeRegs(op3);
op3Reg = op3->GetRegNum();
genConsumeRegs(op4);
op4Reg = op4->GetRegNum();
assert(ival == -1);
if (HWIntrinsicInfo::isImmOp(intrinsicId, op4))
{
auto emitSwCase = [&](int8_t i) { genHWIntrinsic_R_R_R_RM_I(node, ins, simdSize, i); };
if (op4->IsCnsIntOrI())
{
ssize_t ival = op4->AsIntCon()->IconValue();
assert((ival >= 0) && (ival <= 255));
emitSwCase(static_cast<int8_t>(ival));
}
else
{
// We emit a fallback case for the scenario when the imm-op is not a constant. This should
// normally happen when the intrinsic is called indirectly, such as via Reflection. However, it
// can also occur if the consumer calls it directly and just doesn't pass a constant value.
regNumber baseReg = node->ExtractTempReg();
regNumber offsReg = node->GetSingleTempReg();
genHWIntrinsicJumpTableFallback(intrinsicId, op4Reg, baseReg, offsReg, emitSwCase);
}
}
else
{
unreached();
}
break;
}
default:
unreached();
break;
}
if (embMaskOp != nullptr)
{
// Handle an extra operand we need to consume so that
// embedded masking can work without making the overall
// logic significantly more complex.
genConsumeReg(embMaskOp);
}
genProduceReg(node);
return;
}
assert(embMaskOp == nullptr);
switch (isa)
{
case InstructionSet_Vector128:
case InstructionSet_Vector256:
case InstructionSet_Vector512:
genBaseIntrinsic(node);
break;
case InstructionSet_X86Base:
case InstructionSet_X86Base_X64:
genX86BaseIntrinsic(node);
break;
case InstructionSet_SSE:
case InstructionSet_SSE_X64:
genSSEIntrinsic(node, instOptions);
break;
case InstructionSet_SSE2:
case InstructionSet_SSE2_X64:
genSSE2Intrinsic(node, instOptions);
break;
case InstructionSet_SSE41:
case InstructionSet_SSE41_X64:
genSSE41Intrinsic(node);
break;
case InstructionSet_SSE42:
case InstructionSet_SSE42_X64:
genSSE42Intrinsic(node);
break;
case InstructionSet_AVX:
case InstructionSet_AVX2:
case InstructionSet_AVX512F:
case InstructionSet_AVX512F_VL:
case InstructionSet_AVX512F_X64:
case InstructionSet_AVX512BW:
case InstructionSet_AVX512BW_VL:
case InstructionSet_AVX512VBMI:
case InstructionSet_AVX512VBMI_VL:
genAvxFamilyIntrinsic(node, instOptions);
break;
case InstructionSet_AES:
genAESIntrinsic(node);
break;
case InstructionSet_BMI1:
case InstructionSet_BMI1_X64:
case InstructionSet_BMI2:
case InstructionSet_BMI2_X64:
genBMI1OrBMI2Intrinsic(node, instOptions);
break;
case InstructionSet_FMA:
genFMAIntrinsic(node);
break;
case InstructionSet_LZCNT:
case InstructionSet_LZCNT_X64:
genLZCNTIntrinsic(node);
break;
case InstructionSet_PCLMULQDQ:
genPCLMULQDQIntrinsic(node);
break;
case InstructionSet_POPCNT:
case InstructionSet_POPCNT_X64:
genPOPCNTIntrinsic(node);
break;
case InstructionSet_X86Serialize:
case InstructionSet_X86Serialize_X64:
genX86SerializeIntrinsic(node);
break;
default:
unreached();
break;
}
}
//------------------------------------------------------------------------
// genHWIntrinsic_R_RM: Generates code for a hardware intrinsic node that takes a
// register operand and a register/memory operand.
//
// Arguments:
// node - The hardware intrinsic node
// ins - The instruction being generated
// attr - The emit attribute for the instruction being generated
// reg - The register
// rmOp - The register/memory operand node
//
void CodeGen::genHWIntrinsic_R_RM(
GenTreeHWIntrinsic* node, instruction ins, emitAttr attr, regNumber reg, GenTree* rmOp)
{
emitter* emit = GetEmitter();
OperandDesc rmOpDesc = genOperandDesc(rmOp);
if (rmOpDesc.IsContained())
{
assert(HWIntrinsicInfo::SupportsContainment(node->GetHWIntrinsicId()));
assertIsContainableHWIntrinsicOp(compiler->m_pLowering, node, rmOp);
}
switch (rmOpDesc.GetKind())
{
case OperandKind::ClsVar:
emit->emitIns_R_C(ins, attr, reg, rmOpDesc.GetFieldHnd(), 0);
break;
case OperandKind::Local:
emit->emitIns_R_S(ins, attr, reg, rmOpDesc.GetVarNum(), rmOpDesc.GetLclOffset());
break;
case OperandKind::Indir:
{
// Until we improve the handling of addressing modes in the emitter, we'll create a
// temporary GT_IND to generate code with.
GenTreeIndir indirForm;
GenTreeIndir* indir = rmOpDesc.GetIndirForm(&indirForm);
emit->emitIns_R_A(ins, attr, reg, indir);
}
break;
case OperandKind::Reg:
{
regNumber rmOpReg = rmOpDesc.GetReg();
if (emit->IsMovInstruction(ins))
{
emit->emitIns_Mov(ins, attr, reg, rmOpReg, /* canSkip */ false);
}
else
{
if (varTypeIsIntegral(rmOp))
{
bool needsBroadcastFixup = false;
bool needsInstructionFixup = false;
switch (node->GetHWIntrinsicId())
{
case NI_AVX2_BroadcastScalarToVector128:
case NI_AVX2_BroadcastScalarToVector256:
{
if (varTypeIsSmall(node->GetSimdBaseType()))
{
if (compiler->compOpportunisticallyDependsOn(InstructionSet_AVX512BW_VL))
{
needsInstructionFixup = true;
}
else
{
needsBroadcastFixup = true;
}
}
else if (compiler->compOpportunisticallyDependsOn(InstructionSet_AVX512F_VL))
{
needsInstructionFixup = true;
}
else
{
needsBroadcastFixup = true;
}
break;
}
case NI_AVX512F_BroadcastScalarToVector512:
case NI_AVX512BW_BroadcastScalarToVector512:
{
needsInstructionFixup = true;
break;
}
default:
{
break;
}
}
if (needsBroadcastFixup)
{
// In lowering we had the special case of BroadcastScalarToVector(CreateScalarUnsafe(op1))
//
// This is one of the only instructions where it supports taking integer types from
// a SIMD register or directly as a scalar from memory. Most other instructions, in
// comparison, take such values from general-purpose registers instead.
//
// Because of this, we removed the CreateScalarUnsafe and tried to contain op1 directly
// that failed and we either didn't get marked regOptional or we did and didn't get spilled
//
// As such, we need to emulate the removed CreateScalarUnsafe to ensure that op1 is in a
// SIMD register so the broadcast instruction can execute succesfully. We'll just move
// the value into the target register and then broadcast it out from that.
emitAttr movdAttr = emitActualTypeSize(node->GetSimdBaseType());
emit->emitIns_Mov(INS_movd, movdAttr, reg, rmOpReg, /* canSkip */ false);
rmOpReg = reg;
}
else if (needsInstructionFixup)
{
switch (ins)
{
case INS_vpbroadcastb:
{
ins = INS_vpbroadcastb_gpr;
break;
}
case INS_vpbroadcastd:
{
ins = INS_vpbroadcastd_gpr;
break;
}
case INS_vpbroadcastq:
{
ins = INS_vpbroadcastq_gpr;
break;
}
case INS_vpbroadcastw:
{
ins = INS_vpbroadcastw_gpr;
break;
}
default:
{
unreached();
}
}
}
}
emit->emitIns_R_R(ins, attr, reg, rmOpReg);
}
break;
}
default:
unreached();
}
}
//------------------------------------------------------------------------
// genHWIntrinsic_R_RM_I: Generates the code for a hardware intrinsic node that takes a register/memory operand,
// an immediate operand, and that returns a value in register
//
// Arguments:
// node - The hardware intrinsic node
// ins - The instruction being generated
// ival - The immediate value
//
void CodeGen::genHWIntrinsic_R_RM_I(GenTreeHWIntrinsic* node, instruction ins, emitAttr simdSize, int8_t ival)
{
regNumber targetReg = node->GetRegNum();
GenTree* op1 = node->Op(1);
// TODO-XArch-CQ: Commutative operations can have op1 be contained
// TODO-XArch-CQ: Non-VEX encoded instructions can have both ops contained
assert(targetReg != REG_NA);
assert(!node->OperIsCommutative()); // One operand intrinsics cannot be commutative
if (op1->isContained() || op1->isUsedFromSpillTemp())
{
assert(HWIntrinsicInfo::SupportsContainment(node->GetHWIntrinsicId()));
assertIsContainableHWIntrinsicOp(compiler->m_pLowering, node, op1);
}
inst_RV_TT_IV(ins, simdSize, targetReg, op1, ival);
}
//------------------------------------------------------------------------
// genHWIntrinsic_R_R_RM: Generates the code for a hardware intrinsic node that takes a register operand, a
// register/memory operand, and that returns a value in register
//
// Arguments:
// node - The hardware intrinsic node
// ins - The instruction being generated
// attr - The emit attribute for the instruction being generated
// instOptions - The options that modify how the instruction is generated
//
void CodeGen::genHWIntrinsic_R_R_RM(GenTreeHWIntrinsic* node, instruction ins, emitAttr attr, insOpts instOptions)
{
regNumber targetReg = node->GetRegNum();
GenTree* op1 = node->Op(1);
GenTree* op2 = node->Op(2);
regNumber op1Reg = op1->GetRegNum();
assert(targetReg != REG_NA);
assert(op1Reg != REG_NA);
if (op2->isContained() || op2->isUsedFromSpillTemp())
{
assert(HWIntrinsicInfo::SupportsContainment(node->GetHWIntrinsicId()));
assertIsContainableHWIntrinsicOp(compiler->m_pLowering, node, op2);
}
bool isRMW = node->isRMWHWIntrinsic(compiler);
inst_RV_RV_TT(ins, attr, targetReg, op1Reg, op2, isRMW, instOptions);
}
//------------------------------------------------------------------------
// genHWIntrinsic_R_R_RM_I: Generates the code for a hardware intrinsic node that takes a register operand, a
// register/memory operand, an immediate operand, and that returns a value in register
//
// Arguments:
// node - The hardware intrinsic node
// ins - The instruction being generated
// ival - The immediate value
//
void CodeGen::genHWIntrinsic_R_R_RM_I(GenTreeHWIntrinsic* node, instruction ins, emitAttr simdSize, int8_t ival)
{
regNumber targetReg = node->GetRegNum();
GenTree* op1 = node->Op(1);
GenTree* op2 = node->Op(2);
regNumber op1Reg = op1->GetRegNum();
assert(targetReg != REG_NA);
if (op2->isContained() || op2->isUsedFromSpillTemp())
{
assert(HWIntrinsicInfo::SupportsContainment(node->GetHWIntrinsicId()));
assertIsContainableHWIntrinsicOp(compiler->m_pLowering, node, op2);
}
if (ins == INS_insertps)
{
if (op1Reg == REG_NA)
{
// insertps is special and can contain op1 when it is zero
assert(op1->isContained() && op1->IsVectorZero());
op1Reg = targetReg;
}
if (op2->isContained() && op2->IsVectorZero())
{
// insertps can also contain op2 when it is zero in which case
// we just reuse op1Reg since ival specifies the entry to zero