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emitarm.cpp
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// Licensed to the .NET Foundation under one or more agreements.
// The .NET Foundation licenses this file to you under the MIT license.
/*XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
XX XX
XX emitArm.cpp XX
XX XX
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
*/
#include "jitpch.h"
#ifdef _MSC_VER
#pragma hdrstop
#endif
#if defined(TARGET_ARM)
/*****************************************************************************/
/*****************************************************************************/
#include "instr.h"
#include "emit.h"
#include "codegen.h"
/*****************************************************************************/
const instruction emitJumpKindInstructions[] = {
INS_nop,
#define JMP_SMALL(en, rev, ins) INS_##ins,
#include "emitjmps.h"
};
const emitJumpKind emitReverseJumpKinds[] = {
EJ_NONE,
#define JMP_SMALL(en, rev, ins) EJ_##rev,
#include "emitjmps.h"
};
/*****************************************************************************
* Look up the instruction for a jump kind
*/
/*static*/ instruction emitter::emitJumpKindToIns(emitJumpKind jumpKind)
{
assert((unsigned)jumpKind < ArrLen(emitJumpKindInstructions));
return emitJumpKindInstructions[jumpKind];
}
/*****************************************************************************
* Look up the jump kind for an instruction. It better be a conditional
* branch instruction with a jump kind!
*/
/*static*/ emitJumpKind emitter::emitInsToJumpKind(instruction ins)
{
for (unsigned i = 0; i < ArrLen(emitJumpKindInstructions); i++)
{
if (ins == emitJumpKindInstructions[i])
{
emitJumpKind ret = (emitJumpKind)i;
assert(EJ_NONE < ret && ret < EJ_COUNT);
return ret;
}
}
unreached();
}
/*****************************************************************************
* Reverse the conditional jump
*/
/*static*/ emitJumpKind emitter::emitReverseJumpKind(emitJumpKind jumpKind)
{
assert(jumpKind < EJ_COUNT);
return emitReverseJumpKinds[jumpKind];
}
/*****************************************************************************
*
* Return the allocated size (in bytes) of the given instruction descriptor.
*/
size_t emitter::emitSizeOfInsDsc(instrDesc* id) const
{
if (emitIsSmallInsDsc(id))
return SMALL_IDSC_SIZE;
assert((unsigned)id->idInsFmt() < emitFmtCount);
ID_OPS idOp = (ID_OPS)emitFmtToOps[id->idInsFmt()];
bool isCallIns = (id->idIns() == INS_bl) || (id->idIns() == INS_blx);
bool maybeCallIns = (id->idIns() == INS_b) || (id->idIns() == INS_bx);
// An INS_call instruction may use a "fat" direct/indirect call descriptor
// except for a local call to a label (i.e. call to a finally).
// Only ID_OP_CALL and ID_OP_SPEC check for this, so we enforce that the
// INS_call instruction always uses one of these idOps.
assert(!isCallIns || // either not a call or
idOp == ID_OP_CALL || // is a direct call
idOp == ID_OP_SPEC || // is an indirect call
idOp == ID_OP_JMP); // is a local call to finally clause
switch (idOp)
{
case ID_OP_NONE:
break;
case ID_OP_JMP:
return sizeof(instrDescJmp);
case ID_OP_LBL:
return sizeof(instrDescLbl);
case ID_OP_CALL:
case ID_OP_SPEC:
assert(isCallIns || maybeCallIns);
if (id->idIsLargeCall())
{
/* Must be a "fat" indirect call descriptor */
return sizeof(instrDescCGCA);
}
else
{
assert(!id->idIsLargeDsp());
assert(!id->idIsLargeCns());
return sizeof(instrDesc);
}
break;
default:
NO_WAY("unexpected instruction descriptor format");
break;
}
if (id->idInsFmt() == IF_T2_N3)
{
assert((id->idIns() == INS_movw) || (id->idIns() == INS_movt));
return sizeof(instrDescReloc);
}
if (id->idIsLargeCns())
{
if (id->idIsLargeDsp())
return sizeof(instrDescCnsDsp);
else
return sizeof(instrDescCns);
}
else
{
if (id->idIsLargeDsp())
return sizeof(instrDescDsp);
else
return sizeof(instrDesc);
}
}
bool offsetFitsInVectorMem(int disp)
{
unsigned imm = unsigned_abs(disp);
return ((imm & 0x03fc) == imm);
}
#ifdef DEBUG
/*****************************************************************************
*
* The following called for each recorded instruction -- use for debugging.
*/
void emitter::emitInsSanityCheck(instrDesc* id)
{
/* What instruction format have we got? */
switch (id->idInsFmt())
{
case IF_T1_A: // T1_A ................
case IF_T2_A: // T2_A ................ ................
break;
case IF_T1_B: // T1_B ........cccc.... cond
case IF_T2_B: // T2_B ................ ............iiii imm4
assert(emitGetInsSC(id) < 0x10);
break;
case IF_T1_C: // T1_C .....iiiiinnnddd R1 R2 imm5
assert(isLowRegister(id->idReg1()));
assert(isLowRegister(id->idReg2()));
assert(insUnscaleImm(id->idIns(), emitGetInsSC(id)) < 0x20);
break;
case IF_T1_D0: // T1_D0 ........Dmmmmddd R1* R2*
assert(isGeneralRegister(id->idReg1()));
assert(isGeneralRegister(id->idReg2()));
break;
case IF_T1_D1: // T1_D1 .........mmmm... R1*
assert(isGeneralRegister(id->idReg1()));
break;
case IF_T1_D2: // T1_D2 .........mmmm... R3*
assert(isGeneralRegister(id->idReg3()));
break;
case IF_T1_E: // T1_E ..........nnnddd R1 R2
assert(isLowRegister(id->idReg1()));
assert(isLowRegister(id->idReg2()));
assert(id->idSmallCns() < 0x20);
break;
case IF_T1_F: // T1_F .........iiiiiii SP imm7
assert(id->idReg1() == REG_SP);
assert(id->idOpSize() == EA_4BYTE);
assert((emitGetInsSC(id) & ~0x1FC) == 0);
break;
case IF_T1_G: // T1_G .......iiinnnddd R1 R2 imm3
assert(isLowRegister(id->idReg1()));
assert(isLowRegister(id->idReg2()));
assert(id->idSmallCns() < 0x8);
break;
case IF_T1_H: // T1_H .......mmmnnnddd R1 R2 R3
assert(isLowRegister(id->idReg1()));
assert(isLowRegister(id->idReg2()));
assert(isLowRegister(id->idReg3()));
break;
case IF_T1_I: // T1_I ......i.iiiiiddd R1 imm6
assert(isLowRegister(id->idReg1()));
break;
case IF_T1_J0: // T1_J0 .....dddiiiiiiii R1 imm8
assert(isLowRegister(id->idReg1()));
assert(emitGetInsSC(id) < 0x100);
break;
case IF_T1_J1: // T1_J1 .....dddiiiiiiii R1 <regmask8>
assert(isLowRegister(id->idReg1()));
assert(emitGetInsSC(id) < 0x100);
break;
case IF_T1_J2: // T1_J2 .....dddiiiiiiii R1 SP imm8
assert(isLowRegister(id->idReg1()));
assert(id->idReg2() == REG_SP);
assert(id->idOpSize() == EA_4BYTE);
assert((emitGetInsSC(id) & ~0x3FC) == 0);
break;
case IF_T1_L0: // T1_L0 ........iiiiiiii imm8
assert(emitGetInsSC(id) < 0x100);
break;
case IF_T1_L1: // T1_L1 .......Rrrrrrrrr <regmask8+2>
assert(emitGetInsSC(id) < 0x400);
break;
case IF_T2_C0: // T2_C0 ...........Snnnn .iiiddddiishmmmm R1 R2 R3 S, imm5, sh
assert(isGeneralRegister(id->idReg1()));
assert(isGeneralRegister(id->idReg2()));
assert(isGeneralRegister(id->idReg3()));
assert(emitGetInsSC(id) < 0x20);
break;
case IF_T2_C4: // T2_C4 ...........Snnnn ....dddd....mmmm R1 R2 R3 S
case IF_T2_C5: // T2_C5 ............nnnn ....dddd....mmmm R1 R2 R3
case IF_T2_G1: // T2_G1 ............nnnn ttttTTTT........ R1 R2 R3
assert(isGeneralRegister(id->idReg1()));
assert(isGeneralRegister(id->idReg2()));
assert(isGeneralRegister(id->idReg3()));
break;
case IF_T2_C1: // T2_C1 ...........S.... .iiiddddiishmmmm R1 R2 S, imm5, sh
case IF_T2_C2: // T2_C2 ...........S.... .iiiddddii..mmmm R1 R2 S, imm5
case IF_T2_C8: // T2_C8 ............nnnn .iii....iishmmmm R1 R2 imm5, sh
assert(isGeneralRegister(id->idReg1()));
assert(isGeneralRegister(id->idReg2()));
assert(emitGetInsSC(id) < 0x20);
break;
case IF_T2_C6: // T2_C6 ................ ....dddd..iimmmm R1 R2 imm2
case IF_T2_C7: // T2_C7 ............nnnn ..........shmmmm R1 R2 imm2
assert(isGeneralRegister(id->idReg1()));
assert(isGeneralRegister(id->idReg2()));
assert(emitGetInsSC(id) < 0x4);
break;
case IF_T2_C3: // T2_C3 ...........S.... ....dddd....mmmm R1 R2 S
case IF_T2_C9: // T2_C9 ............nnnn ............mmmm R1 R2
case IF_T2_C10: // T2_C10 ............mmmm ....dddd....mmmm R1 R2
assert(isGeneralRegister(id->idReg1()));
assert(isGeneralRegister(id->idReg2()));
break;
case IF_T2_D0: // T2_D0 ............nnnn .iiiddddii.wwwww R1 R2 imm5, imm5
assert(isGeneralRegister(id->idReg1()));
assert(isGeneralRegister(id->idReg2()));
assert(emitGetInsSC(id) < 0x400);
break;
case IF_T2_D1: // T2_D1 ................ .iiiddddii.wwwww R1 imm5, imm5
assert(isGeneralRegister(id->idReg1()));
assert(emitGetInsSC(id) < 0x400);
break;
case IF_T2_E0: // T2_E0 ............nnnn tttt......shmmmm R1 R2 R3 imm2
assert(isGeneralRegister(id->idReg1()));
assert(isGeneralRegister(id->idReg2()));
if (id->idIsLclVar())
{
assert(isGeneralRegister(codeGen->rsGetRsvdReg()));
}
else
{
assert(isGeneralRegister(id->idReg3()));
assert(emitGetInsSC(id) < 0x4);
}
break;
case IF_T2_E1: // T2_E1 ............nnnn tttt............ R1 R2
assert(isGeneralRegister(id->idReg1()));
assert(isGeneralRegister(id->idReg2()));
break;
case IF_T2_E2: // T2_E2 ................ tttt............ R1
assert(isGeneralRegister(id->idReg1()));
break;
case IF_T2_F1: // T2_F1 ............nnnn ttttdddd....mmmm R1 R2 R3 R4
case IF_T2_F2: // T2_F2 ............nnnn aaaadddd....mmmm R1 R2 R3 R4
assert(isGeneralRegister(id->idReg1()));
assert(isGeneralRegister(id->idReg2()));
assert(isGeneralRegister(id->idReg3()));
assert(isGeneralRegister(id->idReg4()));
break;
case IF_T2_G0: // T2_G0 .......PU.W.nnnn ttttTTTTiiiiiiii R1 R2 R3 imm8, PUW
assert(isGeneralRegister(id->idReg1()));
assert(isGeneralRegister(id->idReg2()));
assert(isGeneralRegister(id->idReg3()));
assert(unsigned_abs(emitGetInsSC(id)) < 0x100);
break;
case IF_T2_H0: // T2_H0 ............nnnn tttt.PUWiiiiiiii R1 R2 imm8, PUW
assert(isGeneralRegister(id->idReg1()));
assert(isGeneralRegister(id->idReg2()));
assert(unsigned_abs(emitGetInsSC(id)) < 0x100);
break;
case IF_T2_H1: // T2_H1 ............nnnn tttt....iiiiiiii R1 R2 imm8
assert(isGeneralRegister(id->idReg1()));
assert(isGeneralRegister(id->idReg2()));
assert(emitGetInsSC(id) < 0x100);
break;
case IF_T2_H2: // T2_H2 ............nnnn ........iiiiiiii R1 imm8
assert(isGeneralRegister(id->idReg1()));
assert(emitGetInsSC(id) < 0x100);
break;
case IF_T2_I0: // T2_I0 ..........W.nnnn rrrrrrrrrrrrrrrr R1 W, imm16
assert(isGeneralRegister(id->idReg1()));
assert(emitGetInsSC(id) < 0x10000);
break;
case IF_T2_N: // T2_N .....i......iiii .iiiddddiiiiiiii R1 imm16
assert(isGeneralRegister(id->idReg1()));
assert(!id->idIsReloc());
break;
case IF_T2_N2: // T2_N2 .....i......iiii .iiiddddiiiiiiii R1 imm16
assert(isGeneralRegister(id->idReg1()));
assert((size_t)emitGetInsSC(id) < emitDataSize());
break;
case IF_T2_N3: // T2_N3 .....i......iiii .iiiddddiiiiiiii R1 imm16
assert(isGeneralRegister(id->idReg1()));
assert(id->idIsReloc());
break;
case IF_T2_I1: // T2_I1 ................ rrrrrrrrrrrrrrrr imm16
assert(emitGetInsSC(id) < 0x10000);
break;
case IF_T2_K1: // T2_K1 ............nnnn ttttiiiiiiiiiiii R1 R2 imm12
case IF_T2_M0: // T2_M0 .....i......nnnn .iiiddddiiiiiiii R1 R2 imm12
assert(isGeneralRegister(id->idReg1()));
assert(isGeneralRegister(id->idReg2()));
assert(emitGetInsSC(id) < 0x1000);
break;
case IF_T2_L0: // T2_L0 .....i.....Snnnn .iiiddddiiiiiiii R1 R2 S, imm8<<imm4
assert(isGeneralRegister(id->idReg1()));
assert(isGeneralRegister(id->idReg2()));
assert(isModImmConst(emitGetInsSC(id)));
break;
case IF_T2_K4: // T2_K4 ........U....... ttttiiiiiiiiiiii R1 PC U, imm12
case IF_T2_M1: // T2_M1 .....i.......... .iiiddddiiiiiiii R1 PC imm12
assert(isGeneralRegister(id->idReg1()));
assert(id->idReg2() == REG_PC);
assert(emitGetInsSC(id) < 0x1000);
break;
case IF_T2_K3: // T2_K3 ........U....... ....iiiiiiiiiiii PC U, imm12
assert(id->idReg1() == REG_PC);
assert(emitGetInsSC(id) < 0x1000);
break;
case IF_T2_K2: // T2_K2 ............nnnn ....iiiiiiiiiiii R1 imm12
assert(isGeneralRegister(id->idReg1()));
assert(emitGetInsSC(id) < 0x1000);
break;
case IF_T2_L1: // T2_L1 .....i.....S.... .iiiddddiiiiiiii R1 S, imm8<<imm4
case IF_T2_L2: // T2_L2 .....i......nnnn .iii....iiiiiiii R1 imm8<<imm4
assert(isGeneralRegister(id->idReg1()));
assert(isModImmConst(emitGetInsSC(id)));
break;
case IF_T1_J3: // T1_J3 .....dddiiiiiiii R1 PC imm8
assert(isGeneralRegister(id->idReg1()));
assert(id->idReg2() == REG_PC);
assert(emitGetInsSC(id) < 0x100);
break;
case IF_T1_K: // T1_K ....cccciiiiiiii Branch imm8, cond4
case IF_T1_M: // T1_M .....iiiiiiiiiii Branch imm11
case IF_T2_J1: // T2_J1 .....Scccciiiiii ..j.jiiiiiiiiiii Branch imm20, cond4
case IF_T2_J2: // T2_J2 .....Siiiiiiiiii ..j.jiiiiiiiiii. Branch imm24
case IF_T2_N1: // T2_N .....i......iiii .iiiddddiiiiiiii R1 imm16
case IF_T2_J3: // T2_J3 .....Siiiiiiiiii ..j.jiiiiiiiiii. Call imm24
case IF_LARGEJMP:
break;
case IF_T2_VFP3:
if (id->idOpSize() == EA_8BYTE)
{
assert(isDoubleReg(id->idReg1()));
assert(isDoubleReg(id->idReg2()));
assert(isDoubleReg(id->idReg3()));
}
else
{
assert(id->idOpSize() == EA_4BYTE);
assert(isFloatReg(id->idReg1()));
assert(isFloatReg(id->idReg2()));
assert(isFloatReg(id->idReg3()));
}
break;
case IF_T2_VFP2:
assert(isFloatReg(id->idReg1()));
assert(isFloatReg(id->idReg2()));
break;
case IF_T2_VLDST:
if (id->idOpSize() == EA_8BYTE)
assert(isDoubleReg(id->idReg1()));
else
assert(isFloatReg(id->idReg1()));
assert(isGeneralRegister(id->idReg2()));
assert(offsetFitsInVectorMem(emitGetInsSC(id)));
break;
case IF_T2_VMOVD:
assert(id->idOpSize() == EA_8BYTE);
if (id->idIns() == INS_vmov_d2i)
{
assert(isGeneralRegister(id->idReg1()));
assert(isGeneralRegister(id->idReg2()));
assert(isDoubleReg(id->idReg3()));
}
else
{
assert(id->idIns() == INS_vmov_i2d);
assert(isDoubleReg(id->idReg1()));
assert(isGeneralRegister(id->idReg2()));
assert(isGeneralRegister(id->idReg3()));
}
break;
case IF_T2_VMOVS:
assert(id->idOpSize() == EA_4BYTE);
if (id->idIns() == INS_vmov_i2f)
{
assert(isFloatReg(id->idReg1()));
assert(isGeneralRegister(id->idReg2()));
}
else
{
assert(id->idIns() == INS_vmov_f2i);
assert(isGeneralRegister(id->idReg1()));
assert(isFloatReg(id->idReg2()));
}
break;
default:
printf("unexpected format %s\n", emitIfName(id->idInsFmt()));
assert(!"Unexpected format");
break;
}
}
#endif // DEBUG
bool emitter::emitInsMayWriteToGCReg(instrDesc* id)
{
instruction ins = id->idIns();
insFormat fmt = id->idInsFmt();
switch (fmt)
{
// These are the formats with "destination" or "target" registers:
case IF_T1_C:
case IF_T1_D0:
case IF_T1_E:
case IF_T1_G:
case IF_T1_H:
case IF_T1_J0:
case IF_T1_J1:
case IF_T1_J2:
case IF_T1_J3:
case IF_T2_C0:
case IF_T2_C1:
case IF_T2_C2:
case IF_T2_C3:
case IF_T2_C4:
case IF_T2_C5:
case IF_T2_C6:
case IF_T2_C10:
case IF_T2_D0:
case IF_T2_D1:
case IF_T2_F1:
case IF_T2_F2:
case IF_T2_L0:
case IF_T2_L1:
case IF_T2_M0:
case IF_T2_M1:
case IF_T2_N:
case IF_T2_N1:
case IF_T2_N2:
case IF_T2_N3:
case IF_T2_VFP3:
case IF_T2_VFP2:
case IF_T2_VLDST:
case IF_T2_E0:
case IF_T2_E1:
case IF_T2_E2:
case IF_T2_G0:
case IF_T2_G1:
case IF_T2_H0:
case IF_T2_H1:
case IF_T2_K1:
case IF_T2_K4:
// Some formats with "destination" or "target" registers are actually used for store instructions, for the
// "source" value written to memory.
// Similarly, PUSH has a target register, indicating the start of the set of registers to push. POP
// *does* write to at least one register, so we do not make that a special case.
// Various compare/test instructions do not write (except to the flags). Technically "teq" does not need to
// be
// be in this list because it has no forms matched above, but I'm putting it here for completeness.
switch (ins)
{
case INS_str:
case INS_strb:
case INS_strh:
case INS_strd:
case INS_strex:
case INS_strexb:
case INS_strexd:
case INS_strexh:
case INS_push:
case INS_cmp:
case INS_cmn:
case INS_tst:
case INS_teq:
return false;
default:
return true;
}
case IF_T2_VMOVS:
// VMOV.i2f reads from the integer register. Conversely VMOV.f2i writes to GC pointer-sized
// integer register that might have previously held GC pointers, so they need to be included.
assert(id->idGCref() == GCT_NONE);
return (ins == INS_vmov_f2i);
case IF_T2_VMOVD:
// VMOV.i2d reads from the integer registers. Conversely VMOV.d2i writes to GC pointer-sized
// integer registers that might have previously held GC pointers, so they need to be included.
assert(id->idGCref() == GCT_NONE);
return (ins == INS_vmov_d2i);
default:
return false;
}
}
bool emitter::emitInsWritesToLclVarStackLoc(instrDesc* id)
{
if (!id->idIsLclVar())
return false;
instruction ins = id->idIns();
// This list is related to the list of instructions used to store local vars in emitIns_S_R().
// We don't accept writing to float local vars.
switch (ins)
{
case INS_strb:
case INS_strh:
case INS_str:
return true;
default:
return false;
}
}
bool emitter::emitInsMayWriteMultipleRegs(instrDesc* id)
{
instruction ins = id->idIns();
insFormat fmt = id->idInsFmt();
switch (ins)
{
case INS_ldm:
case INS_ldmdb:
case INS_smlal:
case INS_smull:
case INS_umlal:
case INS_umull:
case INS_vmov_d2i:
return true;
case INS_pop:
if (fmt != IF_T2_E2) // T2_E2 is pop single register encoding
{
return true;
}
return false;
default:
return false;
}
}
/*****************************************************************************
*
* Return a string that represents the given register.
*/
const char* emitter::emitRegName(regNumber reg, emitAttr attr, bool varName) const
{
assert(reg < REG_COUNT);
const char* rn = emitComp->compRegVarName(reg, varName, false);
assert(strlen(rn) >= 1);
return rn;
}
const char* emitter::emitFloatRegName(regNumber reg, emitAttr attr, bool varName)
{
assert(reg < REG_COUNT);
const char* rn = emitComp->compRegVarName(reg, varName, true);
assert(strlen(rn) >= 1);
return rn;
}
/*****************************************************************************
*
* Returns the base encoding of the given CPU instruction.
*/
emitter::insFormat emitter::emitInsFormat(instruction ins)
{
// clang-format off
const static insFormat insFormats[] =
{
#define INST1(id, nm, fp, ldst, fmt, e1 ) fmt,
#define INST2(id, nm, fp, ldst, fmt, e1, e2 ) fmt,
#define INST3(id, nm, fp, ldst, fmt, e1, e2, e3 ) fmt,
#define INST4(id, nm, fp, ldst, fmt, e1, e2, e3, e4 ) fmt,
#define INST5(id, nm, fp, ldst, fmt, e1, e2, e3, e4, e5 ) fmt,
#define INST6(id, nm, fp, ldst, fmt, e1, e2, e3, e4, e5, e6 ) fmt,
#define INST8(id, nm, fp, ldst, fmt, e1, e2, e3, e4, e5, e6, e7, e8 ) fmt,
#define INST9(id, nm, fp, ldst, fmt, e1, e2, e3, e4, e5, e6, e7, e8, e9) fmt,
#include "instrs.h"
};
// clang-format on
assert(ins < ArrLen(insFormats));
assert((insFormats[ins] != IF_NONE));
return insFormats[ins];
}
// INST_FP is 1
#define LD 2
#define ST 4
#define CMP 8
// clang-format off
/*static*/ const BYTE CodeGenInterface::instInfo[] =
{
#define INST1(id, nm, fp, ldst, fmt, e1 ) ldst | INST_FP*fp,
#define INST2(id, nm, fp, ldst, fmt, e1, e2 ) ldst | INST_FP*fp,
#define INST3(id, nm, fp, ldst, fmt, e1, e2, e3 ) ldst | INST_FP*fp,
#define INST4(id, nm, fp, ldst, fmt, e1, e2, e3, e4 ) ldst | INST_FP*fp,
#define INST5(id, nm, fp, ldst, fmt, e1, e2, e3, e4, e5 ) ldst | INST_FP*fp,
#define INST6(id, nm, fp, ldst, fmt, e1, e2, e3, e4, e5, e6 ) ldst | INST_FP*fp,
#define INST8(id, nm, fp, ldst, fmt, e1, e2, e3, e4, e5, e6, e7, e8 ) ldst | INST_FP*fp,
#define INST9(id, nm, fp, ldst, fmt, e1, e2, e3, e4, e5, e6, e7, e8, e9) ldst | INST_FP*fp,
#include "instrs.h"
};
// clang-format on
/*****************************************************************************
*
* Returns true if the instruction is some kind of load instruction
*/
bool emitter::emitInsIsLoad(instruction ins)
{
// We have pseudo ins like lea which are not included in emitInsLdStTab.
if (ins < ArrLen(CodeGenInterface::instInfo))
return (CodeGenInterface::instInfo[ins] & LD) ? true : false;
else
return false;
}
/*****************************************************************************
*
* Returns true if the instruction is some kind of compare or test instruction
*/
bool emitter::emitInsIsCompare(instruction ins)
{
// We have pseudo ins like lea which are not included in emitInsLdStTab.
if (ins < ArrLen(CodeGenInterface::instInfo))
return (CodeGenInterface::instInfo[ins] & CMP) ? true : false;
else
return false;
}
/*****************************************************************************
*
* Returns true if the instruction is some kind of store instruction
*/
bool emitter::emitInsIsStore(instruction ins)
{
// We have pseudo ins like lea which are not included in emitInsLdStTab.
if (ins < ArrLen(CodeGenInterface::instInfo))
return (CodeGenInterface::instInfo[ins] & ST) ? true : false;
else
return false;
}
/*****************************************************************************
*
* Returns true if the instruction is some kind of load/store instruction
*/
bool emitter::emitInsIsLoadOrStore(instruction ins)
{
// We have pseudo ins like lea which are not included in emitInsLdStTab.
if (ins < ArrLen(CodeGenInterface::instInfo))
return (CodeGenInterface::instInfo[ins] & (LD | ST)) ? true : false;
else
return false;
}
#undef LD
#undef ST
#undef CMP
/*****************************************************************************
*
* Returns the specific encoding of the given CPU instruction and format
*/
emitter::code_t emitter::emitInsCode(instruction ins, insFormat fmt)
{
// clang-format off
const static code_t insCodes1[] =
{
#define INST1(id, nm, fp, ldst, fmt, e1 ) e1,
#define INST2(id, nm, fp, ldst, fmt, e1, e2 ) e1,
#define INST3(id, nm, fp, ldst, fmt, e1, e2, e3 ) e1,
#define INST4(id, nm, fp, ldst, fmt, e1, e2, e3, e4 ) e1,
#define INST5(id, nm, fp, ldst, fmt, e1, e2, e3, e4, e5 ) e1,
#define INST6(id, nm, fp, ldst, fmt, e1, e2, e3, e4, e5, e6 ) e1,
#define INST8(id, nm, fp, ldst, fmt, e1, e2, e3, e4, e5, e6, e7, e8 ) e1,
#define INST9(id, nm, fp, ldst, fmt, e1, e2, e3, e4, e5, e6, e7, e8, e9) e1,
#include "instrs.h"
};
const static code_t insCodes2[] =
{
#define INST1(id, nm, fp, ldst, fmt, e1 )
#define INST2(id, nm, fp, ldst, fmt, e1, e2 ) e2,
#define INST3(id, nm, fp, ldst, fmt, e1, e2, e3 ) e2,
#define INST4(id, nm, fp, ldst, fmt, e1, e2, e3, e4 ) e2,
#define INST5(id, nm, fp, ldst, fmt, e1, e2, e3, e4, e5 ) e2,
#define INST6(id, nm, fp, ldst, fmt, e1, e2, e3, e4, e5, e6 ) e2,
#define INST8(id, nm, fp, ldst, fmt, e1, e2, e3, e4, e5, e6, e7, e8 ) e2,
#define INST9(id, nm, fp, ldst, fmt, e1, e2, e3, e4, e5, e6, e7, e8, e9) e2,
#include "instrs.h"
};
const static code_t insCodes3[] =
{
#define INST1(id, nm, fp, ldst, fmt, e1 )
#define INST2(id, nm, fp, ldst, fmt, e1, e2 )
#define INST3(id, nm, fp, ldst, fmt, e1, e2, e3 ) e3,
#define INST4(id, nm, fp, ldst, fmt, e1, e2, e3, e4 ) e3,
#define INST5(id, nm, fp, ldst, fmt, e1, e2, e3, e4, e5 ) e3,
#define INST6(id, nm, fp, ldst, fmt, e1, e2, e3, e4, e5, e6 ) e3,
#define INST8(id, nm, fp, ldst, fmt, e1, e2, e3, e4, e5, e6, e7, e8 ) e3,
#define INST9(id, nm, fp, ldst, fmt, e1, e2, e3, e4, e5, e6, e7, e8, e9) e3,
#include "instrs.h"
};
const static code_t insCodes4[] =
{
#define INST1(id, nm, fp, ldst, fmt, e1 )
#define INST2(id, nm, fp, ldst, fmt, e1, e2 )
#define INST3(id, nm, fp, ldst, fmt, e1, e2, e3 )
#define INST4(id, nm, fp, ldst, fmt, e1, e2, e3, e4 ) e4,
#define INST5(id, nm, fp, ldst, fmt, e1, e2, e3, e4, e5 ) e4,
#define INST6(id, nm, fp, ldst, fmt, e1, e2, e3, e4, e5, e6 ) e4,
#define INST8(id, nm, fp, ldst, fmt, e1, e2, e3, e4, e5, e6, e7, e8 ) e4,
#define INST9(id, nm, fp, ldst, fmt, e1, e2, e3, e4, e5, e6, e7, e8, e9) e4,
#include "instrs.h"
};
const static code_t insCodes5[] =
{
#define INST1(id, nm, fp, ldst, fmt, e1 )
#define INST2(id, nm, fp, ldst, fmt, e1, e2 )
#define INST3(id, nm, fp, ldst, fmt, e1, e2, e3 )
#define INST4(id, nm, fp, ldst, fmt, e1, e2, e3, e4 )
#define INST5(id, nm, fp, ldst, fmt, e1, e2, e3, e4, e5 ) e5,
#define INST6(id, nm, fp, ldst, fmt, e1, e2, e3, e4, e5, e6 ) e5,
#define INST8(id, nm, fp, ldst, fmt, e1, e2, e3, e4, e5, e6, e7, e8 ) e5,
#define INST9(id, nm, fp, ldst, fmt, e1, e2, e3, e4, e5, e6, e7, e8, e9) e5,
#include "instrs.h"
};
const static code_t insCodes6[] =
{
#define INST1(id, nm, fp, ldst, fmt, e1 )
#define INST2(id, nm, fp, ldst, fmt, e1, e2 )
#define INST3(id, nm, fp, ldst, fmt, e1, e2, e3 )
#define INST4(id, nm, fp, ldst, fmt, e1, e2, e3, e4 )
#define INST5(id, nm, fp, ldst, fmt, e1, e2, e3, e4, e5 )
#define INST6(id, nm, fp, ldst, fmt, e1, e2, e3, e4, e5, e6 ) e6,
#define INST8(id, nm, fp, ldst, fmt, e1, e2, e3, e4, e5, e6, e7, e8 ) e6,
#define INST9(id, nm, fp, ldst, fmt, e1, e2, e3, e4, e5, e6, e7, e8, e9) e6,
#include "instrs.h"
};
const static code_t insCodes7[] =
{
#define INST1(id, nm, fp, ldst, fmt, e1 )
#define INST2(id, nm, fp, ldst, fmt, e1, e2 )
#define INST3(id, nm, fp, ldst, fmt, e1, e2, e3 )
#define INST4(id, nm, fp, ldst, fmt, e1, e2, e3, e4 )
#define INST5(id, nm, fp, ldst, fmt, e1, e2, e3, e4, e5 )
#define INST6(id, nm, fp, ldst, fmt, e1, e2, e3, e4, e5, e6 )
#define INST8(id, nm, fp, ldst, fmt, e1, e2, e3, e4, e5, e6, e7, e8 ) e7,
#define INST9(id, nm, fp, ldst, fmt, e1, e2, e3, e4, e5, e6, e7, e8, e9) e7,
#include "instrs.h"
};
const static code_t insCodes8[] =
{
#define INST1(id, nm, fp, ldst, fmt, e1 )
#define INST2(id, nm, fp, ldst, fmt, e1, e2 )
#define INST3(id, nm, fp, ldst, fmt, e1, e2, e3 )
#define INST4(id, nm, fp, ldst, fmt, e1, e2, e3, e4 )
#define INST5(id, nm, fp, ldst, fmt, e1, e2, e3, e4, e5 )
#define INST6(id, nm, fp, ldst, fmt, e1, e2, e3, e4, e5, e6 )
#define INST8(id, nm, fp, ldst, fmt, e1, e2, e3, e4, e5, e6, e7, e8 ) e8,
#define INST9(id, nm, fp, ldst, fmt, e1, e2, e3, e4, e5, e6, e7, e8, e9) e8,
#include "instrs.h"
};
const static code_t insCodes9[] =
{
#define INST1(id, nm, fp, ldst, fmt, e1 )
#define INST2(id, nm, fp, ldst, fmt, e1, e2 )
#define INST3(id, nm, fp, ldst, fmt, e1, e2, e3 )
#define INST4(id, nm, fp, ldst, fmt, e1, e2, e3, e4 )
#define INST5(id, nm, fp, ldst, fmt, e1, e2, e3, e4, e5 )
#define INST6(id, nm, fp, ldst, fmt, e1, e2, e3, e4, e5, e6 )
#define INST8(id, nm, fp, ldst, fmt, e1, e2, e3, e4, e5, e6, e7, e8 )
#define INST9(id, nm, fp, ldst, fmt, e1, e2, e3, e4, e5, e6, e7, e8, e9) e9,
#include "instrs.h"
};
const static insFormat formatEncode9[9] = { IF_T1_D0, IF_T1_H, IF_T1_J0, IF_T1_G, IF_T2_L0, IF_T2_C0, IF_T1_F, IF_T1_J2, IF_T1_J3 };
const static insFormat formatEncode8[8] = { IF_T1_H, IF_T1_C, IF_T2_E0, IF_T2_H0, IF_T2_K1, IF_T2_K4, IF_T1_J2, IF_T1_J3 };
const static insFormat formatEncode6A[6] = { IF_T1_H, IF_T1_C, IF_T2_E0, IF_T2_H0, IF_T2_K1, IF_T2_K4};
const static insFormat formatEncode6B[6] = { IF_T1_H, IF_T1_C, IF_T2_E0, IF_T2_H0, IF_T2_K1, IF_T1_J2 };
const static insFormat formatEncode5A[5] = { IF_T1_E, IF_T1_D0, IF_T1_J0, IF_T2_L1, IF_T2_C3 };
const static insFormat formatEncode5B[5] = { IF_T1_E, IF_T1_D0, IF_T1_J0, IF_T2_L2, IF_T2_C8 };
const static insFormat formatEncode4A[4] = { IF_T1_E, IF_T1_C, IF_T2_C4, IF_T2_C2 };
const static insFormat formatEncode4B[4] = { IF_T2_K2, IF_T2_H2, IF_T2_C7, IF_T2_K3 };
const static insFormat formatEncode4C[4] = { IF_T2_N, IF_T2_N1, IF_T2_N2, IF_T2_N3 };
const static insFormat formatEncode3A[3] = { IF_T1_E, IF_T2_C0, IF_T2_L0 };
const static insFormat formatEncode3B[3] = { IF_T1_E, IF_T2_C8, IF_T2_L2 };
const static insFormat formatEncode3C[3] = { IF_T1_E, IF_T2_C1, IF_T2_L1 };
const static insFormat formatEncode3D[3] = { IF_T1_L1, IF_T2_E2, IF_T2_I1 };
const static insFormat formatEncode3E[3] = { IF_T1_M, IF_T2_J2, IF_T2_J3 };
const static insFormat formatEncode2A[2] = { IF_T1_K, IF_T2_J1 };
const static insFormat formatEncode2B[2] = { IF_T1_D1, IF_T1_D2 };
const static insFormat formatEncode2C[2] = { IF_T1_D2, IF_T2_J3 };
const static insFormat formatEncode2D[2] = { IF_T1_J1, IF_T2_I0 };
const static insFormat formatEncode2E[2] = { IF_T1_E, IF_T2_C6 };
const static insFormat formatEncode2F[2] = { IF_T1_E, IF_T2_C5 };
const static insFormat formatEncode2G[2] = { IF_T1_J3, IF_T2_M1 };
// clang-format on
code_t code = BAD_CODE;
insFormat insFmt = emitInsFormat(ins);
bool found = false;
int index = 0;
switch (insFmt)
{
case IF_EN9:
for (index = 0; index < 9; index++)
{
if (fmt == formatEncode9[index])
{
found = true;
break;
}
}
break;
case IF_EN8:
for (index = 0; index < 8; index++)
{
if (fmt == formatEncode8[index])
{
found = true;
break;
}
}
break;
case IF_EN6A:
for (index = 0; index < 6; index++)
{
if (fmt == formatEncode6A[index])
{
found = true;
break;
}
}
break;
case IF_EN6B:
for (index = 0; index < 6; index++)
{
if (fmt == formatEncode6B[index])
{
found = true;
break;
}
}
break;
case IF_EN5A:
for (index = 0; index < 5; index++)
{
if (fmt == formatEncode5A[index])
{
found = true;
break;
}
}
break;
case IF_EN5B:
for (index = 0; index < 5; index++)
{
if (fmt == formatEncode5B[index])
{
found = true;
break;
}
}
break;
case IF_EN4A:
for (index = 0; index < 4; index++)
{
if (fmt == formatEncode4A[index])
{
found = true;
break;