diff --git a/.gitignore b/.gitignore index d38b628..97493c6 100644 --- a/.gitignore +++ b/.gitignore @@ -1,17 +1,23 @@ *~ *.jou -*.log build *.xcix *.pb .Xil *.zip +*.str -simulation_inputs -simulation_outputs -test_data +__pycache__ +sim_data .idea venv *.pyc +*.run +#notepad++ backup +nppBackup +*.run +*.pyc +*.log +firmware/FT0/bits diff --git a/Jenkinsfile b/Jenkinsfile index ad234d1..d9518d6 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -42,15 +42,30 @@ pipeline { } } stage('Build FIT bitstreams') { - parallel { + stages { + stage('FTM_PM') { + steps { + sh('./software/ci/build.sh FTM_PM') + } + } + stage('FTM_TCM') { + steps { + sh('./software/ci/build.sh FTM_TCM') + } + } stage('PM') { steps { sh('./software/ci/build.sh PM') } } - stage('TCM') { + stage('TCM_proto') { + steps { + sh('./software/ci/build.sh TCM_proto') + } + } + stage('TCM_v1') { steps { - sh('./software/ci/build.sh TCM') + sh('./software/ci/build.sh TCM_v1') } } } diff --git a/README.md b/README.md index ffcd68c..0a0d5dd 100644 --- a/README.md +++ b/README.md @@ -1,4 +1,4 @@ -![PM_TCM](https://repository-images.githubusercontent.com/238522341/aca2c500-48cf-11ea-95b5-4a498a732d8e?dl=0) +![PM_TCM](https://github.com/dfinogee/alice-fit-fpga/blob/devel/photo/FT0_front.jpg?raw=true) ---- # ALICE Fast Interaction Trigger (FIT) firmware repository @@ -11,50 +11,48 @@ Authors: Dmitry.Serebryakov@cern.ch, Dmitry.Finogeev@cern.ch ### Clone the Git repository git clone https://github.com/AliceO2Group/alice-fit-fpga.git - -### Update to latest version - git pull --recurse-submodules ---- -### Set up Vivado 2019.2.1 (NEW !!!) - source /opt/Xilinx/Vivado/2019.2/settings64.sh - - used vivado version: - Vivado v2019.2.1 (64-bit) - SW Build: 2729669 on Thu Dec 5 04:49:17 MST 2019 - IP Build: 2729494 on Thu Dec 5 07:38:25 MST 2019 - ----- -## Generate bitstreams +## Projects compilation +'\' = PM/TCM_v1/TCM_proto/FTM_PM/FTM_TCM -### FIT/FT0/PM +### Vivado tcl mode (linux) - cd alice-fit-fpga/firmware/FT0/PM + cd alice-fit-fpga/firmware/FT0/ vivado -mode batch -source make.tcl -### FIT/FT0/TCM +### Macro (linux) - cd alice-fit-fpga/firmware/FT0/TCM - vivado -mode batch -source make.tcl +Macro will compile project and copy bit + bin + logs files into firmware/FT0/bits/ -### FIT/FT0/FTM + cd alice-fit-fpga/ + ./software/ci/build_local.sh - cd alice-fit-fpga/firmware/FT0/FTM - vivado -mode batch -source make.tcl +### Vivado GUI (win/linux) + +run vivado v2019.2.1/v2020.1 + + (linux) + source /opt/Xilinx/Vivado/2019.2/settings64.sh + vivado + +open tcl console and change directory to the project + + (in tcl console) + cd //alice-fit-fpga/firmware/FT0/ + +remove build directory (if exist) and run compilation + + (in tcl console) + source ./make.tcl ----- -## After any change to IP cores + +### Export IP cores to `ipcore_properties` Open the TCL console in the Vivado window and type in the following commands: source ../../tcl/fit.tcl fit::update_ip_properties -Then git add/commit any new/changed files in the directory `ipcore_properties` - ----- -## After any change to IP cores and/or to VHDL source files - -git add/commit any new/changed VHDL files diff --git a/firmware/FT0/FTM_PM/ipcore_properties/cntpck_fifo_comp.txt b/firmware/FT0/FTM_PM/ipcore_properties/cntpck_fifo_comp.txt index c22a96e..425c87c 100644 --- a/firmware/FT0/FTM_PM/ipcore_properties/cntpck_fifo_comp.txt +++ b/firmware/FT0/FTM_PM/ipcore_properties/cntpck_fifo_comp.txt @@ -14,7 +14,7 @@ CONFIG.Clock_Type_AXI string false Common_Cl CONFIG.Component_Name string false cntpck_fifo_comp CONFIG.DATA_WIDTH string false 64 CONFIG.Data_Count string false false -CONFIG.Data_Count_Width string false 7 +CONFIG.Data_Count_Width string false 8 CONFIG.Disable_Timing_Violations string false false CONFIG.Disable_Timing_Violations_AXI string false false CONFIG.Dout_Reset_Value string false 0 @@ -60,14 +60,14 @@ CONFIG.FIFO_Implementation_wdch string false Common_Cl CONFIG.FIFO_Implementation_wrch string false Common_Clock_Block_RAM CONFIG.Fifo_Implementation string false Independent_Clocks_Block_RAM CONFIG.Full_Flags_Reset_Value string false 1 -CONFIG.Full_Threshold_Assert_Value string false 127 +CONFIG.Full_Threshold_Assert_Value string false 255 CONFIG.Full_Threshold_Assert_Value_axis string false 1023 CONFIG.Full_Threshold_Assert_Value_rach string false 1023 CONFIG.Full_Threshold_Assert_Value_rdch string false 1023 CONFIG.Full_Threshold_Assert_Value_wach string false 1023 CONFIG.Full_Threshold_Assert_Value_wdch string false 1023 CONFIG.Full_Threshold_Assert_Value_wrch string false 1023 -CONFIG.Full_Threshold_Negate_Value string false 126 +CONFIG.Full_Threshold_Negate_Value string false 254 CONFIG.HAS_ACLKEN string false false CONFIG.HAS_TKEEP string false false CONFIG.HAS_TSTRB string false false @@ -87,8 +87,8 @@ CONFIG.Inject_Sbit_Error_rdch string false false CONFIG.Inject_Sbit_Error_wach string false false CONFIG.Inject_Sbit_Error_wdch string false false CONFIG.Inject_Sbit_Error_wrch string false false -CONFIG.Input_Data_Width string false 160 -CONFIG.Input_Depth string false 128 +CONFIG.Input_Data_Width string false 128 +CONFIG.Input_Depth string false 256 CONFIG.Input_Depth_axis string false 1024 CONFIG.Input_Depth_rach string false 16 CONFIG.Input_Depth_rdch string false 1024 @@ -100,8 +100,8 @@ CONFIG.MASTER_ACLK.INSERT_VIP string false 0 CONFIG.M_AXI.INSERT_VIP string false 0 CONFIG.M_AXIS.INSERT_VIP string false 0 CONFIG.Master_interface_Clock_enable_memory_mapped string false false -CONFIG.Output_Data_Width string false 160 -CONFIG.Output_Depth string false 128 +CONFIG.Output_Data_Width string false 128 +CONFIG.Output_Depth string false 256 CONFIG.Output_Register_Type string false Embedded_Reg CONFIG.Overflow_Flag string false false CONFIG.Overflow_Flag_AXI string false false @@ -157,7 +157,7 @@ CONFIG.Underflow_Sense_AXI string false Active_Hi CONFIG.Use_Dout_Reset string false true CONFIG.Use_Embedded_Registers string false false CONFIG.Use_Embedded_Registers_axis string false false -CONFIG.Use_Extra_Logic string false true +CONFIG.Use_Extra_Logic string false false CONFIG.Valid_Flag string false false CONFIG.Valid_Sense string false Active_High CONFIG.WRITE_CLK.FREQ_HZ string false 100000000 diff --git a/firmware/FT0/FTM_PM/ipcore_properties/err_report_fifo.txt b/firmware/FT0/FTM_PM/ipcore_properties/err_report_fifo.txt new file mode 100644 index 0000000..ae3e3d4 --- /dev/null +++ b/firmware/FT0/FTM_PM/ipcore_properties/err_report_fifo.txt @@ -0,0 +1,185 @@ +Property Type Read-only Value +CONFIG.ADDRESS_WIDTH string false 32 +CONFIG.ARUSER_Width string false 0 +CONFIG.AWUSER_Width string false 0 +CONFIG.Add_NGC_Constraint_AXI string false false +CONFIG.Almost_Empty_Flag string false false +CONFIG.Almost_Full_Flag string false false +CONFIG.BUSER_Width string false 0 +CONFIG.CORE_CLK.FREQ_HZ string false 100000000 +CONFIG.CORE_CLK.INSERT_VIP string false 0 +CONFIG.C_SELECT_XPM string false 0 +CONFIG.Clock_Enable_Type string false Slave_Interface_Clock_Enable +CONFIG.Clock_Type_AXI string false Common_Clock +CONFIG.Component_Name string false err_report_fifo +CONFIG.DATA_WIDTH string false 64 +CONFIG.Data_Count string false false +CONFIG.Data_Count_Width string false 11 +CONFIG.Disable_Timing_Violations string false false +CONFIG.Disable_Timing_Violations_AXI string false false +CONFIG.Dout_Reset_Value string false 0 +CONFIG.Empty_Threshold_Assert_Value string false 4 +CONFIG.Empty_Threshold_Assert_Value_axis string false 1022 +CONFIG.Empty_Threshold_Assert_Value_rach string false 1022 +CONFIG.Empty_Threshold_Assert_Value_rdch string false 1022 +CONFIG.Empty_Threshold_Assert_Value_wach string false 1022 +CONFIG.Empty_Threshold_Assert_Value_wdch string false 1022 +CONFIG.Empty_Threshold_Assert_Value_wrch string false 1022 +CONFIG.Empty_Threshold_Negate_Value string false 5 +CONFIG.Enable_Common_Overflow string false false +CONFIG.Enable_Common_Underflow string false false +CONFIG.Enable_Data_Counts_axis string false false +CONFIG.Enable_Data_Counts_rach string false false +CONFIG.Enable_Data_Counts_rdch string false false +CONFIG.Enable_Data_Counts_wach string false false +CONFIG.Enable_Data_Counts_wdch string false false +CONFIG.Enable_Data_Counts_wrch string false false +CONFIG.Enable_ECC string false false +CONFIG.Enable_ECC_Type string false Hard_ECC +CONFIG.Enable_ECC_axis string false false +CONFIG.Enable_ECC_rach string false false +CONFIG.Enable_ECC_rdch string false false +CONFIG.Enable_ECC_wach string false false +CONFIG.Enable_ECC_wdch string false false +CONFIG.Enable_ECC_wrch string false false +CONFIG.Enable_Reset_Synchronization string false true +CONFIG.Enable_Safety_Circuit string false false +CONFIG.Enable_TLAST string false false +CONFIG.Enable_TREADY string false true +CONFIG.FIFO_Application_Type_axis string false Data_FIFO +CONFIG.FIFO_Application_Type_rach string false Data_FIFO +CONFIG.FIFO_Application_Type_rdch string false Data_FIFO +CONFIG.FIFO_Application_Type_wach string false Data_FIFO +CONFIG.FIFO_Application_Type_wdch string false Data_FIFO +CONFIG.FIFO_Application_Type_wrch string false Data_FIFO +CONFIG.FIFO_Implementation_axis string false Common_Clock_Block_RAM +CONFIG.FIFO_Implementation_rach string false Common_Clock_Block_RAM +CONFIG.FIFO_Implementation_rdch string false Common_Clock_Block_RAM +CONFIG.FIFO_Implementation_wach string false Common_Clock_Block_RAM +CONFIG.FIFO_Implementation_wdch string false Common_Clock_Block_RAM +CONFIG.FIFO_Implementation_wrch string false Common_Clock_Block_RAM +CONFIG.Fifo_Implementation string false Common_Clock_Block_RAM +CONFIG.Full_Flags_Reset_Value string false 0 +CONFIG.Full_Threshold_Assert_Value string false 1023 +CONFIG.Full_Threshold_Assert_Value_axis string false 1023 +CONFIG.Full_Threshold_Assert_Value_rach string false 1023 +CONFIG.Full_Threshold_Assert_Value_rdch string false 1023 +CONFIG.Full_Threshold_Assert_Value_wach string false 1023 +CONFIG.Full_Threshold_Assert_Value_wdch string false 1023 +CONFIG.Full_Threshold_Assert_Value_wrch string false 1023 +CONFIG.Full_Threshold_Negate_Value string false 1022 +CONFIG.HAS_ACLKEN string false false +CONFIG.HAS_TKEEP string false false +CONFIG.HAS_TSTRB string false false +CONFIG.ID_WIDTH string false 0 +CONFIG.INTERFACE_TYPE string false Native +CONFIG.Inject_Dbit_Error string false false +CONFIG.Inject_Dbit_Error_axis string false false +CONFIG.Inject_Dbit_Error_rach string false false +CONFIG.Inject_Dbit_Error_rdch string false false +CONFIG.Inject_Dbit_Error_wach string false false +CONFIG.Inject_Dbit_Error_wdch string false false +CONFIG.Inject_Dbit_Error_wrch string false false +CONFIG.Inject_Sbit_Error string false false +CONFIG.Inject_Sbit_Error_axis string false false +CONFIG.Inject_Sbit_Error_rach string false false +CONFIG.Inject_Sbit_Error_rdch string false false +CONFIG.Inject_Sbit_Error_wach string false false +CONFIG.Inject_Sbit_Error_wdch string false false +CONFIG.Inject_Sbit_Error_wrch string false false +CONFIG.Input_Data_Width string false 32 +CONFIG.Input_Depth string false 1024 +CONFIG.Input_Depth_axis string false 1024 +CONFIG.Input_Depth_rach string false 16 +CONFIG.Input_Depth_rdch string false 1024 +CONFIG.Input_Depth_wach string false 16 +CONFIG.Input_Depth_wdch string false 1024 +CONFIG.Input_Depth_wrch string false 16 +CONFIG.MASTER_ACLK.FREQ_HZ string false 100000000 +CONFIG.MASTER_ACLK.INSERT_VIP string false 0 +CONFIG.M_AXI.INSERT_VIP string false 0 +CONFIG.M_AXIS.INSERT_VIP string false 0 +CONFIG.Master_interface_Clock_enable_memory_mapped string false false +CONFIG.Output_Data_Width string false 32 +CONFIG.Output_Depth string false 1024 +CONFIG.Output_Register_Type string false Embedded_Reg +CONFIG.Overflow_Flag string false false +CONFIG.Overflow_Flag_AXI string false false +CONFIG.Overflow_Sense string false Active_High +CONFIG.Overflow_Sense_AXI string false Active_High +CONFIG.PROTOCOL string false AXI4 +CONFIG.Performance_Options string false First_Word_Fall_Through +CONFIG.Programmable_Empty_Type string false No_Programmable_Empty_Threshold +CONFIG.Programmable_Empty_Type_axis string false No_Programmable_Empty_Threshold +CONFIG.Programmable_Empty_Type_rach string false No_Programmable_Empty_Threshold +CONFIG.Programmable_Empty_Type_rdch string false No_Programmable_Empty_Threshold +CONFIG.Programmable_Empty_Type_wach string false No_Programmable_Empty_Threshold +CONFIG.Programmable_Empty_Type_wdch string false No_Programmable_Empty_Threshold +CONFIG.Programmable_Empty_Type_wrch string false No_Programmable_Empty_Threshold +CONFIG.Programmable_Full_Type string false No_Programmable_Full_Threshold +CONFIG.Programmable_Full_Type_axis string false No_Programmable_Full_Threshold +CONFIG.Programmable_Full_Type_rach string false No_Programmable_Full_Threshold +CONFIG.Programmable_Full_Type_rdch string false No_Programmable_Full_Threshold +CONFIG.Programmable_Full_Type_wach string false No_Programmable_Full_Threshold +CONFIG.Programmable_Full_Type_wdch string false No_Programmable_Full_Threshold +CONFIG.Programmable_Full_Type_wrch string false No_Programmable_Full_Threshold +CONFIG.READ_CLK.FREQ_HZ string false 100000000 +CONFIG.READ_CLK.INSERT_VIP string false 0 +CONFIG.READ_WRITE_MODE string false READ_WRITE +CONFIG.RUSER_Width string false 0 +CONFIG.Read_Clock_Frequency string false 1 +CONFIG.Read_Data_Count string false false +CONFIG.Read_Data_Count_Width string false 11 +CONFIG.Register_Slice_Mode_axis string false Fully_Registered +CONFIG.Register_Slice_Mode_rach string false Fully_Registered +CONFIG.Register_Slice_Mode_rdch string false Fully_Registered +CONFIG.Register_Slice_Mode_wach string false Fully_Registered +CONFIG.Register_Slice_Mode_wdch string false Fully_Registered +CONFIG.Register_Slice_Mode_wrch string false Fully_Registered +CONFIG.Reset_Pin string false true +CONFIG.Reset_Type string false Synchronous_Reset +CONFIG.SLAVE_ACLK.FREQ_HZ string false 100000000 +CONFIG.SLAVE_ACLK.INSERT_VIP string false 0 +CONFIG.SLAVE_ARESETN.INSERT_VIP string false 0 +CONFIG.S_AXI.INSERT_VIP string false 0 +CONFIG.S_AXIS.INSERT_VIP string false 0 +CONFIG.Slave_interface_Clock_enable_memory_mapped string false false +CONFIG.TDATA_NUM_BYTES string false 1 +CONFIG.TDEST_WIDTH string false 0 +CONFIG.TID_WIDTH string false 0 +CONFIG.TKEEP_WIDTH string false 1 +CONFIG.TSTRB_WIDTH string false 1 +CONFIG.TUSER_WIDTH string false 4 +CONFIG.Underflow_Flag string false false +CONFIG.Underflow_Flag_AXI string false false +CONFIG.Underflow_Sense string false Active_High +CONFIG.Underflow_Sense_AXI string false Active_High +CONFIG.Use_Dout_Reset string false true +CONFIG.Use_Embedded_Registers string false false +CONFIG.Use_Embedded_Registers_axis string false false +CONFIG.Use_Extra_Logic string false true +CONFIG.Valid_Flag string false false +CONFIG.Valid_Sense string false Active_High +CONFIG.WRITE_CLK.FREQ_HZ string false 100000000 +CONFIG.WRITE_CLK.INSERT_VIP string false 0 +CONFIG.WUSER_Width string false 0 +CONFIG.Write_Acknowledge_Flag string false false +CONFIG.Write_Acknowledge_Sense string false Active_High +CONFIG.Write_Clock_Frequency string false 1 +CONFIG.Write_Data_Count string false false +CONFIG.Write_Data_Count_Width string false 11 +CONFIG.asymmetric_port_width string false false +CONFIG.axis_type string false FIFO +CONFIG.dynamic_power_saving string false false +CONFIG.ecc_pipeline_reg string false false +CONFIG.enable_low_latency string false false +CONFIG.enable_read_pointer_increment_by2 string false false +CONFIG.rach_type string false FIFO +CONFIG.rdch_type string false FIFO +CONFIG.synchronization_stages string false 2 +CONFIG.synchronization_stages_axi string false 2 +CONFIG.use_dout_register string false false +CONFIG.wach_type string false FIFO +CONFIG.wdch_type string false FIFO +CONFIG.wrch_type string false FIFO +IPDEF string true xilinx.com:ip:fifo_generator:13.2 diff --git a/firmware/FT0/FTM_PM/ipcore_properties/ipbus_data_fifo.txt b/firmware/FT0/FTM_PM/ipcore_properties/ipbus_data_fifo.txt index 6553977..d39c73e 100644 --- a/firmware/FT0/FTM_PM/ipcore_properties/ipbus_data_fifo.txt +++ b/firmware/FT0/FTM_PM/ipcore_properties/ipbus_data_fifo.txt @@ -129,7 +129,7 @@ CONFIG.READ_WRITE_MODE string false READ_WRIT CONFIG.RUSER_Width string false 0 CONFIG.Read_Clock_Frequency string false 1 CONFIG.Read_Data_Count string false true -CONFIG.Read_Data_Count_Width string false 13 +CONFIG.Read_Data_Count_Width string false 14 CONFIG.Register_Slice_Mode_axis string false Fully_Registered CONFIG.Register_Slice_Mode_rach string false Fully_Registered CONFIG.Register_Slice_Mode_rdch string false Fully_Registered @@ -157,7 +157,7 @@ CONFIG.Underflow_Sense_AXI string false Active_Hi CONFIG.Use_Dout_Reset string false true CONFIG.Use_Embedded_Registers string false false CONFIG.Use_Embedded_Registers_axis string false false -CONFIG.Use_Extra_Logic string false false +CONFIG.Use_Extra_Logic string false true CONFIG.Valid_Flag string false false CONFIG.Valid_Sense string false Active_High CONFIG.WRITE_CLK.FREQ_HZ string false 100000000 @@ -167,7 +167,7 @@ CONFIG.Write_Acknowledge_Flag string false false CONFIG.Write_Acknowledge_Sense string false Active_High CONFIG.Write_Clock_Frequency string false 1 CONFIG.Write_Data_Count string false false -CONFIG.Write_Data_Count_Width string false 14 +CONFIG.Write_Data_Count_Width string false 15 CONFIG.asymmetric_port_width string false false CONFIG.axis_type string false FIFO CONFIG.dynamic_power_saving string false false diff --git a/firmware/FT0/FTM_PM/ipcore_properties/raw_data_fifo.txt b/firmware/FT0/FTM_PM/ipcore_properties/raw_data_fifo.txt index 8629119..93f3c73 100644 --- a/firmware/FT0/FTM_PM/ipcore_properties/raw_data_fifo.txt +++ b/firmware/FT0/FTM_PM/ipcore_properties/raw_data_fifo.txt @@ -4,7 +4,7 @@ CONFIG.ARUSER_Width string false 0 CONFIG.AWUSER_Width string false 0 CONFIG.Add_NGC_Constraint_AXI string false false CONFIG.Almost_Empty_Flag string false false -CONFIG.Almost_Full_Flag string false false +CONFIG.Almost_Full_Flag string false true CONFIG.BUSER_Width string false 0 CONFIG.CORE_CLK.FREQ_HZ string false 100000000 CONFIG.CORE_CLK.INSERT_VIP string false 0 @@ -60,14 +60,14 @@ CONFIG.FIFO_Implementation_wdch string false Common_Cl CONFIG.FIFO_Implementation_wrch string false Common_Clock_Block_RAM CONFIG.Fifo_Implementation string false Common_Clock_Block_RAM CONFIG.Full_Flags_Reset_Value string false 0 -CONFIG.Full_Threshold_Assert_Value string false 4095 +CONFIG.Full_Threshold_Assert_Value string false 4000 CONFIG.Full_Threshold_Assert_Value_axis string false 1023 CONFIG.Full_Threshold_Assert_Value_rach string false 1023 CONFIG.Full_Threshold_Assert_Value_rdch string false 1023 CONFIG.Full_Threshold_Assert_Value_wach string false 1023 CONFIG.Full_Threshold_Assert_Value_wdch string false 1023 CONFIG.Full_Threshold_Assert_Value_wrch string false 1023 -CONFIG.Full_Threshold_Negate_Value string false 4094 +CONFIG.Full_Threshold_Negate_Value string false 3999 CONFIG.HAS_ACLKEN string false false CONFIG.HAS_TKEEP string false false CONFIG.HAS_TSTRB string false false @@ -116,7 +116,7 @@ CONFIG.Programmable_Empty_Type_rdch string false No_Progra CONFIG.Programmable_Empty_Type_wach string false No_Programmable_Empty_Threshold CONFIG.Programmable_Empty_Type_wdch string false No_Programmable_Empty_Threshold CONFIG.Programmable_Empty_Type_wrch string false No_Programmable_Empty_Threshold -CONFIG.Programmable_Full_Type string false No_Programmable_Full_Threshold +CONFIG.Programmable_Full_Type string false Single_Programmable_Full_Threshold_Constant CONFIG.Programmable_Full_Type_axis string false No_Programmable_Full_Threshold CONFIG.Programmable_Full_Type_rach string false No_Programmable_Full_Threshold CONFIG.Programmable_Full_Type_rdch string false No_Programmable_Full_Threshold diff --git a/firmware/FT0/FTM_PM/ipcore_properties/slct_data_fifo.txt b/firmware/FT0/FTM_PM/ipcore_properties/slct_data_fifo.txt index 52b27f5..e454940 100644 --- a/firmware/FT0/FTM_PM/ipcore_properties/slct_data_fifo.txt +++ b/firmware/FT0/FTM_PM/ipcore_properties/slct_data_fifo.txt @@ -14,7 +14,7 @@ CONFIG.Clock_Type_AXI string false Common_Cl CONFIG.Component_Name string false slct_data_fifo CONFIG.DATA_WIDTH string false 64 CONFIG.Data_Count string false false -CONFIG.Data_Count_Width string false 12 +CONFIG.Data_Count_Width string false 14 CONFIG.Disable_Timing_Violations string false false CONFIG.Disable_Timing_Violations_AXI string false false CONFIG.Dout_Reset_Value string false 0 @@ -60,14 +60,14 @@ CONFIG.FIFO_Implementation_wdch string false Common_Cl CONFIG.FIFO_Implementation_wrch string false Common_Clock_Block_RAM CONFIG.Fifo_Implementation string false Independent_Clocks_Block_RAM CONFIG.Full_Flags_Reset_Value string false 1 -CONFIG.Full_Threshold_Assert_Value string false 4095 +CONFIG.Full_Threshold_Assert_Value string false 16000 CONFIG.Full_Threshold_Assert_Value_axis string false 1023 CONFIG.Full_Threshold_Assert_Value_rach string false 1023 CONFIG.Full_Threshold_Assert_Value_rdch string false 1023 CONFIG.Full_Threshold_Assert_Value_wach string false 1023 CONFIG.Full_Threshold_Assert_Value_wdch string false 1023 CONFIG.Full_Threshold_Assert_Value_wrch string false 1023 -CONFIG.Full_Threshold_Negate_Value string false 4094 +CONFIG.Full_Threshold_Negate_Value string false 15999 CONFIG.HAS_ACLKEN string false false CONFIG.HAS_TKEEP string false false CONFIG.HAS_TSTRB string false false @@ -88,7 +88,7 @@ CONFIG.Inject_Sbit_Error_wach string false false CONFIG.Inject_Sbit_Error_wdch string false false CONFIG.Inject_Sbit_Error_wrch string false false CONFIG.Input_Data_Width string false 80 -CONFIG.Input_Depth string false 4096 +CONFIG.Input_Depth string false 16384 CONFIG.Input_Depth_axis string false 1024 CONFIG.Input_Depth_rach string false 16 CONFIG.Input_Depth_rdch string false 1024 @@ -101,7 +101,7 @@ CONFIG.M_AXI.INSERT_VIP string false 0 CONFIG.M_AXIS.INSERT_VIP string false 0 CONFIG.Master_interface_Clock_enable_memory_mapped string false false CONFIG.Output_Data_Width string false 80 -CONFIG.Output_Depth string false 4096 +CONFIG.Output_Depth string false 16384 CONFIG.Output_Register_Type string false Embedded_Reg CONFIG.Overflow_Flag string false false CONFIG.Overflow_Flag_AXI string false false @@ -116,7 +116,7 @@ CONFIG.Programmable_Empty_Type_rdch string false No_Progra CONFIG.Programmable_Empty_Type_wach string false No_Programmable_Empty_Threshold CONFIG.Programmable_Empty_Type_wdch string false No_Programmable_Empty_Threshold CONFIG.Programmable_Empty_Type_wrch string false No_Programmable_Empty_Threshold -CONFIG.Programmable_Full_Type string false No_Programmable_Full_Threshold +CONFIG.Programmable_Full_Type string false Single_Programmable_Full_Threshold_Constant CONFIG.Programmable_Full_Type_axis string false No_Programmable_Full_Threshold CONFIG.Programmable_Full_Type_rach string false No_Programmable_Full_Threshold CONFIG.Programmable_Full_Type_rdch string false No_Programmable_Full_Threshold @@ -129,7 +129,7 @@ CONFIG.READ_WRITE_MODE string false READ_WRIT CONFIG.RUSER_Width string false 0 CONFIG.Read_Clock_Frequency string false 1 CONFIG.Read_Data_Count string false true -CONFIG.Read_Data_Count_Width string false 13 +CONFIG.Read_Data_Count_Width string false 15 CONFIG.Register_Slice_Mode_axis string false Fully_Registered CONFIG.Register_Slice_Mode_rach string false Fully_Registered CONFIG.Register_Slice_Mode_rdch string false Fully_Registered @@ -167,7 +167,7 @@ CONFIG.Write_Acknowledge_Flag string false false CONFIG.Write_Acknowledge_Sense string false Active_High CONFIG.Write_Clock_Frequency string false 1 CONFIG.Write_Data_Count string false true -CONFIG.Write_Data_Count_Width string false 13 +CONFIG.Write_Data_Count_Width string false 15 CONFIG.asymmetric_port_width string false false CONFIG.axis_type string false FIFO CONFIG.dynamic_power_saving string false false diff --git a/firmware/FT0/FTM_PM/ipcore_properties/trg_fifo_comp.txt b/firmware/FT0/FTM_PM/ipcore_properties/trg_fifo_comp.txt index b59b93e..27c9bd6 100644 --- a/firmware/FT0/FTM_PM/ipcore_properties/trg_fifo_comp.txt +++ b/firmware/FT0/FTM_PM/ipcore_properties/trg_fifo_comp.txt @@ -14,7 +14,7 @@ CONFIG.Clock_Type_AXI string false Common_Cl CONFIG.Component_Name string false trg_fifo_comp CONFIG.DATA_WIDTH string false 64 CONFIG.Data_Count string false false -CONFIG.Data_Count_Width string false 9 +CONFIG.Data_Count_Width string false 12 CONFIG.Disable_Timing_Violations string false false CONFIG.Disable_Timing_Violations_AXI string false false CONFIG.Dout_Reset_Value string false 0 @@ -60,14 +60,14 @@ CONFIG.FIFO_Implementation_wdch string false Common_Cl CONFIG.FIFO_Implementation_wrch string false Common_Clock_Block_RAM CONFIG.Fifo_Implementation string false Independent_Clocks_Block_RAM CONFIG.Full_Flags_Reset_Value string false 1 -CONFIG.Full_Threshold_Assert_Value string false 511 +CONFIG.Full_Threshold_Assert_Value string false 4095 CONFIG.Full_Threshold_Assert_Value_axis string false 1023 CONFIG.Full_Threshold_Assert_Value_rach string false 1023 CONFIG.Full_Threshold_Assert_Value_rdch string false 1023 CONFIG.Full_Threshold_Assert_Value_wach string false 1023 CONFIG.Full_Threshold_Assert_Value_wdch string false 1023 CONFIG.Full_Threshold_Assert_Value_wrch string false 1023 -CONFIG.Full_Threshold_Negate_Value string false 510 +CONFIG.Full_Threshold_Negate_Value string false 4094 CONFIG.HAS_ACLKEN string false false CONFIG.HAS_TKEEP string false false CONFIG.HAS_TSTRB string false false @@ -88,7 +88,7 @@ CONFIG.Inject_Sbit_Error_wach string false false CONFIG.Inject_Sbit_Error_wdch string false false CONFIG.Inject_Sbit_Error_wrch string false false CONFIG.Input_Data_Width string false 76 -CONFIG.Input_Depth string false 512 +CONFIG.Input_Depth string false 4096 CONFIG.Input_Depth_axis string false 1024 CONFIG.Input_Depth_rach string false 16 CONFIG.Input_Depth_rdch string false 1024 @@ -101,7 +101,7 @@ CONFIG.M_AXI.INSERT_VIP string false 0 CONFIG.M_AXIS.INSERT_VIP string false 0 CONFIG.Master_interface_Clock_enable_memory_mapped string false false CONFIG.Output_Data_Width string false 76 -CONFIG.Output_Depth string false 512 +CONFIG.Output_Depth string false 4096 CONFIG.Output_Register_Type string false Embedded_Reg CONFIG.Overflow_Flag string false false CONFIG.Overflow_Flag_AXI string false false @@ -129,7 +129,7 @@ CONFIG.READ_WRITE_MODE string false READ_WRIT CONFIG.RUSER_Width string false 0 CONFIG.Read_Clock_Frequency string false 1 CONFIG.Read_Data_Count string false true -CONFIG.Read_Data_Count_Width string false 10 +CONFIG.Read_Data_Count_Width string false 12 CONFIG.Register_Slice_Mode_axis string false Fully_Registered CONFIG.Register_Slice_Mode_rach string false Fully_Registered CONFIG.Register_Slice_Mode_rdch string false Fully_Registered @@ -157,7 +157,7 @@ CONFIG.Underflow_Sense_AXI string false Active_Hi CONFIG.Use_Dout_Reset string false true CONFIG.Use_Embedded_Registers string false false CONFIG.Use_Embedded_Registers_axis string false false -CONFIG.Use_Extra_Logic string false true +CONFIG.Use_Extra_Logic string false false CONFIG.Valid_Flag string false false CONFIG.Valid_Sense string false Active_High CONFIG.WRITE_CLK.FREQ_HZ string false 100000000 @@ -167,7 +167,7 @@ CONFIG.Write_Acknowledge_Flag string false false CONFIG.Write_Acknowledge_Sense string false Active_High CONFIG.Write_Clock_Frequency string false 1 CONFIG.Write_Data_Count string false true -CONFIG.Write_Data_Count_Width string false 10 +CONFIG.Write_Data_Count_Width string false 12 CONFIG.asymmetric_port_width string false false CONFIG.axis_type string false FIFO CONFIG.dynamic_power_saving string false false diff --git a/firmware/FT0/FTM_PM/make.tcl b/firmware/FT0/FTM_PM/make.tcl index 70c5736..0e20ed4 100644 --- a/firmware/FT0/FTM_PM/make.tcl +++ b/firmware/FT0/FTM_PM/make.tcl @@ -1,146 +1,3 @@ -#***************************************************************************************** -# Vivado (TM) v2018.1 (64-bit) -# -# make.tcl: Tcl script for re-creating and building the bitstream for the project 'FIT_TESTMODULE_v1' -# -# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 -# -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/gbt_bank/xilinx_k7v7/gbt_tx/tx_dpram/xlx_k7v7_tx_dpram.xci" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/IP/xlx_k7v7_gbt_rx_frameclk_phalgnr_mmcm/xlx_k7v7_gbt_rx_frameclk_phalgnr_mmcm.xci" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/sources_1/ip/fifo_generator_0/fifo_generator_0.xci" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/sources_1/ip/raw_data_fifo/raw_data_fifo.xci" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/sources_1/ip/COUNTER_FIFO/COUNTER_FIFO.xci" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/sources_1/ip/gig_ethernet_pcs_pma_0/gig_ethernet_pcs_pma_0.xci" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/sources_1/ip/tri_mode_ethernet_mac_0/tri_mode_ethernet_mac_0.xci" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/sources_1/ip/MMCM320_PH_1/MMCM320_PH.xci" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/sources_1/ip/CDM_Clk_pll/CDM_Clk_pll.xci" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/sources_1/ip/PmClockPll/PmClockPll.xci" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/sources_1/ip/spi_mem/spi_mem.xci" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/sources_1/ip/TCM_PLL320/TCM_PLL320.xci" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/FIT_IPBUS/ipbus_slaves/spi_clgen.v" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/FIT_IPBUS/ipbus_slaves/spi_shift.v" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/FIT_IPBUS/ipbus_slaves/spi_top.v" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/fit_gbt_common_package.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/BC_counter.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/fit_gbt_boardPM_package.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/CRU_ORBC_Gen.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/DataCLK_strobe.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/DataConverter_PM.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/FIT_TESTMODULE_IPBUS_sender.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/Module_Data_Gen_PM.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_DATA_sender.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/TX_Data_Gen.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/FIT_TESTMODULE_core.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/FIT_IPBUS/ipbus_core/ipbus_package.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/FIT_IPBUS/ipbus_clock_div.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/FIT_IPBUS/clocks_7s_serdes.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/FIT_IPBUS/led_stretcher.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/FIT_IPBUS/emac_hostbus_decl.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/FIT_IPBUS/eth_7s_1000basex.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/FIT_IPBUS/ipbus_core/ipbus_trans_decl.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/FIT_IPBUS/ipbus_core/udp_build_arp.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/FIT_IPBUS/ipbus_core/udp_build_ping.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/FIT_IPBUS/ipbus_core/udp_ipaddr_block.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/FIT_IPBUS/ipbus_core/udp_build_payload.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/FIT_IPBUS/ipbus_core/udp_build_resend.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/FIT_IPBUS/ipbus_core/udp_build_status.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/FIT_IPBUS/ipbus_core/udp_status_buffer.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/FIT_IPBUS/ipbus_core/udp_byte_sum.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/FIT_IPBUS/ipbus_core/udp_do_rx_reset.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/FIT_IPBUS/ipbus_core/udp_packet_parser.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/FIT_IPBUS/ipbus_core/udp_rxram_mux.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/FIT_IPBUS/ipbus_core/udp_dualportram.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/FIT_IPBUS/ipbus_core/udp_buffer_selector.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/FIT_IPBUS/ipbus_core/udp_rxram_shim.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/FIT_IPBUS/ipbus_core/udp_dualportram_rx.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/FIT_IPBUS/ipbus_core/udp_rxtransactor_if_simple.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/FIT_IPBUS/ipbus_core/udp_dualportram_tx.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/FIT_IPBUS/ipbus_core/udp_tx_mux.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/FIT_IPBUS/ipbus_core/udp_txtransactor_if_simple.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/FIT_IPBUS/ipbus_core/udp_clock_crossing_if.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/FIT_IPBUS/ipbus_core/udp_if_flat.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/FIT_IPBUS/ipbus_core/transactor_if.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/FIT_IPBUS/ipbus_core/transactor_sm.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/FIT_IPBUS/ipbus_core/transactor_cfg.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/FIT_IPBUS/ipbus_core/transactor.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/FIT_IPBUS/ipbus_core/ipbus_ctrl.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/FIT_IPBUS/kc705_basex_infra.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/FIT_IPBUS/ipbus_slaves/ipbus_spi.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/PLL_Reset_Generator.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/Reset_Generator.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/gbt_bank/xilinx_k7v7/xlx_k7v7_gbt_bank_package.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/gbt_bank/xilinx_k7v7/xlx_k7v7_gbt_banks_user_setup.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/gbt_bank/core_sources/gbt_bank_package.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/core_sources/phaligner_mmcm_controller.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/core_sources/rxframeclk_phalgnr/phaligner_phase_computing.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/core_sources/rxframeclk_phalgnr/phaligner_phase_comparator.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/core_sources/xlx_k7v7_phalgnr_std_mmcm.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/core_sources/rxframeclk_phalgnr/gbt_rx_frameclk_phalgnr.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/core_sources/gbt_bank_reset.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/gbt_bank/core_sources/gbt_tx/gbt_tx_scrambler_21bit.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/gbt_bank/core_sources/gbt_tx/gbt_tx_scrambler.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/gbt_bank/core_sources/gbt_tx/gbt_tx_encoder_gbtframe_polydiv.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/gbt_bank/core_sources/gbt_tx/gbt_tx_encoder_gbtframe_rsencode.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/gbt_bank/core_sources/gbt_tx/gbt_tx_encoder_gbtframe_intlver.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/gbt_bank/core_sources/gbt_tx/gbt_tx_encoder.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/gbt_bank/core_sources/gbt_tx/gbt_tx_gearbox_std_rdwrctrl.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/gbt_bank/xilinx_k7v7/gbt_tx/xlx_k7v7_gbt_tx_gearbox_std_dpram.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/gbt_bank/core_sources/gbt_tx/gbt_tx_gearbox_std.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/gbt_bank/core_sources/gbt_tx/gbt_tx_gearbox.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/gbt_bank/core_sources/gbt_tx/gbt_tx_gearbox_phasemon.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/gbt_bank/core_sources/gbt_tx/gbt_tx.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/gbt_bank/xilinx_k7v7/mgt/mgt_ip_vhd/xlx_k7v7_mgt_ip.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/gbt_bank/core_sources/mgt/mgt_latopt_bitslipctrl.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/gbt_bank/xilinx_k7v7/mgt/xlx_k7v7_mgt_latopt.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/gbt_bank/core_sources/mgt/multi_gigabit_transceivers.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/gbt_bank/core_sources/gbt_rx/gbt_rx_framealigner_wraddr.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/gbt_bank/core_sources/gbt_rx/gbt_rx_framealigner_pattsearch.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/gbt_bank/core_sources/gbt_rx/gbt_rx_framealigner_bscounter.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/gbt_bank/core_sources/gbt_rx/gbt_rx_framealigner_rightshift.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/gbt_bank/core_sources/gbt_rx/gbt_rx_framealigner.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/gbt_bank/core_sources/gbt_rx/gbt_rx_gearbox_latopt.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/gbt_bank/core_sources/gbt_rx/gbt_rx_gearbox.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/gbt_bank/core_sources/gbt_rx/gbt_rx_decoder_gbtframe_deintlver.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/gbt_bank/core_sources/gbt_rx/gbt_rx_decoder_gbtframe_syndrom.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/gbt_bank/core_sources/gbt_rx/gbt_rx_decoder_gbtframe_lmbddet.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/gbt_bank/core_sources/gbt_rx/gbt_rx_decoder_gbtframe_errlcpoly.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/gbt_bank/core_sources/gbt_rx/gbt_rx_decoder_gbtframe_elpeval.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/gbt_bank/core_sources/gbt_rx/gbt_rx_decoder_gbtframe_chnsrch.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/gbt_bank/core_sources/gbt_rx/gbt_rx_decoder_gbtframe_rs2errcor.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/gbt_bank/core_sources/gbt_rx/gbt_rx_decoder_gbtframe_rsdec.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/gbt_bank/core_sources/gbt_rx/gbt_rx_decoder.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/gbt_bank/core_sources/gbt_rx/gbt_rx_descrambler_21bit.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/gbt_bank/core_sources/gbt_rx/gbt_rx_descrambler.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/gbt_bank/core_sources/gbt_rx/gbt_rx_status.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/gbt_bank/core_sources/gbt_rx/gbt_rx.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/gbt_bank/core_sources/gbt_bank.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/GBT_TXRX5.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/sources_1/new/TCM_SPI.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/pm-spi.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/sources_1/new/tcm_sc.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/tcm_sync.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/gbt_bank/xilinx_k7v7/mgt/mgt_ip_vhd/xlx_k7v7_mgt_ip_auto_phase_align.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/gbt_bank/xilinx_k7v7/mgt/mgt_ip_vhd/xlx_k7v7_mgt_ip_cpll_railing.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/gbt_bank/xilinx_k7v7/mgt/mgt_ip_vhd/xlx_k7v7_mgt_ip_gt.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/gbt_bank/xilinx_k7v7/mgt/mgt_ip_vhd/xlx_k7v7_mgt_ip_init.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/gbt_bank/xilinx_k7v7/mgt/mgt_ip_vhd/xlx_k7v7_mgt_ip_multi_gt.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/gbt_bank/xilinx_k7v7/mgt/mgt_ip_vhd/xlx_k7v7_mgt_ip_rx_startup_fsm.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/gbt_bank/xilinx_k7v7/mgt/mgt_ip_vhd/xlx_k7v7_mgt_ip_sync_block.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/gbt_bank/xilinx_k7v7/mgt/mgt_ip_vhd/xlx_k7v7_mgt_ip_sync_pulse.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/gbt_bank/xilinx_k7v7/mgt/mgt_ip_vhd/xlx_k7v7_mgt_ip_tx_manual_phase_align.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/gbt_bank/xilinx_k7v7/mgt/mgt_ip_vhd/xlx_k7v7_mgt_ip_tx_startup_fsm.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/FIT_TESTMODULE_v2.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/FIT_IPBUS/ipbus_core/dss_package.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/FIT_IPBUS/ipbus_slaves/ipbus_reg_types.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/sim_1/testbench_FITTESTMODULE.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/constrs_1/FIT_GBT_kc705_io.xdc" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/constrs_1/FIT_GBT_project_cnstrs.xdc" -# -# 3. The following remote source files that were added to the original project:- -# -# -# -#***************************************************************************************** set part "xc7k325tffg900-2" source ../../tcl/fit.tcl @@ -154,7 +11,7 @@ if { [info exists ::origin_dir_loc] } { } # Set the project name -set project_name "FIT_TESTMODULE_PM" +set project_name "FTM_PM" # Use project name variable, if specified in the tcl shell if { [info exists ::user_project_name] } { @@ -212,7 +69,7 @@ if { $::argc > 0 } { # Set the directory path for the original project from where this script was exported set orig_proj_dir "[file normalize "$origin_dir/build"]" -if {[string equal [open_project -quiet "build/FIT_TESTMODULE_v1.xpr"] ""]} { +if {[string equal [open_project -quiet "build/FTM_PM.xpr"] ""]} { set proj_create "yes" puts ${proj_create} puts ${project_name} @@ -234,7 +91,6 @@ set proj_dir [get_property directory [current_project]] set obj [current_project] set_property \ -dict [list \ - "board_part" "xilinx.com:kc705:part0:1.5" \ "corecontainer.enable" "1" \ "default_lib" "xil_defaultlib" \ "ip_cache_permissions" "read write" \ @@ -253,7 +109,7 @@ if {[string equal [get_filesets -quiet sources_1] ""]} { # Import local files from the original project set files [list \ - [file normalize "${origin_dir}/../../common/ftm/hdl/FIT_TESTMODULE_IPBUS_sender.vhd" ]\ + [file normalize "${origin_dir}/../../common/ftm/hdl/ipbus_face.vhd" ]\ [file normalize "${origin_dir}/../../common/ftm/hdl/PLL_Reset_Generator.vhd" ]\ [file normalize "${origin_dir}/../../common/ftm/hdl/TCM_SPI.vhd" ]\ [file normalize "${origin_dir}/../../common/ftm/hdl/tcm_sc.vhd" ]\ @@ -269,7 +125,6 @@ set files [list \ [file normalize "${origin_dir}/../../common/ipbus/hdl/ipbus_core/ipbus_trans_decl.vhd" ]\ [file normalize "${origin_dir}/../../common/ipbus/hdl/ipbus_core/udp_build_arp.vhd" ]\ [file normalize "${origin_dir}/../../common/ipbus/hdl/ipbus_core/udp_build_ping.vhd" ]\ - [file normalize "${origin_dir}/../../common/ipbus/hdl/ipbus_core/udp_ipaddr_block.vhd" ]\ [file normalize "${origin_dir}/../../common/ipbus/hdl/ipbus_core/udp_build_payload.vhd" ]\ [file normalize "${origin_dir}/../../common/ipbus/hdl/ipbus_core/udp_build_resend.vhd" ]\ [file normalize "${origin_dir}/../../common/ipbus/hdl/ipbus_core/udp_build_status.vhd" ]\ @@ -290,7 +145,6 @@ set files [list \ [file normalize "${origin_dir}/../../common/ipbus/hdl/ipbus_core/udp_if_flat.vhd" ]\ [file normalize "${origin_dir}/../../common/ipbus/hdl/ipbus_core/transactor_if.vhd" ]\ [file normalize "${origin_dir}/../../common/ipbus/hdl/ipbus_core/transactor_sm.vhd" ]\ - [file normalize "${origin_dir}/../../common/ipbus/hdl/ipbus_core/transactor_cfg.vhd" ]\ [file normalize "${origin_dir}/../../common/ipbus/hdl/ipbus_core/transactor.vhd" ]\ [file normalize "${origin_dir}/../../common/ipbus/hdl/ipbus_core/ipbus_ctrl.vhd" ]\ [file normalize "${origin_dir}/../../common/ipbus/hdl/ipbus_core/ipbus_package.vhd" ]\ @@ -302,7 +156,6 @@ set files [list \ [file normalize "${origin_dir}/../../common/ipbus/hdl/ipbus_slaves/spi_shift.v" ]\ [file normalize "${origin_dir}/../../common/ipbus/hdl/ipbus_slaves/spi_top.v" ]\ [file normalize "${origin_dir}/../../common/ipbus/hdl/ipbus_slaves/ipbus_spi.vhd" ]\ - [file normalize "${origin_dir}/../../common/gbt-readout/hdl/GBT_TXRX5.vhd" ]\ [file normalize "${origin_dir}/../../common/gbt-fpga/hdl/core_sources/phaligner_mmcm_controller.vhd" ]\ [file normalize "${origin_dir}/../../common/gbt-fpga/hdl/core_sources/xlx_k7v7_phalgnr_std_mmcm.vhd" ]\ [file normalize "${origin_dir}/../../common/gbt-fpga/hdl/core_sources/rxframeclk_phalgnr/phaligner_phase_computing.vhd" ]\ @@ -360,24 +213,24 @@ set files [list \ [file normalize "${origin_dir}/../../common/gbt-fpga/hdl/gbt_bank/xilinx_k7v7/mgt/mgt_ip_vhd/xlx_k7v7_mgt_ip_tx_manual_phase_align.vhd" ]\ [file normalize "${origin_dir}/../../common/gbt-fpga/hdl/gbt_bank/xilinx_k7v7/mgt/mgt_ip_vhd/xlx_k7v7_mgt_ip_tx_startup_fsm.vhd" ]\ [file normalize "${origin_dir}/../../common/gbt-readout/hdl/GBT_TXRX5.vhd"] \ - [file normalize "${origin_dir}/../../common/gbt-readout/hdl/DataCLK_strobe.vhd" ]\ [file normalize "${origin_dir}/../../common/gbt-readout/hdl/DataConverter_PM.vhd" ]\ - [file normalize "${origin_dir}/../../common/gbt-readout/hdl/RX_Data_Decoder.vhd" ]\ - [file normalize "${origin_dir}/../../common/gbt-readout/hdl/BC_counter.vhd" ]\ + [file normalize "${origin_dir}/../../common/gbt-readout/hdl/bc_indicator.vhd" ]\ + [file normalize "${origin_dir}/../../common/gbt-readout/hdl/ltu_rx_decoder.vhd" ]\ [file normalize "${origin_dir}/../../common/gbt-readout/hdl/Reset_Generator.vhd" ]\ [file normalize "${origin_dir}/../../common/gbt-readout/hdl/fit_gbt_boardPM_package.vhd" ]\ [file normalize "${origin_dir}/../../common/gbt-readout/hdl/FIT_GBT_project.vhd" ]\ [file normalize "${origin_dir}/../../common/gbt-readout/hdl/Module_Data_Gen_PM.vhd" ]\ - [file normalize "${origin_dir}/../../common/gbt-readout/hdl/CRU_ORBC_Gen.vhd" ]\ + [file normalize "${origin_dir}/../../common/gbt-readout/hdl/cru_ltu_emu.vhd" ]\ [file normalize "${origin_dir}/../../common/gbt-readout/hdl/TX_Data_Gen.vhd" ]\ [file normalize "${origin_dir}/../../common/gbt-readout/hdl/Event_selector.vhd" ]\ [file normalize "${origin_dir}/../../common/gbt-readout/hdl/fit_gbt_common_package.vhd" ]\ [file normalize "${origin_dir}/../../common/gbt-readout/hdl/RXDataClkSync.vhd" ]\ [file normalize "${origin_dir}/../../common/gbt-readout/hdl/CRU_packet_Builder.vhd" ]\ - [file normalize "${origin_dir}/../../common/gbt-readout/hdl/Data_Packager.vhd" ]\ + [file normalize "${origin_dir}/../../common/gbt-readout/hdl/snapshot_fifo.vhd" ]\ + [file normalize "${origin_dir}/../../common/gbt-readout/hdl/error_report.vhd" ]\ ] -set imported_files [import_files -fileset sources_1 $files] +add_files -norecurse -fileset sources_1 $files #------------------------------------------------------------------------------- if {[string equal $proj_create "yes"]} { @@ -397,7 +250,7 @@ if {[string equal $proj_create "yes"]} { # Set 'sources_1' fileset properties set_property \ -dict [list \ - "top" "tcm"] \ + "top" "FIT_TESTMODULE_v2"] \ [get_filesets sources_1] # Create 'constrs_1' fileset (if not found) @@ -411,11 +264,14 @@ if {[string equal $proj_create "yes"]} { set file "[file normalize "$origin_dir/xdc/FIT_GBT_project_cnstrs.xdc"]" add_files -fileset constrs_1 [list $file] + + set file "[file normalize "$origin_dir/xdc/FIT_GBT_kc705_chipscope.xdc"]" + add_files -fileset constrs_1 [list $file] set_property -name "file_type" -value "XDC" -objects [get_files -of_objects [get_filesets constrs_1] [list "*/xdc/*.xdc"]] # Set 'constrs_1' fileset properties - set_property -name "target_constrs_file" -value "[get_files *xdc/FIT_GBT_kc705_io.xdc]" -objects [get_filesets constrs_1] + set_property -name "target_constrs_file" -value "[get_files *xdc/FIT_GBT_kc705_chipscope.xdc]" -objects [get_filesets constrs_1] } #------------------------------------------------------------------------------- @@ -431,22 +287,13 @@ foreach ip [get_ips] { - - - - - - - # Create 'sim_1' fileset (if not found) if {[string equal [get_filesets -quiet sim_1] ""]} { create_fileset -simset sim_1 } -# [file normalize "${origin_dir}/hdl/sim_1/testbench_FITTESTMODULE.vhd" ] -# set file "sim_1/testbench_FITTESTMODULE.vhd" -# set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -# set_property -name "file_type" -value "VHDL" -objects $file_obj + + # Set 'sim_1' fileset object set obj [get_filesets sim_1] @@ -455,7 +302,8 @@ set files [list \ [file normalize "${origin_dir}/../../common/gbt-readout/sim/readout_simulation.vhd" ]\ [file normalize "${origin_dir}/../../common/gbt-readout/sim/main_signals.wcfg" ]\ ] -set imported_files [import_files -fileset sim_1 $files] +#set imported_files [import_files -fileset sim_1 $files] +add_files -norecurse -fileset sim_1 $files # Set 'sim_1' fileset properties set obj [get_filesets sim_1] @@ -465,13 +313,6 @@ set_property -name "top" -value "testbench_readout" -objects $obj - - - - - - - # Create 'synth_1' run (if not found) if {[string equal [get_runs -quiet synth_1] ""]} { create_run -name synth_1 -part xc7k325tffg900-2 -flow {Vivado Synthesis 2019} -strategy "Flow_PerfOptimized_high" -report_strategy {No Reports} -constrset constrs_1 @@ -564,3 +405,5 @@ update_compile_order -fileset sources_1 reset_run -quiet synth_1 launch_runs impl_1 -to_step write_bitstream -jobs 7 wait_on_run impl_1 +open_run impl_1 +report_timing_summary -file impl_1_timing_summary.log diff --git a/firmware/FT0/FTM_PM/min_area_pfile.tmp b/firmware/FT0/FTM_PM/min_area_pfile.tmp new file mode 100644 index 0000000..b3f35c6 --- /dev/null +++ b/firmware/FT0/FTM_PM/min_area_pfile.tmp @@ -0,0 +1,21 @@ +10000 +1 +3 +4 +1 +0 +0 +9 +80 +80 +80 +80 +4096 +4096 +4096 +4096 +0 +0 +0 +0 +1 diff --git a/firmware/FT0/FTM_PM/xdc/FIT_GBT_project_cnstrs.xdc b/firmware/FT0/FTM_PM/xdc/FIT_GBT_project_cnstrs.xdc index cb875fb..c146422 100644 --- a/firmware/FT0/FTM_PM/xdc/FIT_GBT_project_cnstrs.xdc +++ b/firmware/FT0/FTM_PM/xdc/FIT_GBT_project_cnstrs.xdc @@ -48,7 +48,7 @@ set_clock_groups -name ASYNC_CLOCIPB -asynchronous -group [get_clocks -include_g #RESET ========================================================================== -set_false_path -from [get_cells Reset_Generator_comp/GenRes_DataClk_ff*_reg] +#set_false_path -from [get_cells Reset_Generator_comp/GenRes_DataClk_ff*_reg] #================================================================================ @@ -58,7 +58,9 @@ set_max_delay -datapath_only -from [get_cells HDMI0/trig_data_reg[*]] -to [get_c set_max_delay -datapath_only -from [get_cells HDMI0/DValid_reg] -to [get_clocks SystemCLK_320] 1.000 set_property ASYNC_REG true [get_cells {hdmi_ready0_reg hdmi_ready1_reg}] -set_false_path -from [get_clocks RXDataCLK] -to [get_cells {FitGbtPrg/gbt_bank_gen.gbtBankDsgn/GBT_Status_O_reg[gbtRx_ErrorDet] FitGbtPrg/gbt_bank_gen.gbtBankDsgn/GBT_Status_O_reg[gbtRx_Ready]}] +set_false_path -from [get_clocks RXDataCLK] -to [get_cells {FitGbtPrg/gbt_bank_gen.gbtBankDsgn/gbtRx_ErrorDet_ff_reg FitGbtPrg/gbt_bank_gen.gbtBankDsgn/GBT_Status_O_reg[*]}] +set_false_path -from [get_clocks RXDataCLK] -to [get_cells {FitGbtPrg/gbt_bank_gen.gbtBankDsgn/gbtRx_ErrorDet_ff_reg FitGbtPrg/gbt_bank_gen.gbtBankDsgn/gbtRx_ErrorDet_ff*}] +set_false_path -from [get_clocks RXDataCLK] -to [get_cells {FitGbtPrg/gbt_bank_gen.gbtBankDsgn/gbtRx_ErrorDet_ff_reg FitGbtPrg/gbt_bank_gen.gbtBankDsgn/Rx_Ready_ff*}] @@ -70,8 +72,14 @@ set_multicycle_path -hold -start -from [get_clocks RxWordCLK] -to [get_cells {Fi FitGbtPrg/gbt_bank_gen.gbtBankDsgn/gbtBank/gbtRx_param_package_src_gen.gbtRx_gen[1].gbtRx/descrambler/gbtFrameOrWideBus_gen.gbtRxDescrambler84bit_gen[?].gbtRxDescrambler21bit/feedbackRegister_reg[*]}] 2 +# RX Sync comp ------------------------------------- +set_max_delay -datapath_only -from [get_clocks RXDataCLK] -to [get_cells {FitGbtPrg/RxData_ClkSync_comp/RX_DATA_sysclk_reg[*]}] 3.000 +set_max_delay -datapath_only -from [get_clocks RXDataCLK] -to [get_cells {FitGbtPrg/RxData_ClkSync_comp/RX_IS_DATA_sysclk_reg*}] 3.000 +set_max_delay -datapath_only -from [get_clocks RXDataCLK] -to [get_cells FitGbtPrg/RxData_ClkSync_comp/RX_CLK_from00_reg] 2.000 set_property ASYNC_REG true [get_cells FitGbtPrg/RxData_ClkSync_comp/RX_CLK_from00_reg] set_property ASYNC_REG true [get_cells FitGbtPrg/RxData_ClkSync_comp/RX_CLK_from01_reg] +set_multicycle_path 8 -setup -from [get_clocks TX_CLK] -to [get_pins FitGbtPrg/RxData_ClkSync_comp/rx_error_reset_sclk_reg/D] +set_multicycle_path 7 -hold -end -from [get_clocks TX_CLK] -to [get_pins FitGbtPrg/RxData_ClkSync_comp/rx_error_reset_sclk_reg/D] #================================================================================ diff --git a/firmware/FT0/FTM_TCM/ipcore_properties/cntpck_fifo_comp.txt b/firmware/FT0/FTM_TCM/ipcore_properties/cntpck_fifo_comp.txt index c22a96e..425c87c 100644 --- a/firmware/FT0/FTM_TCM/ipcore_properties/cntpck_fifo_comp.txt +++ b/firmware/FT0/FTM_TCM/ipcore_properties/cntpck_fifo_comp.txt @@ -14,7 +14,7 @@ CONFIG.Clock_Type_AXI string false Common_Cl CONFIG.Component_Name string false cntpck_fifo_comp CONFIG.DATA_WIDTH string false 64 CONFIG.Data_Count string false false -CONFIG.Data_Count_Width string false 7 +CONFIG.Data_Count_Width string false 8 CONFIG.Disable_Timing_Violations string false false CONFIG.Disable_Timing_Violations_AXI string false false CONFIG.Dout_Reset_Value string false 0 @@ -60,14 +60,14 @@ CONFIG.FIFO_Implementation_wdch string false Common_Cl CONFIG.FIFO_Implementation_wrch string false Common_Clock_Block_RAM CONFIG.Fifo_Implementation string false Independent_Clocks_Block_RAM CONFIG.Full_Flags_Reset_Value string false 1 -CONFIG.Full_Threshold_Assert_Value string false 127 +CONFIG.Full_Threshold_Assert_Value string false 255 CONFIG.Full_Threshold_Assert_Value_axis string false 1023 CONFIG.Full_Threshold_Assert_Value_rach string false 1023 CONFIG.Full_Threshold_Assert_Value_rdch string false 1023 CONFIG.Full_Threshold_Assert_Value_wach string false 1023 CONFIG.Full_Threshold_Assert_Value_wdch string false 1023 CONFIG.Full_Threshold_Assert_Value_wrch string false 1023 -CONFIG.Full_Threshold_Negate_Value string false 126 +CONFIG.Full_Threshold_Negate_Value string false 254 CONFIG.HAS_ACLKEN string false false CONFIG.HAS_TKEEP string false false CONFIG.HAS_TSTRB string false false @@ -87,8 +87,8 @@ CONFIG.Inject_Sbit_Error_rdch string false false CONFIG.Inject_Sbit_Error_wach string false false CONFIG.Inject_Sbit_Error_wdch string false false CONFIG.Inject_Sbit_Error_wrch string false false -CONFIG.Input_Data_Width string false 160 -CONFIG.Input_Depth string false 128 +CONFIG.Input_Data_Width string false 128 +CONFIG.Input_Depth string false 256 CONFIG.Input_Depth_axis string false 1024 CONFIG.Input_Depth_rach string false 16 CONFIG.Input_Depth_rdch string false 1024 @@ -100,8 +100,8 @@ CONFIG.MASTER_ACLK.INSERT_VIP string false 0 CONFIG.M_AXI.INSERT_VIP string false 0 CONFIG.M_AXIS.INSERT_VIP string false 0 CONFIG.Master_interface_Clock_enable_memory_mapped string false false -CONFIG.Output_Data_Width string false 160 -CONFIG.Output_Depth string false 128 +CONFIG.Output_Data_Width string false 128 +CONFIG.Output_Depth string false 256 CONFIG.Output_Register_Type string false Embedded_Reg CONFIG.Overflow_Flag string false false CONFIG.Overflow_Flag_AXI string false false @@ -157,7 +157,7 @@ CONFIG.Underflow_Sense_AXI string false Active_Hi CONFIG.Use_Dout_Reset string false true CONFIG.Use_Embedded_Registers string false false CONFIG.Use_Embedded_Registers_axis string false false -CONFIG.Use_Extra_Logic string false true +CONFIG.Use_Extra_Logic string false false CONFIG.Valid_Flag string false false CONFIG.Valid_Sense string false Active_High CONFIG.WRITE_CLK.FREQ_HZ string false 100000000 diff --git a/firmware/FT0/FTM_TCM/ipcore_properties/err_report_fifo.txt b/firmware/FT0/FTM_TCM/ipcore_properties/err_report_fifo.txt new file mode 100644 index 0000000..ae3e3d4 --- /dev/null +++ b/firmware/FT0/FTM_TCM/ipcore_properties/err_report_fifo.txt @@ -0,0 +1,185 @@ +Property Type Read-only Value +CONFIG.ADDRESS_WIDTH string false 32 +CONFIG.ARUSER_Width string false 0 +CONFIG.AWUSER_Width string false 0 +CONFIG.Add_NGC_Constraint_AXI string false false +CONFIG.Almost_Empty_Flag string false false +CONFIG.Almost_Full_Flag string false false +CONFIG.BUSER_Width string false 0 +CONFIG.CORE_CLK.FREQ_HZ string false 100000000 +CONFIG.CORE_CLK.INSERT_VIP string false 0 +CONFIG.C_SELECT_XPM string false 0 +CONFIG.Clock_Enable_Type string false Slave_Interface_Clock_Enable +CONFIG.Clock_Type_AXI string false Common_Clock +CONFIG.Component_Name string false err_report_fifo +CONFIG.DATA_WIDTH string false 64 +CONFIG.Data_Count string false false +CONFIG.Data_Count_Width string false 11 +CONFIG.Disable_Timing_Violations string false false +CONFIG.Disable_Timing_Violations_AXI string false false +CONFIG.Dout_Reset_Value string false 0 +CONFIG.Empty_Threshold_Assert_Value string false 4 +CONFIG.Empty_Threshold_Assert_Value_axis string false 1022 +CONFIG.Empty_Threshold_Assert_Value_rach string false 1022 +CONFIG.Empty_Threshold_Assert_Value_rdch string false 1022 +CONFIG.Empty_Threshold_Assert_Value_wach string false 1022 +CONFIG.Empty_Threshold_Assert_Value_wdch string false 1022 +CONFIG.Empty_Threshold_Assert_Value_wrch string false 1022 +CONFIG.Empty_Threshold_Negate_Value string false 5 +CONFIG.Enable_Common_Overflow string false false +CONFIG.Enable_Common_Underflow string false false +CONFIG.Enable_Data_Counts_axis string false false +CONFIG.Enable_Data_Counts_rach string false false +CONFIG.Enable_Data_Counts_rdch string false false +CONFIG.Enable_Data_Counts_wach string false false +CONFIG.Enable_Data_Counts_wdch string false false +CONFIG.Enable_Data_Counts_wrch string false false +CONFIG.Enable_ECC string false false +CONFIG.Enable_ECC_Type string false Hard_ECC +CONFIG.Enable_ECC_axis string false false +CONFIG.Enable_ECC_rach string false false +CONFIG.Enable_ECC_rdch string false false +CONFIG.Enable_ECC_wach string false false +CONFIG.Enable_ECC_wdch string false false +CONFIG.Enable_ECC_wrch string false false +CONFIG.Enable_Reset_Synchronization string false true +CONFIG.Enable_Safety_Circuit string false false +CONFIG.Enable_TLAST string false false +CONFIG.Enable_TREADY string false true +CONFIG.FIFO_Application_Type_axis string false Data_FIFO +CONFIG.FIFO_Application_Type_rach string false Data_FIFO +CONFIG.FIFO_Application_Type_rdch string false Data_FIFO +CONFIG.FIFO_Application_Type_wach string false Data_FIFO +CONFIG.FIFO_Application_Type_wdch string false Data_FIFO +CONFIG.FIFO_Application_Type_wrch string false Data_FIFO +CONFIG.FIFO_Implementation_axis string false Common_Clock_Block_RAM +CONFIG.FIFO_Implementation_rach string false Common_Clock_Block_RAM +CONFIG.FIFO_Implementation_rdch string false Common_Clock_Block_RAM +CONFIG.FIFO_Implementation_wach string false Common_Clock_Block_RAM +CONFIG.FIFO_Implementation_wdch string false Common_Clock_Block_RAM +CONFIG.FIFO_Implementation_wrch string false Common_Clock_Block_RAM +CONFIG.Fifo_Implementation string false Common_Clock_Block_RAM +CONFIG.Full_Flags_Reset_Value string false 0 +CONFIG.Full_Threshold_Assert_Value string false 1023 +CONFIG.Full_Threshold_Assert_Value_axis string false 1023 +CONFIG.Full_Threshold_Assert_Value_rach string false 1023 +CONFIG.Full_Threshold_Assert_Value_rdch string false 1023 +CONFIG.Full_Threshold_Assert_Value_wach string false 1023 +CONFIG.Full_Threshold_Assert_Value_wdch string false 1023 +CONFIG.Full_Threshold_Assert_Value_wrch string false 1023 +CONFIG.Full_Threshold_Negate_Value string false 1022 +CONFIG.HAS_ACLKEN string false false +CONFIG.HAS_TKEEP string false false +CONFIG.HAS_TSTRB string false false +CONFIG.ID_WIDTH string false 0 +CONFIG.INTERFACE_TYPE string false Native +CONFIG.Inject_Dbit_Error string false false +CONFIG.Inject_Dbit_Error_axis string false false +CONFIG.Inject_Dbit_Error_rach string false false +CONFIG.Inject_Dbit_Error_rdch string false false +CONFIG.Inject_Dbit_Error_wach string false false +CONFIG.Inject_Dbit_Error_wdch string false false +CONFIG.Inject_Dbit_Error_wrch string false false +CONFIG.Inject_Sbit_Error string false false +CONFIG.Inject_Sbit_Error_axis string false false +CONFIG.Inject_Sbit_Error_rach string false false +CONFIG.Inject_Sbit_Error_rdch string false false +CONFIG.Inject_Sbit_Error_wach string false false +CONFIG.Inject_Sbit_Error_wdch string false false +CONFIG.Inject_Sbit_Error_wrch string false false +CONFIG.Input_Data_Width string false 32 +CONFIG.Input_Depth string false 1024 +CONFIG.Input_Depth_axis string false 1024 +CONFIG.Input_Depth_rach string false 16 +CONFIG.Input_Depth_rdch string false 1024 +CONFIG.Input_Depth_wach string false 16 +CONFIG.Input_Depth_wdch string false 1024 +CONFIG.Input_Depth_wrch string false 16 +CONFIG.MASTER_ACLK.FREQ_HZ string false 100000000 +CONFIG.MASTER_ACLK.INSERT_VIP string false 0 +CONFIG.M_AXI.INSERT_VIP string false 0 +CONFIG.M_AXIS.INSERT_VIP string false 0 +CONFIG.Master_interface_Clock_enable_memory_mapped string false false +CONFIG.Output_Data_Width string false 32 +CONFIG.Output_Depth string false 1024 +CONFIG.Output_Register_Type string false Embedded_Reg +CONFIG.Overflow_Flag string false false +CONFIG.Overflow_Flag_AXI string false false +CONFIG.Overflow_Sense string false Active_High +CONFIG.Overflow_Sense_AXI string false Active_High +CONFIG.PROTOCOL string false AXI4 +CONFIG.Performance_Options string false First_Word_Fall_Through +CONFIG.Programmable_Empty_Type string false No_Programmable_Empty_Threshold +CONFIG.Programmable_Empty_Type_axis string false No_Programmable_Empty_Threshold +CONFIG.Programmable_Empty_Type_rach string false No_Programmable_Empty_Threshold +CONFIG.Programmable_Empty_Type_rdch string false No_Programmable_Empty_Threshold +CONFIG.Programmable_Empty_Type_wach string false No_Programmable_Empty_Threshold +CONFIG.Programmable_Empty_Type_wdch string false No_Programmable_Empty_Threshold +CONFIG.Programmable_Empty_Type_wrch string false No_Programmable_Empty_Threshold +CONFIG.Programmable_Full_Type string false No_Programmable_Full_Threshold +CONFIG.Programmable_Full_Type_axis string false No_Programmable_Full_Threshold +CONFIG.Programmable_Full_Type_rach string false No_Programmable_Full_Threshold +CONFIG.Programmable_Full_Type_rdch string false No_Programmable_Full_Threshold +CONFIG.Programmable_Full_Type_wach string false No_Programmable_Full_Threshold +CONFIG.Programmable_Full_Type_wdch string false No_Programmable_Full_Threshold +CONFIG.Programmable_Full_Type_wrch string false No_Programmable_Full_Threshold +CONFIG.READ_CLK.FREQ_HZ string false 100000000 +CONFIG.READ_CLK.INSERT_VIP string false 0 +CONFIG.READ_WRITE_MODE string false READ_WRITE +CONFIG.RUSER_Width string false 0 +CONFIG.Read_Clock_Frequency string false 1 +CONFIG.Read_Data_Count string false false +CONFIG.Read_Data_Count_Width string false 11 +CONFIG.Register_Slice_Mode_axis string false Fully_Registered +CONFIG.Register_Slice_Mode_rach string false Fully_Registered +CONFIG.Register_Slice_Mode_rdch string false Fully_Registered +CONFIG.Register_Slice_Mode_wach string false Fully_Registered +CONFIG.Register_Slice_Mode_wdch string false Fully_Registered +CONFIG.Register_Slice_Mode_wrch string false Fully_Registered +CONFIG.Reset_Pin string false true +CONFIG.Reset_Type string false Synchronous_Reset +CONFIG.SLAVE_ACLK.FREQ_HZ string false 100000000 +CONFIG.SLAVE_ACLK.INSERT_VIP string false 0 +CONFIG.SLAVE_ARESETN.INSERT_VIP string false 0 +CONFIG.S_AXI.INSERT_VIP string false 0 +CONFIG.S_AXIS.INSERT_VIP string false 0 +CONFIG.Slave_interface_Clock_enable_memory_mapped string false false +CONFIG.TDATA_NUM_BYTES string false 1 +CONFIG.TDEST_WIDTH string false 0 +CONFIG.TID_WIDTH string false 0 +CONFIG.TKEEP_WIDTH string false 1 +CONFIG.TSTRB_WIDTH string false 1 +CONFIG.TUSER_WIDTH string false 4 +CONFIG.Underflow_Flag string false false +CONFIG.Underflow_Flag_AXI string false false +CONFIG.Underflow_Sense string false Active_High +CONFIG.Underflow_Sense_AXI string false Active_High +CONFIG.Use_Dout_Reset string false true +CONFIG.Use_Embedded_Registers string false false +CONFIG.Use_Embedded_Registers_axis string false false +CONFIG.Use_Extra_Logic string false true +CONFIG.Valid_Flag string false false +CONFIG.Valid_Sense string false Active_High +CONFIG.WRITE_CLK.FREQ_HZ string false 100000000 +CONFIG.WRITE_CLK.INSERT_VIP string false 0 +CONFIG.WUSER_Width string false 0 +CONFIG.Write_Acknowledge_Flag string false false +CONFIG.Write_Acknowledge_Sense string false Active_High +CONFIG.Write_Clock_Frequency string false 1 +CONFIG.Write_Data_Count string false false +CONFIG.Write_Data_Count_Width string false 11 +CONFIG.asymmetric_port_width string false false +CONFIG.axis_type string false FIFO +CONFIG.dynamic_power_saving string false false +CONFIG.ecc_pipeline_reg string false false +CONFIG.enable_low_latency string false false +CONFIG.enable_read_pointer_increment_by2 string false false +CONFIG.rach_type string false FIFO +CONFIG.rdch_type string false FIFO +CONFIG.synchronization_stages string false 2 +CONFIG.synchronization_stages_axi string false 2 +CONFIG.use_dout_register string false false +CONFIG.wach_type string false FIFO +CONFIG.wdch_type string false FIFO +CONFIG.wrch_type string false FIFO +IPDEF string true xilinx.com:ip:fifo_generator:13.2 diff --git a/firmware/FT0/FTM_TCM/ipcore_properties/ipbus_data_fifo.txt b/firmware/FT0/FTM_TCM/ipcore_properties/ipbus_data_fifo.txt index 6553977..d39c73e 100644 --- a/firmware/FT0/FTM_TCM/ipcore_properties/ipbus_data_fifo.txt +++ b/firmware/FT0/FTM_TCM/ipcore_properties/ipbus_data_fifo.txt @@ -129,7 +129,7 @@ CONFIG.READ_WRITE_MODE string false READ_WRIT CONFIG.RUSER_Width string false 0 CONFIG.Read_Clock_Frequency string false 1 CONFIG.Read_Data_Count string false true -CONFIG.Read_Data_Count_Width string false 13 +CONFIG.Read_Data_Count_Width string false 14 CONFIG.Register_Slice_Mode_axis string false Fully_Registered CONFIG.Register_Slice_Mode_rach string false Fully_Registered CONFIG.Register_Slice_Mode_rdch string false Fully_Registered @@ -157,7 +157,7 @@ CONFIG.Underflow_Sense_AXI string false Active_Hi CONFIG.Use_Dout_Reset string false true CONFIG.Use_Embedded_Registers string false false CONFIG.Use_Embedded_Registers_axis string false false -CONFIG.Use_Extra_Logic string false false +CONFIG.Use_Extra_Logic string false true CONFIG.Valid_Flag string false false CONFIG.Valid_Sense string false Active_High CONFIG.WRITE_CLK.FREQ_HZ string false 100000000 @@ -167,7 +167,7 @@ CONFIG.Write_Acknowledge_Flag string false false CONFIG.Write_Acknowledge_Sense string false Active_High CONFIG.Write_Clock_Frequency string false 1 CONFIG.Write_Data_Count string false false -CONFIG.Write_Data_Count_Width string false 14 +CONFIG.Write_Data_Count_Width string false 15 CONFIG.asymmetric_port_width string false false CONFIG.axis_type string false FIFO CONFIG.dynamic_power_saving string false false diff --git a/firmware/FT0/FTM_TCM/ipcore_properties/raw_data_fifo.txt b/firmware/FT0/FTM_TCM/ipcore_properties/raw_data_fifo.txt index 8629119..93f3c73 100644 --- a/firmware/FT0/FTM_TCM/ipcore_properties/raw_data_fifo.txt +++ b/firmware/FT0/FTM_TCM/ipcore_properties/raw_data_fifo.txt @@ -4,7 +4,7 @@ CONFIG.ARUSER_Width string false 0 CONFIG.AWUSER_Width string false 0 CONFIG.Add_NGC_Constraint_AXI string false false CONFIG.Almost_Empty_Flag string false false -CONFIG.Almost_Full_Flag string false false +CONFIG.Almost_Full_Flag string false true CONFIG.BUSER_Width string false 0 CONFIG.CORE_CLK.FREQ_HZ string false 100000000 CONFIG.CORE_CLK.INSERT_VIP string false 0 @@ -60,14 +60,14 @@ CONFIG.FIFO_Implementation_wdch string false Common_Cl CONFIG.FIFO_Implementation_wrch string false Common_Clock_Block_RAM CONFIG.Fifo_Implementation string false Common_Clock_Block_RAM CONFIG.Full_Flags_Reset_Value string false 0 -CONFIG.Full_Threshold_Assert_Value string false 4095 +CONFIG.Full_Threshold_Assert_Value string false 4000 CONFIG.Full_Threshold_Assert_Value_axis string false 1023 CONFIG.Full_Threshold_Assert_Value_rach string false 1023 CONFIG.Full_Threshold_Assert_Value_rdch string false 1023 CONFIG.Full_Threshold_Assert_Value_wach string false 1023 CONFIG.Full_Threshold_Assert_Value_wdch string false 1023 CONFIG.Full_Threshold_Assert_Value_wrch string false 1023 -CONFIG.Full_Threshold_Negate_Value string false 4094 +CONFIG.Full_Threshold_Negate_Value string false 3999 CONFIG.HAS_ACLKEN string false false CONFIG.HAS_TKEEP string false false CONFIG.HAS_TSTRB string false false @@ -116,7 +116,7 @@ CONFIG.Programmable_Empty_Type_rdch string false No_Progra CONFIG.Programmable_Empty_Type_wach string false No_Programmable_Empty_Threshold CONFIG.Programmable_Empty_Type_wdch string false No_Programmable_Empty_Threshold CONFIG.Programmable_Empty_Type_wrch string false No_Programmable_Empty_Threshold -CONFIG.Programmable_Full_Type string false No_Programmable_Full_Threshold +CONFIG.Programmable_Full_Type string false Single_Programmable_Full_Threshold_Constant CONFIG.Programmable_Full_Type_axis string false No_Programmable_Full_Threshold CONFIG.Programmable_Full_Type_rach string false No_Programmable_Full_Threshold CONFIG.Programmable_Full_Type_rdch string false No_Programmable_Full_Threshold diff --git a/firmware/FT0/FTM_TCM/ipcore_properties/slct_data_fifo.txt b/firmware/FT0/FTM_TCM/ipcore_properties/slct_data_fifo.txt index 52b27f5..e454940 100644 --- a/firmware/FT0/FTM_TCM/ipcore_properties/slct_data_fifo.txt +++ b/firmware/FT0/FTM_TCM/ipcore_properties/slct_data_fifo.txt @@ -14,7 +14,7 @@ CONFIG.Clock_Type_AXI string false Common_Cl CONFIG.Component_Name string false slct_data_fifo CONFIG.DATA_WIDTH string false 64 CONFIG.Data_Count string false false -CONFIG.Data_Count_Width string false 12 +CONFIG.Data_Count_Width string false 14 CONFIG.Disable_Timing_Violations string false false CONFIG.Disable_Timing_Violations_AXI string false false CONFIG.Dout_Reset_Value string false 0 @@ -60,14 +60,14 @@ CONFIG.FIFO_Implementation_wdch string false Common_Cl CONFIG.FIFO_Implementation_wrch string false Common_Clock_Block_RAM CONFIG.Fifo_Implementation string false Independent_Clocks_Block_RAM CONFIG.Full_Flags_Reset_Value string false 1 -CONFIG.Full_Threshold_Assert_Value string false 4095 +CONFIG.Full_Threshold_Assert_Value string false 16000 CONFIG.Full_Threshold_Assert_Value_axis string false 1023 CONFIG.Full_Threshold_Assert_Value_rach string false 1023 CONFIG.Full_Threshold_Assert_Value_rdch string false 1023 CONFIG.Full_Threshold_Assert_Value_wach string false 1023 CONFIG.Full_Threshold_Assert_Value_wdch string false 1023 CONFIG.Full_Threshold_Assert_Value_wrch string false 1023 -CONFIG.Full_Threshold_Negate_Value string false 4094 +CONFIG.Full_Threshold_Negate_Value string false 15999 CONFIG.HAS_ACLKEN string false false CONFIG.HAS_TKEEP string false false CONFIG.HAS_TSTRB string false false @@ -88,7 +88,7 @@ CONFIG.Inject_Sbit_Error_wach string false false CONFIG.Inject_Sbit_Error_wdch string false false CONFIG.Inject_Sbit_Error_wrch string false false CONFIG.Input_Data_Width string false 80 -CONFIG.Input_Depth string false 4096 +CONFIG.Input_Depth string false 16384 CONFIG.Input_Depth_axis string false 1024 CONFIG.Input_Depth_rach string false 16 CONFIG.Input_Depth_rdch string false 1024 @@ -101,7 +101,7 @@ CONFIG.M_AXI.INSERT_VIP string false 0 CONFIG.M_AXIS.INSERT_VIP string false 0 CONFIG.Master_interface_Clock_enable_memory_mapped string false false CONFIG.Output_Data_Width string false 80 -CONFIG.Output_Depth string false 4096 +CONFIG.Output_Depth string false 16384 CONFIG.Output_Register_Type string false Embedded_Reg CONFIG.Overflow_Flag string false false CONFIG.Overflow_Flag_AXI string false false @@ -116,7 +116,7 @@ CONFIG.Programmable_Empty_Type_rdch string false No_Progra CONFIG.Programmable_Empty_Type_wach string false No_Programmable_Empty_Threshold CONFIG.Programmable_Empty_Type_wdch string false No_Programmable_Empty_Threshold CONFIG.Programmable_Empty_Type_wrch string false No_Programmable_Empty_Threshold -CONFIG.Programmable_Full_Type string false No_Programmable_Full_Threshold +CONFIG.Programmable_Full_Type string false Single_Programmable_Full_Threshold_Constant CONFIG.Programmable_Full_Type_axis string false No_Programmable_Full_Threshold CONFIG.Programmable_Full_Type_rach string false No_Programmable_Full_Threshold CONFIG.Programmable_Full_Type_rdch string false No_Programmable_Full_Threshold @@ -129,7 +129,7 @@ CONFIG.READ_WRITE_MODE string false READ_WRIT CONFIG.RUSER_Width string false 0 CONFIG.Read_Clock_Frequency string false 1 CONFIG.Read_Data_Count string false true -CONFIG.Read_Data_Count_Width string false 13 +CONFIG.Read_Data_Count_Width string false 15 CONFIG.Register_Slice_Mode_axis string false Fully_Registered CONFIG.Register_Slice_Mode_rach string false Fully_Registered CONFIG.Register_Slice_Mode_rdch string false Fully_Registered @@ -167,7 +167,7 @@ CONFIG.Write_Acknowledge_Flag string false false CONFIG.Write_Acknowledge_Sense string false Active_High CONFIG.Write_Clock_Frequency string false 1 CONFIG.Write_Data_Count string false true -CONFIG.Write_Data_Count_Width string false 13 +CONFIG.Write_Data_Count_Width string false 15 CONFIG.asymmetric_port_width string false false CONFIG.axis_type string false FIFO CONFIG.dynamic_power_saving string false false diff --git a/firmware/FT0/FTM_TCM/ipcore_properties/trg_fifo_comp.txt b/firmware/FT0/FTM_TCM/ipcore_properties/trg_fifo_comp.txt index b59b93e..27c9bd6 100644 --- a/firmware/FT0/FTM_TCM/ipcore_properties/trg_fifo_comp.txt +++ b/firmware/FT0/FTM_TCM/ipcore_properties/trg_fifo_comp.txt @@ -14,7 +14,7 @@ CONFIG.Clock_Type_AXI string false Common_Cl CONFIG.Component_Name string false trg_fifo_comp CONFIG.DATA_WIDTH string false 64 CONFIG.Data_Count string false false -CONFIG.Data_Count_Width string false 9 +CONFIG.Data_Count_Width string false 12 CONFIG.Disable_Timing_Violations string false false CONFIG.Disable_Timing_Violations_AXI string false false CONFIG.Dout_Reset_Value string false 0 @@ -60,14 +60,14 @@ CONFIG.FIFO_Implementation_wdch string false Common_Cl CONFIG.FIFO_Implementation_wrch string false Common_Clock_Block_RAM CONFIG.Fifo_Implementation string false Independent_Clocks_Block_RAM CONFIG.Full_Flags_Reset_Value string false 1 -CONFIG.Full_Threshold_Assert_Value string false 511 +CONFIG.Full_Threshold_Assert_Value string false 4095 CONFIG.Full_Threshold_Assert_Value_axis string false 1023 CONFIG.Full_Threshold_Assert_Value_rach string false 1023 CONFIG.Full_Threshold_Assert_Value_rdch string false 1023 CONFIG.Full_Threshold_Assert_Value_wach string false 1023 CONFIG.Full_Threshold_Assert_Value_wdch string false 1023 CONFIG.Full_Threshold_Assert_Value_wrch string false 1023 -CONFIG.Full_Threshold_Negate_Value string false 510 +CONFIG.Full_Threshold_Negate_Value string false 4094 CONFIG.HAS_ACLKEN string false false CONFIG.HAS_TKEEP string false false CONFIG.HAS_TSTRB string false false @@ -88,7 +88,7 @@ CONFIG.Inject_Sbit_Error_wach string false false CONFIG.Inject_Sbit_Error_wdch string false false CONFIG.Inject_Sbit_Error_wrch string false false CONFIG.Input_Data_Width string false 76 -CONFIG.Input_Depth string false 512 +CONFIG.Input_Depth string false 4096 CONFIG.Input_Depth_axis string false 1024 CONFIG.Input_Depth_rach string false 16 CONFIG.Input_Depth_rdch string false 1024 @@ -101,7 +101,7 @@ CONFIG.M_AXI.INSERT_VIP string false 0 CONFIG.M_AXIS.INSERT_VIP string false 0 CONFIG.Master_interface_Clock_enable_memory_mapped string false false CONFIG.Output_Data_Width string false 76 -CONFIG.Output_Depth string false 512 +CONFIG.Output_Depth string false 4096 CONFIG.Output_Register_Type string false Embedded_Reg CONFIG.Overflow_Flag string false false CONFIG.Overflow_Flag_AXI string false false @@ -129,7 +129,7 @@ CONFIG.READ_WRITE_MODE string false READ_WRIT CONFIG.RUSER_Width string false 0 CONFIG.Read_Clock_Frequency string false 1 CONFIG.Read_Data_Count string false true -CONFIG.Read_Data_Count_Width string false 10 +CONFIG.Read_Data_Count_Width string false 12 CONFIG.Register_Slice_Mode_axis string false Fully_Registered CONFIG.Register_Slice_Mode_rach string false Fully_Registered CONFIG.Register_Slice_Mode_rdch string false Fully_Registered @@ -157,7 +157,7 @@ CONFIG.Underflow_Sense_AXI string false Active_Hi CONFIG.Use_Dout_Reset string false true CONFIG.Use_Embedded_Registers string false false CONFIG.Use_Embedded_Registers_axis string false false -CONFIG.Use_Extra_Logic string false true +CONFIG.Use_Extra_Logic string false false CONFIG.Valid_Flag string false false CONFIG.Valid_Sense string false Active_High CONFIG.WRITE_CLK.FREQ_HZ string false 100000000 @@ -167,7 +167,7 @@ CONFIG.Write_Acknowledge_Flag string false false CONFIG.Write_Acknowledge_Sense string false Active_High CONFIG.Write_Clock_Frequency string false 1 CONFIG.Write_Data_Count string false true -CONFIG.Write_Data_Count_Width string false 10 +CONFIG.Write_Data_Count_Width string false 12 CONFIG.asymmetric_port_width string false false CONFIG.axis_type string false FIFO CONFIG.dynamic_power_saving string false false diff --git a/firmware/FT0/FTM_TCM/make.tcl b/firmware/FT0/FTM_TCM/make.tcl index 5f7c241..e3aa752 100644 --- a/firmware/FT0/FTM_TCM/make.tcl +++ b/firmware/FT0/FTM_TCM/make.tcl @@ -1,146 +1,3 @@ -#***************************************************************************************** -# Vivado (TM) v2018.1 (64-bit) -# -# make.tcl: Tcl script for re-creating and building the bitstream for the project 'FIT_TESTMODULE_v1' -# -# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 -# -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/gbt_bank/xilinx_k7v7/gbt_tx/tx_dpram/xlx_k7v7_tx_dpram.xci" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/IP/xlx_k7v7_gbt_rx_frameclk_phalgnr_mmcm/xlx_k7v7_gbt_rx_frameclk_phalgnr_mmcm.xci" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/sources_1/ip/fifo_generator_0/fifo_generator_0.xci" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/sources_1/ip/raw_data_fifo/raw_data_fifo.xci" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/sources_1/ip/COUNTER_FIFO/COUNTER_FIFO.xci" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/sources_1/ip/gig_ethernet_pcs_pma_0/gig_ethernet_pcs_pma_0.xci" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/sources_1/ip/tri_mode_ethernet_mac_0/tri_mode_ethernet_mac_0.xci" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/sources_1/ip/MMCM320_PH_1/MMCM320_PH.xci" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/sources_1/ip/CDM_Clk_pll/CDM_Clk_pll.xci" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/sources_1/ip/PmClockPll/PmClockPll.xci" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/sources_1/ip/spi_mem/spi_mem.xci" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/sources_1/ip/TCM_PLL320/TCM_PLL320.xci" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/FIT_IPBUS/ipbus_slaves/spi_clgen.v" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/FIT_IPBUS/ipbus_slaves/spi_shift.v" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/FIT_IPBUS/ipbus_slaves/spi_top.v" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/fit_gbt_common_package.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/BC_counter.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/fit_gbt_boardPM_package.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/CRU_ORBC_Gen.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/DataCLK_strobe.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/DataConverter_PM.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/FIT_TESTMODULE_IPBUS_sender.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/Module_Data_Gen_PM.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_DATA_sender.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/TX_Data_Gen.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/FIT_TESTMODULE_core.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/FIT_IPBUS/ipbus_core/ipbus_package.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/FIT_IPBUS/ipbus_clock_div.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/FIT_IPBUS/clocks_7s_serdes.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/FIT_IPBUS/led_stretcher.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/FIT_IPBUS/emac_hostbus_decl.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/FIT_IPBUS/eth_7s_1000basex.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/FIT_IPBUS/ipbus_core/ipbus_trans_decl.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/FIT_IPBUS/ipbus_core/udp_build_arp.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/FIT_IPBUS/ipbus_core/udp_build_ping.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/FIT_IPBUS/ipbus_core/udp_ipaddr_block.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/FIT_IPBUS/ipbus_core/udp_build_payload.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/FIT_IPBUS/ipbus_core/udp_build_resend.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/FIT_IPBUS/ipbus_core/udp_build_status.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/FIT_IPBUS/ipbus_core/udp_status_buffer.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/FIT_IPBUS/ipbus_core/udp_byte_sum.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/FIT_IPBUS/ipbus_core/udp_do_rx_reset.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/FIT_IPBUS/ipbus_core/udp_packet_parser.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/FIT_IPBUS/ipbus_core/udp_rxram_mux.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/FIT_IPBUS/ipbus_core/udp_dualportram.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/FIT_IPBUS/ipbus_core/udp_buffer_selector.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/FIT_IPBUS/ipbus_core/udp_rxram_shim.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/FIT_IPBUS/ipbus_core/udp_dualportram_rx.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/FIT_IPBUS/ipbus_core/udp_rxtransactor_if_simple.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/FIT_IPBUS/ipbus_core/udp_dualportram_tx.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/FIT_IPBUS/ipbus_core/udp_tx_mux.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/FIT_IPBUS/ipbus_core/udp_txtransactor_if_simple.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/FIT_IPBUS/ipbus_core/udp_clock_crossing_if.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/FIT_IPBUS/ipbus_core/udp_if_flat.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/FIT_IPBUS/ipbus_core/transactor_if.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/FIT_IPBUS/ipbus_core/transactor_sm.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/FIT_IPBUS/ipbus_core/transactor_cfg.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/FIT_IPBUS/ipbus_core/transactor.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/FIT_IPBUS/ipbus_core/ipbus_ctrl.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/FIT_IPBUS/kc705_basex_infra.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/FIT_IPBUS/ipbus_slaves/ipbus_spi.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/PLL_Reset_Generator.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/Reset_Generator.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/gbt_bank/xilinx_k7v7/xlx_k7v7_gbt_bank_package.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/gbt_bank/xilinx_k7v7/xlx_k7v7_gbt_banks_user_setup.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/gbt_bank/core_sources/gbt_bank_package.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/core_sources/phaligner_mmcm_controller.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/core_sources/rxframeclk_phalgnr/phaligner_phase_computing.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/core_sources/rxframeclk_phalgnr/phaligner_phase_comparator.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/core_sources/xlx_k7v7_phalgnr_std_mmcm.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/core_sources/rxframeclk_phalgnr/gbt_rx_frameclk_phalgnr.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/core_sources/gbt_bank_reset.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/gbt_bank/core_sources/gbt_tx/gbt_tx_scrambler_21bit.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/gbt_bank/core_sources/gbt_tx/gbt_tx_scrambler.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/gbt_bank/core_sources/gbt_tx/gbt_tx_encoder_gbtframe_polydiv.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/gbt_bank/core_sources/gbt_tx/gbt_tx_encoder_gbtframe_rsencode.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/gbt_bank/core_sources/gbt_tx/gbt_tx_encoder_gbtframe_intlver.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/gbt_bank/core_sources/gbt_tx/gbt_tx_encoder.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/gbt_bank/core_sources/gbt_tx/gbt_tx_gearbox_std_rdwrctrl.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/gbt_bank/xilinx_k7v7/gbt_tx/xlx_k7v7_gbt_tx_gearbox_std_dpram.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/gbt_bank/core_sources/gbt_tx/gbt_tx_gearbox_std.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/gbt_bank/core_sources/gbt_tx/gbt_tx_gearbox.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/gbt_bank/core_sources/gbt_tx/gbt_tx_gearbox_phasemon.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/gbt_bank/core_sources/gbt_tx/gbt_tx.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/gbt_bank/xilinx_k7v7/mgt/mgt_ip_vhd/xlx_k7v7_mgt_ip.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/gbt_bank/core_sources/mgt/mgt_latopt_bitslipctrl.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/gbt_bank/xilinx_k7v7/mgt/xlx_k7v7_mgt_latopt.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/gbt_bank/core_sources/mgt/multi_gigabit_transceivers.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/gbt_bank/core_sources/gbt_rx/gbt_rx_framealigner_wraddr.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/gbt_bank/core_sources/gbt_rx/gbt_rx_framealigner_pattsearch.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/gbt_bank/core_sources/gbt_rx/gbt_rx_framealigner_bscounter.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/gbt_bank/core_sources/gbt_rx/gbt_rx_framealigner_rightshift.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/gbt_bank/core_sources/gbt_rx/gbt_rx_framealigner.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/gbt_bank/core_sources/gbt_rx/gbt_rx_gearbox_latopt.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/gbt_bank/core_sources/gbt_rx/gbt_rx_gearbox.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/gbt_bank/core_sources/gbt_rx/gbt_rx_decoder_gbtframe_deintlver.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/gbt_bank/core_sources/gbt_rx/gbt_rx_decoder_gbtframe_syndrom.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/gbt_bank/core_sources/gbt_rx/gbt_rx_decoder_gbtframe_lmbddet.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/gbt_bank/core_sources/gbt_rx/gbt_rx_decoder_gbtframe_errlcpoly.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/gbt_bank/core_sources/gbt_rx/gbt_rx_decoder_gbtframe_elpeval.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/gbt_bank/core_sources/gbt_rx/gbt_rx_decoder_gbtframe_chnsrch.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/gbt_bank/core_sources/gbt_rx/gbt_rx_decoder_gbtframe_rs2errcor.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/gbt_bank/core_sources/gbt_rx/gbt_rx_decoder_gbtframe_rsdec.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/gbt_bank/core_sources/gbt_rx/gbt_rx_decoder.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/gbt_bank/core_sources/gbt_rx/gbt_rx_descrambler_21bit.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/gbt_bank/core_sources/gbt_rx/gbt_rx_descrambler.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/gbt_bank/core_sources/gbt_rx/gbt_rx_status.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/gbt_bank/core_sources/gbt_rx/gbt_rx.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/gbt_bank/core_sources/gbt_bank.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/GBT_TXRX5.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/sources_1/new/TCM_SPI.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/pm-spi.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/sources_1/new/tcm_sc.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/tcm_sync.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/gbt_bank/xilinx_k7v7/mgt/mgt_ip_vhd/xlx_k7v7_mgt_ip_auto_phase_align.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/gbt_bank/xilinx_k7v7/mgt/mgt_ip_vhd/xlx_k7v7_mgt_ip_cpll_railing.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/gbt_bank/xilinx_k7v7/mgt/mgt_ip_vhd/xlx_k7v7_mgt_ip_gt.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/gbt_bank/xilinx_k7v7/mgt/mgt_ip_vhd/xlx_k7v7_mgt_ip_init.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/gbt_bank/xilinx_k7v7/mgt/mgt_ip_vhd/xlx_k7v7_mgt_ip_multi_gt.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/gbt_bank/xilinx_k7v7/mgt/mgt_ip_vhd/xlx_k7v7_mgt_ip_rx_startup_fsm.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/gbt_bank/xilinx_k7v7/mgt/mgt_ip_vhd/xlx_k7v7_mgt_ip_sync_block.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/gbt_bank/xilinx_k7v7/mgt/mgt_ip_vhd/xlx_k7v7_mgt_ip_sync_pulse.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/gbt_bank/xilinx_k7v7/mgt/mgt_ip_vhd/xlx_k7v7_mgt_ip_tx_manual_phase_align.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/GBT_project/gbt_bank/xilinx_k7v7/mgt/mgt_ip_vhd/xlx_k7v7_mgt_ip_tx_startup_fsm.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/FIT_TESTMODULE_v2.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/FIT_IPBUS/ipbus_core/dss_package.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/FIT_IPBUS/ipbus_slaves/ipbus_reg_types.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/sim_1/testbench_FITTESTMODULE.vhd" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/constrs_1/FIT_GBT_kc705_io.xdc" -# "/home/cmayer/20200311/FIT_TESTMODULE_v20_lsfix_2020-03-04/FIT_TESTMODULE_v1.srcs/constrs_1/FIT_GBT_project_cnstrs.xdc" -# -# 3. The following remote source files that were added to the original project:- -# -# -# -#***************************************************************************************** set part "xc7k325tffg900-2" source ../../tcl/fit.tcl @@ -154,7 +11,7 @@ if { [info exists ::origin_dir_loc] } { } # Set the project name -set project_name "FIT_TESTMODULE_TCM" +set project_name "FTM_TCM" # Use project name variable, if specified in the tcl shell if { [info exists ::user_project_name] } { @@ -212,7 +69,7 @@ if { $::argc > 0 } { # Set the directory path for the original project from where this script was exported set orig_proj_dir "[file normalize "$origin_dir/build"]" -if {[string equal [open_project -quiet "build/FIT_TESTMODULE_v1.xpr"] ""]} { +if {[string equal [open_project -quiet "build/FTM_TCM.xpr"] ""]} { set proj_create "yes" puts ${proj_create} puts ${project_name} @@ -253,7 +110,7 @@ if {[string equal [get_filesets -quiet sources_1] ""]} { # Import local files from the original project set files [list \ - [file normalize "${origin_dir}/../../common/ftm/hdl/FIT_TESTMODULE_IPBUS_sender.vhd" ]\ + [file normalize "${origin_dir}/../../common/ftm/hdl/ipbus_face.vhd" ]\ [file normalize "${origin_dir}/../../common/ftm/hdl/PLL_Reset_Generator.vhd" ]\ [file normalize "${origin_dir}/../../common/ftm/hdl/TCM_SPI.vhd" ]\ [file normalize "${origin_dir}/../../common/ftm/hdl/tcm_sc.vhd" ]\ @@ -269,7 +126,6 @@ set files [list \ [file normalize "${origin_dir}/../../common/ipbus/hdl/ipbus_core/ipbus_trans_decl.vhd" ]\ [file normalize "${origin_dir}/../../common/ipbus/hdl/ipbus_core/udp_build_arp.vhd" ]\ [file normalize "${origin_dir}/../../common/ipbus/hdl/ipbus_core/udp_build_ping.vhd" ]\ - [file normalize "${origin_dir}/../../common/ipbus/hdl/ipbus_core/udp_ipaddr_block.vhd" ]\ [file normalize "${origin_dir}/../../common/ipbus/hdl/ipbus_core/udp_build_payload.vhd" ]\ [file normalize "${origin_dir}/../../common/ipbus/hdl/ipbus_core/udp_build_resend.vhd" ]\ [file normalize "${origin_dir}/../../common/ipbus/hdl/ipbus_core/udp_build_status.vhd" ]\ @@ -290,7 +146,6 @@ set files [list \ [file normalize "${origin_dir}/../../common/ipbus/hdl/ipbus_core/udp_if_flat.vhd" ]\ [file normalize "${origin_dir}/../../common/ipbus/hdl/ipbus_core/transactor_if.vhd" ]\ [file normalize "${origin_dir}/../../common/ipbus/hdl/ipbus_core/transactor_sm.vhd" ]\ - [file normalize "${origin_dir}/../../common/ipbus/hdl/ipbus_core/transactor_cfg.vhd" ]\ [file normalize "${origin_dir}/../../common/ipbus/hdl/ipbus_core/transactor.vhd" ]\ [file normalize "${origin_dir}/../../common/ipbus/hdl/ipbus_core/ipbus_ctrl.vhd" ]\ [file normalize "${origin_dir}/../../common/ipbus/hdl/ipbus_core/ipbus_package.vhd" ]\ @@ -360,26 +215,25 @@ set files [list \ [file normalize "${origin_dir}/../../common/gbt-fpga/hdl/gbt_bank/xilinx_k7v7/mgt/mgt_ip_vhd/xlx_k7v7_mgt_ip_tx_manual_phase_align.vhd" ]\ [file normalize "${origin_dir}/../../common/gbt-fpga/hdl/gbt_bank/xilinx_k7v7/mgt/mgt_ip_vhd/xlx_k7v7_mgt_ip_tx_startup_fsm.vhd" ]\ [file normalize "${origin_dir}/../../common/gbt-readout/hdl/GBT_TXRX5.vhd"] \ - [file normalize "${origin_dir}/../../common/gbt-readout/hdl/DataCLK_strobe.vhd" ]\ [file normalize "${origin_dir}/../../common/gbt-readout/hdl/DataConverter_TCM.vhd" ]\ - [file normalize "${origin_dir}/../../common/gbt-readout/hdl/RX_Data_Decoder.vhd" ]\ - [file normalize "${origin_dir}/../../common/gbt-readout/hdl/BC_counter.vhd" ]\ + [file normalize "${origin_dir}/../../common/gbt-readout/hdl/ltu_rx_decoder.vhd" ]\ + [file normalize "${origin_dir}/../../common/gbt-readout/hdl/bc_indicator.vhd" ]\ [file normalize "${origin_dir}/../../common/gbt-readout/hdl/Reset_Generator.vhd" ]\ [file normalize "${origin_dir}/../../common/gbt-readout/hdl/fit_gbt_boardTCM_package.vhd" ]\ [file normalize "${origin_dir}/../../common/gbt-readout/hdl/FIT_GBT_project.vhd" ]\ [file normalize "${origin_dir}/../../common/gbt-readout/hdl/Module_Data_Gen_TCM.vhd" ]\ - [file normalize "${origin_dir}/../../common/gbt-readout/hdl/CRU_ORBC_Gen.vhd" ]\ + [file normalize "${origin_dir}/../../common/gbt-readout/hdl/cru_ltu_emu.vhd" ]\ [file normalize "${origin_dir}/../../common/gbt-readout/hdl/TX_Data_Gen.vhd" ]\ [file normalize "${origin_dir}/../../common/gbt-readout/hdl/Event_selector.vhd" ]\ [file normalize "${origin_dir}/../../common/gbt-readout/hdl/fit_gbt_common_package.vhd" ]\ [file normalize "${origin_dir}/../../common/gbt-readout/hdl/RXDataClkSync.vhd" ]\ [file normalize "${origin_dir}/../../common/gbt-readout/hdl/CRU_packet_Builder.vhd" ]\ - [file normalize "${origin_dir}/../../common/gbt-readout/hdl/Data_Packager.vhd" ]\ + [file normalize "${origin_dir}/../../common/gbt-readout/hdl/snapshot_fifo.vhd" ]\ + [file normalize "${origin_dir}/../../common/gbt-readout/hdl/error_report.vhd" ]\ ] -#set imported_files [import_files -fileset sources_1 $files] add_files -norecurse -fileset sources_1 $files -#set imported_files [add_files -norecurse -fileset sources_1 $files] + #------------------------------------------------------------------------------- if {[string equal $proj_create "yes"]} { # Set 'sources_1' fileset object @@ -398,7 +252,7 @@ if {[string equal $proj_create "yes"]} { # Set 'sources_1' fileset properties set_property \ -dict [list \ - "top" "tcm"] \ + "top" "FIT_TESTMODULE_v2"] \ [get_filesets sources_1] # Create 'constrs_1' fileset (if not found) @@ -412,11 +266,14 @@ if {[string equal $proj_create "yes"]} { set file "[file normalize "$origin_dir/xdc/FIT_GBT_project_cnstrs.xdc"]" add_files -fileset constrs_1 [list $file] + + set file "[file normalize "$origin_dir/xdc/FIT_GBT_kc705_chipscope.xdc"]" + add_files -fileset constrs_1 [list $file] set_property -name "file_type" -value "XDC" -objects [get_files -of_objects [get_filesets constrs_1] [list "*/xdc/*.xdc"]] # Set 'constrs_1' fileset properties - set_property -name "target_constrs_file" -value "[get_files *xdc/FIT_GBT_kc705_io.xdc]" -objects [get_filesets constrs_1] + set_property -name "target_constrs_file" -value "[get_files *xdc/FIT_GBT_kc705_chipscope.xdc]" -objects [get_filesets constrs_1] } #------------------------------------------------------------------------------- @@ -432,19 +289,14 @@ foreach ip [get_ips] { - - - - - - - # Create 'sim_1' fileset (if not found) if {[string equal [get_filesets -quiet sim_1] ""]} { create_fileset -simset sim_1 } + + # Set 'sim_1' fileset object set obj [get_filesets sim_1] # Import local files from the original project @@ -463,13 +315,6 @@ set_property -name "top" -value "testbench_readout" -objects $obj - - - - - - - # Create 'synth_1' run (if not found) if {[string equal [get_runs -quiet synth_1] ""]} { create_run -name synth_1 -part xc7k325tffg900-2 -flow {Vivado Synthesis 2019} -strategy "Flow_PerfOptimized_high" -report_strategy {No Reports} -constrset constrs_1 @@ -551,6 +396,7 @@ set_property -name "steps.phys_opt_design.args.directive" -value "AggressiveExpl set_property -name "steps.route_design.args.directive" -value "NoTimingRelaxation" -objects $obj set_property -name "steps.write_bitstream.args.readback_file" -value "0" -objects $obj set_property -name "steps.write_bitstream.args.verbose" -value "0" -objects $obj +set_property -name "steps.write_bitstream.args.bin_file" -value "1" -objects $obj # set the current impl run current_run -implementation [get_runs impl_1] @@ -561,3 +407,5 @@ update_compile_order -fileset sources_1 reset_run -quiet synth_1 launch_runs impl_1 -to_step write_bitstream -jobs 7 wait_on_run impl_1 +open_run impl_1 +report_timing_summary -file impl_1_timing_summary.log diff --git a/firmware/FT0/FTM_TCM/xdc/FIT_GBT_project_cnstrs.xdc b/firmware/FT0/FTM_TCM/xdc/FIT_GBT_project_cnstrs.xdc index 3ef8cd6..339f61d 100644 --- a/firmware/FT0/FTM_TCM/xdc/FIT_GBT_project_cnstrs.xdc +++ b/firmware/FT0/FTM_TCM/xdc/FIT_GBT_project_cnstrs.xdc @@ -48,7 +48,7 @@ set_clock_groups -name ASYNC_CLOCIPB -asynchronous -group [get_clocks -include_g #RESET ========================================================================== -set_false_path -from [get_cells Reset_Generator_comp/GenRes_DataClk_ff*_reg] +#set_false_path -from [get_cells Reset_Generator_comp/GenRes_DataClk_ff*_reg] #================================================================================ @@ -58,7 +58,9 @@ set_max_delay -datapath_only -from [get_cells HDMI0/trig_data_reg[*]] -to [get_c set_max_delay -datapath_only -from [get_cells HDMI0/DValid_reg] -to [get_clocks SystemCLK_320] 1.000 set_property ASYNC_REG true [get_cells {hdmi_ready0_reg hdmi_ready1_reg}] -set_false_path -from [get_clocks RXDataCLK] -to [get_cells {FitGbtPrg/gbt_bank_gen.gbtBankDsgn/GBT_Status_O_reg[gbtRx_ErrorDet] FitGbtPrg/gbt_bank_gen.gbtBankDsgn/GBT_Status_O_reg[gbtRx_Ready]}] +set_false_path -from [get_clocks RXDataCLK] -to [get_cells {FitGbtPrg/gbt_bank_gen.gbtBankDsgn/gbtRx_ErrorDet_ff_reg FitGbtPrg/gbt_bank_gen.gbtBankDsgn/GBT_Status_O_reg[*]}] +set_false_path -from [get_clocks RXDataCLK] -to [get_cells {FitGbtPrg/gbt_bank_gen.gbtBankDsgn/gbtRx_ErrorDet_ff_reg FitGbtPrg/gbt_bank_gen.gbtBankDsgn/gbtRx_ErrorDet_ff*}] +set_false_path -from [get_clocks RXDataCLK] -to [get_cells {FitGbtPrg/gbt_bank_gen.gbtBankDsgn/gbtRx_ErrorDet_ff_reg FitGbtPrg/gbt_bank_gen.gbtBankDsgn/Rx_Ready_ff*}] @@ -70,8 +72,14 @@ set_multicycle_path -hold -start -from [get_clocks RxWordCLK] -to [get_cells {Fi FitGbtPrg/gbt_bank_gen.gbtBankDsgn/gbtBank/gbtRx_param_package_src_gen.gbtRx_gen[1].gbtRx/descrambler/gbtFrameOrWideBus_gen.gbtRxDescrambler84bit_gen[?].gbtRxDescrambler21bit/feedbackRegister_reg[*]}] 2 +# RX Sync comp ------------------------------------- +set_max_delay -datapath_only -from [get_clocks RXDataCLK] -to [get_cells {FitGbtPrg/RxData_ClkSync_comp/RX_DATA_sysclk_reg[*]}] 3.000 +set_max_delay -datapath_only -from [get_clocks RXDataCLK] -to [get_cells {FitGbtPrg/RxData_ClkSync_comp/RX_IS_DATA_sysclk_reg*}] 3.000 +set_max_delay -datapath_only -from [get_clocks RXDataCLK] -to [get_cells FitGbtPrg/RxData_ClkSync_comp/RX_CLK_from00_reg] 2.000 set_property ASYNC_REG true [get_cells FitGbtPrg/RxData_ClkSync_comp/RX_CLK_from00_reg] set_property ASYNC_REG true [get_cells FitGbtPrg/RxData_ClkSync_comp/RX_CLK_from01_reg] +set_multicycle_path 8 -setup -from [get_clocks TX_CLK] -to [get_pins FitGbtPrg/RxData_ClkSync_comp/rx_error_reset_sclk_reg/D] +set_multicycle_path 7 -hold -end -from [get_clocks TX_CLK] -to [get_pins FitGbtPrg/RxData_ClkSync_comp/rx_error_reset_sclk_reg/D] #================================================================================ diff --git a/firmware/FT0/PM/hdl/Channel.vhd b/firmware/FT0/PM/hdl/Channel.vhd index 27e8134..6fb16eb 100644 --- a/firmware/FT0/PM/hdl/Channel.vhd +++ b/firmware/FT0/PM/hdl/Channel.vhd @@ -47,6 +47,7 @@ entity Channel is gate_time_low : in STD_LOGIC_VECTOR (7 downto 0); gate_time_high : in STD_LOGIC_VECTOR (7 downto 0); Ampl_sat : in STD_LOGIC_VECTOR (11 downto 0); + ampl_low : in STD_LOGIC_VECTOR (3 downto 0); CH0_zero : out STD_LOGIC_VECTOR (11 downto 0); CH1_zero : out STD_LOGIC_VECTOR (11 downto 0); CH_trig_outt : out STD_LOGIC; @@ -68,7 +69,11 @@ entity Channel is R0_corr : in STD_LOGIC_VECTOR (11 downto 0); R1_corr : in STD_LOGIC_VECTOR (11 downto 0); pulse_in : out STD_LOGIC; - chan_ena : in STD_LOGIC + chan_ena : in STD_LOGIC; + trig_dis : in STD_LOGIC; + fdd : in STD_LOGIC; + CH_trig_int : in STD_LOGIC; + CH_trig_outtn : out STD_LOGIC ); end Channel; @@ -97,7 +102,7 @@ signal RDF_in : STD_LOGIC_VECTOR(32 downto 0); signal TDC_pause : STD_LOGIC_VECTOR(5 downto 0); signal TDC_load : STD_LOGIC_VECTOR(3 downto 0); -signal Cal_d, Cal_d0, Cal_d1, CH_new, ev_p0, ev_p1, ev_p00, ev_p01, ch_bp, rt_sel : STD_LOGIC; +signal Cal_d, Cal_d0, Cal_d1, CH_new, ev_p0, ev_p1, ev_p00, ev_p01, ch_bp, rt_sel, trig_ena : STD_LOGIC; signal mt_cou_c : STD_LOGIC_VECTOR(2 downto 0); signal ch_tc0, ch_tc1, ch_tc2, ch_tc : STD_LOGIC_VECTOR(1 downto 0); signal Z : STD_LOGIC_VECTOR(9 downto 0); @@ -139,17 +144,19 @@ END COMPONENT; begin CH_ampl<=CH_ampl0; -CH_trig_outt<=CH_trig_f; +CH_trig_outtn<=CH_trig_f; +CH_trig_outt<=CH_trig_f when (fdd='0') else CH_trig_f and CH_trig_int; CH_trig_outa<=CH_trig_a; pulse_in<=EV_E; Event_in<=Event_inp; +trig_ena<= not trig_dis; EVENTFIFO: EVENT_FIFO port map (clk => clk320, srst =>RESET, din =>EVENTFIFO_in, wr_en => EVENTFIFO_wr, rd_en =>EVENTFIFO_rd, dout => C_FOUT, full =>open, empty =>EVENTFIFO_empty); EVENTFIFO_in <=EV_dly(3)(10 downto 9) & ampl_dat & EV_am_fl & EV_dly(3)(7 downto 0); -ampl_dat <=CH_0(12)& Ampl_fin when (CH_trig_a='1') else (others=>'0'); +ampl_dat <=CH_0(12)& Ampl_fin when (EV_am_fl='1') else (others=>'0'); RD_FIFO: CHAN_RD_FIFO port map (clk => clk320, srst =>FIFO_rst, din =>RDF_in, wr_en => RDF_wr, rd_en =>DATA_rd, dout => DATA_out, full =>open, empty =>rd_empty); @@ -170,14 +177,18 @@ process (clk320) begin if (clk320'event and clk320='1') then -TDC_rdy320_0<=TDC_rdy_in; TDC_rdy320<=TDC_rdy320_0; TDC_rdy320_1<=TDC_rdy320; +if (chan_ena='1') then TDC_rdy320_0<=TDC_rdy_in; else TDC_rdy320_0<='0'; end if; + +TDC_rdy320<=TDC_rdy320_0; TDC_rdy320_1<=TDC_rdy320; spi_lock0<=spi_lock; if (chan_ena='1') then EV_0<=CGE; else EV_0<='0'; end if; EV_rdy<= EV; EV<=EV_2; EV_2<=EV_1; EV_1<=EV_0; -CSTR_0<=CSTR; CSTR_1<=CSTR_0; CSTR_2<=CSTR_1; CSTR_3<=CSTR_2; +if (chan_ena='1') then CSTR_0<=CSTR; else CSTR_0<='0'; end if; + +CSTR_1<=CSTR_0; CSTR_2<=CSTR_1; CSTR_3<=CSTR_2; if (CSTR_1='1') and (CSTR_2='0') then CH_0<=CH; end if; if (Cal_d='1') then @@ -300,7 +311,7 @@ if (mt_cou="011") then EV_am_en<=EV_dly(2)(8); end if; -if (mt_cou="100") then EV_am_fl0<='0'; EV_am_fl<=EV_am_fl0; CH_trig_a<=EV_dly(3)(8) and EV_am_fl0; CH_trig_bgnd<= EV_dly(3)(8) and not EV_am_fl0; +if (mt_cou="100") then EV_am_fl0<='0'; EV_am_fl<=EV_am_fl0; CH_trig_a<= trig_ena and EV_am_fl0; CH_trig_bgnd<= EV_dly(3)(8) and (not EV_am_fl0) and trig_ena; else if (CSTR_1='1') and (CSTR_2='0') then EV_am_fl0<=EV_am_en; end if; end if; @@ -346,7 +357,7 @@ ch_tc0<="11" when TDC(11 downto 9) = "011" else "10" when (TDC(11) = '1') or (TDC(10 downto 9) = "00") else "00"; -CH_t_trig0<= '1' when ((CH_TIME0 > "1111" & gate_time_low) OR (CH_TIME0 < "0000" & gate_time_high)) else '0'; +CH_t_trig0<= trig_ena when ((CH_TIME0 > "1111" & gate_time_low) OR (CH_TIME0 < "0000" & gate_time_high)) else '0'; TDC_rdy_en<=TDC_rdy320 and not TDC_rdy320_1; TDC_out<=(not TDC_rdy320) and TDC_rdy320_1; @@ -362,8 +373,8 @@ CH_tr_en<=C_FOUT(8) and Ampl_OK and Time_OK and not C_FOUT(7); CH_BS<=('0'& CH_0(11 downto 0)) - ('0'&CH0_Z(21 downto 10)) when (CH_0(12)='0') else ('0'& CH_0(11 downto 0)) - ('0'&CH1_Z(21 downto 10)); -CH_TIME<=CH_TIME1 (9 downto 0) when (CH_trig_f='1') and (((CH_dt='0') and (CH_ds='0')) or ((CH_t_trig1='1') and (CH_ds='1'))) else - CH_TIME2 (9 downto 0) when (CH_trig_f='1') and (((CH_dt='1') and (CH_ds='0')) or ((CH_t_trig2='1') and (CH_ds='1'))) else +CH_TIME<=CH_TIME1 (9 downto 0) when (CH_trig_f='1') and ((fdd='0') or (CH_trig_int='1')) and (((CH_dt='0') and (CH_ds='0')) or ((CH_t_trig1='1') and (CH_ds='1'))) and (trig_ena='1') else + CH_TIME2 (9 downto 0) when (CH_trig_f='1') and (((CH_dt='1') and (CH_ds='0')) or ((CH_t_trig2='1') and (CH_ds='1'))) and (trig_ena='1') else "0000000000"; rt_sel<='1' when (((CH_dt='1') and (CH_ds='0')) or ((CH_t_trig2='1') and (CH_ds='1'))) else '0'; @@ -387,7 +398,7 @@ Ampl_corr<= std_logic_vector(signed(CH_BS) * signed('0'& R_corr)); Ampl_fin<= Ampl_corr(23 downto 11) when (signed(Ampl_corr(25 downto 23))<1) else '0' & x"FFF"; -Ampl_OK<='1' when (signed(C_FOUT(21 downto 9)) < signed('0' & Ampl_sat)) else '0'; +Ampl_OK<='1' when (C_FOUT(21)='0') and (C_FOUT(20 downto 9) <= Ampl_sat) and (C_FOUT(20 downto 9) > x"00" & Ampl_low) else '0'; end RTL; diff --git a/firmware/FT0/PM/hdl/autophase.vhd b/firmware/FT0/PM/hdl/autophase.vhd index 86a5f45..945a113 100644 --- a/firmware/FT0/PM/hdl/autophase.vhd +++ b/firmware/FT0/PM/hdl/autophase.vhd @@ -46,63 +46,75 @@ end autophase; architecture RTL of autophase is signal ms_cou : STD_LOGIC_VECTOR (18 downto 0); -signal t1ms, tstr, dir, done_i, lock_i : STD_LOGIC; +signal t1ms, tstr, dir, done_i, lock_i, wasjmp : STD_LOGIC; signal state : STD_LOGIC_VECTOR (2 downto 0); -signal j_cou : STD_LOGIC_VECTOR (3 downto 0); -signal m0, ml, mh0 : STD_LOGIC_VECTOR (5 downto 0); +signal m0, ml : STD_LOGIC_VECTOR (6 downto 0); +signal mh0 : STD_LOGIC_VECTOR (7 downto 0); begin psincdec<=dir; done<=done_i; -t1ms<='1' when (ms_cou=299999) else '0'; -mh0<= m0+ml; -shift<=m0; +mh0<= std_logic_vector(resize(signed(m0),8))+std_logic_vector(resize(signed(ml),8)); +shift<=m0(5 downto 0); process(clk, lock) begin -if (lock='0') then lock_i<='0'; +if (lock='0') then lock_i<='0'; ms_cou <=(others=>'0'); state <=(others=>'0'); wasjmp <='0'; done_i<='0'; dir<='0'; m0 <=(others=>'0'); psen<='0'; tstr<='0'; t1ms<='0'; else if (clk'event and clk='1') then lock_i<='1'; -tstr<=t1ms; psen<=tstr and (not done_i); +tstr<=t1ms; psen<=tstr and (not done_i); -if (lock_i='0') then ms_cou <=(others=>'0'); state <=(others=>'0'); j_cou <=(others=>'0'); done_i<='0'; dir<='0'; m0 <=(others=>'0'); - else - if (done_i='0') then - if (tstr='1') then + +if (done_i='0') and (lock_i='1') then + if (tstr='1') then if (dir='0') then m0<=m0-1; else m0<=m0+1; end if; - end if; + end if; -if (t1ms='1') then ms_cou <=(others=>'0'); j_cou <=(others=>'0'); + if (jump='1') then wasjmp <='1'; + else if (tstr='1') then wasjmp<='0'; end if; + end if; + +if (ms_cou=299999) then ms_cou <=(others=>'0'); t1ms<='1'; + else ms_cou<=ms_cou+1; t1ms<='0'; end if; + +if (t1ms='1') then case to_integer(unsigned(state)) is - when 0 => if (j_cou>=10) then state<="001"; dir<='1'; - else - if (m0="100000") then state<="110"; dir<='1'; end if; + when 0 => if (m0="1010110") then state<="110"; dir<='1'; + else + if (wasjmp='1') then state<="001"; dir<='1'; end if; end if; - when 1 => if (j_cou=0) then state<="010"; ml<= m0; end if; - when 2 => if (m0=(ml+"000111")) then state<="011"; end if; - when 3 => if (j_cou>=10) then state<="100"; dir<='0'; - else - if (m0="011111") then state<="111"; dir<='0'; end if; + when 1 => if (wasjmp='0') then state<="010"; ml<= m0; end if; + when 2 => if (wasjmp='1') then state<="001"; + else + if (m0=(ml+"0000111")) then state<="011"; end if; end if; - when 4 => if (j_cou=0) then state<="101"; ml<= mh0(5) & mh0(5 downto 1); end if; + when 3 => if (m0="0101010") then state<="110"; dir<='0'; + else + if (wasjmp='1') then state<="100"; dir<='0'; end if; + end if; + when 4 => if (wasjmp='0') then state<="101"; + if (mh0(7)='0') and (mh0(6 downto 1)>14) then ml<= mh0(7 downto 1)-28; + + elsif (mh0(7)='1') and (mh0(6 downto 1)<"110010") then ml<= mh0(7 downto 1)+28; dir<='1'; + + else + ml<= mh0(7 downto 1); + end if; + end if; when 5 => if (m0=ml) then done_i<='1'; end if; - when 6 => if (signed(m0)=10) then state<="000"; dir<='0'; end if; - when 7 => if (signed(m0)=-10) then state<="000"; end if; + when 6 => if (m0=0) then state<="000"; dir<='0'; end if; + when others => null; end case; -else - ms_cou<=ms_cou+1; - if (jump='1') and (j_cou/=15) then j_cou <=j_cou+1; end if; -end if; - + end if; -end if; end if; end if; + end if; end process; diff --git a/firmware/FT0/PM/hdl/fit.vhd b/firmware/FT0/PM/hdl/fit.vhd index 4418710..3d2e882 100644 --- a/firmware/FT0/PM/hdl/fit.vhd +++ b/firmware/FT0/PM/hdl/fit.vhd @@ -43,7 +43,7 @@ use work.fit_gbt_board_package.all; -entity fit is +entity PM12 is Port ( TDCCLK1_P : in STD_LOGIC; TDCCLK1_N : in STD_LOGIC; RDA1_P : in STD_LOGIC; @@ -198,10 +198,10 @@ entity fit is FMISO : in STD_LOGIC ); -end fit; +end PM12; -architecture RTL of fit is +architecture RTL of PM12 is type data_vector is array (0 to 11) of STD_LOGIC_VECTOR (32 downto 0); type trig_ampl is array (0 to 11) of STD_LOGIC_VECTOR(10 downto 0); @@ -281,7 +281,8 @@ signal N1_chans, N2_chans : STD_LOGIC_VECTOR (2 downto 0); signal TT_mode : STD_LOGIC; signal ampl_sat : STD_LOGIC_VECTOR (11 downto 0); -signal Event_in, DATA_rd, DATA_rdy, inp_cou, CH_trig, CH_triga, CH_do, Z_alarm, trig_bgnd, cnt_trig : STD_LOGIC_VECTOR (11 downto 0); +signal ampl_low : STD_LOGIC_VECTOR (3 downto 0); +signal Event_in, DATA_rd, DATA_rdy, inp_cou, CH_trig, CH_triga, CH_do, Z_alarm, trig_bgnd, cnt_trig, trig_dis, ch_trig_outtn : STD_LOGIC_VECTOR (11 downto 0); signal inp_event, EV_ID_wr, EV_ID_rd, EV_ID_empty, Event_ready, Event_ready_0, Event_free, wr_out_id, New_BCID, DATA80_rd, DATA_empty, FIFO_dis, wr_nch, ev_tout, ev_tout0 : STD_LOGIC; signal ev_tout_cnt : STD_LOGIC_VECTOR (7 downto 0); @@ -292,9 +293,9 @@ signal Orbit_ID, hspid_w32, hspid_r32, tstamp, hspib_32, mcu_tstamp : STD_LOGIC_ signal xadc_r, xadc_out : STD_LOGIC_VECTOR (15 downto 0); signal xadc_a: STD_LOGIC_VECTOR (6 downto 0); signal EV_ID_in, EV_ID_out : STD_LOGIC_VECTOR (55 downto 0); -signal EV_DATA80, DATA80_in : STD_LOGIC_VECTOR (79 downto 0); ---signal mux_out, str_la : STD_LOGIC; -signal WR_fifo_out, wr_hspi32, rd_hspi32, flsh_sel, TCM_req, TCM_reqh, TCM_req0, TCM_req1, TCM_req2, fl_rst, rd_xadc, xadc_en, xadc_rdy, gs0, gs1, rdo_sel : STD_LOGIC; +signal EV_DATA80, DATA80_in, data_word : STD_LOGIC_VECTOR (79 downto 0); +signal is_data, is_header : STD_LOGIC; +signal WR_fifo_out, wr_hspi32, rd_hspi32, flsh_sel, TCM_req, TCM_reqh, TCM_req0, TCM_req1, TCM_req2, fl_rst, rd_xadc, xadc_en, xadc_rdy, gs0_0, gs1_0, gs0_1, gs1_1, rdo_sel, fdd : STD_LOGIC; signal DATA_out : data_vector; @@ -308,13 +309,15 @@ signal pshift1, pshift2, pshift3 : STD_LOGIC_VECTOR (5 downto 0); signal rx_phase_status : std_logic_vector(3 downto 0); signal hyst_md : std_logic_vector(15 downto 0); -signal start_hyst, h_busy, wr_hyst_a, rd_hyst_d, hysta_sel, hystd_sel, hyst_stp : std_logic; +signal start_hyst, h_busy, wr_hyst_a, rd_hyst_d, hysta_sel, hystd_sel, hyst_stp, hyst_rst, hyst_clr : std_logic; signal cnt_md : std_logic := '0'; signal hyst_data : hyst_vector; signal hyst_a, hyst_t : std_logic_vector(11 downto 0); signal hyst_addr : std_logic_vector(16 downto 0); signal hyst_r_data : std_logic_vector(31 downto 0); + + component PLL320 port ( mclk_in : in std_logic; @@ -386,6 +389,7 @@ component TDCCHAN is FIFO_dis: in STD_LOGIC; gate_time_high : in STD_LOGIC_VECTOR (7 downto 0); Ampl_sat : in STD_LOGIC_VECTOR (11 downto 0); + ampl_low : in STD_LOGIC_VECTOR (3 downto 0); CH0_zero : out STD_LOGIC_VECTOR (11 downto 0); CH1_zero : out STD_LOGIC_VECTOR (11 downto 0); CH_trig_outt : out STD_LOGIC; @@ -406,7 +410,11 @@ component TDCCHAN is R0_corr : in STD_LOGIC_VECTOR (11 downto 0); R1_corr : in STD_LOGIC_VECTOR (11 downto 0); pulse_in : out STD_LOGIC; - chan_ena : in STD_LOGIC + chan_ena : in STD_LOGIC; + trig_dis : in STD_LOGIC; + fdd : in STD_LOGIC; + CH_trig_int : in STD_LOGIC; + CH_trig_outtn : out STD_LOGIC ); end component; @@ -426,8 +434,8 @@ component TDCCHAN is -- ############################################### -- ######### GBT Readout ######################## -- ############################################### - signal FIT_GBT_status : FIT_GBT_status_type; - signal FIT_GBT_control : CONTROL_REGISTER_type; + signal readout_status : readout_status_t; + signal readout_control : readout_control_t; signal Data_from_FITrd : std_logic_vector(GBT_data_word_bitdepth-1 downto 0); @@ -438,14 +446,16 @@ component TDCCHAN is signal PM_data_toreadout : board_data_type; - signal ipbus_control_reg : cntr_reg_addrreg_type; - signal ipbus_status_reg: status_reg_addrreg_type; + signal ipbus_control_reg : ctrl_reg_t; + signal ipbus_status_reg: stat_reg_t; signal gbt_global_status : std_logic_vector(3 downto 0); + signal err_report_fifo_rden : std_logic; + signal readout_err_rden : std_logic; component FIT_GBT_project is generic ( - GENERATE_GBT_BANK : integer := 1 + IS_SIMULATION : integer := 0 ); Port ( @@ -455,9 +465,14 @@ component TDCCHAN is MgtRefClk_I : in STD_LOGIC; -- 200MHz ref clock RxDataClk_I : in STD_LOGIC; -- 40MHz data clock in RX domain GBT_RxFrameClk_O : out STD_LOGIC; --Rx GBT frame clk 40MHz + FSM_Clocks_O : out rdclocks_t; + + IPbusClk_I : in std_logic; -- IPbus clock for error fifo read + err_report_fifo_rden_i : in std_logic; -- IPbus error report fifo read enable Board_data_I : in board_data_type; --PM or TCM data - Control_register_I : in CONTROL_REGISTER_type; + Control_register_I : in readout_control_t; + errors_rden_I : in std_logic; -- status register EA (errors) was read MGT_RX_P_I : in STD_LOGIC; MGT_RX_N_I : in STD_LOGIC; @@ -476,10 +491,8 @@ component TDCCHAN is IsData_to_GBT_I : in STD_LOGIC; RxData_rxclk_from_GBT_O : out std_logic_vector(GBT_data_word_bitdepth-1 downto 0); IsRxData_rxclk_from_GBT_O : out STD_LOGIC; - rx_ph320 : out std_logic_vector(2 downto 0); - ph_error320 : out std_logic; -- FIT readour status, including BCOR_ID to PM/TCM - FIT_GBT_status_O : out FIT_GBT_status_type + readout_status_o : out readout_status_t ); end component; @@ -609,6 +622,17 @@ component hyst ); end component; + + + -- attribute mark_debug : string; + -- attribute mark_debug of rd_hspi32 : signal is "true"; + -- attribute mark_debug of hspib_32 : signal is "true"; + -- attribute mark_debug of hspi_addr : signal is "true"; + -- attribute mark_debug of err_report_fifo_rden : signal is "true"; + -- attribute mark_debug of readout_err_rden : signal is "true"; + + + begin TCLK1: IBUFDS @@ -913,7 +937,7 @@ at0<=tao(0); at1<=tao(1); tt0<=tto(0); tt1<=tto(1); -- FIT GBT project ===================================== FitGbtPrg: FIT_GBT_project generic map( - GENERATE_GBT_BANK => 1 + IS_SIMULATION => 0 ) Port map( @@ -923,9 +947,14 @@ FitGbtPrg: FIT_GBT_project MgtRefClk_I => MGTCLK, RxDataClk_I => RX_CLK, -- 40MHz data clock in RX domain (loop back) GBT_RxFrameClk_O => RX_CLK, + FSM_Clocks_O => open, + + IPbusClk_I => TX_CLK, + err_report_fifo_rden_i => err_report_fifo_rden, Board_data_I => PM_data_toreadout, - Control_register_I => FIT_GBT_control, + Control_register_I => readout_control, + errors_rden_I => readout_err_rden, MGT_RX_P_I => GBT_RX_P, MGT_RX_N_I => GBT_RX_N, @@ -942,18 +971,14 @@ FitGbtPrg: FIT_GBT_project RxData_rxclk_from_GBT_O => RxData_rxclk_from_GBT, IsRxData_rxclk_from_GBT_O => IsRxData_rxclk_from_GBT, - rx_ph320 => rx_phase_status(2 downto 0), - ph_error320 => rx_phase_status(3), - FIT_GBT_status_O => FIT_GBT_status + readout_status_o => readout_status ); -- ===================================================== +GBTRX_ready <= readout_status.GBT_status.gbtRx_Ready; GBT_is_RXD <= IsRxData_rxclk_from_GBT; -GBTRX_ready <= FIT_GBT_status.GBT_status.gbtRx_Ready; -RX_err <= FIT_GBT_status.GBT_status.gbtRx_ErrorDet; - - +RX_err <= readout_status.GBT_status.gbtRx_ErrorDet; --PM_data_toreadout.is_header <= GBT_is_TXD; --PM_data_toreadout.is_data <= GBT_is_TXD; @@ -961,18 +986,18 @@ RX_err <= FIT_GBT_status.GBT_status.gbtRx_ErrorDet; --PM_data_toreadout.data_word <= GBT_TX_D; -FIT_GBT_control <= func_CNTRREG_getcntrreg(ipbus_control_reg); -ipbus_status_reg <= func_STATREG_getaddrreg(FIT_GBT_status); +readout_control <= func_CNTRREG_getcntrreg(ipbus_control_reg); +ipbus_status_reg <= func_STATREG_getaddrreg(readout_status); -gbt_global_status(0) <= FIT_GBT_status.GBT_status.Rx_Phase_error; -gbt_global_status(1) <= '1' when FIT_GBT_status.BCIDsync_Mode = mode_LOST else '0'; ---gbt_global_status(2) <= '1' when FIT_GBT_status.hits_rd_counter_selector.hits_skipped /= x"0000_0000" else '0'; +gbt_global_status(0) <= readout_status.Rx_Phase_error; +gbt_global_status(1) <= '1' when readout_status.BCIDsync_Mode = mode_LOST else '0'; +--gbt_global_status(2) <= '1' when readout_status.hits_rd_counter_selector.hits_skipped /= x"0000_0000" else '0'; gbt_global_status(3) <= '0'; process (clk320) begin if (clk320'event and clk320='1') then - if ( FIT_GBT_status.hits_rd_counter_selector.hits_skipped = x"0000_0000") then + if ( readout_status.fsm_errors = x"00") then gbt_global_status(2) <= '0'; else gbt_global_status(2) <= '1'; @@ -1111,64 +1136,64 @@ TDC3_CHD: TDCCHAN port map( pin_in =>CGE12i, pin_out =>CGE12, clk300 =>clk300_3, CHANNEL1A : channel port map (CGE =>CGE1, clk320 =>clk320, reset =>sreset, tdc_rdy_in=> TDC1A_rdy0, mt_cou =>mt_cou, bc_cou =>BC_COU(5 downto 0), TR_bc =>TR_to, TDC =>TDC1A, CSTR =>CSTR1, CH =>CH1, CH_shift => CH1A_shift, - gate_time_low => gate_time_low, gate_time_high =>gate_time_high, Ampl_sat =>Ampl_sat, CH0_zero =>CH1_0_zero, CH1_zero =>CH1_1_zero, CH_trig_outt =>CH_trig(0), CH_trig_outa =>CH_triga(0), CH_trig_bgnd=> trig_bgnd(0), CH_TIME =>CH_TIME_T(0), + gate_time_low => gate_time_low, gate_time_high =>gate_time_high, Ampl_sat =>Ampl_sat, ampl_low =>ampl_low, CH0_zero =>CH1_0_zero, CH1_zero =>CH1_1_zero, CH_trig_outt =>CH_trig(0), CH_trig_outa =>CH_triga(0), CH_trig_bgnd=> trig_bgnd(0), CH_TIME =>CH_TIME_T(0), CH_ampl =>CH_ampl0(0), DATA_out=>DATA_out(0), DATA_ready=>DATA_rdy(0), DATA_rd=>DATA_rd(0), FIFO_dis=>FIFO_dis, Event_in=>Event_in(0), Z0_cal=>CH1_Z0, Z1_cal=>CH1_Z1, Z_alarm=>Z_alarm(0), spi_lock=>spi_lock320, R0_cal=>CH1_0_rg, - R1_cal=>CH1_1_rg, R0_corr=>CH1_0_rc, R1_corr=>CH1_1_rc, pulse_in=>inp_cou(0), chan_ena=>chans_ena(0)); + R1_cal=>CH1_1_rg, R0_corr=>CH1_0_rc, R1_corr=>CH1_1_rc, pulse_in=>inp_cou(0), chan_ena=>chans_ena(0), trig_dis=>trig_dis(0), fdd=>fdd, ch_trig_int=>ch_trig_outtn(1), ch_trig_outtn=>ch_trig_outtn(0)); CHANNEL1B : channel port map (CGE =>CGE2, clk320 =>clk320, reset =>sreset, tdc_rdy_in=> TDC1B_rdy0, mt_cou =>mt_cou, bc_cou =>BC_COU(5 downto 0), TR_bc =>TR_to, TDC =>TDC1B, CSTR =>CSTR2, CH =>CH2, CH_shift => CH1B_shift, - gate_time_low => gate_time_low, gate_time_high =>gate_time_high, Ampl_sat =>Ampl_sat, CH0_zero =>CH2_0_zero, CH1_zero =>CH2_1_zero, CH_trig_outt =>CH_trig(1), CH_trig_outa =>CH_triga(1), CH_trig_bgnd=> trig_bgnd(1), CH_TIME =>CH_TIME_T(1), + gate_time_low => gate_time_low, gate_time_high =>gate_time_high, Ampl_sat =>Ampl_sat, ampl_low =>ampl_low, CH0_zero =>CH2_0_zero, CH1_zero =>CH2_1_zero, CH_trig_outt =>CH_trig(1), CH_trig_outa =>CH_triga(1), CH_trig_bgnd=> trig_bgnd(1), CH_TIME =>CH_TIME_T(1), CH_ampl =>CH_ampl0(1), DATA_out=>DATA_out(1), DATA_ready=>DATA_rdy(1), DATA_rd=>DATA_rd(1), FIFO_dis=>FIFO_dis, Event_in=>Event_in(1), Z0_cal=>CH2_Z0, Z1_cal=>CH2_Z1, Z_alarm=>Z_alarm(1), spi_lock=>spi_lock320, R0_cal=>CH2_0_rg, - R1_cal=>CH2_1_rg, R0_corr=>CH2_0_rc, R1_corr=>CH2_1_rc, pulse_in=>inp_cou(1), chan_ena=>chans_ena(1)); + R1_cal=>CH2_1_rg, R0_corr=>CH2_0_rc, R1_corr=>CH2_1_rc, pulse_in=>inp_cou(1), chan_ena=>chans_ena(1), trig_dis=>trig_dis(1), fdd=>fdd, ch_trig_int=>ch_trig_outtn(0), ch_trig_outtn=>ch_trig_outtn(1)); CHANNEL1C : channel port map (CGE =>CGE3, clk320 =>clk320, reset =>sreset, tdc_rdy_in=> TDC1C_rdy0, mt_cou =>mt_cou, bc_cou =>BC_COU(5 downto 0), TR_bc =>TR_to, TDC =>TDC1C, CSTR =>CSTR3, CH =>CH3, CH_shift => CH1C_shift, - gate_time_low => gate_time_low, gate_time_high =>gate_time_high, Ampl_sat =>Ampl_sat, CH0_zero =>CH3_0_zero, CH1_zero =>CH3_1_zero, CH_trig_outt =>CH_trig(2), CH_trig_outa =>CH_triga(2), CH_trig_bgnd=> trig_bgnd(2), CH_TIME =>CH_TIME_T(2), + gate_time_low => gate_time_low, gate_time_high =>gate_time_high, Ampl_sat =>Ampl_sat, ampl_low =>ampl_low, CH0_zero =>CH3_0_zero, CH1_zero =>CH3_1_zero, CH_trig_outt =>CH_trig(2), CH_trig_outa =>CH_triga(2), CH_trig_bgnd=> trig_bgnd(2), CH_TIME =>CH_TIME_T(2), CH_ampl =>CH_ampl0(2), DATA_out=>DATA_out(2),DATA_ready=>DATA_rdy(2), DATA_rd=>DATA_rd(2), FIFO_dis=>FIFO_dis, Event_in=>Event_in(2), Z0_cal=>CH3_Z0, Z1_cal=>CH3_Z1, Z_alarm=>Z_alarm(2), spi_lock=>spi_lock320, R0_cal=>CH3_0_rg, - R1_cal=>CH3_1_rg, R0_corr=>CH3_0_rc, R1_corr=>CH3_1_rc, pulse_in=>inp_cou(2), chan_ena=>chans_ena(2)); + R1_cal=>CH3_1_rg, R0_corr=>CH3_0_rc, R1_corr=>CH3_1_rc, pulse_in=>inp_cou(2), chan_ena=>chans_ena(2), trig_dis=>trig_dis(2), fdd=>fdd, ch_trig_int=>ch_trig_outtn(3), ch_trig_outtn=>ch_trig_outtn(2)); CHANNEL1D : channel port map (CGE =>CGE4, clk320 =>clk320, reset =>sreset, tdc_rdy_in=> TDC1D_rdy0, mt_cou =>mt_cou, bc_cou =>BC_COU(5 downto 0), TR_bc =>TR_to, TDC =>TDC1D, CSTR =>CSTR4, CH =>CH4, CH_shift => CH1D_shift, - gate_time_low => gate_time_low, gate_time_high =>gate_time_high, Ampl_sat =>Ampl_sat, CH0_zero =>CH4_0_zero, CH1_zero =>CH4_1_zero, CH_trig_outt =>CH_trig(3), CH_trig_outa =>CH_triga(3), CH_trig_bgnd=> trig_bgnd(3), CH_TIME =>CH_TIME_T(3), + gate_time_low => gate_time_low, gate_time_high =>gate_time_high, Ampl_sat =>Ampl_sat, ampl_low =>ampl_low, CH0_zero =>CH4_0_zero, CH1_zero =>CH4_1_zero, CH_trig_outt =>CH_trig(3), CH_trig_outa =>CH_triga(3), CH_trig_bgnd=> trig_bgnd(3), CH_TIME =>CH_TIME_T(3), CH_ampl =>CH_ampl0(3), DATA_out=>DATA_out(3), DATA_ready=>DATA_rdy(3), DATA_rd=>DATA_rd(3), FIFO_dis=>FIFO_dis, Event_in=>Event_in(3), Z0_cal=>CH4_Z0, Z1_cal=>CH4_Z1, Z_alarm=>Z_alarm(3), spi_lock=>spi_lock320, R0_cal=>CH4_0_rg, - R1_cal=>CH4_1_rg, R0_corr=>CH4_0_rc, R1_corr=>CH4_1_rc, pulse_in=>inp_cou(3), chan_ena=>chans_ena(3)); + R1_cal=>CH4_1_rg, R0_corr=>CH4_0_rc, R1_corr=>CH4_1_rc, pulse_in=>inp_cou(3), chan_ena=>chans_ena(3), trig_dis=>trig_dis(3), fdd=>fdd, ch_trig_int=>ch_trig_outtn(2), ch_trig_outtn=>ch_trig_outtn(3)); CHANNEL2A : channel port map (CGE =>CGE5, clk320 =>clk320, reset =>sreset, tdc_rdy_in=> TDC2A_rdy0, mt_cou =>mt_cou, bc_cou =>BC_COU(5 downto 0), TR_bc =>TR_to, TDC =>TDC2A, CSTR =>CSTR5, CH =>CH5, CH_shift => CH2A_shift, - gate_time_low => gate_time_low, gate_time_high =>gate_time_high, Ampl_sat =>Ampl_sat, CH0_zero =>CH5_0_zero, CH1_zero =>CH5_1_zero, CH_trig_outt =>CH_trig(4), CH_trig_outa =>CH_triga(4), CH_trig_bgnd=> trig_bgnd(4), CH_TIME =>CH_TIME_T(4), + gate_time_low => gate_time_low, gate_time_high =>gate_time_high, Ampl_sat =>Ampl_sat, ampl_low =>ampl_low, CH0_zero =>CH5_0_zero, CH1_zero =>CH5_1_zero, CH_trig_outt =>CH_trig(4), CH_trig_outa =>CH_triga(4), CH_trig_bgnd=> trig_bgnd(4), CH_TIME =>CH_TIME_T(4), CH_ampl =>CH_ampl0(4), DATA_out=>DATA_out(4), DATA_ready=>DATA_rdy(4), DATA_rd=>DATA_rd(4), FIFO_dis=>FIFO_dis, Event_in=>Event_in(4), Z0_cal=>CH5_Z0, Z1_cal=>CH5_Z1, Z_alarm=>Z_alarm(4), spi_lock=>spi_lock320, R0_cal=>CH5_0_rg, - R1_cal=>CH5_1_rg, R0_corr=>CH5_0_rc, R1_corr=>CH5_1_rc, pulse_in=>inp_cou(4), chan_ena=>chans_ena(4)); + R1_cal=>CH5_1_rg, R0_corr=>CH5_0_rc, R1_corr=>CH5_1_rc, pulse_in=>inp_cou(4), chan_ena=>chans_ena(4), trig_dis=>trig_dis(4), fdd=>fdd, ch_trig_int=>ch_trig_outtn(5), ch_trig_outtn=>ch_trig_outtn(4)); CHANNEL2B : channel port map (CGE =>CGE6, clk320 =>clk320, reset =>sreset, tdc_rdy_in=> TDC2B_rdy0, mt_cou =>mt_cou, bc_cou =>BC_COU(5 downto 0), TR_bc =>TR_to, TDC =>TDC2B, CSTR =>CSTR6, CH =>CH6, CH_shift => CH2B_shift, - gate_time_low => gate_time_low, gate_time_high =>gate_time_high, Ampl_sat =>Ampl_sat, CH0_zero =>CH6_0_zero, CH1_zero =>CH6_1_zero, CH_trig_outt =>CH_trig(5), CH_trig_outa =>CH_triga(5), CH_trig_bgnd=> trig_bgnd(5), CH_TIME =>CH_TIME_T(5), + gate_time_low => gate_time_low, gate_time_high =>gate_time_high, Ampl_sat =>Ampl_sat, ampl_low =>ampl_low, CH0_zero =>CH6_0_zero, CH1_zero =>CH6_1_zero, CH_trig_outt =>CH_trig(5), CH_trig_outa =>CH_triga(5), CH_trig_bgnd=> trig_bgnd(5), CH_TIME =>CH_TIME_T(5), CH_ampl =>CH_ampl0(5), DATA_out=>DATA_out(5), DATA_ready=>DATA_rdy(5), DATA_rd=>DATA_rd(5), FIFO_dis=>FIFO_dis, Event_in=>Event_in(5), Z0_cal=>CH6_Z0, Z1_cal=>CH6_Z1, Z_alarm=>Z_alarm(5), spi_lock=>spi_lock320, R0_cal=>CH6_0_rg, - R1_cal=>CH6_1_rg, R0_corr=>CH6_0_rc, R1_corr=>CH6_1_rc, pulse_in=>inp_cou(5), chan_ena=>chans_ena(5)); + R1_cal=>CH6_1_rg, R0_corr=>CH6_0_rc, R1_corr=>CH6_1_rc, pulse_in=>inp_cou(5), chan_ena=>chans_ena(5), trig_dis=>trig_dis(5), fdd=>fdd, ch_trig_int=>ch_trig_outtn(4), ch_trig_outtn=>ch_trig_outtn(5)); CHANNEL2C : channel port map (CGE =>CGE7, clk320 =>clk320, reset =>sreset, tdc_rdy_in=> TDC2C_rdy0, mt_cou =>mt_cou, bc_cou =>BC_COU(5 downto 0), TR_bc =>TR_to, TDC =>TDC2C, CSTR =>CSTR7, CH =>CH7, CH_shift => CH2C_shift, - gate_time_low => gate_time_low, gate_time_high =>gate_time_high, Ampl_sat =>Ampl_sat, CH0_zero =>CH7_0_zero, CH1_zero =>CH7_1_zero, CH_trig_outt =>CH_trig(6), CH_trig_outa =>CH_triga(6), CH_trig_bgnd=> trig_bgnd(6), CH_TIME =>CH_TIME_T(6), + gate_time_low => gate_time_low, gate_time_high =>gate_time_high, Ampl_sat =>Ampl_sat, ampl_low =>ampl_low, CH0_zero =>CH7_0_zero, CH1_zero =>CH7_1_zero, CH_trig_outt =>CH_trig(6), CH_trig_outa =>CH_triga(6), CH_trig_bgnd=> trig_bgnd(6), CH_TIME =>CH_TIME_T(6), CH_ampl =>CH_ampl0(6), DATA_out=>DATA_out(6), DATA_ready=>DATA_rdy(6), DATA_rd=>DATA_rd(6), FIFO_dis=>FIFO_dis, Event_in=>Event_in(6), Z0_cal=>CH7_Z0, Z1_cal=>CH7_Z1, Z_alarm=>Z_alarm(6), spi_lock=>spi_lock320, R0_cal=>CH7_0_rg, - R1_cal=>CH7_1_rg, R0_corr=>CH7_0_rc, R1_corr=>CH7_1_rc, pulse_in=>inp_cou(6), chan_ena=>chans_ena(6)); - CHANNEL2D : channel port map (CGE =>CGE8, clk320 =>clk320, reset =>sreset, tdc_rdy_in=> TDC2D_rdy0, mt_cou =>mt_cou, bc_cou =>BC_COU(5 downto 0), TR_bc =>TR_to, TDC =>TDC2D, CSTR =>CSTR8, CH =>CH8, CH_shift => CH2D_shift, - - gate_time_low => gate_time_low, gate_time_high =>gate_time_high, Ampl_sat =>Ampl_sat, CH0_zero =>CH8_0_zero, CH1_zero =>CH8_1_zero, CH_trig_outt =>CH_trig(7), CH_trig_outa =>CH_triga(7), CH_trig_bgnd=> trig_bgnd(7), CH_TIME =>CH_TIME_T(7), + R1_cal=>CH7_1_rg, R0_corr=>CH7_0_rc, R1_corr=>CH7_1_rc, pulse_in=>inp_cou(6), chan_ena=>chans_ena(6), trig_dis=>trig_dis(6), fdd=>fdd, ch_trig_int=>ch_trig_outtn(7), ch_trig_outtn=>ch_trig_outtn(6)); + +CHANNEL2D : channel port map (CGE =>CGE8, clk320 =>clk320, reset =>sreset, tdc_rdy_in=> TDC2D_rdy0, mt_cou =>mt_cou, bc_cou =>BC_COU(5 downto 0), TR_bc =>TR_to, TDC =>TDC2D, CSTR =>CSTR8, CH =>CH8, CH_shift => CH2D_shift, + gate_time_low => gate_time_low, gate_time_high =>gate_time_high, Ampl_sat =>Ampl_sat, ampl_low =>ampl_low, CH0_zero =>CH8_0_zero, CH1_zero =>CH8_1_zero, CH_trig_outt =>CH_trig(7), CH_trig_outa =>CH_triga(7), CH_trig_bgnd=> trig_bgnd(7), CH_TIME =>CH_TIME_T(7), CH_ampl =>CH_ampl0(7), DATA_out=>DATA_out(7), DATA_ready=>DATA_rdy(7), DATA_rd=>DATA_rd(7), FIFO_dis=>FIFO_dis, Event_in=>Event_in(7), Z0_cal=>CH8_Z0, Z1_cal=>CH8_Z1, Z_alarm=>Z_alarm(7), spi_lock=>spi_lock320, R0_cal=>CH8_0_rg, - R1_cal=>CH8_1_rg, R0_corr=>CH8_0_rc, R1_corr=>CH8_1_rc, pulse_in=>inp_cou(7), chan_ena=>chans_ena(7)); + R1_cal=>CH8_1_rg, R0_corr=>CH8_0_rc, R1_corr=>CH8_1_rc, pulse_in=>inp_cou(7), chan_ena=>chans_ena(7), trig_dis=>trig_dis(7), fdd=>fdd, ch_trig_int=>ch_trig_outtn(6), ch_trig_outtn=>ch_trig_outtn(7)); CHANNEL3A : channel port map (CGE =>CGE9, clk320 =>clk320, reset =>sreset, tdc_rdy_in=> TDC3A_rdy0, mt_cou =>mt_cou, bc_cou =>BC_COU(5 downto 0), TR_bc =>TR_to, TDC =>TDC3A, CSTR =>CSTR9, CH =>CH9, CH_shift => CH3A_shift, - gate_time_low => gate_time_low, gate_time_high =>gate_time_high, Ampl_sat =>Ampl_sat, CH0_zero =>CH9_0_zero, CH1_zero =>CH9_1_zero, CH_trig_outt =>CH_trig(8), CH_trig_outa =>CH_triga(8), CH_trig_bgnd=> trig_bgnd(8), CH_TIME =>CH_TIME_T(8), + gate_time_low => gate_time_low, gate_time_high =>gate_time_high, Ampl_sat =>Ampl_sat, ampl_low =>ampl_low, CH0_zero =>CH9_0_zero, CH1_zero =>CH9_1_zero, CH_trig_outt =>CH_trig(8), CH_trig_outa =>CH_triga(8), CH_trig_bgnd=> trig_bgnd(8), CH_TIME =>CH_TIME_T(8), CH_ampl =>CH_ampl0(8), DATA_out=>DATA_out(8), DATA_ready=>DATA_rdy(8), DATA_rd=>DATA_rd(8), FIFO_dis=>FIFO_dis, Event_in=>Event_in(8), Z0_cal=>CH9_Z0, Z1_cal=>CH9_Z1, Z_alarm=>Z_alarm(8), spi_lock=>spi_lock320, R0_cal=>CH9_0_rg, - R1_cal=>CH9_1_rg, R0_corr=>CH9_0_rc, R1_corr=>CH9_1_rc, pulse_in=>inp_cou(8), chan_ena=>chans_ena(8)); + R1_cal=>CH9_1_rg, R0_corr=>CH9_0_rc, R1_corr=>CH9_1_rc, pulse_in=>inp_cou(8), chan_ena=>chans_ena(8), trig_dis=>trig_dis(8), fdd=>fdd, ch_trig_int=>ch_trig_outtn(9), ch_trig_outtn=>ch_trig_outtn(8)); CHANNEL3B : channel port map (CGE =>CGE10, clk320 =>clk320, reset =>sreset, tdc_rdy_in=> TDC3B_rdy0, mt_cou =>mt_cou, bc_cou =>BC_COU(5 downto 0), TR_bc =>TR_to, TDC =>TDC3B, CSTR =>CSTR10, CH =>CH10, CH_shift => CH3B_shift, - gate_time_low => gate_time_low, gate_time_high =>gate_time_high, Ampl_sat =>Ampl_sat, CH0_zero =>CH10_0_zero, CH1_zero =>CH10_1_zero, CH_trig_outt =>CH_trig(9), CH_trig_outa =>CH_triga(9), CH_trig_bgnd=> trig_bgnd(9), CH_TIME =>CH_TIME_T(9), + gate_time_low => gate_time_low, gate_time_high =>gate_time_high, Ampl_sat =>Ampl_sat, ampl_low =>ampl_low, CH0_zero =>CH10_0_zero, CH1_zero =>CH10_1_zero, CH_trig_outt =>CH_trig(9), CH_trig_outa =>CH_triga(9), CH_trig_bgnd=> trig_bgnd(9), CH_TIME =>CH_TIME_T(9), CH_ampl =>CH_ampl0(9), DATA_out=>DATA_out(9), DATA_ready=>DATA_rdy(9), DATA_rd=>DATA_rd(9), FIFO_dis=>FIFO_dis, Event_in=>Event_in(9), Z0_cal=>CH10_Z0, Z1_cal=>CH10_Z1, Z_alarm=>Z_alarm(9), spi_lock=>spi_lock320, R0_cal=>CH10_0_rg, - R1_cal=>CH10_1_rg, R0_corr=>CH10_0_rc, R1_corr=>CH10_1_rc, pulse_in=>inp_cou(9), chan_ena=>chans_ena(9)); + R1_cal=>CH10_1_rg, R0_corr=>CH10_0_rc, R1_corr=>CH10_1_rc, pulse_in=>inp_cou(9), chan_ena=>chans_ena(9), trig_dis=>trig_dis(9), fdd=>fdd, ch_trig_int=>ch_trig_outtn(8), ch_trig_outtn=>ch_trig_outtn(9)); CHANNEL3C : channel port map (CGE =>CGE11, clk320 =>clk320, reset =>sreset, tdc_rdy_in=> TDC3C_rdy0, mt_cou =>mt_cou, bc_cou =>BC_COU(5 downto 0), TR_bc =>TR_to, TDC =>TDC3C, CSTR =>CSTR11, CH =>CH11, CH_shift => CH3C_shift, - gate_time_low => gate_time_low, gate_time_high =>gate_time_high, Ampl_sat =>Ampl_sat, CH0_zero =>CH11_0_zero, CH1_zero =>CH11_1_zero, CH_trig_outt =>CH_trig(10), CH_trig_outa =>CH_triga(10), CH_trig_bgnd=> trig_bgnd(10), CH_TIME =>CH_TIME_T(10), + gate_time_low => gate_time_low, gate_time_high =>gate_time_high, Ampl_sat =>Ampl_sat, ampl_low =>ampl_low, CH0_zero =>CH11_0_zero, CH1_zero =>CH11_1_zero, CH_trig_outt =>CH_trig(10), CH_trig_outa =>CH_triga(10), CH_trig_bgnd=> trig_bgnd(10), CH_TIME =>CH_TIME_T(10), CH_ampl =>CH_ampl0(10), DATA_out=>DATA_out(10), DATA_ready=>DATA_rdy(10), DATA_rd=>DATA_rd(10), FIFO_dis=>FIFO_dis, Event_in=>Event_in(10), Z0_cal=>CH11_Z0, Z1_cal=>CH11_Z1, Z_alarm=>Z_alarm(10), spi_lock=>spi_lock320, R0_cal=>CH11_0_rg, - R1_cal=>CH11_1_rg, R0_corr=>CH11_0_rc, R1_corr=>CH11_1_rc, pulse_in=>inp_cou(10), chan_ena=>chans_ena(10)); + R1_cal=>CH11_1_rg, R0_corr=>CH11_0_rc, R1_corr=>CH11_1_rc, pulse_in=>inp_cou(10), chan_ena=>chans_ena(10), trig_dis=>trig_dis(10), fdd=>fdd, ch_trig_int=>ch_trig_outtn(11), ch_trig_outtn=>ch_trig_outtn(10)); CHANNEL3D : channel port map (CGE =>CGE12, clk320 =>clk320, reset =>sreset, tdc_rdy_in=> TDC3D_rdy0, mt_cou =>mt_cou, bc_cou =>BC_COU(5 downto 0), TR_bc =>TR_to, TDC =>TDC3D, CSTR =>CSTR12, CH =>CH12, CH_shift => CH3D_shift, - gate_time_low => gate_time_low, gate_time_high =>gate_time_high, Ampl_sat =>Ampl_sat, CH0_zero =>CH12_0_zero, CH1_zero =>CH12_1_zero, CH_trig_outt =>CH_trig(11), CH_trig_outa =>CH_triga(11), CH_trig_bgnd=> trig_bgnd(11), CH_TIME =>CH_TIME_T(11), + gate_time_low => gate_time_low, gate_time_high =>gate_time_high, Ampl_sat =>Ampl_sat, ampl_low =>ampl_low, CH0_zero =>CH12_0_zero, CH1_zero =>CH12_1_zero, CH_trig_outt =>CH_trig(11), CH_trig_outa =>CH_triga(11), CH_trig_bgnd=> trig_bgnd(11), CH_TIME =>CH_TIME_T(11), CH_ampl =>CH_ampl0(11), DATA_out=>DATA_out(11), DATA_ready=>DATA_rdy(11), DATA_rd=>DATA_rd(11), FIFO_dis=>FIFO_dis, Event_in=>Event_in(11), Z0_cal=>CH12_Z0, Z1_cal=>CH12_Z1, Z_alarm=>Z_alarm(11), spi_lock=>spi_lock320, R0_cal=>CH12_0_rg, - R1_cal=>CH12_1_rg, R0_corr=>CH12_0_rc, R1_corr=>CH12_1_rc, pulse_in=>inp_cou(11), chan_ena=>chans_ena(11)); + R1_cal=>CH12_1_rg, R0_corr=>CH12_0_rc, R1_corr=>CH12_1_rc, pulse_in=>inp_cou(11), chan_ena=>chans_ena(11), trig_dis=>trig_dis(11), fdd=>fdd, ch_trig_int=>ch_trig_outtn(10), ch_trig_outtn=>ch_trig_outtn(11)); TRG0: trigger port map ( clk320=>clk320, mt_cou=>mt_cou, CH_trigt=>CH_trig, CH_triga=>CH_triga, CH_trigb=>trig_bgnd, CH_TIME_T=>CH_TIME_T, CH_ampl0=>CH_ampl0, tcm_req=>tcm_req, tt=>tt, ta=>ta); @@ -1261,19 +1286,19 @@ if (HSCKI'event and HSCKI='0') then else case to_integer(unsigned(hspi_addr(7 downto 0))) is - when 0 => HSPI_DATA<=x"00" & gate_time_high; - when 1 => HSPI_DATA<=x"0" & CH1A_shift; - when 2 => HSPI_DATA<=x"0" & CH1B_shift; - when 3 => HSPI_DATA<=x"0" & CH1C_shift; - when 4 => HSPI_DATA<=x"0" & CH1D_shift; - when 5 => HSPI_DATA<=x"0" & CH2A_shift; - when 6 => HSPI_DATA<=x"0" & CH2B_shift; - when 7 => HSPI_DATA<=x"0" & CH2C_shift; - when 8 => HSPI_DATA<=x"0" & CH2D_shift; - when 9 => HSPI_DATA<=x"0" & CH3A_shift; - when 16#A# => HSPI_DATA<=x"0" & CH3B_shift; - when 16#B# => HSPI_DATA<=x"0" & CH3C_shift; - when 16#C# => HSPI_DATA<=x"0" & CH3D_shift; + when 0 => HSPI_DATA<="0000000" & fdd & gate_time_high; + when 1 => HSPI_DATA<="000" & trig_dis(0) & CH1A_shift; + when 2 => HSPI_DATA<="000" & trig_dis(1) & CH1B_shift; + when 3 => HSPI_DATA<="000" & trig_dis(2) & CH1C_shift; + when 4 => HSPI_DATA<="000" & trig_dis(3) & CH1D_shift; + when 5 => HSPI_DATA<="000" & trig_dis(4) & CH2A_shift; + when 6 => HSPI_DATA<="000" & trig_dis(5) & CH2B_shift; + when 7 => HSPI_DATA<="000" & trig_dis(6) & CH2C_shift; + when 8 => HSPI_DATA<="000" & trig_dis(7) & CH2D_shift; + when 9 => HSPI_DATA<="000" & trig_dis(8) & CH3A_shift; + when 16#A# => HSPI_DATA<="000" & trig_dis(9) & CH3B_shift; + when 16#B# => HSPI_DATA<="000" & trig_dis(10) & CH3C_shift; + when 16#C# => HSPI_DATA<="000" & trig_dis(11) & CH3D_shift; when 16#D# => HSPI_DATA<=x"0" & CH1_0_zero; when 16#E# => HSPI_DATA<=x"0" & CH1_1_zero; @@ -1324,7 +1349,7 @@ if (HSCKI'event and HSCKI='0') then when 16#3A# => HSPI_DATA<=x"0" & CH11_1_rc; when 16#3B# => HSPI_DATA<=x"0" & CH12_0_rc; when 16#3C# => HSPI_DATA<=x"0" & CH12_1_rc; - when 16#3D# => HSPI_DATA<=x"0" & Ampl_sat; + when 16#3D# => HSPI_DATA<= ampl_low & Ampl_sat; when 16#3E# => HSPI_DATA<=pshift2(5) & pshift2(5) & pshift2 & pshift1(5) & pshift1(5) & pshift1; when 16#3F# => HSPI_DATA<=x"00" & pshift3(5) & pshift3(5) & pshift3; @@ -1432,10 +1457,10 @@ end if; end if; end process; -h0: hyst Port map(clk320 =>clk320, hyst_inp_data =>hyst_data, hyst_a =>hyst_a, hyst_t =>hyst_t, hyst_st =>start_hyst, cnt_clr =>cnt_rst, busy =>h_busy, hyst_addr_i =>hspid_w32(16 downto 0), hyst_addr_o =>hyst_addr, +h0: hyst Port map(clk320 =>clk320, hyst_inp_data =>hyst_data, hyst_a =>hyst_a, hyst_t =>hyst_t, hyst_st =>start_hyst, cnt_clr =>hyst_clr, busy =>h_busy, hyst_addr_i =>hspid_w32(16 downto 0), hyst_addr_o =>hyst_addr, wr_addr =>wr_hyst_a, hyst_data_o =>hyst_r_data, n_addr =>rd_hyst_d, lock320 =>hspi_lock320, stp=> hyst_stp); -wr_hyst_a <= reg32_320_wr and hysta_sel; rd_hyst_d<= reg32_320_str and hystd_sel; +wr_hyst_a <= reg32_320_wr and hysta_sel; rd_hyst_d<= reg32_320_str and hystd_sel; hyst_clr<=cnt_rst or hyst_rst; h1: for i in 0 to 11 generate hyst_data(i) <= DATA_out(i)(25 downto 0); @@ -1646,9 +1671,12 @@ str_reg32 <= '1' when (reg32_str2='0') and (reg32_str1='1') else '0'; reg_wr_data<= spi_wr_data when (spi_wr_req='1') else hspi_wr_data; reg_wr_addr<= spi_addr when (spi_wr_req='1') else hspi_addr; +err_report_fifo_rden <= '1' when (str_reg32='1') and (to_integer(unsigned(hspi_addr(7 downto 0)))=16#F2#) else '0'; +readout_err_rden <= '1' when (str_reg32='1') and (to_integer(unsigned(hspi_addr(7 downto 0)))=16#EA#) else '0'; + process(TX_CLK, sreset) begin -if sreset='1' then buf_vector<=x"000000000000000"; buf_cou<=x"A0"; dcs_irq<='0'; vect_clr_req<='0'; ipbus_control_reg(0)<= x"0040_0000"; +if sreset='1' then buf_vector<=x"000000000000000"; buf_cou<=x"A0"; dcs_irq<='0'; vect_clr_req<='0'; else if (TX_CLK'event and TX_CLK='1') then @@ -1658,11 +1686,16 @@ spibuf_rd2<=spibuf_rd1; spibuf_rd1<=spibuf_rd0; spibuf_rd0<=spibuf_rd; hspibuf_r buf_lock2<=buf_lock1; buf_lock1<=buf_lock0; buf_lock0<=buf_lock; -hbuf_req <= (not hspibuf_wr2) and hspibuf_wr1 and sbuf_wrena; - +hbuf_req <= (not hspibuf_wr2) and hspibuf_wr1 and sbuf_wrena; + +--err_report_fifo_rden <= '0'; if (rd_hspi32='1') then - if (rdo_sel='1') then hspib_32 <=ipbus_status_reg(to_integer(unsigned(hspi_addr(7 downto 0)))-16#E8#); - else if (flsh_sel='1') then hspib_32 <=hspid_r32; end if; + + if (rdo_sel='1') then + hspib_32 <=ipbus_status_reg(to_integer(unsigned(hspi_addr(7 downto 0)))-16#E8#); + --if (to_integer(unsigned(hspi_addr(7 downto 0)))-16#E8#) = 10 then err_report_fifo_rden <= '1'; end if; + else if (flsh_sel='1') then hspib_32 <=hspid_r32; end if; + end if; end if; @@ -1681,13 +1714,10 @@ end if; else if (stat_clr1='1') and (stat_clr='0') then dcs_irq<='0'; end if; end if; -if (GBTRX_ready='0') and (GBTRX_ready0='1') then ipbus_control_reg(0)(22)<='1'; - else - if (reg32_wr2='0') and (reg32_wr1='1') and (hspi_addr(7 downto 0)<=16#E7#) then - if (hspi_addr(7 downto 0)=16#D8#) then ipbus_control_reg(0)<= hspid_w32(31 downto 23) & (hspid_w32(22) or not GBTRX_ready) & hspid_w32(21 downto 0); - else ipbus_control_reg(to_integer(unsigned(hspi_addr(7 downto 0)))-16#D8#)<= hspid_w32; - end if; - end if; + if (reg32_wr2='0') and (reg32_wr1='1') and (hspi_addr(7 downto 0)<=16#E7#) then + if (hspi_addr(7 downto 0)=16#D8#) then ipbus_control_reg(0)<= hspid_w32; + else ipbus_control_reg(to_integer(unsigned(hspi_addr(7 downto 0)))-16#D8#)<= hspid_w32; + end if; end if; @@ -1704,7 +1734,7 @@ sbuf_ena<=sbuf_wrena or sbuf_rdena; hbuf_ena<=hbuf_wrena or hbuf_rdena; Xmegamem : Xmega_buf PORT MAP (clka => TX_CLK, ena => hbuf_ena, wea(0) => hbuf_wrena, addra => hspi_addr(5 downto 0), dina => hspi_wr_data, douta=>hspi_buf_out, clkb => TX_CLK, enb => sbuf_ena, web(0) => sbuf_wrena, addrb => spi_addr(5 downto 0), dinb => spi_wr_data, doutb => spi_buf_out); -tcm_req <= ((not tcm_req2) and tcm_req1) or ((not gs0) and gbt_global_status(0)) or ((not gs1) and gbt_global_status(1)); +tcm_req <= ((not tcm_req2) and tcm_req1) or ((not gs0_1) and gs0_0) or ((not gs1_1) and gs1_0); reg32_320_wr<= reg32_320_wr1 and (not reg32_320_wr2); reg32_320_str<= reg32_320_str1 and (not reg32_320_str2); @@ -1714,7 +1744,7 @@ if (clk320'event and clk320='1') then reg32_320_wr2 <=reg32_320_wr1; reg32_320_wr1 <=reg32_320_wr0; reg32_320_wr0 <=reg32_wr; reg32_320_str2 <=reg32_320_str1; reg32_320_str1 <=reg32_320_str0; reg32_320_str0 <=reg32_str; -gs0<=gbt_global_status(0); gs1<=gbt_global_status(1); +gs0_1<=gs0_0; gs0_0<=gbt_global_status(0); gs1_1<=gs1_0; gs1_0<=gbt_global_status(1); spi_wr2<=spi_wr1; spi_wr1<=spi_wr0; spi_wr0<=spi_wr_rdy; hspi_wr2<=hspi_wr1; hspi_wr1<=hspi_wr0; hspi_wr0<=hspi_wr_rdy; @@ -1723,25 +1753,25 @@ tcm_req2<=tcm_req1; tcm_req1<=tcm_req0; tcm_req0<=tcm_reqh; if (spi_wr2='0') and (spi_wr1='1') then spi_wr_req<='1'; end if; if (hspi_wr2='0') and (hspi_wr1='1') then hspi_wr_req<='1'; end if; -if (cnt_rst='1') then cnt_rst<='0'; end if; +if (cnt_rst='1') then cnt_rst<='0'; end if; if (hyst_rst='1') then hyst_rst<='0'; end if; if (sreset='1') then chans_block <= '0'; hyst_md(15)<='0'; is_rst<='1'; else if (spi_wr_req='1') or (hspi_wr_req='1') then case reg_wr_addr(7 downto 0) is - when x"00" => gate_time_high<=reg_wr_data(7 downto 0); - when x"01" => CH1A_shift<=reg_wr_data(11 downto 0); - when x"02" => CH1B_shift<=reg_wr_data(11 downto 0); - when x"03" => CH1C_shift<=reg_wr_data(11 downto 0); - when x"04" => CH1D_shift<=reg_wr_data(11 downto 0); - when x"05" => CH2A_shift<=reg_wr_data(11 downto 0); - when x"06" => CH2B_shift<=reg_wr_data(11 downto 0); - when x"07" => CH2C_shift<=reg_wr_data(11 downto 0); - when x"08" => CH2D_shift<=reg_wr_data(11 downto 0); - when x"09" => CH3A_shift<=reg_wr_data(11 downto 0); - when x"0A" => CH3B_shift<=reg_wr_data(11 downto 0); - when x"0B" => CH3C_shift<=reg_wr_data(11 downto 0); - when x"0C" => CH3D_shift<=reg_wr_data(11 downto 0); + when x"00" => gate_time_high<=reg_wr_data(7 downto 0); if (spi_wr_req='0') then fdd<=reg_wr_data(8); end if; + when x"01" => CH1A_shift<=reg_wr_data(11 downto 0); if (spi_wr_req='0') then trig_dis(0)<=reg_wr_data(12); end if; + when x"02" => CH1B_shift<=reg_wr_data(11 downto 0); if (spi_wr_req='0') then trig_dis(1)<=reg_wr_data(12); end if; + when x"03" => CH1C_shift<=reg_wr_data(11 downto 0); if (spi_wr_req='0') then trig_dis(2)<=reg_wr_data(12); end if; + when x"04" => CH1D_shift<=reg_wr_data(11 downto 0); if (spi_wr_req='0') then trig_dis(3)<=reg_wr_data(12); end if; + when x"05" => CH2A_shift<=reg_wr_data(11 downto 0); if (spi_wr_req='0') then trig_dis(4)<=reg_wr_data(12); end if; + when x"06" => CH2B_shift<=reg_wr_data(11 downto 0); if (spi_wr_req='0') then trig_dis(5)<=reg_wr_data(12); end if; + when x"07" => CH2C_shift<=reg_wr_data(11 downto 0); if (spi_wr_req='0') then trig_dis(6)<=reg_wr_data(12); end if; + when x"08" => CH2D_shift<=reg_wr_data(11 downto 0); if (spi_wr_req='0') then trig_dis(7)<=reg_wr_data(12); end if; + when x"09" => CH3A_shift<=reg_wr_data(11 downto 0); if (spi_wr_req='0') then trig_dis(8)<=reg_wr_data(12); end if; + when x"0A" => CH3B_shift<=reg_wr_data(11 downto 0); if (spi_wr_req='0') then trig_dis(9)<=reg_wr_data(12); end if; + when x"0B" => CH3C_shift<=reg_wr_data(11 downto 0); if (spi_wr_req='0') then trig_dis(10)<=reg_wr_data(12); end if; + when x"0C" => CH3D_shift<=reg_wr_data(11 downto 0); if (spi_wr_req='0') then trig_dis(11)<=reg_wr_data(12); end if; when x"25" => CH1_0_rc<=reg_wr_data(11 downto 0); @@ -1768,11 +1798,12 @@ if (cnt_rst='1') then cnt_rst<='0'; end if; when x"3A" => CH11_1_rc<=reg_wr_data(11 downto 0); when x"3B" => CH12_0_rc<=reg_wr_data(11 downto 0); when x"3C" => CH12_1_rc<=reg_wr_data(11 downto 0); - when x"3D" => Ampl_sat <=reg_wr_data(11 downto 0); + when x"3D" => Ampl_sat <=reg_wr_data(11 downto 0); ampl_low <=reg_wr_data(15 downto 12); when x"7C" => chans_ena_r <=reg_wr_data(11 downto 0); - when x"7E" => hyst_md(14 downto 0) <=reg_wr_data(14 downto 0); + when x"7E" => hyst_md(14 downto 0) <=reg_wr_data(14) & '0' & reg_wr_data(12 downto 0) ; + if (hyst_rst='0') and (reg_wr_data(13)='1') then hyst_rst<='1'; end if; when x"7F" => if (cnt_rst='0') and (reg_wr_data(9)='1') then cnt_rst<='1'; end if; if (hspi_wr_req='1') and (spi_wr_req='0') then cnt_md <= reg_wr_data(10); end if; @@ -1903,21 +1934,24 @@ hclr30<=Hs_rd; hclr31<=hclr30; h_clr3<=hclr31; end if; end process; -PM_data_toreadout.data_word <= DATA80_in; +PM_data_toreadout.data_word <= data_word; process (clk320) begin if (clk320'event and clk320='1') then +rx_phase_status(2 downto 0) <= readout_status.rx_phase; +rx_phase_status(3) <= readout_status.Rx_Phase_error; + spi_lock320<=spi_lock320_0; spi_lock320_0<= rd_lock; hspi_lock320<=hspi_lock320_0; hspi_lock320_0<= rd_lock_hspi; tto<=tt; tao<=ta; MCLK40_0<=MCLK40T; MCLK40_1<=MCLK40_0; if (MCLK40_0/=MCLK40_1) then mt_cou<="000"; else mt_cou<=mt_cou+1; end if; -PM_data_toreadout.is_header <= wr_out_id; -PM_data_toreadout.is_data <= Event_ready or wr_out_id; -PM_data_toreadout.is_packet <= Event_ready or wr_out_id; +PM_data_toreadout.is_header <= is_header; is_header<= wr_out_id; +PM_data_toreadout.is_data <= is_data; is_data<= Event_ready or wr_out_id; +data_word <=DATA80_in; if (wr_out_id='1') then DATA80_in<= x"F" & '0' & WRDS_NUM & x"000000" & rx_phase_status & EV_ID_out(55 downto 12); else DATA80_in<=EV_DATA80; @@ -1925,13 +1959,13 @@ end if; if (Event_free='1') or (wr_out_id='1') then ev_tout_cnt<=(others=>'0'); else ev_tout_cnt<=ev_tout_cnt+1; end if; -if (ev_tout_cnt=96) then ev_tout<='1'; else ev_tout<='0'; end if; +if (ev_tout_cnt=96) and (wr_out_id='0') then ev_tout<='1'; else ev_tout<='0'; end if; ev_tout0 <= ev_tout; --if (wr_out_id='1') or (Event_ready='1') then WR_fifo_out<='1'; else WR_fifo_out<='0'; end if; if (Event_ready='0') then - if (Event_ready_0='1') then Event_ready<='1'; end if; + if (Event_ready_0='1') and (ev_tout='0') then Event_ready<='1'; end if; else if (CH_do=0) then Event_ready<='0'; end if; end if; @@ -1987,8 +2021,8 @@ end if; if (Event_ready='1') or (Event_ready_0='1') then CH_N0<= CH_N0_0; CH_N1<= CH_N1_0; end if; if (mt_cou="001") then - if (New_BCID='1') then BC_COU<=FIT_GBT_status. BCID_from_CRU_corrected; Orbit_ID<=FIT_GBT_status. ORBIT_from_CRU_corrected; - if (FIT_GBT_status. BCID_from_CRU_corrected>x"003") then TR_to<=FIT_GBT_status. BCID_from_CRU_corrected(5 downto 0)-"000100"; else TR_to<="1010" & FIT_GBT_status. BCID_from_CRU_corrected(1 downto 0); end if; + if (New_BCID='1') then BC_COU<=readout_status. BCID_from_CRU_corrected; Orbit_ID<=readout_status. ORBIT_from_CRU_corrected; + if (readout_status. BCID_from_CRU_corrected>x"003") then TR_to<=readout_status. BCID_from_CRU_corrected(5 downto 0)-"000100"; else TR_to<="1010" & readout_status. BCID_from_CRU_corrected(1 downto 0); end if; else if (BC_COU=x"DEB") then BC_cou<=x"000"; Orbit_ID<=Orbit_ID+1; else BC_cou<=BC_cou+1; end if; @@ -2002,7 +2036,7 @@ if (mt_cou="001") then end if; end process; -New_BCID <= FIT_GBT_status.Start_run when (FIT_GBT_status.BCIDsync_Mode=mode_SYNC) else '0'; +New_BCID <= readout_status.bc_delay_apply; CH_N0_0<= x"1" when CH_do(0)='1' else x"2" when CH_do(1)='1' diff --git a/firmware/FT0/PM/hdl/pin_capt.vhd b/firmware/FT0/PM/hdl/pin_capt.vhd index 493051e..c474c59 100644 --- a/firmware/FT0/PM/hdl/pin_capt.vhd +++ b/firmware/FT0/PM/hdl/pin_capt.vhd @@ -44,7 +44,7 @@ architecture RTL of pin_capt is signal ISER_BITS : STD_LOGIC_VECTOR (3 downto 0); signal ISER_BITS1, ISER_COUL : STD_LOGIC_VECTOR (2 downto 0); signal ISER_COU : STD_LOGIC_VECTOR (1 downto 0); -signal clk600B, clk600B_90, ena, ena1,PC_STR : STD_LOGIC; +signal clk600B, clk600B_90, PC_STR, clk300t, clk300t1, clk300t2 : STD_LOGIC; begin @@ -85,15 +85,22 @@ ISERDES_1 : ISERDESE2 RST => '0', SHIFTIN1 => '0', SHIFTIN2 => '0' ); +process(clk300) +begin + +if (clk300'event and clk300='1') then clk300t<=not clk300t; end if; + +end process; + +str<=PC_STR; process(clk600) begin -if (clk600'event and clk600='0') then ena1<=clk300; end if; - if (clk600'event and clk600='1') then -ISER_BITS1<=ISER_COUL; ena<=ena1; str<=PC_STR; -if ena='1' then + +ISER_BITS1<=ISER_COUL; clk300t2<=clk300t1; clk300t1<=clk300t; +if (clk300t1/=clk300t2) then PC_STR<=ISER_BITS(0); if (PC_STR='0') and (ISER_BITS(0)='1') then ptime(2)<=ISER_BITS1(2); ptime(1 downto 0)<= ISER_COU; end if; end if; diff --git a/firmware/FT0/PM/ipcore_properties/cntpck_fifo_comp.txt b/firmware/FT0/PM/ipcore_properties/cntpck_fifo_comp.txt index c22a96e..abb5b43 100644 --- a/firmware/FT0/PM/ipcore_properties/cntpck_fifo_comp.txt +++ b/firmware/FT0/PM/ipcore_properties/cntpck_fifo_comp.txt @@ -14,7 +14,7 @@ CONFIG.Clock_Type_AXI string false Common_Cl CONFIG.Component_Name string false cntpck_fifo_comp CONFIG.DATA_WIDTH string false 64 CONFIG.Data_Count string false false -CONFIG.Data_Count_Width string false 7 +CONFIG.Data_Count_Width string false 8 CONFIG.Disable_Timing_Violations string false false CONFIG.Disable_Timing_Violations_AXI string false false CONFIG.Dout_Reset_Value string false 0 @@ -60,14 +60,14 @@ CONFIG.FIFO_Implementation_wdch string false Common_Cl CONFIG.FIFO_Implementation_wrch string false Common_Clock_Block_RAM CONFIG.Fifo_Implementation string false Independent_Clocks_Block_RAM CONFIG.Full_Flags_Reset_Value string false 1 -CONFIG.Full_Threshold_Assert_Value string false 127 +CONFIG.Full_Threshold_Assert_Value string false 255 CONFIG.Full_Threshold_Assert_Value_axis string false 1023 CONFIG.Full_Threshold_Assert_Value_rach string false 1023 CONFIG.Full_Threshold_Assert_Value_rdch string false 1023 CONFIG.Full_Threshold_Assert_Value_wach string false 1023 CONFIG.Full_Threshold_Assert_Value_wdch string false 1023 CONFIG.Full_Threshold_Assert_Value_wrch string false 1023 -CONFIG.Full_Threshold_Negate_Value string false 126 +CONFIG.Full_Threshold_Negate_Value string false 254 CONFIG.HAS_ACLKEN string false false CONFIG.HAS_TKEEP string false false CONFIG.HAS_TSTRB string false false @@ -87,8 +87,8 @@ CONFIG.Inject_Sbit_Error_rdch string false false CONFIG.Inject_Sbit_Error_wach string false false CONFIG.Inject_Sbit_Error_wdch string false false CONFIG.Inject_Sbit_Error_wrch string false false -CONFIG.Input_Data_Width string false 160 -CONFIG.Input_Depth string false 128 +CONFIG.Input_Data_Width string false 128 +CONFIG.Input_Depth string false 256 CONFIG.Input_Depth_axis string false 1024 CONFIG.Input_Depth_rach string false 16 CONFIG.Input_Depth_rdch string false 1024 @@ -100,9 +100,9 @@ CONFIG.MASTER_ACLK.INSERT_VIP string false 0 CONFIG.M_AXI.INSERT_VIP string false 0 CONFIG.M_AXIS.INSERT_VIP string false 0 CONFIG.Master_interface_Clock_enable_memory_mapped string false false -CONFIG.Output_Data_Width string false 160 -CONFIG.Output_Depth string false 128 -CONFIG.Output_Register_Type string false Embedded_Reg +CONFIG.Output_Data_Width string false 128 +CONFIG.Output_Depth string false 256 +CONFIG.Output_Register_Type string false Fabric_Reg CONFIG.Overflow_Flag string false false CONFIG.Overflow_Flag_AXI string false false CONFIG.Overflow_Sense string false Active_High @@ -155,9 +155,9 @@ CONFIG.Underflow_Flag_AXI string false false CONFIG.Underflow_Sense string false Active_High CONFIG.Underflow_Sense_AXI string false Active_High CONFIG.Use_Dout_Reset string false true -CONFIG.Use_Embedded_Registers string false false +CONFIG.Use_Embedded_Registers string false true CONFIG.Use_Embedded_Registers_axis string false false -CONFIG.Use_Extra_Logic string false true +CONFIG.Use_Extra_Logic string false false CONFIG.Valid_Flag string false false CONFIG.Valid_Sense string false Active_High CONFIG.WRITE_CLK.FREQ_HZ string false 100000000 diff --git a/firmware/FT0/PM/ipcore_properties/err_report_fifo.txt b/firmware/FT0/PM/ipcore_properties/err_report_fifo.txt new file mode 100644 index 0000000..ae3e3d4 --- /dev/null +++ b/firmware/FT0/PM/ipcore_properties/err_report_fifo.txt @@ -0,0 +1,185 @@ +Property Type Read-only Value +CONFIG.ADDRESS_WIDTH string false 32 +CONFIG.ARUSER_Width string false 0 +CONFIG.AWUSER_Width string false 0 +CONFIG.Add_NGC_Constraint_AXI string false false +CONFIG.Almost_Empty_Flag string false false +CONFIG.Almost_Full_Flag string false false +CONFIG.BUSER_Width string false 0 +CONFIG.CORE_CLK.FREQ_HZ string false 100000000 +CONFIG.CORE_CLK.INSERT_VIP string false 0 +CONFIG.C_SELECT_XPM string false 0 +CONFIG.Clock_Enable_Type string false Slave_Interface_Clock_Enable +CONFIG.Clock_Type_AXI string false Common_Clock +CONFIG.Component_Name string false err_report_fifo +CONFIG.DATA_WIDTH string false 64 +CONFIG.Data_Count string false false +CONFIG.Data_Count_Width string false 11 +CONFIG.Disable_Timing_Violations string false false +CONFIG.Disable_Timing_Violations_AXI string false false +CONFIG.Dout_Reset_Value string false 0 +CONFIG.Empty_Threshold_Assert_Value string false 4 +CONFIG.Empty_Threshold_Assert_Value_axis string false 1022 +CONFIG.Empty_Threshold_Assert_Value_rach string false 1022 +CONFIG.Empty_Threshold_Assert_Value_rdch string false 1022 +CONFIG.Empty_Threshold_Assert_Value_wach string false 1022 +CONFIG.Empty_Threshold_Assert_Value_wdch string false 1022 +CONFIG.Empty_Threshold_Assert_Value_wrch string false 1022 +CONFIG.Empty_Threshold_Negate_Value string false 5 +CONFIG.Enable_Common_Overflow string false false +CONFIG.Enable_Common_Underflow string false false +CONFIG.Enable_Data_Counts_axis string false false +CONFIG.Enable_Data_Counts_rach string false false +CONFIG.Enable_Data_Counts_rdch string false false +CONFIG.Enable_Data_Counts_wach string false false +CONFIG.Enable_Data_Counts_wdch string false false +CONFIG.Enable_Data_Counts_wrch string false false +CONFIG.Enable_ECC string false false +CONFIG.Enable_ECC_Type string false Hard_ECC +CONFIG.Enable_ECC_axis string false false +CONFIG.Enable_ECC_rach string false false +CONFIG.Enable_ECC_rdch string false false +CONFIG.Enable_ECC_wach string false false +CONFIG.Enable_ECC_wdch string false false +CONFIG.Enable_ECC_wrch string false false +CONFIG.Enable_Reset_Synchronization string false true +CONFIG.Enable_Safety_Circuit string false false +CONFIG.Enable_TLAST string false false +CONFIG.Enable_TREADY string false true +CONFIG.FIFO_Application_Type_axis string false Data_FIFO +CONFIG.FIFO_Application_Type_rach string false Data_FIFO +CONFIG.FIFO_Application_Type_rdch string false Data_FIFO +CONFIG.FIFO_Application_Type_wach string false Data_FIFO +CONFIG.FIFO_Application_Type_wdch string false Data_FIFO +CONFIG.FIFO_Application_Type_wrch string false Data_FIFO +CONFIG.FIFO_Implementation_axis string false Common_Clock_Block_RAM +CONFIG.FIFO_Implementation_rach string false Common_Clock_Block_RAM +CONFIG.FIFO_Implementation_rdch string false Common_Clock_Block_RAM +CONFIG.FIFO_Implementation_wach string false Common_Clock_Block_RAM +CONFIG.FIFO_Implementation_wdch string false Common_Clock_Block_RAM +CONFIG.FIFO_Implementation_wrch string false Common_Clock_Block_RAM +CONFIG.Fifo_Implementation string false Common_Clock_Block_RAM +CONFIG.Full_Flags_Reset_Value string false 0 +CONFIG.Full_Threshold_Assert_Value string false 1023 +CONFIG.Full_Threshold_Assert_Value_axis string false 1023 +CONFIG.Full_Threshold_Assert_Value_rach string false 1023 +CONFIG.Full_Threshold_Assert_Value_rdch string false 1023 +CONFIG.Full_Threshold_Assert_Value_wach string false 1023 +CONFIG.Full_Threshold_Assert_Value_wdch string false 1023 +CONFIG.Full_Threshold_Assert_Value_wrch string false 1023 +CONFIG.Full_Threshold_Negate_Value string false 1022 +CONFIG.HAS_ACLKEN string false false +CONFIG.HAS_TKEEP string false false +CONFIG.HAS_TSTRB string false false +CONFIG.ID_WIDTH string false 0 +CONFIG.INTERFACE_TYPE string false Native +CONFIG.Inject_Dbit_Error string false false +CONFIG.Inject_Dbit_Error_axis string false false +CONFIG.Inject_Dbit_Error_rach string false false +CONFIG.Inject_Dbit_Error_rdch string false false +CONFIG.Inject_Dbit_Error_wach string false false +CONFIG.Inject_Dbit_Error_wdch string false false +CONFIG.Inject_Dbit_Error_wrch string false false +CONFIG.Inject_Sbit_Error string false false +CONFIG.Inject_Sbit_Error_axis string false false +CONFIG.Inject_Sbit_Error_rach string false false +CONFIG.Inject_Sbit_Error_rdch string false false +CONFIG.Inject_Sbit_Error_wach string false false +CONFIG.Inject_Sbit_Error_wdch string false false +CONFIG.Inject_Sbit_Error_wrch string false false +CONFIG.Input_Data_Width string false 32 +CONFIG.Input_Depth string false 1024 +CONFIG.Input_Depth_axis string false 1024 +CONFIG.Input_Depth_rach string false 16 +CONFIG.Input_Depth_rdch string false 1024 +CONFIG.Input_Depth_wach string false 16 +CONFIG.Input_Depth_wdch string false 1024 +CONFIG.Input_Depth_wrch string false 16 +CONFIG.MASTER_ACLK.FREQ_HZ string false 100000000 +CONFIG.MASTER_ACLK.INSERT_VIP string false 0 +CONFIG.M_AXI.INSERT_VIP string false 0 +CONFIG.M_AXIS.INSERT_VIP string false 0 +CONFIG.Master_interface_Clock_enable_memory_mapped string false false +CONFIG.Output_Data_Width string false 32 +CONFIG.Output_Depth string false 1024 +CONFIG.Output_Register_Type string false Embedded_Reg +CONFIG.Overflow_Flag string false false +CONFIG.Overflow_Flag_AXI string false false +CONFIG.Overflow_Sense string false Active_High +CONFIG.Overflow_Sense_AXI string false Active_High +CONFIG.PROTOCOL string false AXI4 +CONFIG.Performance_Options string false First_Word_Fall_Through +CONFIG.Programmable_Empty_Type string false No_Programmable_Empty_Threshold +CONFIG.Programmable_Empty_Type_axis string false No_Programmable_Empty_Threshold +CONFIG.Programmable_Empty_Type_rach string false No_Programmable_Empty_Threshold +CONFIG.Programmable_Empty_Type_rdch string false No_Programmable_Empty_Threshold +CONFIG.Programmable_Empty_Type_wach string false No_Programmable_Empty_Threshold +CONFIG.Programmable_Empty_Type_wdch string false No_Programmable_Empty_Threshold +CONFIG.Programmable_Empty_Type_wrch string false No_Programmable_Empty_Threshold +CONFIG.Programmable_Full_Type string false No_Programmable_Full_Threshold +CONFIG.Programmable_Full_Type_axis string false No_Programmable_Full_Threshold +CONFIG.Programmable_Full_Type_rach string false No_Programmable_Full_Threshold +CONFIG.Programmable_Full_Type_rdch string false No_Programmable_Full_Threshold +CONFIG.Programmable_Full_Type_wach string false No_Programmable_Full_Threshold +CONFIG.Programmable_Full_Type_wdch string false No_Programmable_Full_Threshold +CONFIG.Programmable_Full_Type_wrch string false No_Programmable_Full_Threshold +CONFIG.READ_CLK.FREQ_HZ string false 100000000 +CONFIG.READ_CLK.INSERT_VIP string false 0 +CONFIG.READ_WRITE_MODE string false READ_WRITE +CONFIG.RUSER_Width string false 0 +CONFIG.Read_Clock_Frequency string false 1 +CONFIG.Read_Data_Count string false false +CONFIG.Read_Data_Count_Width string false 11 +CONFIG.Register_Slice_Mode_axis string false Fully_Registered +CONFIG.Register_Slice_Mode_rach string false Fully_Registered +CONFIG.Register_Slice_Mode_rdch string false Fully_Registered +CONFIG.Register_Slice_Mode_wach string false Fully_Registered +CONFIG.Register_Slice_Mode_wdch string false Fully_Registered +CONFIG.Register_Slice_Mode_wrch string false Fully_Registered +CONFIG.Reset_Pin string false true +CONFIG.Reset_Type string false Synchronous_Reset +CONFIG.SLAVE_ACLK.FREQ_HZ string false 100000000 +CONFIG.SLAVE_ACLK.INSERT_VIP string false 0 +CONFIG.SLAVE_ARESETN.INSERT_VIP string false 0 +CONFIG.S_AXI.INSERT_VIP string false 0 +CONFIG.S_AXIS.INSERT_VIP string false 0 +CONFIG.Slave_interface_Clock_enable_memory_mapped string false false +CONFIG.TDATA_NUM_BYTES string false 1 +CONFIG.TDEST_WIDTH string false 0 +CONFIG.TID_WIDTH string false 0 +CONFIG.TKEEP_WIDTH string false 1 +CONFIG.TSTRB_WIDTH string false 1 +CONFIG.TUSER_WIDTH string false 4 +CONFIG.Underflow_Flag string false false +CONFIG.Underflow_Flag_AXI string false false +CONFIG.Underflow_Sense string false Active_High +CONFIG.Underflow_Sense_AXI string false Active_High +CONFIG.Use_Dout_Reset string false true +CONFIG.Use_Embedded_Registers string false false +CONFIG.Use_Embedded_Registers_axis string false false +CONFIG.Use_Extra_Logic string false true +CONFIG.Valid_Flag string false false +CONFIG.Valid_Sense string false Active_High +CONFIG.WRITE_CLK.FREQ_HZ string false 100000000 +CONFIG.WRITE_CLK.INSERT_VIP string false 0 +CONFIG.WUSER_Width string false 0 +CONFIG.Write_Acknowledge_Flag string false false +CONFIG.Write_Acknowledge_Sense string false Active_High +CONFIG.Write_Clock_Frequency string false 1 +CONFIG.Write_Data_Count string false false +CONFIG.Write_Data_Count_Width string false 11 +CONFIG.asymmetric_port_width string false false +CONFIG.axis_type string false FIFO +CONFIG.dynamic_power_saving string false false +CONFIG.ecc_pipeline_reg string false false +CONFIG.enable_low_latency string false false +CONFIG.enable_read_pointer_increment_by2 string false false +CONFIG.rach_type string false FIFO +CONFIG.rdch_type string false FIFO +CONFIG.synchronization_stages string false 2 +CONFIG.synchronization_stages_axi string false 2 +CONFIG.use_dout_register string false false +CONFIG.wach_type string false FIFO +CONFIG.wdch_type string false FIFO +CONFIG.wrch_type string false FIFO +IPDEF string true xilinx.com:ip:fifo_generator:13.2 diff --git a/firmware/FT0/PM/ipcore_properties/raw_data_fifo.txt b/firmware/FT0/PM/ipcore_properties/raw_data_fifo.txt index 8629119..4837ca1 100644 --- a/firmware/FT0/PM/ipcore_properties/raw_data_fifo.txt +++ b/firmware/FT0/PM/ipcore_properties/raw_data_fifo.txt @@ -4,7 +4,7 @@ CONFIG.ARUSER_Width string false 0 CONFIG.AWUSER_Width string false 0 CONFIG.Add_NGC_Constraint_AXI string false false CONFIG.Almost_Empty_Flag string false false -CONFIG.Almost_Full_Flag string false false +CONFIG.Almost_Full_Flag string false true CONFIG.BUSER_Width string false 0 CONFIG.CORE_CLK.FREQ_HZ string false 100000000 CONFIG.CORE_CLK.INSERT_VIP string false 0 @@ -60,14 +60,14 @@ CONFIG.FIFO_Implementation_wdch string false Common_Cl CONFIG.FIFO_Implementation_wrch string false Common_Clock_Block_RAM CONFIG.Fifo_Implementation string false Common_Clock_Block_RAM CONFIG.Full_Flags_Reset_Value string false 0 -CONFIG.Full_Threshold_Assert_Value string false 4095 +CONFIG.Full_Threshold_Assert_Value string false 4000 CONFIG.Full_Threshold_Assert_Value_axis string false 1023 CONFIG.Full_Threshold_Assert_Value_rach string false 1023 CONFIG.Full_Threshold_Assert_Value_rdch string false 1023 CONFIG.Full_Threshold_Assert_Value_wach string false 1023 CONFIG.Full_Threshold_Assert_Value_wdch string false 1023 CONFIG.Full_Threshold_Assert_Value_wrch string false 1023 -CONFIG.Full_Threshold_Negate_Value string false 4094 +CONFIG.Full_Threshold_Negate_Value string false 3999 CONFIG.HAS_ACLKEN string false false CONFIG.HAS_TKEEP string false false CONFIG.HAS_TSTRB string false false @@ -102,7 +102,7 @@ CONFIG.M_AXIS.INSERT_VIP string false 0 CONFIG.Master_interface_Clock_enable_memory_mapped string false false CONFIG.Output_Data_Width string false 80 CONFIG.Output_Depth string false 4096 -CONFIG.Output_Register_Type string false Embedded_Reg +CONFIG.Output_Register_Type string false Fabric_Reg CONFIG.Overflow_Flag string false false CONFIG.Overflow_Flag_AXI string false false CONFIG.Overflow_Sense string false Active_High @@ -116,7 +116,7 @@ CONFIG.Programmable_Empty_Type_rdch string false No_Progra CONFIG.Programmable_Empty_Type_wach string false No_Programmable_Empty_Threshold CONFIG.Programmable_Empty_Type_wdch string false No_Programmable_Empty_Threshold CONFIG.Programmable_Empty_Type_wrch string false No_Programmable_Empty_Threshold -CONFIG.Programmable_Full_Type string false No_Programmable_Full_Threshold +CONFIG.Programmable_Full_Type string false Single_Programmable_Full_Threshold_Constant CONFIG.Programmable_Full_Type_axis string false No_Programmable_Full_Threshold CONFIG.Programmable_Full_Type_rach string false No_Programmable_Full_Threshold CONFIG.Programmable_Full_Type_rdch string false No_Programmable_Full_Threshold @@ -155,7 +155,7 @@ CONFIG.Underflow_Flag_AXI string false false CONFIG.Underflow_Sense string false Active_High CONFIG.Underflow_Sense_AXI string false Active_High CONFIG.Use_Dout_Reset string false true -CONFIG.Use_Embedded_Registers string false false +CONFIG.Use_Embedded_Registers string false true CONFIG.Use_Embedded_Registers_axis string false false CONFIG.Use_Extra_Logic string false true CONFIG.Valid_Flag string false false diff --git a/firmware/FT0/PM/ipcore_properties/slct_data_fifo.txt b/firmware/FT0/PM/ipcore_properties/slct_data_fifo.txt index 52b27f5..556b30a 100644 --- a/firmware/FT0/PM/ipcore_properties/slct_data_fifo.txt +++ b/firmware/FT0/PM/ipcore_properties/slct_data_fifo.txt @@ -14,7 +14,7 @@ CONFIG.Clock_Type_AXI string false Common_Cl CONFIG.Component_Name string false slct_data_fifo CONFIG.DATA_WIDTH string false 64 CONFIG.Data_Count string false false -CONFIG.Data_Count_Width string false 12 +CONFIG.Data_Count_Width string false 14 CONFIG.Disable_Timing_Violations string false false CONFIG.Disable_Timing_Violations_AXI string false false CONFIG.Dout_Reset_Value string false 0 @@ -60,14 +60,14 @@ CONFIG.FIFO_Implementation_wdch string false Common_Cl CONFIG.FIFO_Implementation_wrch string false Common_Clock_Block_RAM CONFIG.Fifo_Implementation string false Independent_Clocks_Block_RAM CONFIG.Full_Flags_Reset_Value string false 1 -CONFIG.Full_Threshold_Assert_Value string false 4095 +CONFIG.Full_Threshold_Assert_Value string false 16000 CONFIG.Full_Threshold_Assert_Value_axis string false 1023 CONFIG.Full_Threshold_Assert_Value_rach string false 1023 CONFIG.Full_Threshold_Assert_Value_rdch string false 1023 CONFIG.Full_Threshold_Assert_Value_wach string false 1023 CONFIG.Full_Threshold_Assert_Value_wdch string false 1023 CONFIG.Full_Threshold_Assert_Value_wrch string false 1023 -CONFIG.Full_Threshold_Negate_Value string false 4094 +CONFIG.Full_Threshold_Negate_Value string false 15999 CONFIG.HAS_ACLKEN string false false CONFIG.HAS_TKEEP string false false CONFIG.HAS_TSTRB string false false @@ -88,7 +88,7 @@ CONFIG.Inject_Sbit_Error_wach string false false CONFIG.Inject_Sbit_Error_wdch string false false CONFIG.Inject_Sbit_Error_wrch string false false CONFIG.Input_Data_Width string false 80 -CONFIG.Input_Depth string false 4096 +CONFIG.Input_Depth string false 16384 CONFIG.Input_Depth_axis string false 1024 CONFIG.Input_Depth_rach string false 16 CONFIG.Input_Depth_rdch string false 1024 @@ -101,8 +101,8 @@ CONFIG.M_AXI.INSERT_VIP string false 0 CONFIG.M_AXIS.INSERT_VIP string false 0 CONFIG.Master_interface_Clock_enable_memory_mapped string false false CONFIG.Output_Data_Width string false 80 -CONFIG.Output_Depth string false 4096 -CONFIG.Output_Register_Type string false Embedded_Reg +CONFIG.Output_Depth string false 16384 +CONFIG.Output_Register_Type string false Fabric_Reg CONFIG.Overflow_Flag string false false CONFIG.Overflow_Flag_AXI string false false CONFIG.Overflow_Sense string false Active_High @@ -116,7 +116,7 @@ CONFIG.Programmable_Empty_Type_rdch string false No_Progra CONFIG.Programmable_Empty_Type_wach string false No_Programmable_Empty_Threshold CONFIG.Programmable_Empty_Type_wdch string false No_Programmable_Empty_Threshold CONFIG.Programmable_Empty_Type_wrch string false No_Programmable_Empty_Threshold -CONFIG.Programmable_Full_Type string false No_Programmable_Full_Threshold +CONFIG.Programmable_Full_Type string false Single_Programmable_Full_Threshold_Constant CONFIG.Programmable_Full_Type_axis string false No_Programmable_Full_Threshold CONFIG.Programmable_Full_Type_rach string false No_Programmable_Full_Threshold CONFIG.Programmable_Full_Type_rdch string false No_Programmable_Full_Threshold @@ -129,7 +129,7 @@ CONFIG.READ_WRITE_MODE string false READ_WRIT CONFIG.RUSER_Width string false 0 CONFIG.Read_Clock_Frequency string false 1 CONFIG.Read_Data_Count string false true -CONFIG.Read_Data_Count_Width string false 13 +CONFIG.Read_Data_Count_Width string false 15 CONFIG.Register_Slice_Mode_axis string false Fully_Registered CONFIG.Register_Slice_Mode_rach string false Fully_Registered CONFIG.Register_Slice_Mode_rdch string false Fully_Registered @@ -155,7 +155,7 @@ CONFIG.Underflow_Flag_AXI string false false CONFIG.Underflow_Sense string false Active_High CONFIG.Underflow_Sense_AXI string false Active_High CONFIG.Use_Dout_Reset string false true -CONFIG.Use_Embedded_Registers string false false +CONFIG.Use_Embedded_Registers string false true CONFIG.Use_Embedded_Registers_axis string false false CONFIG.Use_Extra_Logic string false true CONFIG.Valid_Flag string false false @@ -167,7 +167,7 @@ CONFIG.Write_Acknowledge_Flag string false false CONFIG.Write_Acknowledge_Sense string false Active_High CONFIG.Write_Clock_Frequency string false 1 CONFIG.Write_Data_Count string false true -CONFIG.Write_Data_Count_Width string false 13 +CONFIG.Write_Data_Count_Width string false 15 CONFIG.asymmetric_port_width string false false CONFIG.axis_type string false FIFO CONFIG.dynamic_power_saving string false false diff --git a/firmware/FT0/PM/ipcore_properties/trg_fifo_comp.txt b/firmware/FT0/PM/ipcore_properties/trg_fifo_comp.txt index b59b93e..ba10aac 100644 --- a/firmware/FT0/PM/ipcore_properties/trg_fifo_comp.txt +++ b/firmware/FT0/PM/ipcore_properties/trg_fifo_comp.txt @@ -14,7 +14,7 @@ CONFIG.Clock_Type_AXI string false Common_Cl CONFIG.Component_Name string false trg_fifo_comp CONFIG.DATA_WIDTH string false 64 CONFIG.Data_Count string false false -CONFIG.Data_Count_Width string false 9 +CONFIG.Data_Count_Width string false 12 CONFIG.Disable_Timing_Violations string false false CONFIG.Disable_Timing_Violations_AXI string false false CONFIG.Dout_Reset_Value string false 0 @@ -60,14 +60,14 @@ CONFIG.FIFO_Implementation_wdch string false Common_Cl CONFIG.FIFO_Implementation_wrch string false Common_Clock_Block_RAM CONFIG.Fifo_Implementation string false Independent_Clocks_Block_RAM CONFIG.Full_Flags_Reset_Value string false 1 -CONFIG.Full_Threshold_Assert_Value string false 511 +CONFIG.Full_Threshold_Assert_Value string false 4095 CONFIG.Full_Threshold_Assert_Value_axis string false 1023 CONFIG.Full_Threshold_Assert_Value_rach string false 1023 CONFIG.Full_Threshold_Assert_Value_rdch string false 1023 CONFIG.Full_Threshold_Assert_Value_wach string false 1023 CONFIG.Full_Threshold_Assert_Value_wdch string false 1023 CONFIG.Full_Threshold_Assert_Value_wrch string false 1023 -CONFIG.Full_Threshold_Negate_Value string false 510 +CONFIG.Full_Threshold_Negate_Value string false 4094 CONFIG.HAS_ACLKEN string false false CONFIG.HAS_TKEEP string false false CONFIG.HAS_TSTRB string false false @@ -88,7 +88,7 @@ CONFIG.Inject_Sbit_Error_wach string false false CONFIG.Inject_Sbit_Error_wdch string false false CONFIG.Inject_Sbit_Error_wrch string false false CONFIG.Input_Data_Width string false 76 -CONFIG.Input_Depth string false 512 +CONFIG.Input_Depth string false 4096 CONFIG.Input_Depth_axis string false 1024 CONFIG.Input_Depth_rach string false 16 CONFIG.Input_Depth_rdch string false 1024 @@ -101,8 +101,8 @@ CONFIG.M_AXI.INSERT_VIP string false 0 CONFIG.M_AXIS.INSERT_VIP string false 0 CONFIG.Master_interface_Clock_enable_memory_mapped string false false CONFIG.Output_Data_Width string false 76 -CONFIG.Output_Depth string false 512 -CONFIG.Output_Register_Type string false Embedded_Reg +CONFIG.Output_Depth string false 4096 +CONFIG.Output_Register_Type string false Fabric_Reg CONFIG.Overflow_Flag string false false CONFIG.Overflow_Flag_AXI string false false CONFIG.Overflow_Sense string false Active_High @@ -129,7 +129,7 @@ CONFIG.READ_WRITE_MODE string false READ_WRIT CONFIG.RUSER_Width string false 0 CONFIG.Read_Clock_Frequency string false 1 CONFIG.Read_Data_Count string false true -CONFIG.Read_Data_Count_Width string false 10 +CONFIG.Read_Data_Count_Width string false 12 CONFIG.Register_Slice_Mode_axis string false Fully_Registered CONFIG.Register_Slice_Mode_rach string false Fully_Registered CONFIG.Register_Slice_Mode_rdch string false Fully_Registered @@ -155,9 +155,9 @@ CONFIG.Underflow_Flag_AXI string false false CONFIG.Underflow_Sense string false Active_High CONFIG.Underflow_Sense_AXI string false Active_High CONFIG.Use_Dout_Reset string false true -CONFIG.Use_Embedded_Registers string false false +CONFIG.Use_Embedded_Registers string false true CONFIG.Use_Embedded_Registers_axis string false false -CONFIG.Use_Extra_Logic string false true +CONFIG.Use_Extra_Logic string false false CONFIG.Valid_Flag string false false CONFIG.Valid_Sense string false Active_High CONFIG.WRITE_CLK.FREQ_HZ string false 100000000 @@ -167,7 +167,7 @@ CONFIG.Write_Acknowledge_Flag string false false CONFIG.Write_Acknowledge_Sense string false Active_High CONFIG.Write_Clock_Frequency string false 1 CONFIG.Write_Data_Count string false true -CONFIG.Write_Data_Count_Width string false 10 +CONFIG.Write_Data_Count_Width string false 12 CONFIG.asymmetric_port_width string false false CONFIG.axis_type string false FIFO CONFIG.dynamic_power_saving string false false diff --git a/firmware/FT0/PM/make.tcl b/firmware/FT0/PM/make.tcl index ba7982a..b6e6cdc 100644 --- a/firmware/FT0/PM/make.tcl +++ b/firmware/FT0/PM/make.tcl @@ -20,7 +20,7 @@ if { [info exists ::origin_dir_loc] } { } # Set the project name -set project_name "PM" +set project_name "PM12" # Use project name variable, if specified in the tcl shell if { [info exists ::user_project_name] } { @@ -78,7 +78,7 @@ if { $::argc > 0 } { # Set the directory path for the original project from where this script was exported set orig_proj_dir "[file normalize "$origin_dir/build"]" -if {[string equal [open_project -quiet "build/PM.xpr"] ""]} { +if {[string equal [open_project -quiet "build/PM12.xpr"] ""]} { set proj_create "yes" puts ${proj_create} puts ${project_name} @@ -186,21 +186,21 @@ set files [list \ [file normalize "${origin_dir}/../../common/gbt-fpga/hdl/gbt_bank/xilinx_k7v7/mgt/mgt_ip_vhd/xlx_k7v7_mgt_ip_tx_startup_fsm.vhd" ]\ [file normalize "${origin_dir}/../../common/gbt-fpga/hdl/gbt_bank/xilinx_k7v7/gbt_tx/xlx_k7v7_gbt_tx_gearbox_std_dpram.vhd" ]\ [file normalize "${origin_dir}/../../common/gbt-readout/hdl/GBT_TXRX5.vhd"] \ - [file normalize "${origin_dir}/../../common/gbt-readout/hdl/DataCLK_strobe.vhd" ]\ [file normalize "${origin_dir}/../../common/gbt-readout/hdl/DataConverter_PM.vhd" ]\ - [file normalize "${origin_dir}/../../common/gbt-readout/hdl/RX_Data_Decoder.vhd" ]\ - [file normalize "${origin_dir}/../../common/gbt-readout/hdl/BC_counter.vhd" ]\ + [file normalize "${origin_dir}/../../common/gbt-readout/hdl/ltu_rx_decoder.vhd" ]\ + [file normalize "${origin_dir}/../../common/gbt-readout/hdl/bc_indicator.vhd" ]\ [file normalize "${origin_dir}/../../common/gbt-readout/hdl/Reset_Generator.vhd" ]\ [file normalize "${origin_dir}/../../common/gbt-readout/hdl/fit_gbt_boardPM_package.vhd" ]\ [file normalize "${origin_dir}/../../common/gbt-readout/hdl/FIT_GBT_project.vhd" ]\ [file normalize "${origin_dir}/../../common/gbt-readout/hdl/Module_Data_Gen_PM.vhd" ]\ - [file normalize "${origin_dir}/../../common/gbt-readout/hdl/CRU_ORBC_Gen.vhd" ]\ + [file normalize "${origin_dir}/../../common/gbt-readout/hdl/cru_ltu_emu.vhd" ]\ [file normalize "${origin_dir}/../../common/gbt-readout/hdl/TX_Data_Gen.vhd" ]\ [file normalize "${origin_dir}/../../common/gbt-readout/hdl/Event_selector.vhd" ]\ [file normalize "${origin_dir}/../../common/gbt-readout/hdl/fit_gbt_common_package.vhd" ]\ [file normalize "${origin_dir}/../../common/gbt-readout/hdl/RXDataClkSync.vhd" ]\ [file normalize "${origin_dir}/../../common/gbt-readout/hdl/CRU_packet_Builder.vhd" ]\ - [file normalize "${origin_dir}/../../common/gbt-readout/hdl/Data_Packager.vhd" ]\ + [file normalize "${origin_dir}/../../common/gbt-readout/hdl/snapshot_fifo.vhd" ]\ + [file normalize "${origin_dir}/../../common/gbt-readout/hdl/error_report.vhd" ]\ ] add_files -norecurse -fileset sources_1 $files @@ -219,7 +219,7 @@ if {[string equal $proj_create "yes"]} { # Set 'sources_1' fileset properties set_property \ -dict [list \ - "top" "PM"\ + "top" "PM12"\ "edif_extra_search_paths" "D:/proj/PM/ipcore_dir"] \ [get_filesets sources_1] @@ -233,6 +233,7 @@ if {[string equal $proj_create "yes"]} { [file normalize "$origin_dir/xdc/Timing.xdc"]\ [file normalize "$origin_dir/xdc/fit.xdc"]\ [file normalize "$origin_dir/xdc/ios.xdc"]\ + [file normalize "$origin_dir/xdc/chipscope.xdc"]\ ] add_files -fileset constrs_1 ${constr_files} @@ -250,7 +251,7 @@ if {[string equal $proj_create "yes"]} { # Set 'constrs_1' fileset properties set obj [get_filesets constrs_1] - set_property -name "target_constrs_file" -value "[get_files *xdc/ios.xdc]" -objects $obj + set_property -name "target_constrs_file" -value "[get_files *xdc/chipscope.xdc]" -objects $obj } @@ -339,6 +340,11 @@ set_property -name "steps.synth_design.args.shreg_min_size" -value "5" -objects # set the current synth run current_run -synthesis [get_runs synth_1] +#launch_runs synth_1 +#wait_on_run synth_1 +#open_run synth_1 +#report_timing_summary -file synth_1_timing_summary.log + # Create 'impl_1' run (if not found) if {[string equal [get_runs -quiet impl_1] ""]} { @@ -378,7 +384,7 @@ gen_report impl_1_post_route_phys_opt_report_bus_skew_0 report_bus_skew:1.1 post set obj [get_runs impl_1] set_property -name "part" -value ${part} -objects $obj set_property -name "strategy" -value "Performance_NetDelay_low" -objects $obj -set_property -name "steps.opt_design.args.directive" -value "Explore" -objects $obj +set_property -name "steps.opt_design.args.directive" -value "ExploreWithRemap" -objects $obj set_property -name "steps.place_design.args.directive" -value "ExtraNetDelay_low" -objects $obj set_property -name "steps.phys_opt_design.is_enabled" -value "1" -objects $obj set_property -name "steps.phys_opt_design.args.directive" -value "AggressiveExplore" -objects $obj @@ -396,3 +402,6 @@ update_compile_order -fileset sources_1 reset_run -quiet synth_1 launch_runs impl_1 -to_step write_bitstream -jobs 7 wait_on_run impl_1 + +open_run impl_1 +report_timing_summary -file impl_1_timing_summary.log diff --git a/firmware/FT0/PM/xdc/Timing.xdc b/firmware/FT0/PM/xdc/Timing.xdc index 3da8154..83dc80e 100644 --- a/firmware/FT0/PM/xdc/Timing.xdc +++ b/firmware/FT0/PM/xdc/Timing.xdc @@ -1,12 +1,20 @@ -set_multicycle_path -setup -start -from [get_clocks CLK600_1] -to [get_cells {{BC_PER1_reg[?]} {TDC1_CH?/C_PER_reg[?]} }] 2 -set_multicycle_path -hold -start -from [get_clocks CLK600_1] -to [get_cells {{BC_PER1_reg[?]} {TDC1_CH?/C_PER_reg[?]} }] 1 -set_multicycle_path -setup -start -from [get_clocks CLK600_2] -to [get_cells {{BC_PER2_reg[?]} {TDC2_CH?/C_PER_reg[?]} }] 2 -set_multicycle_path -hold -start -from [get_clocks CLK600_2] -to [get_cells {{BC_PER2_reg[?]} {TDC2_CH?/C_PER_reg[?]} }] 1 -set_multicycle_path -setup -start -from [get_clocks CLK600_3] -to [get_cells {{BC_PER3_reg[?]} {TDC3_CH?/C_PER_reg[?]} }] 2 -set_multicycle_path -hold -start -from [get_clocks CLK600_3] -to [get_cells {{BC_PER3_reg[?]} {TDC3_CH?/C_PER_reg[?]} }] 1 +set_multicycle_path -setup -start -from [get_clocks CLK600_1] -to [get_cells {{BC_PER1_reg[?]} {TDC1_CH?/C_PER_reg[?]} {TDC1_CH?/C_STR1_reg} BC_STR11_reg}] 2 +set_multicycle_path -hold -start -from [get_clocks CLK600_1] -to [get_cells {{BC_PER1_reg[?]} {TDC1_CH?/C_PER_reg[?]} {TDC1_CH?/C_STR1_reg} BC_STR11_reg }] 1 +set_multicycle_path -setup -start -from [get_clocks CLK600_2] -to [get_cells {{BC_PER2_reg[?]} {TDC2_CH?/C_PER_reg[?]} {TDC2_CH?/C_STR1_reg} BC_STR21_reg }] 2 +set_multicycle_path -hold -start -from [get_clocks CLK600_2] -to [get_cells {{BC_PER2_reg[?]} {TDC2_CH?/C_PER_reg[?]} {TDC2_CH?/C_STR1_reg} BC_STR21_reg }] 1 +set_multicycle_path -setup -start -from [get_clocks CLK600_3] -to [get_cells {{BC_PER3_reg[?]} {TDC3_CH?/C_PER_reg[?]} {TDC3_CH?/C_STR1_reg} BC_STR31_reg }] 2 +set_multicycle_path -hold -start -from [get_clocks CLK600_3] -to [get_cells {{BC_PER3_reg[?]} {TDC3_CH?/C_PER_reg[?]} {TDC3_CH?/C_STR1_reg} BC_STR31_reg }] 1 set_max_delay -datapath_only -from [get_clocks CLK320] -to [get_ports {TT* AT*}] 1.800 +#set_multicycle_path -setup -from [get_pins {af1/m0_reg[?]/C af1/ml_reg[?]/C}] -to [get_cells {af1/ml_reg[?]}] 2 +#set_multicycle_path -hold -from [get_pins {af1/m0_reg[?]/C af1/ml_reg[?]/C}] -to [get_cells {af1/ml_reg[?]}] 1 +#set_multicycle_path -setup -from [get_pins {af2/m0_reg[?]/C af2/ml_reg[?]/C}] -to [get_cells {af2/ml_reg[?]}] 2 +#set_multicycle_path -hold -from [get_pins {af2/m0_reg[?]/C af2/ml_reg[?]/C}] -to [get_cells {af2/ml_reg[?]}] 1 +#set_multicycle_path -setup -from [get_pins {af3/m0_reg[?]/C af3/ml_reg[?]/C}] -to [get_cells {af3/ml_reg[?]}] 2 +#set_multicycle_path -hold -from [get_pins {af3/m0_reg[?]/C af3/ml_reg[?]/C}] -to [get_cells {af3/ml_reg[?}}] 1 + + set_max_delay -datapath_only -from [get_clocks {TDCCLK1 CLK300_1}] -to [get_cells {TDC1_CH?/tdc_raw_i_reg[*]}] 3.000 set_max_delay -datapath_only -from [get_clocks {TDCCLK2 CLK300_2}] -to [get_cells {TDC2_CH?/tdc_raw_i_reg[*]}] 3.000 set_max_delay -datapath_only -from [get_clocks {TDCCLK3 CLK300_3}] -to [get_cells {TDC3_CH?/tdc_raw_i_reg[*]}] 3.000 @@ -52,14 +60,20 @@ set_false_path -to [get_pins all_locked_reg/D] set_multicycle_path -setup -from [get_clocks CLK320] -through [get_cells CHANNEL??/Ampl_corr] 2 set_multicycle_path -hold -from [get_clocks CLK320] -through [get_cells CHANNEL??/Ampl_corr] 1 + +set_multicycle_path -setup -from [get_clocks TX_CLK] -to [get_cells {BC_cou_reg[*] Orbit_ID_reg[*] TR_to_reg[*]}] 2 +set_multicycle_path -hold -end -from [get_clocks TX_CLK] -to [get_cells {BC_cou_reg[*] Orbit_ID_reg[*] TR_to_reg[*]}] 1 + #set_multicycle_path -setup -from [get_cells {CHANNEL??/CH_0_reg[*]}] -to [get_cells {{CHANNEL??/CH_R0_reg[*]} {CHANNEL??/CH_R1_reg[*]}}] 2 #set_multicycle_path -hold -from [get_cells {CHANNEL??/CH_0_reg[*]}] -to [get_cells {{CHANNEL??/CH_R0_reg[*]} {CHANNEL??/CH_R1_reg[*]}}] 1 -set_false_path -from [get_cells {{CH*_shift_reg[*]} {CH*_rc_reg[*]} {ampl_sat_reg[*]} {gate_time_high_reg[*]} {chans_ena_r_reg[*]}}] -to [get_clocks CLK320] +set_false_path -from [get_cells {{CH*_shift_reg[*]} {CH*_rc_reg[*]} {ampl_sat_reg[*]} {ampl_low_reg[*]} {gate_time_high_reg[*]} {chans_ena_r_reg[*]} {trig_dis_reg[*]} chans_block_reg fdd_reg}] -to [get_clocks CLK320] set_false_path -from [get_cells ipbus_control_reg_reg[*][*]] #set_max_delay -datapath_only -from [get_clocks RXDataCLK] -to [get_pins IsRXData0_reg/D] 5.000 -set_false_path -from [get_clocks RXDataCLK] -to [get_cells {FitGbtPrg/gbt_bank_gen.gbtBankDsgn/GBT_Status_O_reg[gbtRx_ErrorDet] FitGbtPrg/gbt_bank_gen.gbtBankDsgn/GBT_Status_O_reg[gbtRx_Ready] IsRXData0_reg}] +set_false_path -from [get_clocks RXDataCLK] -to [get_cells {FitGbtPrg/gbt_bank_gen.gbtBankDsgn/gbtRx_ErrorDet_ff_reg FitGbtPrg/gbt_bank_gen.gbtBankDsgn/GBT_Status_O_reg[*] IsRXData0_reg}] +set_false_path -from [get_clocks RXDataCLK] -to [get_cells {FitGbtPrg/gbt_bank_gen.gbtBankDsgn/gbtRx_ErrorDet_ff_reg FitGbtPrg/gbt_bank_gen.gbtBankDsgn/gbtRx_ErrorDet_ff*}] +set_false_path -from [get_clocks RXDataCLK] -to [get_cells {FitGbtPrg/gbt_bank_gen.gbtBankDsgn/gbtRx_ErrorDet_ff_reg FitGbtPrg/gbt_bank_gen.gbtBankDsgn/Rx_Ready_ff*}] @@ -90,30 +104,91 @@ set_multicycle_path -hold -start -from [get_clocks RxWordCLK] -to [get_cells {Fi # GBT readout ##################################################################### +# TOP +set_multicycle_path 8 -setup -from [get_clocks TX_CLK] -to [get_pins {gbt_global_status_reg[*]/D}] +set_multicycle_path 7 -hold -end -from [get_clocks TX_CLK] -to [get_pins {gbt_global_status_reg[*]/D}] +set_multicycle_path 8 -setup -from [get_clocks TX_CLK] -to [get_pins {rx_phase_status_reg[*]/D}] +set_multicycle_path 7 -hold -end -from [get_clocks TX_CLK] -to [get_pins {rx_phase_status_reg[*]/D}] + +# Reset_Generator ---------------------------------- +set_multicycle_path 8 -setup -from [get_clocks TX_CLK] -to [get_pins FitGbtPrg/Reset_Generator_comp/reset_sclk_reg/D] +set_multicycle_path 7 -hold -end -from [get_clocks TX_CLK] -to [get_pins FitGbtPrg/Reset_Generator_comp/reset_sclk_reg/D] +set_multicycle_path 8 -setup -from [get_clocks TX_CLK] -to [get_pins FitGbtPrg/Reset_Generator_comp/DataClk_qff00_sysclk_reg/D] +set_multicycle_path 7 -hold -end -from [get_clocks TX_CLK] -to [get_pins FitGbtPrg/Reset_Generator_comp/DataClk_qff00_sysclk_reg/D] +set_false_path -from [get_clocks TX_CLK] -to [get_pins {FitGbtPrg/Reset_Generator_comp/Reset_SClk_O*/D}] +set_false_path -from [get_clocks TX_CLK] -to [get_pins {FitGbtPrg/Reset_Generator_comp/count_ready_reg*/D}] + +# RXDATA_CLKSync ---------------------------------- +set_max_delay -datapath_only -from [get_clocks RXDataCLK] -to [get_cells {FitGbtPrg/RxData_ClkSync_comp/RX_DATA_sysclk_reg[*]}] 3.000 +set_max_delay -datapath_only -from [get_clocks RXDataCLK] -to [get_cells {FitGbtPrg/RxData_ClkSync_comp/RX_IS_DATA_sysclk_reg*}] 3.000 +set_max_delay -datapath_only -from [get_clocks RXDataCLK] -to [get_cells FitGbtPrg/RxData_ClkSync_comp/RX_CLK_from00_reg] 2.000 -#set_false_path -from [get_cells ipbus_control_reg_reg[*][*]] -to [all_registers] +set_multicycle_path 8 -setup -from [get_clocks TX_CLK] -to [get_pins FitGbtPrg/RxData_ClkSync_comp/rx_error_reset_sclk_reg/D] +set_multicycle_path 7 -hold -end -from [get_clocks TX_CLK] -to [get_pins FitGbtPrg/RxData_ClkSync_comp/rx_error_reset_sclk_reg/D] + + +# Module_Data_Gen ---------------------------------- +set_multicycle_path 8 -setup -from [get_clocks TX_CLK] -to [get_pins FitGbtPrg/Module_Data_Gen_comp/using_generator_sc_reg/D] +set_multicycle_path 7 -hold -end -from [get_clocks TX_CLK] -to [get_pins FitGbtPrg/Module_Data_Gen_comp/using_generator_sc_reg/D] +set_multicycle_path 8 -setup -from [get_clocks TX_CLK] -to [get_pins FitGbtPrg/Module_Data_Gen_comp/event_orbit_sc_reg[*]/D] +set_multicycle_path 7 -hold -end -from [get_clocks TX_CLK] -to [get_pins FitGbtPrg/Module_Data_Gen_comp/event_orbit_sc_reg[*]/D] +set_multicycle_path 8 -setup -from [get_clocks TX_CLK] -to [get_pins FitGbtPrg/Module_Data_Gen_comp/event_bc_sc_reg[*]/D] +set_multicycle_path 7 -hold -end -from [get_clocks TX_CLK] -to [get_pins FitGbtPrg/Module_Data_Gen_comp/event_bc_sc_reg[*]/D] +set_multicycle_path 8 -setup -from [get_clocks TX_CLK] -to [get_pins FitGbtPrg/Module_Data_Gen_comp/event_rx_ph_err_reg/D] +set_multicycle_path 7 -hold -end -from [get_clocks TX_CLK] -to [get_pins FitGbtPrg/Module_Data_Gen_comp/event_rx_ph_err_reg/D] +set_multicycle_path 8 -setup -from [get_clocks TX_CLK] -to [get_pins FitGbtPrg/Module_Data_Gen_comp/event_rx_ph_reg[*]/D] +set_multicycle_path 7 -hold -end -from [get_clocks TX_CLK] -to [get_pins FitGbtPrg/Module_Data_Gen_comp/event_rx_ph_reg[*]/D] + +# Module_Data_Gen ---------------------------------- +set_multicycle_path 8 -setup -from [get_clocks TX_CLK] -to [get_pins FitGbtPrg/Event_Selector_comp/curr_orbit_sc_reg[*]/D] +set_multicycle_path 7 -hold -end -from [get_clocks TX_CLK] -to [get_pins FitGbtPrg/Event_Selector_comp/curr_orbit_sc_reg[*]/D] +set_multicycle_path 8 -setup -from [get_clocks TX_CLK] -to [get_pins FitGbtPrg/Event_Selector_comp/curr_bc_sc_reg[*]/D] +set_multicycle_path 7 -hold -end -from [get_clocks TX_CLK] -to [get_pins FitGbtPrg/Event_Selector_comp/curr_bc_sc_reg[*]/D] +set_multicycle_path 8 -setup -from [get_clocks TX_CLK] -to [get_pins FitGbtPrg/Event_Selector_comp/data_enabled_sc_reg/D] +set_multicycle_path 7 -hold -end -from [get_clocks TX_CLK] -to [get_pins FitGbtPrg/Event_Selector_comp/data_enabled_sc_reg/D] +set_multicycle_path 8 -setup -from [get_clocks TX_CLK] -to [get_pins FitGbtPrg/Event_Selector_comp/is_readout_sc_reg/D] +set_multicycle_path 7 -hold -end -from [get_clocks TX_CLK] -to [get_pins FitGbtPrg/Event_Selector_comp/is_readout_sc_reg/D] +set_multicycle_path 8 -setup -from [get_clocks TX_CLK] -to [get_pins FitGbtPrg/Event_Selector_comp/is_readout_ff3_sc_reg/D] +set_multicycle_path 7 -hold -end -from [get_clocks TX_CLK] -to [get_pins FitGbtPrg/Event_Selector_comp/is_readout_ff3_sc_reg/D] +set_multicycle_path 8 -setup -from [get_clocks TX_CLK] -to [get_pins FitGbtPrg/Event_Selector_comp/start_of_run_reg/D] +set_multicycle_path 7 -hold -end -from [get_clocks TX_CLK] -to [get_pins FitGbtPrg/Event_Selector_comp/start_of_run_reg/D] +set_multicycle_path 8 -setup -from [get_clocks TX_CLK] -to [get_pins FitGbtPrg/Event_Selector_comp/trigger_select_val_sc_reg[*]/D] +set_multicycle_path 7 -hold -end -from [get_clocks TX_CLK] -to [get_pins FitGbtPrg/Event_Selector_comp/trigger_select_val_sc_reg[*]/D] +set_multicycle_path 8 -setup -from [get_clocks TX_CLK] -to [get_pins FitGbtPrg/Event_Selector_comp/reset_dt_counters_sc_reg/D] +set_multicycle_path 7 -hold -end -from [get_clocks TX_CLK] -to [get_pins FitGbtPrg/Event_Selector_comp/reset_dt_counters_sc_reg/D] +set_multicycle_path 8 -setup -from [get_clocks TX_CLK] -to [get_pins FitGbtPrg/Event_Selector_comp/hb_rdh_response_reg/D] +set_multicycle_path 7 -hold -end -from [get_clocks TX_CLK] -to [get_pins FitGbtPrg/Event_Selector_comp/hb_rdh_response_reg/D] +set_multicycle_path 8 -setup -from [get_clocks TX_CLK] -to [get_pins FitGbtPrg/Event_Selector_comp/start_of_run_reg/D] +set_multicycle_path 7 -hold -end -from [get_clocks TX_CLK] -to [get_pins FitGbtPrg/Event_Selector_comp/start_of_run_reg/D] +set_multicycle_path 8 -setup -from [get_clocks TX_CLK] -to [get_pins FitGbtPrg/Event_Selector_comp/readout_bypass_reg/D] +set_multicycle_path 7 -hold -end -from [get_clocks TX_CLK] -to [get_pins FitGbtPrg/Event_Selector_comp/readout_bypass_reg/D] +set_multicycle_path 8 -setup -from [get_clocks TX_CLK] -to [get_pins FitGbtPrg/Event_Selector_comp/hb_reject_reg/D] +set_multicycle_path 7 -hold -end -from [get_clocks TX_CLK] -to [get_pins FitGbtPrg/Event_Selector_comp/hb_reject_reg/D] + +# bc_indicator ---------------------------------- +set_multicycle_path 8 -setup -from [get_clocks TX_CLK] -to [get_pins FitGbtPrg/bc_indicator_data_comp/reset_reg/D] +set_multicycle_path 7 -hold -end -from [get_clocks TX_CLK] -to [get_pins FitGbtPrg/bc_indicator_data_comp/reset_reg/D] + +# DataConverter ---------------------------------- +set_multicycle_path 8 -setup -from [get_clocks TX_CLK] -to [get_pins FitGbtPrg/DataConverter_comp/reset_drop_counters_reg/D] +set_multicycle_path 7 -hold -end -from [get_clocks TX_CLK] -to [get_pins FitGbtPrg/DataConverter_comp/reset_drop_counters_reg/D] +set_multicycle_path 8 -setup -from [get_clocks TX_CLK] -to [get_pins FitGbtPrg/DataConverter_comp/start_of_run_reg/D] +set_multicycle_path 7 -hold -end -from [get_clocks TX_CLK] -to [get_pins FitGbtPrg/DataConverter_comp/start_of_run_reg/D] +set_multicycle_path 8 -setup -from [get_clocks TX_CLK] -to [get_pins FitGbtPrg/DataConverter_comp/readout_bypass_reg/D] +set_multicycle_path 7 -hold -end -from [get_clocks TX_CLK] -to [get_pins FitGbtPrg/DataConverter_comp/readout_bypass_reg/D] +set_multicycle_path 8 -setup -from [get_clocks TX_CLK] -to [get_pins FitGbtPrg/DataConverter_comp/data_enabled_sclk_reg/D] +set_multicycle_path 7 -hold -end -from [get_clocks TX_CLK] -to [get_pins FitGbtPrg/DataConverter_comp/data_enabled_sclk_reg/D] + +# Error report ---------------------------------- +#set_false_path -from [get_clocks TX_CLK] -to [get_pins {FitGbtPrg/Reset_Generator_comp/Reset_SClk_O*/D}] +#set_false_path -from [get_clocks TX_CLK] -to [get_pins {FitGbtPrg/Reset_Generator_comp/count_ready_reg*/D}] -# Reset generator multipath ------------------------------------- -#set_false_path -from [get_cells FitGbtPrg/Reset_Generator_comp/GenRes_DataClk_ff1_reg] -#set_multicycle_path -setup -from [get_cells {FitGbtPrg/Data_Packager_comp/Event_Selector_comp/fromcru_dec_orbit_ff_reg[*]}] -to [get_cells FitGbtPrg/Data_Packager_comp/Event_Selector_comp/is_sending_packet_ff_reg] 7 -#set_multicycle_path -hold -end -from [get_cells {FitGbtPrg/Data_Packager_comp/Event_Selector_comp/fromcru_dec_orbit_ff_reg[*]}] -to [get_cells FitGbtPrg/Data_Packager_comp/Event_Selector_comp/is_sending_packet_ff_reg] 6 -# RX Sync comp ------------------------------------- -set_max_delay -datapath_only -from [get_clocks RXDataCLK] -to [get_cells {FitGbtPrg/RxData_ClkSync_comp/RX_DATA_DATACLK_reg[*]}] 3.000 -set_max_delay -datapath_only -from [get_clocks RXDataCLK] -to [get_cells {FitGbtPrg/RxData_ClkSync_comp/RX_IS_DATA_DATACLK_reg*}] 3.000 -set_max_delay -datapath_only -from [get_clocks RXDataCLK] -to [get_cells FitGbtPrg/RxData_ClkSync_comp/RX_CLK_from00_reg] 2.000 -set_false_path -from [get_clocks -include_generated_clocks MCLK1] -to [get_clocks RXDataCLK] -#set_multicycle_path -setup -start -from [get_cells {FitGbtPrg/RxData_ClkSync_comp/RX_DATA_DATACLK_ffsc_reg[*]}] -to [get_cells {FitGbtPrg/RxData_ClkSync_comp/RX_DATA_DATACLK_ffdc_reg[*]}] 7 -#set_multicycle_path -hold -from [get_cells {FitGbtPrg/RxData_ClkSync_comp/RX_DATA_DATACLK_ffsc_reg[*]}] -to [get_cells {FitGbtPrg/RxData_ClkSync_comp/RX_DATA_DATACLK_ffdc_reg[*]}] 6 -#set_multicycle_path -setup -start -from [get_cells {FitGbtPrg/DataClk_I_strobe_comp/count_ready_reg}] -to [get_cells {FitGbtPrg/DataClk_I_strobe_comp/count_ready_dtclk_ff_reg}] 7 -#set_multicycle_path -hold -from [get_cells {FitGbtPrg/DataClk_I_strobe_comp/count_ready_reg}] -to [get_cells {FitGbtPrg/DataClk_I_strobe_comp/count_ready_dtclk_ff_reg}] 6 -#set_multicycle_path -setup -start -from [get_cells {FitGbtPrg/RxData_ClkSync_comp/RX_IS_DATA_DATACLK_ffsc_reg}] -to [get_cells {FitGbtPrg/RxData_ClkSync_comp/RX_IS_DATA_DATACLK_ffdc_reg}] 7 -#set_multicycle_path -hold -from [get_cells {FitGbtPrg/RxData_ClkSync_comp/RX_IS_DATA_DATACLK_ffsc_reg}] -to [get_cells {FitGbtPrg/RxData_ClkSync_comp/RX_IS_DATA_DATACLK_ffdc_reg}] 6 diff --git a/firmware/FT0/PM/xdc/chipscope.xdc b/firmware/FT0/PM/xdc/chipscope.xdc new file mode 100644 index 0000000..e69de29 diff --git a/firmware/FT0/TCM/hdl/tcm_proto.vhd b/firmware/FT0/TCM_proto/hdl/tcm_proto.vhd similarity index 81% rename from firmware/FT0/TCM/hdl/tcm_proto.vhd rename to firmware/FT0/TCM_proto/hdl/tcm_proto.vhd index 39d67a5..d3db97b 100644 --- a/firmware/FT0/TCM/hdl/tcm_proto.vhd +++ b/firmware/FT0/TCM_proto/hdl/tcm_proto.vhd @@ -157,14 +157,13 @@ type rdout_stat_arr is array (7 downto 0) of std_logic_vector (31 downto 0); signal HDMIA_P, HDMIA_N, HDMIC_P, HDMIC_N, TDA_P, TDA_N, TDC_P, TDC_N : HDMI_trig; signal TDA, TDC, TDC0, TDC1, TDC2 : Trgdat; -signal hdmia_config, hdmic_config, Status_A, Status_C, f_out, f_inp, l_mode, l_patt0, l_patt1, Orbit_ID, flash_data_out, t_stmp, rout_buf, mcu_ts, bc_corrl, bc_corrA, bc_corrC : STD_LOGIC_VECTOR (31 downto 0); +signal hdmia_config, hdmic_config, Status_A, Status_C, f_out, f_inp, l_mode, l_patt0, l_patt1, Orbit_ID, flash_data_out, t_stmp, rout_buf, mcu_ts, bc_corrl, bc_corrA, bc_corrC, bc_maskO : STD_LOGIC_VECTOR (31 downto 0); signal trig_mod: STD_LOGIC_VECTOR (14 downto 0); signal trg_r_wr : STD_LOGIC_VECTOR (4 downto 0); signal trg_r : Tout_arr; signal count_r : cou_arr; signal Tout_sel, Tmode_sel : STD_LOGIC; -signal CLK320A, CLK320C, Vertex, Vertex_0, OrA_i, OrC_i, OrA,S, OrC, SC, SC_0, C, C_0, B_rdy, B_rdy0, B_rdy1, B_rdy2, B_rdy3, OrC_B, OrC_B0, OrC_B1, OrC_B2, reset, rsti, lasi, irqi, mgtclk, clka, clkc : STD_LOGIC; -signal clksys40 : std_logic; +signal CLK320A, CLK320C, Vertex, Vertex_0, OrA_i, OrC_i, OrA,S, OrC, SC, SC_0, C, C_0, B_rdy, B_rdy0, B_rdy1, B_rdy2, B_rdy3, OrA_B, OrC_B, OrC_B0, OrC_B1, OrC_B2, reset, rsti, lasi, irqi, mgtclk, clka, clkc : STD_LOGIC; signal CSi, MOSIi, MISOi, SCKi : STD_LOGIC; signal bitcnt_A, bitcnt_C : STD_LOGIC_VECTOR (2 downto 0); signal Tcnt_cnt : STD_LOGIC_VECTOR (3 downto 0); @@ -203,7 +202,8 @@ signal TimeC, TimeC0, TimeC1, TimeC2, TimeA : STD_LOGIC_VECTOR (8 downto 0); signal TimeA_o, TimeC_o : STD_LOGIC_VECTOR (15 downto 0); signal AvgA, AvgC : STD_LOGIC_VECTOR (13 downto 0); signal TresbM, TdiffM : STD_LOGIC_VECTOR (23 downto 0); -signal hdmiac_select, hdmicc_select, hdmias_select, hdmics_select, pll_lock_a, pll_lock_c, hdmis_ack, mul_ena, mul_enc, sideA_OK, sideC_OK, stat_clrA, stat_clrC, as_chg, cs_chg, rst_fl : STD_LOGIC; +signal hdmiac_select, hdmicc_select, hdmias_select, hdmics_select, pll_lock_a, pll_lock_c, hdmis_ack, mul_ena, mul_enc, sideA_OK, sideC_OK, stat_clr_cmd, as_chg, cs_chg, rst_fl, as_blk, cs_blk, hdmi_to0, hdmi_to : STD_LOGIC; +signal PM_tcou : STD_LOGIC_VECTOR (25 downto 0); signal dly_rst, cnt_rd, pm_adr_sel, pm_rdy, cnt_ctrl_sel, cnt_ctrl_rdy, ipb_locked, cnt_clr, cnt_lock, Tcnt_sel, Tcnt_0_rd, cnt_lock0, cnt_lock1, cnt_lock2, Tcnt_clr, cnt_clr0, cnt_clr1, cnt_clr2, Tcnt_ack, Tcnt_err : STD_LOGIC; signal fifo_sel, fifo_csel, f_rd, f_empty, f_wr, f_full, lclk160, lmode_sel, lpatt0_sel, lpatt1_sel, l_on, l_on0, l_on1, l_tg1, l_tg, l_fbin, l_fbout, a_t, a0_t, an_t : STD_LOGIC; signal l_cnt : STD_LOGIC_VECTOR (1 downto 0); @@ -215,24 +215,31 @@ signal lpatt_sreg : STD_LOGIC_VECTOR (63 downto 0); signal lfreq_cnt : STD_LOGIC_VECTOR (23 downto 0); signal BC_cou : STD_LOGIC_VECTOR(11 downto 0); signal ldr : STD_LOGIC_VECTOR(3 downto 0); -signal Tmode : STD_LOGIC_VECTOR(7 downto 0); +signal Tmode : STD_LOGIC_VECTOR(9 downto 0); signal Rd_word, FIFO_in : STD_LOGIC_VECTOR(159 downto 0); -signal gbt_wr, gbt_empty, rdoutc_sel, rdoutc_ack, rdoutc_wr, rdouts_sel, rdouts_ack, RST_req : STD_LOGIC; ---signal readout_conf : rdout_conf_arr; ---signal readout_stat : rdout_stat_arr; -signal readout_conf : cntr_reg_addrreg_type; -signal readout_stat : status_reg_addrreg_type; +signal gbt_wr, gbt_empty, rdoutc_sel, rdoutc_ack, rdoutc_wr, rdouts_sel, rdouts_rdy, RST_req : STD_LOGIC; +signal rdouts_cnt, bc_mask : STD_LOGIC_VECTOR(1 DOWNTO 0); +signal readout_control_reg : ctrl_reg_t; +signal readout_status_reg : stat_reg_t; signal New_BCID : STD_LOGIC; -signal las_o, l_st, flshreg_sel, bkgndA, bkgndC, bkgndC0, bkgndC1, bkgndC2, bgA_inc, bgC_inc, bgOr, bgAnd, orA_str, orA_cnt, orC_cnt, Or_or, Or_and, Bg_Aclr, Bg_Cclr, Bg_Orclr, Bg_Andclr, sca, scc, ca, cc, scb, cb : STD_LOGIC; +signal las_o, l_st, flshreg_sel, NoiseA, NoiseC, NoiseC0, NoiseC1, NoiseC2, NoiseA_inc, NoiseC_inc, NoiseAll, orA_str, Interact, OrA_T, OrC_T, Interact_T, V_T, sca, scc, ca, cc, scb, cb, BG_A, BG_C : STD_LOGIC; signal tstamp_sel, d_rd, d_rdy, adc_sel, adc_sel1, rout_lock0, rout_lock1, rout_lock2, PM_rst, cctrl_rst, clk_src, clk_l, clk_frs, mcuts_sel, pmena_sel, pm_err, bccorr_sel, bccorr_ack, corr_inc, SC_str, CC_str, V_str : STD_LOGIC; -signal bccorrA_sel, bccorrC_sel, bccorr_ack0, bccorr_rd : STD_LOGIC; +signal bccorrA_sel, bccorrC_sel, bccorr_ack0, bccorr_rd, bc_mask_sel : STD_LOGIC; signal d_addr : STD_LOGIC_VECTOR(6 DOWNTO 0); signal d_sns : STD_LOGIC_VECTOR(15 DOWNTO 0); signal rx_phase_status : std_logic_vector(3 downto 0); -signal laser_t0, laser_t : std_logic; +signal laser_t0, laser_t, tr_valid, tblock_sel, tblock0, tblock, tblock1, tblock2, t_blk : std_logic; + signal pm_ena : std_logic_vector(19 downto 0) := x"00000"; +signal tblock_md : std_logic_vector(7 downto 0); +signal tblock_dly : STD_LOGIC_VECTOR (65 downto 0); +signal tblock_mux : STD_LOGIC_VECTOR (2 downto 0); + +signal AmplAI, AmplAO : STD_LOGIC_VECTOR (15 downto 0); +signal nsca, nscc, nscb, sct, nt, irt, ort, ovtx, orct, sc_i, c_i : STD_LOGIC; +signal Nchan_S : STD_LOGIC_VECTOR (7 downto 0); @@ -261,7 +268,9 @@ component tcm_side is Avg_o : out STD_LOGIC_VECTOR (13 downto 0); Nchan : out STD_LOGIC_VECTOR (6 downto 0); req : out STD_LOGIC_VECTOR (9 downto 0); - bkgnd : out STD_LOGIC + bkgnd : out STD_LOGIC; + AmplI_o : out STD_LOGIC_VECTOR (15 downto 0); + AmplO_o : out STD_LOGIC_VECTOR (15 downto 0) ); end component; @@ -354,8 +363,8 @@ end component; -- ############################################### -- ######### GBT Readout ######################## -- ############################################### - signal FIT_GBT_status : FIT_GBT_status_type; - signal FIT_GBT_control : CONTROL_REGISTER_type; + signal readout_status : readout_status_t; + signal readout_control : readout_control_t; signal Data_from_FITrd : std_logic_vector(GBT_data_word_bitdepth-1 downto 0); signal IsData_from_FITrd : STD_LOGIC; @@ -368,13 +377,10 @@ end component; signal gbt_global_status : std_logic_vector(3 downto 0); signal readout_laser_out, readout_laser_out_ff0, readout_laser_out_ff1 : std_logic; - signal ipbus_control_reg : cntr_reg_addrreg_type; - signal ipbus_status_reg: status_reg_addrreg_type; - component FIT_GBT_project is generic ( - GENERATE_GBT_BANK : integer := 1 + IS_SIMULATION : integer := 0 ); Port ( @@ -385,8 +391,11 @@ end component; RxDataClk_I : in STD_LOGIC; -- 40MHz data clock in RX domain GBT_RxFrameClk_O : out STD_LOGIC; --Rx GBT frame clk 40MHz + IPbusClk_I : in std_logic; -- IPbus clock for error fifo read + err_report_fifo_rden_i : in std_logic; -- IPbus error report fifo read enable + Board_data_I : in board_data_type; --PM or TCM data - Control_register_I : in CONTROL_REGISTER_type; + Control_register_I : in readout_control_t; MGT_RX_P_I : in STD_LOGIC; MGT_RX_N_I : in STD_LOGIC; @@ -407,11 +416,7 @@ end component; IsRxData_rxclk_from_GBT_O : out STD_LOGIC; -- FIT readour status, including BCOR_ID to PM/TCM - FIT_GBT_status_O : out FIT_GBT_status_type; - rx_ph320 : out std_logic_vector(2 downto 0); - ph_error320 : out std_logic - - --GPIO_O : out std_logic_vector(15 downto 0) + readout_status_O : out readout_status_t ); end component; -- ############################################### @@ -536,6 +541,23 @@ END COMPONENT; busy_out : OUT STD_LOGIC ); END COMPONENT; + + COMPONENT Mask_mem + PORT ( + clka : IN STD_LOGIC; + wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0); + dina : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + douta : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + clkb : IN STD_LOGIC; + enb : IN STD_LOGIC; + web : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + addrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dinb : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) + ); + END COMPONENT; + attribute IODELAY_GROUP : STRING; @@ -696,8 +718,6 @@ ipbus_module: IPBUS_basex_infra port map( fl_upg: FLASH generic map (clk_freq => 31250 ) port map (rst=>ipb_rst, clk => ipb_clk, data_in =>ipb_data_out, data_out =>flash_data_out, A =>ipb_addr(1 downto 0), wr_flshreg =>ipb_iswr, rd_flshreg =>ipb_isrd, flshreg_sel=>flshreg_sel, FSEL =>FSEL, FMOSI =>FMOSI, FMISO =>FMISO); -TX_CLK<=clksys40; - @@ -727,19 +747,23 @@ TX_CLK<=clksys40; -- FIT GBT project ===================================== FitGbtPrg: FIT_GBT_project generic map( - GENERATE_GBT_BANK => 1 + IS_SIMULATION => 0 ) Port map( RESET_I => sreset, SysClk_I => CLK320A, - DataClk_I => clksys40, + DataClk_I => TX_CLK, MgtRefClk_I => MGTCLK, RxDataClk_I => RX_CLK, -- 40MHz data clock in RX domain (loop back) GBT_RxFrameClk_O => RX_CLK, + -- not connected + IPbusClk_I => '0', + err_report_fifo_rden_i => '0', + Board_data_I => TCM_data_toreadout, - Control_register_I => FIT_GBT_control, + Control_register_I => readout_control, MGT_RX_P_I => GBT_RX_P, MGT_RX_N_I => GBT_RX_N, @@ -757,18 +781,14 @@ FitGbtPrg: FIT_GBT_project RxData_rxclk_from_GBT_O => RxData_rxclk_from_GBT, IsRxData_rxclk_from_GBT_O => IsRxData_rxclk_from_GBT, - rx_ph320 => rx_phase_status(2 downto 0), - ph_error320 => rx_phase_status(3), - - FIT_GBT_status_O => FIT_GBT_status --- GPIO_O => GPIO + readout_status_O => readout_status ); -- ===================================================== GBT_is_RXD <= IsRxData_rxclk_from_GBT; -GBTRX_ready <= FIT_GBT_status.GBT_status.gbtRx_Ready; -RX_err <= FIT_GBT_status.GBT_status.gbtRx_ErrorDet; +GBTRX_ready <= readout_status.GBT_status.gbtRx_Ready; +RX_err <= readout_status.GBT_status.gbtRx_ErrorDet; --PM_data_toreadout.is_header <= GBT_is_TXD; --PM_data_toreadout.is_data <= GBT_is_TXD; @@ -776,35 +796,32 @@ RX_err <= FIT_GBT_status.GBT_status.gbtRx_ErrorDet; --PM_data_toreadout.data_word <= GBT_TX_D; -FIT_GBT_control <= func_CNTRREG_getcntrreg(ipbus_control_reg); -ipbus_status_reg <= func_STATREG_getaddrreg(FIT_GBT_status); +readout_control <= func_CNTRREG_getcntrreg(readout_control_reg); +readout_status_reg <= func_STATREG_getaddrreg(readout_status); -ipbus_control_reg <= readout_conf; -readout_stat <= ipbus_status_reg; - -gbt_global_status(0) <= FIT_GBT_status.GBT_status.Rx_Phase_error; ---gbt_global_status(1) <= '1' when FIT_GBT_status.BCIDsync_Mode = mode_LOST else '0'; ---gbt_global_status(2) <= '1' when FIT_GBT_status.hits_rd_counter_selector.hits_skipped /= x"0000_0000" else '0'; +gbt_global_status(0) <= readout_status.Rx_Phase_error; +--gbt_global_status(1) <= '1' when readout_status.BCIDsync_Mode = mode_LOST else '0'; +--gbt_global_status(2) <= '1' when readout_status.hits_rd_counter_selector.hits_skipped /= x"0000_0000" else '0'; gbt_global_status(3) <= '0'; -process (clksys40) +process (TX_CLK) begin - if (clksys40'event and clksys40='1') then - if ( FIT_GBT_status.BCIDsync_Mode = mode_LOST) then + if (TX_CLK'event and TX_CLK='1') then + if ( readout_status.BCIDsync_Mode = mode_LOST) then gbt_global_status(1) <= '1'; else gbt_global_status(1) <= '0'; end if; - if ( FIT_GBT_status.hits_rd_counter_selector.hits_skipped = x"0000_0000") then + if ( readout_status.fsm_errors = x"00") then gbt_global_status(2) <= '0'; else gbt_global_status(2) <= '1'; end if; - if ( FIT_GBT_status.Trigger_from_CRU and FIT_GBT_control.Data_Gen.trigger_resp_mask ) /= 0 then + if readout_status.laser_start = '1' then readout_laser_out <= '1'; else readout_laser_out <= '0'; @@ -842,6 +859,9 @@ process (TX_CLK) begin if (TX_CLK'event and TX_CLK='1') then +rout_lock2<=rout_lock1; rout_lock1<=rout_lock0; rout_lock0<=rdouts_sel and (not rdouts_rdy); +if (rout_lock1='1') and (rout_lock2='0') then rout_buf <=readout_status_reg(to_integer(unsigned(ipb_addr(5 downto 0)))-16#28#); end if; + GBT_is_TXD<=IsData_from_FITrd; IsRXData0<=GBT_is_RXD; @@ -894,6 +914,7 @@ lmode_sel<= ipb_str when ipb_addr(31 downto 0)= x"0000001B" else '0'; lpatt0_sel<= ipb_str when ipb_addr(31 downto 0)= x"0000001C" else '0'; lpatt1_sel<= ipb_str when ipb_addr(31 downto 0)= x"0000001D" else '0'; pmena_sel<= ipb_str when ipb_addr(31 downto 0)= x"0000001E" else '0'; +tblock_sel<= ipb_str when ipb_addr(31 downto 0)= x"0000001F" else '0'; hdmics_select <= ipb_str when (ipb_addr(31 downto 4)= x"0000003") and (ipb_addr(3 downto 0) open, DATA => t_stmp, DATAVALID => open ); SNS : SENSOR PORT MAP ( di_in => (others=>'0'), daddr_in => d_addr, den_in => d_rd, dwe_in => '0', drdy_out => d_rdy, do_out => d_sns, dclk_in => ipb_clk, @@ -1032,6 +1056,8 @@ process(CLKA) begin if (CLKA'event) and (CLKA='1') then +tblock_dly<= tblock_dly(64 downto 0) & l_st; tblock<=tblock0; + a_t<=not a_t; l_on1<=l_on0; l_on0 <= l_st; readout_laser_out_ff0 <= readout_laser_out; readout_laser_out_ff1 <= readout_laser_out_ff0; @@ -1049,6 +1075,12 @@ end process; l_st<= readout_laser_out_ff1 when (l_mode(31)='0') else lpatt_sreg(63); +tblock_mux(0)<= tblock_dly(to_integer(unsigned(tblock_md(5 downto 0)))); +tblock_mux(1)<= tblock_dly(to_integer(unsigned(tblock_md(5 downto 0)))+1); +tblock_mux(2)<= tblock_dly(to_integer(unsigned(tblock_md(5 downto 0)))+2); + +tblock0<= '1' when ((tblock_md(7 downto 6)>="01") and (tblock_mux(0)='1')) or ((tblock_md(7 downto 6)>="10") and (tblock_mux(1)='1')) or ((tblock_md(7 downto 6)="11") and (tblock_mux(2)='1')) else '0'; + process (LCLK160) begin if (LCLK160'event and LCLK160='0') then an_t<=a_t; end if; @@ -1063,7 +1095,7 @@ a0_t<=an_t; l_tg1<=l_tg; l_tg<=l_on and (not l_tg1); lasi<=l_on and (not l_tg1); -if (a0_t XOR an_t)='1' then l_cnt<="01"; else l_cnt<=l_cnt+1; end if; +if (a0_t XOR an_t)='1' then l_cnt<="10"; else l_cnt<=l_cnt+1; end if; if (ldr(1 downto 0)=l_cnt) then case ldr(3 downto 2) is @@ -1077,11 +1109,11 @@ end if; end if; end process; -tcma: tcm_side port map(CLKA=>CLKA, RST=>reset, SRST=>sreset, TD_P=>TDA_P, TD_N=>TDA_N, Config=>hdmia_config, Status=>Status_a, stat_adr=> ipb_addr(3 downto 0), stat_clr=>stat_clrA, stat_chg=>as_chg, side_OK=>sideA_OK, TDD=>TDA, rd_lock=> rd_lock_a, - Or_o=>OrA_i, CLK320_o=>CLK320A, clksys40_o => clksys40, pll_lock=> pll_lock_a, mt_cou_o=>bitcnt_A, Time_o=>TimeA_o, Avg_o=>AvgA, Ampl_O=>AmplA, Nchan=> Nchan_A, req=> reqA, bkgnd=> bkgndA); +tcma: tcm_side port map(CLKA=>CLKA, RST=>reset, SRST=>sreset, TD_P=>TDA_P, TD_N=>TDA_N, Config=>hdmia_config, Status=>Status_a, stat_adr=> ipb_addr(3 downto 0), stat_clr=>stat_clr_cmd, stat_chg=>as_blk, side_OK=>sideA_OK, TDD=>TDA, rd_lock=> rd_lock_a, + Or_o=>OrA_B, CLK320_o=>CLK320A, clksys40_o => TX_CLK, pll_lock=> pll_lock_a, mt_cou_o=>bitcnt_A, Time_o=>TimeA_o, Avg_o=>AvgA, Ampl_O=>AmplA, Nchan=> Nchan_A, req=> reqA, bkgnd=> NoiseA, AmplI_O=> AmplAI, AmplO_O=> AmplAO ); -tcmc: tcm_side port map(CLKA=>CLKC, RST=>reset, SRST=>sreset, TD_P=>TDC_P, TD_N=>TDC_N, Config=>hdmic_config, Status=>Status_C, stat_adr=> ipb_addr(3 downto 0), stat_clr=>stat_clrC, stat_chg=>cs_chg, side_OK=>sideC_OK, TDD=>TDC0, rd_lock=> rd_lock_c, - Or_o=>OrC_B, CLK320_o=>CLK320C, clksys40_o=> open, pll_lock=> pll_lock_c, mt_cou_o=>bitcnt_c, Time_o=>TimeC_o, Avg_o=>AvgC, Ampl_o=>AmplC0, Nchan=> Nchan_C0, req=> reqC, bkgnd=> bkgndC0); +tcmc: tcm_side port map(CLKA=>CLKC, RST=>reset, SRST=>sreset, TD_P=>TDC_P, TD_N=>TDC_N, Config=>hdmic_config, Status=>Status_C, stat_adr=> ipb_addr(3 downto 0), stat_clr=>stat_clr_cmd, stat_chg=>cs_blk, side_OK=>sideC_OK, TDD=>TDC0, rd_lock=> rd_lock_c, + Or_o=>OrC_B, CLK320_o=>CLK320C, clksys40_o=> open, pll_lock=> pll_lock_c, mt_cou_o=>bitcnt_c, Time_o=>TimeC_o, Avg_o=>AvgC, Ampl_o=>AmplC0, Nchan=> Nchan_C0, req=> reqC, bkgnd=> NoiseC0, AmplI_O=> open, AmplO_O=> open); TresbM<=TimeC(8) & TimeC & "00000000000000"; Tdiff<=TdiffM(23 downto 14); @@ -1140,7 +1172,7 @@ if (SCKi'event and SCKi='1') then when 3 => SPI_DATA<= SC_C; when 4 => SPI_DATA<= C_A; when 5 => SPI_DATA<= C_C; - when 6 => SPI_DATA<=x"00" & Tmode; + when 6 => SPI_DATA<="000000" & Tmode; when 16#10# to 16#17# => SPI_DATA<=spi_buf_out; when 16#18# => SPI_DATA<= x"000" & ldr; @@ -1171,12 +1203,19 @@ irqi<= dcs_irq or IPB_chg or GBT_chg or GBTRXerr or RST_req when (irq_cnt="11") PM_rst <= rst_spi2 and (not rst_spi1); -bccorr_rd<= bccorr_sel or bccorrA_sel or bccorrC_sel; bccorr_ack<=bccorr_ack0 and bccorr_rd; +bccorr_rd<= bccorr_sel or bccorrA_sel or bccorrC_sel or (bc_mask_sel and ipb_isrd); bccorr_ack<=bccorr_ack0 and bccorr_rd; + +hdmi_to0<='1' when (PM_tcou/=31250000) else '0'; +as_blk<=as_chg or hdmi_to; cs_blk<=cs_chg or hdmi_to; + +rdouts_rdy<='1' when (rdouts_cnt="10") else '0'; process(ipb_clk) begin if (ipb_clk'event and ipb_clk='1') then +if (rdouts_sel='0') or (rdouts_rdy='1') then rdouts_cnt<= (others=>'0'); else rdouts_cnt<=rdouts_cnt+1; end if; + if (bccorr_ack0='0') and (bccorr_rd='1') then bccorr_ack0<='1'; else bccorr_ack0<='0'; end if; adc_sel1<=adc_sel and not d_rdy; @@ -1210,8 +1249,22 @@ if (rst_spi1='1') then RST_req<='0'; clk_frs<='0'; end if; +if (ipb_rst='1') then hdmia_config<=(others=>'0'); hdmic_config<=(others=>'0'); + else + hdmi_to<=hdmi_to0; + if (PM_rst='1') then PM_tcou<=(others=>'0'); + else + if (hdmi_to0='1') then PM_tcou<=PM_tcou+1; end if; + end if; + if (hdmiac_select='1') and (ipb_iswr='1') then hdmia_config<=ipb_data_out; as_chg<='1'; end if; if (hdmicc_select='1') and (ipb_iswr='1') then hdmic_config<=ipb_data_out; cs_chg<='1'; end if; +end if; + +if (ipb_rst='1') then tblock_md<=(others=>'0'); + else + if (tblock_sel='1') and (ipb_iswr='1') then tblock_md<=ipb_data_out(7 downto 0); end if; +end if; if (as_chg='1') then as_chg<='0'; end if; if (cs_chg='1') then cs_chg<='0'; end if; @@ -1224,12 +1277,12 @@ if (lpatt0_sel='1') and (ipb_iswr='1') then l_patt0<=ipb_data_out(31 downto 0); if (lpatt1_sel='1') and (ipb_iswr='1') then l_patt1<=ipb_data_out(31 downto 0); end if; if (pmena_sel='1') and (ipb_iswr='1') then pm_ena<=ipb_data_out(19 downto 0); end if; -if (rst_spi1='1') or ((GBTRX_ready2='1') and (GBTRX_ready1='0')) then readout_conf(0)(22)<='1'; +if (rst_spi1='1') or ((GBTRX_ready2='1') and (GBTRX_ready1='0')) then readout_control_reg(0)(14)<='1'; else if (rdoutc_sel='1') and (ipb_iswr='1') then - if (ipb_addr(7 downto 0)=16#D8#) then readout_conf(0)<= ipb_data_out(31 downto 23) & (ipb_data_out(22) or not GBTRX_ready1) & ipb_data_out(21 downto 0); + if (ipb_addr(7 downto 0)=16#D8#) then readout_control_reg(0)<= ipb_data_out; else - readout_conf(to_integer(unsigned(ipb_addr(7 downto 0)))-16#D8#)<=ipb_data_out(31 downto 0); + readout_control_reg(to_integer(unsigned(ipb_addr(7 downto 0)))-16#D8#)<=ipb_data_out(31 downto 0); end if; end if; end if; @@ -1252,7 +1305,7 @@ end if; if (rst_spi1='1') then rst_fl<='1'; else - if (ipb_stat_rd='1') then rst_fl<='0'; end if; + if (stat_clr_cmd='1') then rst_fl<='0'; end if; end if; if (stat_clr1='1') and (stat_clr='0') then irq_cnt<="00"; @@ -1295,7 +1348,7 @@ spi_wr2<=spi_wr1; spi_wr1<=spi_wr0; spi_wr0<=spi_wr_rdy; when "011" => SC_C<=Treg_data; when "100" => C_A<=Treg_data; when "101" => C_C<=Treg_data; - when "110" => Tmode<=Treg_data(7 downto 0); + when "110" => Tmode<=Treg_data(9 downto 0); when others => null; end case; @@ -1332,31 +1385,32 @@ C_SC : trigger_out port map ( clk320 => clk320A, T_in=>SC_0, T_out =>SC, mode C_FC : trigger_out port map ( clk320 => clk320A, T_in=>C_0, T_out =>C, mode=>trig_mod(11 downto 9), ipb_clk=>ipb_clk, DI=>ipb_data_out, DO=>trg_r(3), CO=>count_r(3), A=>ipb_addr(0), wr=>trg_r_wr(3), c_rd=>cnt_lock, c_clr=>cnt_clr, mt_cnt=>bitcnt_A, T_r=>trigs(3)); C_vertex : trigger_out port map ( clk320 => clk320A, T_in=>Vertex_0, T_out =>Vertex, mode=>trig_mod(14 downto 12), ipb_clk=>ipb_clk, DI=>ipb_data_out, CO=>count_r(4), DO=>trg_r(4), A=>ipb_addr(0), wr=>trg_r_wr(4), c_rd=>cnt_lock, c_clr=>cnt_clr, mt_cnt=>bitcnt_A, T_r=>trigs(4)); -bgA_inc<= '1' when (bkgndA='1') and (bitcnt_A="011") else '0'; -bgC_inc<= '1' when (bkgndC='1') and (bitcnt_A="011") else '0'; -bgAnd<= bgA_inc and bgC_inc; -bgOr<= bgA_inc or bgC_inc; - -orA_cnt<= '1' when (orA_str='1') and (bitcnt_A="011") else '0'; -orC_cnt<= '1' when (OrC_i='1') and (bitcnt_A="011") else '0'; - -Or_or<= orA_cnt or orC_cnt; -Or_and<= orA_cnt and orC_cnt; -Bg_Aclr<= bgA_inc and not orA_cnt; -Bg_Cclr<= bgC_inc and not orC_cnt; -Bg_Orclr<= Bg_Aclr or Bg_Cclr; -Bg_Andclr<= Bg_Aclr and Bg_Cclr; - -cou_bA: counter32 port map (clk320=> clk320A, cout=> count_r(5), rd=> cnt_lock, clr=> cnt_clr, inc=> bgA_inc); -cou_bC: counter32 port map (clk320=> clk320A, cout=> count_r(6), rd=> cnt_lock, clr=> cnt_clr, inc=> bgC_inc); -cou_bAnd: counter32 port map (clk320=> clk320A, cout=> count_r(7), rd=> cnt_lock, clr=> cnt_clr, inc=> bgAnd); -cou_bor: counter32 port map (clk320=> clk320A, cout=> count_r(8), rd=> cnt_lock, clr=> cnt_clr, inc=> bgOr); -cou_oror: counter32 port map (clk320=> clk320A, cout=> count_r(9), rd=> cnt_lock, clr=> cnt_clr, inc=> Or_or); -cou_orand: counter32 port map (clk320=> clk320A, cout=> count_r(10), rd=> cnt_lock, clr=> cnt_clr, inc=> Or_and); -cou_AC: counter32 port map (clk320=> clk320A, cout=> count_r(11), rd=> cnt_lock, clr=> cnt_clr, inc=> bg_Aclr); -cou_CC: counter32 port map (clk320=> clk320A, cout=> count_r(12), rd=> cnt_lock, clr=> cnt_clr, inc=> bg_Cclr); -cou_orc: counter32 port map (clk320=> clk320A, cout=> count_r(13), rd=> cnt_lock, clr=> cnt_clr, inc=> bg_Orclr); -cou_andc: counter32 port map (clk320=> clk320A, cout=> count_r(14), rd=> cnt_lock, clr=> cnt_clr, inc=> bg_Andclr); +NoiseA_inc<= t_blk when (NoiseA='1') and (orA_str='0') and (bitcnt_A="011") else '0'; +NoiseC_inc<= t_blk when (NoiseC='1') and (orCt='0') and (Tmode(9)='0') and (bitcnt_A="011") else '0'; +NoiseAll<= NoiseA_inc or NoiseC_inc; + +Interact<= '1' when (orA_str='1') and (OrCt='1') and (bitcnt_A="011") else '0'; + +cou_NA: counter32 port map (clk320=> clk320A, cout=> count_r(5), rd=> cnt_lock, clr=> cnt_clr, inc=> NoiseA_inc); +cou_NC: counter32 port map (clk320=> clk320A, cout=> count_r(6), rd=> cnt_lock, clr=> cnt_clr, inc=> NoiseC_inc); +cou_NAll: counter32 port map (clk320=> clk320A, cout=> count_r(7), rd=> cnt_lock, clr=> cnt_clr, inc=> NoiseAll); +cou_int: counter32 port map (clk320=> clk320A, cout=> count_r(10), rd=> cnt_lock, clr=> cnt_clr, inc=> Interact); + +bc_m: Mask_mem PORT MAP (clka => clk320A, wea => "0", addra => BC_cou, dina => (others=>'0'), douta => bc_mask, clkb => ipb_clk, enb => bc_mask_sel, web(0) => ipb_wr, addrb => ipb_addr(7 downto 0), dinb => ipb_data_out, doutb => bc_maskO); + +OrA_T<= '1' when (OrA_str='1') and (bc_mask="11") and (bitcnt_A="011") else '0'; +OrC_T<= '1' when (OrCt='1') and (bc_mask="11") and (bitcnt_A="011") else '0'; +Interact_T<= '1' when (OrCt='1') and (OrA_str='1') and (bc_mask="11") and (bitcnt_A="011") else '0'; +V_T<= '1' when (V_str='1') and (bc_mask="11") and (bitcnt_A="011") else '0'; +BG_A<= '1' when (OrCt='1') and (bc_mask="01") and (bitcnt_A="011") else '0'; +BG_C<= '1' when (OrA_str='1') and (bc_mask="10") and (bitcnt_A="011") else '0'; + +AT: counter32 port map (clk320=> clk320A, cout=> count_r(8), rd=> cnt_lock, clr=> cnt_clr, inc=> OrA_T); +CT: counter32 port map (clk320=> clk320A, cout=> count_r(9), rd=> cnt_lock, clr=> cnt_clr, inc=> OrC_T); +IT: counter32 port map (clk320=> clk320A, cout=> count_r(11), rd=> cnt_lock, clr=> cnt_clr, inc=> Interact_T); +VT: counter32 port map (clk320=> clk320A, cout=> count_r(12), rd=> cnt_lock, clr=> cnt_clr, inc=> V_T); +BGA: counter32 port map (clk320=> clk320A, cout=> count_r(13), rd=> cnt_lock, clr=> cnt_clr, inc=> BG_A); +BGC: counter32 port map (clk320=> clk320A, cout=> count_r(14), rd=> cnt_lock, clr=> cnt_clr, inc=> BG_C); with Tmode(7 downto 4) select corr_inc<= '0' when x"0", @@ -1365,22 +1419,28 @@ with Tmode(7 downto 4) select corr_inc<= SC_str when x"3", CC_str when x"4", V_str when x"5", - bkgndA when x"6", - bkgndC when x"7", - bkgndA and bkgndC when x"8", - bkgndA or bkgndC when x"9", - orA_str and orC_i when x"A", - orA_str or orC_i when x"B", - bkgndA and not orA_str when x"C", - bkgndC and not orC_i when x"D", - (bkgndA and not orA_str) or (bkgndC and not orC_i) when x"E", - (bkgndA and not orA_str) and (bkgndC and not orC_i) when x"F"; + NoiseA when x"6", + NoiseC when x"7", + NoiseA or NoiseC when x"8", + orA_str and OrCt when x"9", + orA_str and bc_mask(0) and bc_mask(1) when x"A", + orCt and bc_mask(0) and bc_mask(1) when x"B", + orA_str and orCt and bc_mask(0) and bc_mask(1) when x"C", + V_str and bc_mask(0) and bc_mask(1) when x"D", + orCt and bc_mask(0) and (not bc_mask(1)) when x"E", + orA_str and bc_mask(1) and (not bc_mask(0)) when x"F"; m_cr: BC_correlator port map(clk320 =>CLK320A, BC_cou =>BC_COU, mt_cou =>bitcnt_A, inc =>corr_inc, clr =>cnt_clr, ipb_clk => ipb_clk, rd =>bccorr_sel, addr =>ipb_addr(11 downto 0), data =>bc_corrl); m_crA: BC_correlator port map(clk320 =>CLK320A, BC_cou =>BC_COU, mt_cou =>bitcnt_A, inc =>orA_str, clr =>cnt_clr, ipb_clk => ipb_clk, rd =>bccorrA_sel, addr =>ipb_addr(11 downto 0), data =>bc_corrA); m_crC: BC_correlator port map(clk320 =>CLK320A, BC_cou =>BC_COU, mt_cou =>bitcnt_A, inc =>orC_i, clr =>cnt_clr, ipb_clk => ipb_clk, rd =>bccorrC_sel, addr =>ipb_addr(11 downto 0), data =>bc_corrC); -Vertex_0<= '1' when (signed(Tdiff)>=signed(Tlow)) and (signed(Tdiff)<=signed(Thigh)) and (OrA_i='1') and (OrC_i='1') else '0'; +Vertex_0<= ovtx and t_blk when Tmode(9)='0' else irt and t_blk; + +OrA_i<= ORA_B and t_blk; + +OrC_i<= OrCt and t_blk when Tmode(9)='0' else ort and t_blk; + +ovtx <= '1' when (signed(Tdiff)>=signed(Tlow)) and (signed(Tdiff)<=signed(Thigh)) and (OrA_B='1') and (OrCt='1') else '0'; AmplS<= (AmplA(16) & AmplA) + (AmplC(16) & AmplC); @@ -1391,38 +1451,55 @@ cc<= '1' when (unsigned(AmplC(15 downto 0))>unsigned(C_C & '0')) and (AmplC(16) scb<= '1' when (unsigned(AmplS(16 downto 0))>unsigned(SC_A & '0')) and (AmplS(17)='0') else '0'; cb<= '1' when (unsigned(AmplS(16 downto 0))>unsigned(C_A & '0')) and (AmplS(17)='0') else '0'; -SC_0<= not C_0 when (((sca='1') or (Tmode(1)='1')) and ((scc='1') or (Tmode(2)='1')) and (Tmode(2 downto 1)/="11")) or ((scb='1') and Tmode(2 downto 1)="11") else '0'; +Nchan_S<= ("0" & Nchan_A) + ("0" & Nchan_C); + +nsca <= '1' when (unsigned(Nchan_A) > unsigned(SC_A) ) else '0'; +nscc <= '1' when (unsigned(Nchan_C) > unsigned(SC_C) ) else '0'; +nscb <= '1' when (unsigned(Nchan_S) > unsigned(SC_A) ) else '0'; + +sct <= '1' when (((sca='1') or (Tmode(1)='1')) and ((scc='1') or (Tmode(2)='1') or (Tmode(9)='1')) and ((Tmode(2 downto 1)/="11") or (Tmode(9)='1'))) or ((scb='1') and (Tmode(2 downto 1)="11") and (Tmode(9)='0')) else '0'; +nt<= '1' when (((nsca='1') or (Tmode(1)='1')) and ((nscc='1') or (Tmode(2)='1') or (Tmode(9)='1')) and ((Tmode(2 downto 1)/="11") or (Tmode(9)='1'))) or ((nscb='1') and (Tmode(2 downto 1)="11") and (Tmode(9)='0')) else '0'; + +irt <= '1' when (unsigned(AmplAI(14 downto 0))>unsigned(SC_C & '0')) and (AmplAI(15)='0') else '0'; +ort <= '1' when (unsigned(AmplAO(14 downto 0))>unsigned(C_C & '0')) and (AmplAO(15)='0') else '0'; + +SC_i<= (not C_0) and sct when (Tmode(8)='0') else nt and t_blk; SC_0<= SC_i and t_blk; -C_0<= '1' when (((ca='1') or (Tmode(1)='1')) and ((cc='1') or (Tmode(2)='1')) and (Tmode(2 downto 1)/="11")) or ((cb='1') and Tmode(2 downto 1)="11") else '0'; - +C_i<= '1' when (((ca='1') or (Tmode(1)='1')) and ((cc='1') or (Tmode(2)='1') or (Tmode(9)='1')) and ((Tmode(2 downto 1)/="11") or (Tmode(9)='1'))) or ((cb='1') and (Tmode(2 downto 1)="11") and (Tmode(9)='0')) else '0'; +C_0<= C_i and t_blk; + +tr_valid <= OrA_B or ORC_t or SC_i or C_i or (Tmode(9) and (ort or irt)); cnt_lock<=(cnt_lock1 and (not cnt_lock2)) or cnt_rd; cnt_clr<=cnt_clr1 and (not cnt_clr2); process (CLK320A) begin if (CLK320A'event and CLK320A='1') then - -laser_t0<=l_on0; laser_t<=laser_t0; - cnt_lock2<=cnt_lock1; cnt_lock1<=cnt_lock0; cnt_lock0<=Tcnt_0_rd; cnt_clr2<=cnt_clr1; cnt_clr1<=cnt_clr0; cnt_clr0<=Tcnt_clr; - rout_lock2<=rout_lock1; rout_lock1<=rout_lock0; rout_lock0<=rdouts_sel and ipb_clk; - if (rout_lock1='1') and (rout_lock2='0') then rout_buf <=readout_stat(to_integer(unsigned(ipb_addr(5 downto 0)))-16#28#); end if; +laser_t0<=l_on0; laser_t<=laser_t0; tblock2<=tblock1; tblock1<=tblock; + +rx_phase_status(2 downto 0) <= readout_status.rx_phase; +rx_phase_status(3) <= readout_status.Rx_Phase_error; + cnt_lock2<=cnt_lock1; cnt_lock1<=cnt_lock0; cnt_lock0<=Tcnt_0_rd; cnt_clr2<=cnt_clr1; cnt_clr1<=cnt_clr0; cnt_clr0<=Tcnt_clr; + B_rdy3<=B_rdy2; B_rdy2<=B_rdy1; B_rdy1<=B_rdy0; B_rdy0<=B_rdy; -if (B_rdy1='1') and (B_rdy2='0') then TimeC1<=TimeC0; AmplC1<=AmplC0; OrC_B1<=OrC_B; Nchan_C1<=Nchan_C0; bkgndC1<= bkgndC0; end if; +if (B_rdy1='1') and (B_rdy2='0') then TimeC1<=TimeC0; AmplC1<=AmplC0; OrC_B1<=OrC_B; Nchan_C1<=Nchan_C0; NoiseC1<= NoiseC0; end if; if (B_rdy2='1') and (B_rdy3='0') then TDC1<=TDC0; end if; if (bitcnt_A="000") then + t_blk<=not tblock2; + if (Tmode(0)='1') then - if (B_rdy1='1') and (B_rdy2='0') then TimeC2<=TimeC0; AmplC2<=AmplC0; OrC_B2<=OrC_B; Nchan_C2<=Nchan_C0; bkgndC2<= bkgndC0; - else TimeC2<=TimeC1; AmplC2<=AmplC1; OrC_B2<=OrC_B1; Nchan_C2<=Nchan_C1; bkgndC2<= bkgndC1; + if (B_rdy1='1') and (B_rdy2='0') then TimeC2<=TimeC0; AmplC2<=AmplC0; OrC_B2<=OrC_B; Nchan_C2<=Nchan_C0; NoiseC2<= NoiseC0; + else TimeC2<=TimeC1; AmplC2<=AmplC1; OrC_B2<=OrC_B1; Nchan_C2<=Nchan_C1; NoiseC2<= NoiseC1; end if; - TimeC<=TimeC2; AmplC<=AmplC2; OrC_i<=OrC_B2; Nchan_C<=Nchan_C2; bkgndC<= bkgndC2; + TimeC<=TimeC2; AmplC<=AmplC2; OrCt<=OrC_B2; Nchan_C<=Nchan_C2; NoiseC<= NoiseC2; else - if (B_rdy1='1') and (B_rdy2='0') then TimeC<=TimeC0; AmplC<=AmplC0; ORC_i<=OrC_B; Nchan_C<=Nchan_C0; bkgndC<= bkgndC0; - else TimeC<=TimeC1; AmplC<=AmplC1; OrC_i<=OrC_B1; Nchan_C<=Nchan_C1; bkgndC<= bkgndC1; + if (B_rdy1='1') and (B_rdy2='0') then TimeC<=TimeC0; AmplC<=AmplC0; ORCt<=OrC_B; Nchan_C<=Nchan_C0; NoiseC<= NoiseC0; + else TimeC<=TimeC1; AmplC<=AmplC1; OrCt<=OrC_B1; Nchan_C<=Nchan_C1; NoiseC<= NoiseC1; end if; end if; end if; @@ -1430,7 +1507,7 @@ end if; if (bitcnt_A="001") then - if (New_BCID='1') then BC_COU<=FIT_GBT_status. BCID_from_CRU_corrected; Orbit_ID<=FIT_GBT_status. ORBIT_from_CRU_corrected; + if (New_BCID='1') then BC_COU<=readout_status. BCID_from_CRU_corrected; Orbit_ID<=readout_status. ORBIT_from_CRU_corrected; else if (BC_COU=x"DEB") then BC_cou<=x"000"; Orbit_ID<=Orbit_ID+1; else BC_cou<=BC_cou+1; end if; end if; @@ -1450,9 +1527,11 @@ if (Tmode(0)='1') then end if; if (bitcnt_A="010") then - if ((OrA_i or ORC_i or SC_0 or C_0 or laser_t)='1') then - Rd_Word<= x"F" & Tmode(3) &"001" & x"000000" & rx_phase_status & Orbit_ID & BC_COU & '0' & TimeC & '0' & TimeA & '0' & AmplC & '0' & AmplA & '0' & Nchan_C & '0' & Nchan_A & "00" & laser_t & trigs; - --Rd_Word<= x"F" & Tmode(3) &"001" & x"00000" &"000" & "00000" & Orbit_ID & BC_COU & '0' & TimeC & '0' & TimeA & '0' & AmplC & '0' & AmplA & '0' & Nchan_C & '0' & Nchan_A & "000" & trigs; + if (trigs/=0) or (laser_t='1')or (tr_valid='1') then + Rd_Word(159 downto 80) <= x"F" & Tmode(3) &"001" & x"000000" & rx_phase_status & Orbit_ID & BC_COU; + Rd_word(79 downto 59) <= '0' & TimeC & '0' & TimeA & '0'; + if (Tmode(9)='0') then Rd_word(58 downto 42) <= AmplC; else Rd_word(58 downto 42) <= AmplAI(15) & AmplAI; end if; + Rd_word(41 downto 0) <= '0' & AmplA & '0' & Nchan_C & '0' & Nchan_A & tr_valid & (not t_blk) & laser_t & trigs; gbt_wr<='1'; end if; @@ -1472,7 +1551,7 @@ end if; end if; end process; -New_BCID <= FIT_GBT_status.Start_run when (FIT_GBT_status.BCIDsync_Mode=mode_SYNC) else '0'; +New_BCID <= readout_status.bc_delay_apply; FIFO_in<= TDA(2)(15 downto 0) & TDA(1) & TDA(0) & TDA(4) & TDA(3) & TDA(2)(31 downto 16) when (bitcnt_A="100") and (gbt_wr='1') diff --git a/firmware/FT0/TCM/ip/ROM7x15/div7x14.coe b/firmware/FT0/TCM_proto/ip/ROM7x15/div7x14.coe similarity index 100% rename from firmware/FT0/TCM/ip/ROM7x15/div7x14.coe rename to firmware/FT0/TCM_proto/ip/ROM7x15/div7x14.coe diff --git a/firmware/FT0/TCM/ipcore_properties/BC_corr_mem.txt b/firmware/FT0/TCM_proto/ipcore_properties/BC_corr_mem.txt similarity index 99% rename from firmware/FT0/TCM/ipcore_properties/BC_corr_mem.txt rename to firmware/FT0/TCM_proto/ipcore_properties/BC_corr_mem.txt index 9b506f4..0115a01 100644 --- a/firmware/FT0/TCM/ipcore_properties/BC_corr_mem.txt +++ b/firmware/FT0/TCM_proto/ipcore_properties/BC_corr_mem.txt @@ -51,7 +51,7 @@ CONFIG.RST.ARESETN.INSERT_VIP string false 0 CONFIG.Read_Width_A string false 32 CONFIG.Read_Width_B string false 32 CONFIG.Register_PortA_Output_of_Memory_Core string false false -CONFIG.Register_PortA_Output_of_Memory_Primitives string false false +CONFIG.Register_PortA_Output_of_Memory_Primitives string false true CONFIG.Register_PortB_Output_of_Memory_Core string false false CONFIG.Register_PortB_Output_of_Memory_Primitives string false false CONFIG.Remaining_Memory_Locations string false 0 diff --git a/firmware/FT0/TCM/ipcore_properties/COUNTER_FIFO.txt b/firmware/FT0/TCM_proto/ipcore_properties/COUNTER_FIFO.txt similarity index 100% rename from firmware/FT0/TCM/ipcore_properties/COUNTER_FIFO.txt rename to firmware/FT0/TCM_proto/ipcore_properties/COUNTER_FIFO.txt diff --git a/firmware/FT0/TCM/ipcore_properties/FLASH_FIFO.txt b/firmware/FT0/TCM_proto/ipcore_properties/FLASH_FIFO.txt similarity index 100% rename from firmware/FT0/TCM/ipcore_properties/FLASH_FIFO.txt rename to firmware/FT0/TCM_proto/ipcore_properties/FLASH_FIFO.txt diff --git a/firmware/FT0/TCM/ipcore_properties/LCLK_PLL.txt b/firmware/FT0/TCM_proto/ipcore_properties/LCLK_PLL.txt similarity index 100% rename from firmware/FT0/TCM/ipcore_properties/LCLK_PLL.txt rename to firmware/FT0/TCM_proto/ipcore_properties/LCLK_PLL.txt diff --git a/firmware/FT0/TCM/ipcore_properties/MMCM125ETH.txt b/firmware/FT0/TCM_proto/ipcore_properties/MMCM125ETH.txt similarity index 100% rename from firmware/FT0/TCM/ipcore_properties/MMCM125ETH.txt rename to firmware/FT0/TCM_proto/ipcore_properties/MMCM125ETH.txt diff --git a/firmware/FT0/TCM/ipcore_properties/MMCM320_PH.txt b/firmware/FT0/TCM_proto/ipcore_properties/MMCM320_PH.txt similarity index 100% rename from firmware/FT0/TCM/ipcore_properties/MMCM320_PH.txt rename to firmware/FT0/TCM_proto/ipcore_properties/MMCM320_PH.txt diff --git a/firmware/FT0/TCM/ipcore_properties/MULADD.txt b/firmware/FT0/TCM_proto/ipcore_properties/MULADD.txt similarity index 100% rename from firmware/FT0/TCM/ipcore_properties/MULADD.txt rename to firmware/FT0/TCM_proto/ipcore_properties/MULADD.txt diff --git a/firmware/FT0/TCM/ipcore_properties/MULT14xS16.txt b/firmware/FT0/TCM_proto/ipcore_properties/MULT14xS16.txt similarity index 100% rename from firmware/FT0/TCM/ipcore_properties/MULT14xS16.txt rename to firmware/FT0/TCM_proto/ipcore_properties/MULT14xS16.txt diff --git a/firmware/FT0/TCM_proto/ipcore_properties/Mask_mem.txt b/firmware/FT0/TCM_proto/ipcore_properties/Mask_mem.txt new file mode 100644 index 0000000..862de0a --- /dev/null +++ b/firmware/FT0/TCM_proto/ipcore_properties/Mask_mem.txt @@ -0,0 +1,78 @@ +Property Type Read-only Value +CONFIG.AXILITE_SLAVE_S_AXI.INSERT_VIP string false 0 +CONFIG.AXI_ID_Width string false 4 +CONFIG.AXI_SLAVE_S_AXI.INSERT_VIP string false 0 +CONFIG.AXI_Slave_Type string false Memory_Slave +CONFIG.AXI_Type string false AXI4_Full +CONFIG.Additional_Inputs_for_Power_Estimation string false false +CONFIG.Algorithm string false Minimum_Area +CONFIG.Assume_Synchronous_Clk string false false +CONFIG.Byte_Size string false 9 +CONFIG.CLK.ACLK.INSERT_VIP string false 0 +CONFIG.CTRL_ECC_ALGO string false NONE +CONFIG.Coe_File string false no_coe_file_loaded +CONFIG.Collision_Warnings string false ALL +CONFIG.Component_Name string false Mask_mem +CONFIG.Disable_Collision_Warnings string false false +CONFIG.Disable_Out_of_Range_Warnings string false false +CONFIG.ECC string false false +CONFIG.EN_DEEPSLEEP_PIN string false false +CONFIG.EN_ECC_PIPE string false false +CONFIG.EN_SAFETY_CKT string false false +CONFIG.EN_SHUTDOWN_PIN string false false +CONFIG.EN_SLEEP_PIN string false false +CONFIG.Enable_32bit_Address string false false +CONFIG.Enable_A string false Always_Enabled +CONFIG.Enable_B string false Use_ENB_Pin +CONFIG.Error_Injection_Type string false Single_Bit_Error_Injection +CONFIG.Fill_Remaining_Memory_Locations string false false +CONFIG.Interface_Type string false Native +CONFIG.Load_Init_File string false false +CONFIG.MEM_FILE string false no_mem_loaded +CONFIG.Memory_Type string false True_Dual_Port_RAM +CONFIG.Operating_Mode_A string false NO_CHANGE +CONFIG.Operating_Mode_B string false NO_CHANGE +CONFIG.Output_Reset_Value_A string false 0 +CONFIG.Output_Reset_Value_B string false 0 +CONFIG.PRIM_type_to_Implement string false BRAM +CONFIG.Pipeline_Stages string false 0 +CONFIG.Port_A_Clock string false 100 +CONFIG.Port_A_Enable_Rate string false 100 +CONFIG.Port_A_Write_Rate string false 50 +CONFIG.Port_B_Clock string false 100 +CONFIG.Port_B_Enable_Rate string false 100 +CONFIG.Port_B_Write_Rate string false 50 +CONFIG.Primitive string false 8kx2 +CONFIG.RD_ADDR_CHNG_A string false false +CONFIG.RD_ADDR_CHNG_B string false false +CONFIG.READ_LATENCY_A string false 1 +CONFIG.READ_LATENCY_B string false 1 +CONFIG.RST.ARESETN.INSERT_VIP string false 0 +CONFIG.Read_Width_A string false 2 +CONFIG.Read_Width_B string false 32 +CONFIG.Register_PortA_Output_of_Memory_Core string false false +CONFIG.Register_PortA_Output_of_Memory_Primitives string false true +CONFIG.Register_PortB_Output_of_Memory_Core string false false +CONFIG.Register_PortB_Output_of_Memory_Primitives string false false +CONFIG.Remaining_Memory_Locations string false 0 +CONFIG.Reset_Memory_Latch_A string false false +CONFIG.Reset_Memory_Latch_B string false false +CONFIG.Reset_Priority_A string false CE +CONFIG.Reset_Priority_B string false CE +CONFIG.Reset_Type string false SYNC +CONFIG.Use_AXI_ID string false false +CONFIG.Use_Byte_Write_Enable string false false +CONFIG.Use_Error_Injection_Pins string false false +CONFIG.Use_REGCEA_Pin string false false +CONFIG.Use_REGCEB_Pin string false false +CONFIG.Use_RSTA_Pin string false false +CONFIG.Use_RSTB_Pin string false false +CONFIG.Write_Depth_A string false 4096 +CONFIG.Write_Width_A string false 2 +CONFIG.Write_Width_B string false 32 +CONFIG.ecctype string false No_ECC +CONFIG.register_porta_input_of_softecc string false false +CONFIG.register_portb_output_of_softecc string false false +CONFIG.softecc string false false +CONFIG.use_bram_block string false Stand_Alone +IPDEF string true xilinx.com:ip:blk_mem_gen:8.4 diff --git a/firmware/FT0/TCM/ipcore_properties/PLL125.txt b/firmware/FT0/TCM_proto/ipcore_properties/PLL125.txt similarity index 100% rename from firmware/FT0/TCM/ipcore_properties/PLL125.txt rename to firmware/FT0/TCM_proto/ipcore_properties/PLL125.txt diff --git a/firmware/FT0/TCM/ipcore_properties/ROM7x15.txt b/firmware/FT0/TCM_proto/ipcore_properties/ROM7x15.txt similarity index 100% rename from firmware/FT0/TCM/ipcore_properties/ROM7x15.txt rename to firmware/FT0/TCM_proto/ipcore_properties/ROM7x15.txt diff --git a/firmware/FT0/TCM/ipcore_properties/SENSOR.txt b/firmware/FT0/TCM_proto/ipcore_properties/SENSOR.txt similarity index 100% rename from firmware/FT0/TCM/ipcore_properties/SENSOR.txt rename to firmware/FT0/TCM_proto/ipcore_properties/SENSOR.txt diff --git a/firmware/FT0/TCM/ipcore_properties/Xmega_buf.txt b/firmware/FT0/TCM_proto/ipcore_properties/Xmega_buf.txt similarity index 100% rename from firmware/FT0/TCM/ipcore_properties/Xmega_buf.txt rename to firmware/FT0/TCM_proto/ipcore_properties/Xmega_buf.txt diff --git a/firmware/FT0/TCM/ipcore_properties/cntpck_fifo_comp.txt b/firmware/FT0/TCM_proto/ipcore_properties/cntpck_fifo_comp.txt similarity index 99% rename from firmware/FT0/TCM/ipcore_properties/cntpck_fifo_comp.txt rename to firmware/FT0/TCM_proto/ipcore_properties/cntpck_fifo_comp.txt index c22a96e..425c87c 100644 --- a/firmware/FT0/TCM/ipcore_properties/cntpck_fifo_comp.txt +++ b/firmware/FT0/TCM_proto/ipcore_properties/cntpck_fifo_comp.txt @@ -14,7 +14,7 @@ CONFIG.Clock_Type_AXI string false Common_Cl CONFIG.Component_Name string false cntpck_fifo_comp CONFIG.DATA_WIDTH string false 64 CONFIG.Data_Count string false false -CONFIG.Data_Count_Width string false 7 +CONFIG.Data_Count_Width string false 8 CONFIG.Disable_Timing_Violations string false false CONFIG.Disable_Timing_Violations_AXI string false false CONFIG.Dout_Reset_Value string false 0 @@ -60,14 +60,14 @@ CONFIG.FIFO_Implementation_wdch string false Common_Cl CONFIG.FIFO_Implementation_wrch string false Common_Clock_Block_RAM CONFIG.Fifo_Implementation string false Independent_Clocks_Block_RAM CONFIG.Full_Flags_Reset_Value string false 1 -CONFIG.Full_Threshold_Assert_Value string false 127 +CONFIG.Full_Threshold_Assert_Value string false 255 CONFIG.Full_Threshold_Assert_Value_axis string false 1023 CONFIG.Full_Threshold_Assert_Value_rach string false 1023 CONFIG.Full_Threshold_Assert_Value_rdch string false 1023 CONFIG.Full_Threshold_Assert_Value_wach string false 1023 CONFIG.Full_Threshold_Assert_Value_wdch string false 1023 CONFIG.Full_Threshold_Assert_Value_wrch string false 1023 -CONFIG.Full_Threshold_Negate_Value string false 126 +CONFIG.Full_Threshold_Negate_Value string false 254 CONFIG.HAS_ACLKEN string false false CONFIG.HAS_TKEEP string false false CONFIG.HAS_TSTRB string false false @@ -87,8 +87,8 @@ CONFIG.Inject_Sbit_Error_rdch string false false CONFIG.Inject_Sbit_Error_wach string false false CONFIG.Inject_Sbit_Error_wdch string false false CONFIG.Inject_Sbit_Error_wrch string false false -CONFIG.Input_Data_Width string false 160 -CONFIG.Input_Depth string false 128 +CONFIG.Input_Data_Width string false 128 +CONFIG.Input_Depth string false 256 CONFIG.Input_Depth_axis string false 1024 CONFIG.Input_Depth_rach string false 16 CONFIG.Input_Depth_rdch string false 1024 @@ -100,8 +100,8 @@ CONFIG.MASTER_ACLK.INSERT_VIP string false 0 CONFIG.M_AXI.INSERT_VIP string false 0 CONFIG.M_AXIS.INSERT_VIP string false 0 CONFIG.Master_interface_Clock_enable_memory_mapped string false false -CONFIG.Output_Data_Width string false 160 -CONFIG.Output_Depth string false 128 +CONFIG.Output_Data_Width string false 128 +CONFIG.Output_Depth string false 256 CONFIG.Output_Register_Type string false Embedded_Reg CONFIG.Overflow_Flag string false false CONFIG.Overflow_Flag_AXI string false false @@ -157,7 +157,7 @@ CONFIG.Underflow_Sense_AXI string false Active_Hi CONFIG.Use_Dout_Reset string false true CONFIG.Use_Embedded_Registers string false false CONFIG.Use_Embedded_Registers_axis string false false -CONFIG.Use_Extra_Logic string false true +CONFIG.Use_Extra_Logic string false false CONFIG.Valid_Flag string false false CONFIG.Valid_Sense string false Active_High CONFIG.WRITE_CLK.FREQ_HZ string false 100000000 diff --git a/firmware/FT0/TCM_proto/ipcore_properties/err_report_fifo.txt b/firmware/FT0/TCM_proto/ipcore_properties/err_report_fifo.txt new file mode 100644 index 0000000..ae3e3d4 --- /dev/null +++ b/firmware/FT0/TCM_proto/ipcore_properties/err_report_fifo.txt @@ -0,0 +1,185 @@ +Property Type Read-only Value +CONFIG.ADDRESS_WIDTH string false 32 +CONFIG.ARUSER_Width string false 0 +CONFIG.AWUSER_Width string false 0 +CONFIG.Add_NGC_Constraint_AXI string false false +CONFIG.Almost_Empty_Flag string false false +CONFIG.Almost_Full_Flag string false false +CONFIG.BUSER_Width string false 0 +CONFIG.CORE_CLK.FREQ_HZ string false 100000000 +CONFIG.CORE_CLK.INSERT_VIP string false 0 +CONFIG.C_SELECT_XPM string false 0 +CONFIG.Clock_Enable_Type string false Slave_Interface_Clock_Enable +CONFIG.Clock_Type_AXI string false Common_Clock +CONFIG.Component_Name string false err_report_fifo +CONFIG.DATA_WIDTH string false 64 +CONFIG.Data_Count string false false +CONFIG.Data_Count_Width string false 11 +CONFIG.Disable_Timing_Violations string false false +CONFIG.Disable_Timing_Violations_AXI string false false +CONFIG.Dout_Reset_Value string false 0 +CONFIG.Empty_Threshold_Assert_Value string false 4 +CONFIG.Empty_Threshold_Assert_Value_axis string false 1022 +CONFIG.Empty_Threshold_Assert_Value_rach string false 1022 +CONFIG.Empty_Threshold_Assert_Value_rdch string false 1022 +CONFIG.Empty_Threshold_Assert_Value_wach string false 1022 +CONFIG.Empty_Threshold_Assert_Value_wdch string false 1022 +CONFIG.Empty_Threshold_Assert_Value_wrch string false 1022 +CONFIG.Empty_Threshold_Negate_Value string false 5 +CONFIG.Enable_Common_Overflow string false false +CONFIG.Enable_Common_Underflow string false false +CONFIG.Enable_Data_Counts_axis string false false +CONFIG.Enable_Data_Counts_rach string false false +CONFIG.Enable_Data_Counts_rdch string false false +CONFIG.Enable_Data_Counts_wach string false false +CONFIG.Enable_Data_Counts_wdch string false false +CONFIG.Enable_Data_Counts_wrch string false false +CONFIG.Enable_ECC string false false +CONFIG.Enable_ECC_Type string false Hard_ECC +CONFIG.Enable_ECC_axis string false false +CONFIG.Enable_ECC_rach string false false +CONFIG.Enable_ECC_rdch string false false +CONFIG.Enable_ECC_wach string false false +CONFIG.Enable_ECC_wdch string false false +CONFIG.Enable_ECC_wrch string false false +CONFIG.Enable_Reset_Synchronization string false true +CONFIG.Enable_Safety_Circuit string false false +CONFIG.Enable_TLAST string false false +CONFIG.Enable_TREADY string false true +CONFIG.FIFO_Application_Type_axis string false Data_FIFO +CONFIG.FIFO_Application_Type_rach string false Data_FIFO +CONFIG.FIFO_Application_Type_rdch string false Data_FIFO +CONFIG.FIFO_Application_Type_wach string false Data_FIFO +CONFIG.FIFO_Application_Type_wdch string false Data_FIFO +CONFIG.FIFO_Application_Type_wrch string false Data_FIFO +CONFIG.FIFO_Implementation_axis string false Common_Clock_Block_RAM +CONFIG.FIFO_Implementation_rach string false Common_Clock_Block_RAM +CONFIG.FIFO_Implementation_rdch string false Common_Clock_Block_RAM +CONFIG.FIFO_Implementation_wach string false Common_Clock_Block_RAM +CONFIG.FIFO_Implementation_wdch string false Common_Clock_Block_RAM +CONFIG.FIFO_Implementation_wrch string false Common_Clock_Block_RAM +CONFIG.Fifo_Implementation string false Common_Clock_Block_RAM +CONFIG.Full_Flags_Reset_Value string false 0 +CONFIG.Full_Threshold_Assert_Value string false 1023 +CONFIG.Full_Threshold_Assert_Value_axis string false 1023 +CONFIG.Full_Threshold_Assert_Value_rach string false 1023 +CONFIG.Full_Threshold_Assert_Value_rdch string false 1023 +CONFIG.Full_Threshold_Assert_Value_wach string false 1023 +CONFIG.Full_Threshold_Assert_Value_wdch string false 1023 +CONFIG.Full_Threshold_Assert_Value_wrch string false 1023 +CONFIG.Full_Threshold_Negate_Value string false 1022 +CONFIG.HAS_ACLKEN string false false +CONFIG.HAS_TKEEP string false false +CONFIG.HAS_TSTRB string false false +CONFIG.ID_WIDTH string false 0 +CONFIG.INTERFACE_TYPE string false Native +CONFIG.Inject_Dbit_Error string false false +CONFIG.Inject_Dbit_Error_axis string false false +CONFIG.Inject_Dbit_Error_rach string false false +CONFIG.Inject_Dbit_Error_rdch string false false +CONFIG.Inject_Dbit_Error_wach string false false +CONFIG.Inject_Dbit_Error_wdch string false false +CONFIG.Inject_Dbit_Error_wrch string false false +CONFIG.Inject_Sbit_Error string false false +CONFIG.Inject_Sbit_Error_axis string false false +CONFIG.Inject_Sbit_Error_rach string false false +CONFIG.Inject_Sbit_Error_rdch string false false +CONFIG.Inject_Sbit_Error_wach string false false +CONFIG.Inject_Sbit_Error_wdch string false false +CONFIG.Inject_Sbit_Error_wrch string false false +CONFIG.Input_Data_Width string false 32 +CONFIG.Input_Depth string false 1024 +CONFIG.Input_Depth_axis string false 1024 +CONFIG.Input_Depth_rach string false 16 +CONFIG.Input_Depth_rdch string false 1024 +CONFIG.Input_Depth_wach string false 16 +CONFIG.Input_Depth_wdch string false 1024 +CONFIG.Input_Depth_wrch string false 16 +CONFIG.MASTER_ACLK.FREQ_HZ string false 100000000 +CONFIG.MASTER_ACLK.INSERT_VIP string false 0 +CONFIG.M_AXI.INSERT_VIP string false 0 +CONFIG.M_AXIS.INSERT_VIP string false 0 +CONFIG.Master_interface_Clock_enable_memory_mapped string false false +CONFIG.Output_Data_Width string false 32 +CONFIG.Output_Depth string false 1024 +CONFIG.Output_Register_Type string false Embedded_Reg +CONFIG.Overflow_Flag string false false +CONFIG.Overflow_Flag_AXI string false false +CONFIG.Overflow_Sense string false Active_High +CONFIG.Overflow_Sense_AXI string false Active_High +CONFIG.PROTOCOL string false AXI4 +CONFIG.Performance_Options string false First_Word_Fall_Through +CONFIG.Programmable_Empty_Type string false No_Programmable_Empty_Threshold +CONFIG.Programmable_Empty_Type_axis string false No_Programmable_Empty_Threshold +CONFIG.Programmable_Empty_Type_rach string false No_Programmable_Empty_Threshold +CONFIG.Programmable_Empty_Type_rdch string false No_Programmable_Empty_Threshold +CONFIG.Programmable_Empty_Type_wach string false No_Programmable_Empty_Threshold +CONFIG.Programmable_Empty_Type_wdch string false No_Programmable_Empty_Threshold +CONFIG.Programmable_Empty_Type_wrch string false No_Programmable_Empty_Threshold +CONFIG.Programmable_Full_Type string false No_Programmable_Full_Threshold +CONFIG.Programmable_Full_Type_axis string false No_Programmable_Full_Threshold +CONFIG.Programmable_Full_Type_rach string false No_Programmable_Full_Threshold +CONFIG.Programmable_Full_Type_rdch string false No_Programmable_Full_Threshold +CONFIG.Programmable_Full_Type_wach string false No_Programmable_Full_Threshold +CONFIG.Programmable_Full_Type_wdch string false No_Programmable_Full_Threshold +CONFIG.Programmable_Full_Type_wrch string false No_Programmable_Full_Threshold +CONFIG.READ_CLK.FREQ_HZ string false 100000000 +CONFIG.READ_CLK.INSERT_VIP string false 0 +CONFIG.READ_WRITE_MODE string false READ_WRITE +CONFIG.RUSER_Width string false 0 +CONFIG.Read_Clock_Frequency string false 1 +CONFIG.Read_Data_Count string false false +CONFIG.Read_Data_Count_Width string false 11 +CONFIG.Register_Slice_Mode_axis string false Fully_Registered +CONFIG.Register_Slice_Mode_rach string false Fully_Registered +CONFIG.Register_Slice_Mode_rdch string false Fully_Registered +CONFIG.Register_Slice_Mode_wach string false Fully_Registered +CONFIG.Register_Slice_Mode_wdch string false Fully_Registered +CONFIG.Register_Slice_Mode_wrch string false Fully_Registered +CONFIG.Reset_Pin string false true +CONFIG.Reset_Type string false Synchronous_Reset +CONFIG.SLAVE_ACLK.FREQ_HZ string false 100000000 +CONFIG.SLAVE_ACLK.INSERT_VIP string false 0 +CONFIG.SLAVE_ARESETN.INSERT_VIP string false 0 +CONFIG.S_AXI.INSERT_VIP string false 0 +CONFIG.S_AXIS.INSERT_VIP string false 0 +CONFIG.Slave_interface_Clock_enable_memory_mapped string false false +CONFIG.TDATA_NUM_BYTES string false 1 +CONFIG.TDEST_WIDTH string false 0 +CONFIG.TID_WIDTH string false 0 +CONFIG.TKEEP_WIDTH string false 1 +CONFIG.TSTRB_WIDTH string false 1 +CONFIG.TUSER_WIDTH string false 4 +CONFIG.Underflow_Flag string false false +CONFIG.Underflow_Flag_AXI string false false +CONFIG.Underflow_Sense string false Active_High +CONFIG.Underflow_Sense_AXI string false Active_High +CONFIG.Use_Dout_Reset string false true +CONFIG.Use_Embedded_Registers string false false +CONFIG.Use_Embedded_Registers_axis string false false +CONFIG.Use_Extra_Logic string false true +CONFIG.Valid_Flag string false false +CONFIG.Valid_Sense string false Active_High +CONFIG.WRITE_CLK.FREQ_HZ string false 100000000 +CONFIG.WRITE_CLK.INSERT_VIP string false 0 +CONFIG.WUSER_Width string false 0 +CONFIG.Write_Acknowledge_Flag string false false +CONFIG.Write_Acknowledge_Sense string false Active_High +CONFIG.Write_Clock_Frequency string false 1 +CONFIG.Write_Data_Count string false false +CONFIG.Write_Data_Count_Width string false 11 +CONFIG.asymmetric_port_width string false false +CONFIG.axis_type string false FIFO +CONFIG.dynamic_power_saving string false false +CONFIG.ecc_pipeline_reg string false false +CONFIG.enable_low_latency string false false +CONFIG.enable_read_pointer_increment_by2 string false false +CONFIG.rach_type string false FIFO +CONFIG.rdch_type string false FIFO +CONFIG.synchronization_stages string false 2 +CONFIG.synchronization_stages_axi string false 2 +CONFIG.use_dout_register string false false +CONFIG.wach_type string false FIFO +CONFIG.wdch_type string false FIFO +CONFIG.wrch_type string false FIFO +IPDEF string true xilinx.com:ip:fifo_generator:13.2 diff --git a/firmware/FT0/TCM/ipcore_properties/gig_ethernet_pcs_pma_0.txt b/firmware/FT0/TCM_proto/ipcore_properties/gig_ethernet_pcs_pma_0.txt similarity index 100% rename from firmware/FT0/TCM/ipcore_properties/gig_ethernet_pcs_pma_0.txt rename to firmware/FT0/TCM_proto/ipcore_properties/gig_ethernet_pcs_pma_0.txt diff --git a/firmware/FT0/TCM/ipcore_properties/raw_data_fifo.txt b/firmware/FT0/TCM_proto/ipcore_properties/raw_data_fifo.txt similarity index 99% rename from firmware/FT0/TCM/ipcore_properties/raw_data_fifo.txt rename to firmware/FT0/TCM_proto/ipcore_properties/raw_data_fifo.txt index 8629119..93f3c73 100644 --- a/firmware/FT0/TCM/ipcore_properties/raw_data_fifo.txt +++ b/firmware/FT0/TCM_proto/ipcore_properties/raw_data_fifo.txt @@ -4,7 +4,7 @@ CONFIG.ARUSER_Width string false 0 CONFIG.AWUSER_Width string false 0 CONFIG.Add_NGC_Constraint_AXI string false false CONFIG.Almost_Empty_Flag string false false -CONFIG.Almost_Full_Flag string false false +CONFIG.Almost_Full_Flag string false true CONFIG.BUSER_Width string false 0 CONFIG.CORE_CLK.FREQ_HZ string false 100000000 CONFIG.CORE_CLK.INSERT_VIP string false 0 @@ -60,14 +60,14 @@ CONFIG.FIFO_Implementation_wdch string false Common_Cl CONFIG.FIFO_Implementation_wrch string false Common_Clock_Block_RAM CONFIG.Fifo_Implementation string false Common_Clock_Block_RAM CONFIG.Full_Flags_Reset_Value string false 0 -CONFIG.Full_Threshold_Assert_Value string false 4095 +CONFIG.Full_Threshold_Assert_Value string false 4000 CONFIG.Full_Threshold_Assert_Value_axis string false 1023 CONFIG.Full_Threshold_Assert_Value_rach string false 1023 CONFIG.Full_Threshold_Assert_Value_rdch string false 1023 CONFIG.Full_Threshold_Assert_Value_wach string false 1023 CONFIG.Full_Threshold_Assert_Value_wdch string false 1023 CONFIG.Full_Threshold_Assert_Value_wrch string false 1023 -CONFIG.Full_Threshold_Negate_Value string false 4094 +CONFIG.Full_Threshold_Negate_Value string false 3999 CONFIG.HAS_ACLKEN string false false CONFIG.HAS_TKEEP string false false CONFIG.HAS_TSTRB string false false @@ -116,7 +116,7 @@ CONFIG.Programmable_Empty_Type_rdch string false No_Progra CONFIG.Programmable_Empty_Type_wach string false No_Programmable_Empty_Threshold CONFIG.Programmable_Empty_Type_wdch string false No_Programmable_Empty_Threshold CONFIG.Programmable_Empty_Type_wrch string false No_Programmable_Empty_Threshold -CONFIG.Programmable_Full_Type string false No_Programmable_Full_Threshold +CONFIG.Programmable_Full_Type string false Single_Programmable_Full_Threshold_Constant CONFIG.Programmable_Full_Type_axis string false No_Programmable_Full_Threshold CONFIG.Programmable_Full_Type_rach string false No_Programmable_Full_Threshold CONFIG.Programmable_Full_Type_rdch string false No_Programmable_Full_Threshold diff --git a/firmware/FT0/TCM/ipcore_properties/slct_data_fifo.txt b/firmware/FT0/TCM_proto/ipcore_properties/slct_data_fifo.txt similarity index 99% rename from firmware/FT0/TCM/ipcore_properties/slct_data_fifo.txt rename to firmware/FT0/TCM_proto/ipcore_properties/slct_data_fifo.txt index 52b27f5..e454940 100644 --- a/firmware/FT0/TCM/ipcore_properties/slct_data_fifo.txt +++ b/firmware/FT0/TCM_proto/ipcore_properties/slct_data_fifo.txt @@ -14,7 +14,7 @@ CONFIG.Clock_Type_AXI string false Common_Cl CONFIG.Component_Name string false slct_data_fifo CONFIG.DATA_WIDTH string false 64 CONFIG.Data_Count string false false -CONFIG.Data_Count_Width string false 12 +CONFIG.Data_Count_Width string false 14 CONFIG.Disable_Timing_Violations string false false CONFIG.Disable_Timing_Violations_AXI string false false CONFIG.Dout_Reset_Value string false 0 @@ -60,14 +60,14 @@ CONFIG.FIFO_Implementation_wdch string false Common_Cl CONFIG.FIFO_Implementation_wrch string false Common_Clock_Block_RAM CONFIG.Fifo_Implementation string false Independent_Clocks_Block_RAM CONFIG.Full_Flags_Reset_Value string false 1 -CONFIG.Full_Threshold_Assert_Value string false 4095 +CONFIG.Full_Threshold_Assert_Value string false 16000 CONFIG.Full_Threshold_Assert_Value_axis string false 1023 CONFIG.Full_Threshold_Assert_Value_rach string false 1023 CONFIG.Full_Threshold_Assert_Value_rdch string false 1023 CONFIG.Full_Threshold_Assert_Value_wach string false 1023 CONFIG.Full_Threshold_Assert_Value_wdch string false 1023 CONFIG.Full_Threshold_Assert_Value_wrch string false 1023 -CONFIG.Full_Threshold_Negate_Value string false 4094 +CONFIG.Full_Threshold_Negate_Value string false 15999 CONFIG.HAS_ACLKEN string false false CONFIG.HAS_TKEEP string false false CONFIG.HAS_TSTRB string false false @@ -88,7 +88,7 @@ CONFIG.Inject_Sbit_Error_wach string false false CONFIG.Inject_Sbit_Error_wdch string false false CONFIG.Inject_Sbit_Error_wrch string false false CONFIG.Input_Data_Width string false 80 -CONFIG.Input_Depth string false 4096 +CONFIG.Input_Depth string false 16384 CONFIG.Input_Depth_axis string false 1024 CONFIG.Input_Depth_rach string false 16 CONFIG.Input_Depth_rdch string false 1024 @@ -101,7 +101,7 @@ CONFIG.M_AXI.INSERT_VIP string false 0 CONFIG.M_AXIS.INSERT_VIP string false 0 CONFIG.Master_interface_Clock_enable_memory_mapped string false false CONFIG.Output_Data_Width string false 80 -CONFIG.Output_Depth string false 4096 +CONFIG.Output_Depth string false 16384 CONFIG.Output_Register_Type string false Embedded_Reg CONFIG.Overflow_Flag string false false CONFIG.Overflow_Flag_AXI string false false @@ -116,7 +116,7 @@ CONFIG.Programmable_Empty_Type_rdch string false No_Progra CONFIG.Programmable_Empty_Type_wach string false No_Programmable_Empty_Threshold CONFIG.Programmable_Empty_Type_wdch string false No_Programmable_Empty_Threshold CONFIG.Programmable_Empty_Type_wrch string false No_Programmable_Empty_Threshold -CONFIG.Programmable_Full_Type string false No_Programmable_Full_Threshold +CONFIG.Programmable_Full_Type string false Single_Programmable_Full_Threshold_Constant CONFIG.Programmable_Full_Type_axis string false No_Programmable_Full_Threshold CONFIG.Programmable_Full_Type_rach string false No_Programmable_Full_Threshold CONFIG.Programmable_Full_Type_rdch string false No_Programmable_Full_Threshold @@ -129,7 +129,7 @@ CONFIG.READ_WRITE_MODE string false READ_WRIT CONFIG.RUSER_Width string false 0 CONFIG.Read_Clock_Frequency string false 1 CONFIG.Read_Data_Count string false true -CONFIG.Read_Data_Count_Width string false 13 +CONFIG.Read_Data_Count_Width string false 15 CONFIG.Register_Slice_Mode_axis string false Fully_Registered CONFIG.Register_Slice_Mode_rach string false Fully_Registered CONFIG.Register_Slice_Mode_rdch string false Fully_Registered @@ -167,7 +167,7 @@ CONFIG.Write_Acknowledge_Flag string false false CONFIG.Write_Acknowledge_Sense string false Active_High CONFIG.Write_Clock_Frequency string false 1 CONFIG.Write_Data_Count string false true -CONFIG.Write_Data_Count_Width string false 13 +CONFIG.Write_Data_Count_Width string false 15 CONFIG.asymmetric_port_width string false false CONFIG.axis_type string false FIFO CONFIG.dynamic_power_saving string false false diff --git a/firmware/FT0/TCM/ipcore_properties/tcm_data_160to80bit_fifo.txt b/firmware/FT0/TCM_proto/ipcore_properties/tcm_data_160to80bit_fifo.txt similarity index 100% rename from firmware/FT0/TCM/ipcore_properties/tcm_data_160to80bit_fifo.txt rename to firmware/FT0/TCM_proto/ipcore_properties/tcm_data_160to80bit_fifo.txt diff --git a/firmware/FT0/TCM/ipcore_properties/trg_fifo_comp.txt b/firmware/FT0/TCM_proto/ipcore_properties/trg_fifo_comp.txt similarity index 99% rename from firmware/FT0/TCM/ipcore_properties/trg_fifo_comp.txt rename to firmware/FT0/TCM_proto/ipcore_properties/trg_fifo_comp.txt index b59b93e..27c9bd6 100644 --- a/firmware/FT0/TCM/ipcore_properties/trg_fifo_comp.txt +++ b/firmware/FT0/TCM_proto/ipcore_properties/trg_fifo_comp.txt @@ -14,7 +14,7 @@ CONFIG.Clock_Type_AXI string false Common_Cl CONFIG.Component_Name string false trg_fifo_comp CONFIG.DATA_WIDTH string false 64 CONFIG.Data_Count string false false -CONFIG.Data_Count_Width string false 9 +CONFIG.Data_Count_Width string false 12 CONFIG.Disable_Timing_Violations string false false CONFIG.Disable_Timing_Violations_AXI string false false CONFIG.Dout_Reset_Value string false 0 @@ -60,14 +60,14 @@ CONFIG.FIFO_Implementation_wdch string false Common_Cl CONFIG.FIFO_Implementation_wrch string false Common_Clock_Block_RAM CONFIG.Fifo_Implementation string false Independent_Clocks_Block_RAM CONFIG.Full_Flags_Reset_Value string false 1 -CONFIG.Full_Threshold_Assert_Value string false 511 +CONFIG.Full_Threshold_Assert_Value string false 4095 CONFIG.Full_Threshold_Assert_Value_axis string false 1023 CONFIG.Full_Threshold_Assert_Value_rach string false 1023 CONFIG.Full_Threshold_Assert_Value_rdch string false 1023 CONFIG.Full_Threshold_Assert_Value_wach string false 1023 CONFIG.Full_Threshold_Assert_Value_wdch string false 1023 CONFIG.Full_Threshold_Assert_Value_wrch string false 1023 -CONFIG.Full_Threshold_Negate_Value string false 510 +CONFIG.Full_Threshold_Negate_Value string false 4094 CONFIG.HAS_ACLKEN string false false CONFIG.HAS_TKEEP string false false CONFIG.HAS_TSTRB string false false @@ -88,7 +88,7 @@ CONFIG.Inject_Sbit_Error_wach string false false CONFIG.Inject_Sbit_Error_wdch string false false CONFIG.Inject_Sbit_Error_wrch string false false CONFIG.Input_Data_Width string false 76 -CONFIG.Input_Depth string false 512 +CONFIG.Input_Depth string false 4096 CONFIG.Input_Depth_axis string false 1024 CONFIG.Input_Depth_rach string false 16 CONFIG.Input_Depth_rdch string false 1024 @@ -101,7 +101,7 @@ CONFIG.M_AXI.INSERT_VIP string false 0 CONFIG.M_AXIS.INSERT_VIP string false 0 CONFIG.Master_interface_Clock_enable_memory_mapped string false false CONFIG.Output_Data_Width string false 76 -CONFIG.Output_Depth string false 512 +CONFIG.Output_Depth string false 4096 CONFIG.Output_Register_Type string false Embedded_Reg CONFIG.Overflow_Flag string false false CONFIG.Overflow_Flag_AXI string false false @@ -129,7 +129,7 @@ CONFIG.READ_WRITE_MODE string false READ_WRIT CONFIG.RUSER_Width string false 0 CONFIG.Read_Clock_Frequency string false 1 CONFIG.Read_Data_Count string false true -CONFIG.Read_Data_Count_Width string false 10 +CONFIG.Read_Data_Count_Width string false 12 CONFIG.Register_Slice_Mode_axis string false Fully_Registered CONFIG.Register_Slice_Mode_rach string false Fully_Registered CONFIG.Register_Slice_Mode_rdch string false Fully_Registered @@ -157,7 +157,7 @@ CONFIG.Underflow_Sense_AXI string false Active_Hi CONFIG.Use_Dout_Reset string false true CONFIG.Use_Embedded_Registers string false false CONFIG.Use_Embedded_Registers_axis string false false -CONFIG.Use_Extra_Logic string false true +CONFIG.Use_Extra_Logic string false false CONFIG.Valid_Flag string false false CONFIG.Valid_Sense string false Active_High CONFIG.WRITE_CLK.FREQ_HZ string false 100000000 @@ -167,7 +167,7 @@ CONFIG.Write_Acknowledge_Flag string false false CONFIG.Write_Acknowledge_Sense string false Active_High CONFIG.Write_Clock_Frequency string false 1 CONFIG.Write_Data_Count string false true -CONFIG.Write_Data_Count_Width string false 10 +CONFIG.Write_Data_Count_Width string false 12 CONFIG.asymmetric_port_width string false false CONFIG.axis_type string false FIFO CONFIG.dynamic_power_saving string false false diff --git a/firmware/FT0/TCM/ipcore_properties/tri_mode_ethernet_mac_0.txt b/firmware/FT0/TCM_proto/ipcore_properties/tri_mode_ethernet_mac_0.txt similarity index 100% rename from firmware/FT0/TCM/ipcore_properties/tri_mode_ethernet_mac_0.txt rename to firmware/FT0/TCM_proto/ipcore_properties/tri_mode_ethernet_mac_0.txt diff --git a/firmware/FT0/TCM/ipcore_properties/xlx_k7v7_gbt_rx_frameclk_phalgnr_mmcm.txt b/firmware/FT0/TCM_proto/ipcore_properties/xlx_k7v7_gbt_rx_frameclk_phalgnr_mmcm.txt similarity index 100% rename from firmware/FT0/TCM/ipcore_properties/xlx_k7v7_gbt_rx_frameclk_phalgnr_mmcm.txt rename to firmware/FT0/TCM_proto/ipcore_properties/xlx_k7v7_gbt_rx_frameclk_phalgnr_mmcm.txt diff --git a/firmware/FT0/TCM/ipcore_properties/xlx_k7v7_tx_dpram.txt b/firmware/FT0/TCM_proto/ipcore_properties/xlx_k7v7_tx_dpram.txt similarity index 100% rename from firmware/FT0/TCM/ipcore_properties/xlx_k7v7_tx_dpram.txt rename to firmware/FT0/TCM_proto/ipcore_properties/xlx_k7v7_tx_dpram.txt diff --git a/firmware/FT0/TCM/make.tcl b/firmware/FT0/TCM_proto/make.tcl similarity index 96% rename from firmware/FT0/TCM/make.tcl rename to firmware/FT0/TCM_proto/make.tcl index bfe9dc7..b627fd9 100644 --- a/firmware/FT0/TCM/make.tcl +++ b/firmware/FT0/TCM_proto/make.tcl @@ -20,7 +20,7 @@ if { [info exists ::origin_dir_loc] } { } # Set the project name -set project_name "TCM" +set project_name "TCM_proto" # Use project name variable, if specified in the tcl shell if { [info exists ::user_project_name] } { @@ -120,15 +120,15 @@ if {[string equal [get_filesets -quiet sources_1] ""]} { set obj [get_filesets sources_1] # Import local files from the original project set files [list \ - [file normalize "${origin_dir}/hdl/counter32.vhd" ]\ - [file normalize "${origin_dir}/hdl/Flash_prog.vhd" ]\ [file normalize "${origin_dir}/hdl/tcm_proto.vhd" ]\ - [file normalize "${origin_dir}/hdl/pm-spi.vhd" ]\ - [file normalize "${origin_dir}/hdl/cnt_ctrl.vhd" ]\ - [file normalize "${origin_dir}/hdl/trigger_out.vhd" ]\ - [file normalize "${origin_dir}/hdl/tcm_side.vhd" ]\ - [file normalize "${origin_dir}/hdl/HDMIRX.vhd" ]\ - [file normalize "${origin_dir}/../TCM/hdl/BC_correlator.vhd" ]\ + [file normalize "${origin_dir}/../TCM_v1/hdl/counter32.vhd" ]\ + [file normalize "${origin_dir}/../TCM_v1/hdl/Flash_prog.vhd" ]\ + [file normalize "${origin_dir}/../TCM_v1/hdl/pm-spi.vhd" ]\ + [file normalize "${origin_dir}/../TCM_v1/hdl/cnt_ctrl.vhd" ]\ + [file normalize "${origin_dir}/../TCM_v1/hdl/trigger_out.vhd" ]\ + [file normalize "${origin_dir}/../TCM_v1/hdl/tcm_side.vhd" ]\ + [file normalize "${origin_dir}/../TCM_v1/hdl/HDMIRX.vhd" ]\ + [file normalize "${origin_dir}/../TCM_v1/hdl/BC_correlator.vhd" ]\ [file normalize "${origin_dir}/../../common/ipbus/hdl/ipbus_core/udp_dualportram.vhd" ]\ [file normalize "${origin_dir}/../../common/ipbus/hdl/ipbus_core/udp_build_arp.vhd" ]\ [file normalize "${origin_dir}/../../common/ipbus/hdl/ipbus_core/udp_txtransactor_if_simple.vhd" ]\ @@ -219,21 +219,21 @@ set files [list \ [file normalize "${origin_dir}/../../common/gbt-fpga/hdl/gbt_bank/core_sources/gbt_bank.vhd" ]\ [file normalize "${origin_dir}/../../common/gbt-fpga/hdl/gbt_bank/core_sources/gbt_rx/gbt_rx_decoder_gbtframe_syndrom.vhd" ]\ [file normalize "${origin_dir}/../../common/gbt-readout/hdl/GBT_TXRX5.vhd"] \ - [file normalize "${origin_dir}/../../common/gbt-readout/hdl/DataCLK_strobe.vhd" ]\ [file normalize "${origin_dir}/../../common/gbt-readout/hdl/DataConverter_TCM.vhd" ]\ - [file normalize "${origin_dir}/../../common/gbt-readout/hdl/RX_Data_Decoder.vhd" ]\ - [file normalize "${origin_dir}/../../common/gbt-readout/hdl/BC_counter.vhd" ]\ + [file normalize "${origin_dir}/../../common/gbt-readout/hdl/ltu_rx_decoder.vhd" ]\ + [file normalize "${origin_dir}/../../common/gbt-readout/hdl/bc_indicator.vhd" ]\ [file normalize "${origin_dir}/../../common/gbt-readout/hdl/Reset_Generator.vhd" ]\ [file normalize "${origin_dir}/../../common/gbt-readout/hdl/fit_gbt_boardTCM_package.vhd" ]\ [file normalize "${origin_dir}/../../common/gbt-readout/hdl/FIT_GBT_project.vhd" ]\ [file normalize "${origin_dir}/../../common/gbt-readout/hdl/Module_Data_Gen_TCM.vhd" ]\ - [file normalize "${origin_dir}/../../common/gbt-readout/hdl/CRU_ORBC_Gen.vhd" ]\ + [file normalize "${origin_dir}/../../common/gbt-readout/hdl/cru_ltu_emu.vhd" ]\ [file normalize "${origin_dir}/../../common/gbt-readout/hdl/TX_Data_Gen.vhd" ]\ [file normalize "${origin_dir}/../../common/gbt-readout/hdl/Event_selector.vhd" ]\ [file normalize "${origin_dir}/../../common/gbt-readout/hdl/fit_gbt_common_package.vhd" ]\ [file normalize "${origin_dir}/../../common/gbt-readout/hdl/RXDataClkSync.vhd" ]\ [file normalize "${origin_dir}/../../common/gbt-readout/hdl/CRU_packet_Builder.vhd" ]\ - [file normalize "${origin_dir}/../../common/gbt-readout/hdl/Data_Packager.vhd" ]\ + [file normalize "${origin_dir}/../../common/gbt-readout/hdl/snapshot_fifo.vhd" ]\ + [file normalize "${origin_dir}/../../common/gbt-readout/hdl/error_report.vhd" ]\ ] #set imported_files [import_files -fileset sources_1 $files] add_files -norecurse -fileset sources_1 $files diff --git a/firmware/FT0/TCM/xdc/tcm.xdc b/firmware/FT0/TCM_proto/xdc/tcm.xdc similarity index 96% rename from firmware/FT0/TCM/xdc/tcm.xdc rename to firmware/FT0/TCM_proto/xdc/tcm.xdc index 5303bca..fd903b7 100644 --- a/firmware/FT0/TCM/xdc/tcm.xdc +++ b/firmware/FT0/TCM_proto/xdc/tcm.xdc @@ -65,8 +65,10 @@ set_property ASYNC_REG true [get_cells readout_laser_out_ff?_reg] set_property IOB TRUE [get_cells -hierarchical T_o_reg] set_property IOB TRUE [get_cells lasi_reg] -set_property ASYNC_REG true [get_cells {l_on_reg l_on0_reg}] +#set_property ASYNC_REG true [get_cells {l_on_reg l_on0_reg}] set_property ASYNC_REG true [get_cells {laser_t0_reg laser_t_reg}] +set_property ASYNC_REG true [get_cells {tblock1_reg tblock2_reg}] + set_property ASYNC_REG true [get_cells B_rdy0_reg] set_property ASYNC_REG true [get_cells B_rdy1_reg] diff --git a/firmware/FT0/TCM/xdc/tcm_pins.xdc b/firmware/FT0/TCM_proto/xdc/tcm_pins.xdc similarity index 100% rename from firmware/FT0/TCM/xdc/tcm_pins.xdc rename to firmware/FT0/TCM_proto/xdc/tcm_pins.xdc diff --git a/firmware/FT0/TCM/xdc/timing.xdc b/firmware/FT0/TCM_proto/xdc/timing.xdc similarity index 72% rename from firmware/FT0/TCM/xdc/timing.xdc rename to firmware/FT0/TCM_proto/xdc/timing.xdc index 5382c70..57f62a7 100644 --- a/firmware/FT0/TCM/xdc/timing.xdc +++ b/firmware/FT0/TCM_proto/xdc/timing.xdc @@ -2,7 +2,10 @@ set_false_path -through [get_pins ipbus_module/clocks/nuke_i_reg/Q] set_max_delay -datapath_only -from [get_clocks *] -to [get_ports {LA?[*] LAC* LED*}] 15.000 -set_false_path -from [get_clocks RXDataCLK] -to [get_cells {FitGbtPrg/gbt_bank_gen.gbtBankDsgn/GBT_Status_O_reg[gbtRx_ErrorDet] FitGbtPrg/gbt_bank_gen.gbtBankDsgn/GBT_Status_O_reg[gbtRx_Ready] IsRXData0_reg}] +set_false_path -from [get_clocks RXDataCLK] -to [get_cells {FitGbtPrg/gbt_bank_gen.gbtBankDsgn/gbtRx_ErrorDet_ff_reg FitGbtPrg/gbt_bank_gen.gbtBankDsgn/GBT_Status_O_reg[*] IsRXData0_reg}] +set_false_path -from [get_clocks RXDataCLK] -to [get_cells {FitGbtPrg/gbt_bank_gen.gbtBankDsgn/gbtRx_ErrorDet_ff_reg FitGbtPrg/gbt_bank_gen.gbtBankDsgn/gbtRx_ErrorDet_ff*}] +set_false_path -from [get_clocks RXDataCLK] -to [get_cells {FitGbtPrg/gbt_bank_gen.gbtBankDsgn/gbtRx_ErrorDet_ff_reg FitGbtPrg/gbt_bank_gen.gbtBankDsgn/Rx_Ready_ff*}] + ## GBT RX: ##-------- @@ -23,21 +26,17 @@ set_multicycle_path -hold -start -from [get_clocks RxWordCLK] -to [get_cells {Fi set_max_delay -datapath_only -from [get_clocks CLKsys40] -to [get_pins readout_laser_out_ff0_reg/D] 3.000 set_max_delay -datapath_only -from [get_clocks MCLKA] -to [get_cells laser_t0_reg] 3.000 -set_multicycle_path -setup -from [get_clocks CLKA320] -to [get_cells {{C_vertex/T_?_reg} {Rd_word_reg[*]} V_str_reg}] 2 -set_multicycle_path -hold -from [get_clocks CLKA320] -to [get_cells {{C_vertex/T_?_reg} {Rd_word_reg[*]} V_str_reg}] 1 +set_multicycle_path -setup -from [get_clocks CLKA320] -to [get_cells {{*/T_?_reg} *_str_reg gbt_wr_reg}] 2 +set_multicycle_path -hold -from [get_clocks CLKA320] -to [get_cells {{*/T_?_reg} *_str_reg gbt_wr_reg}] 1 +set_multicycle_path -setup -from [get_cells {{tcma/Ampl_o_reg[*]} {tcma/AmplI_o_reg[*]} {tcma/Nchan_A_reg[*]} {tcma/Time_o_reg[*]} {tcma/Avg_reg[*]} {AmplC_reg[*]} {Nchan_C_reg[*]} {TimeC_reg[*]} t_blk_reg}] -to [get_cells {Rd_word_reg[*]}] 2 +set_multicycle_path -hold -from [get_cells {{tcma/Ampl_o_reg[*]} {tcma/AmplI_o_reg[*]} {tcma/Nchan_A_reg[*]} {tcma/Time_o_reg[*]} {tcma/Avg_reg[*]} {AmplC_reg[*]} {Nchan_C_reg[*]} {TimeC_reg[*]} t_blk_reg}] -to [get_cells {Rd_word_reg[*]}] 1 set_multicycle_path -setup -from [get_cells {tcma/NC_reg[?][?]}] -to [get_clocks CLKA320] 2 set_multicycle_path -hold -from [get_cells {tcma/NC_reg[?][?]}] -to [get_clocks CLKA320] 1 set_multicycle_path -setup -from [get_cells {tcmc/NC_reg[?][?]}] -to [get_clocks CLKC320] 2 set_multicycle_path -hold -from [get_cells {tcmc/NC_reg[?][?]}] -to [get_clocks CLKC320] 1 -set_multicycle_path -setup -from [get_cells {{tcma/Ampl_o_reg[*]} {AmplC_reg[*]}}] -to [get_cells {C_FC/T_?_reg C_SC/T_?_reg {Rd_word_reg[*]} gbt_wr_reg SC_str_reg CC_str_reg}] 2 -set_multicycle_path -hold -from [get_cells {{tcma/Ampl_o_reg[*]} {AmplC_reg[*]}}] -to [get_cells {C_FC/T_?_reg C_SC/T_?_reg {Rd_word_reg[*]} gbt_wr_reg SC_str_reg CC_str_reg}] 1 - -set_multicycle_path -setup -from [get_cells -hierarchical -filter { PRIMITIVE_TYPE =~ BMEM.bram.* && NAME =~ "m_cr*/m0/*"}] -to [get_clocks CLKA320] 2 -set_multicycle_path -hold -from [get_cells -hierarchical -filter { PRIMITIVE_TYPE =~ BMEM.bram.* && NAME =~ "m_cr*/m0/*"}] -to [get_clocks CLKA320] 1 - set_max_delay -datapath_only -from [get_clocks CLKC320] -to [get_clocks CLKA320] 3.000 @@ -51,13 +50,17 @@ set_false_path -from [get_cells sreset_reg -include_replicated_objects] #set_false_path -from [get_cells FitGbtPrg/Reset_Generator_comp/GenRes_DataClk_ff*_reg] -to [all_registers] # RX Sync comp ------------------------------------- -set_max_delay -datapath_only -from [get_clocks RXDataCLK] -to [get_cells {FitGbtPrg/RxData_ClkSync_comp/RX_DATA_DATACLK_reg[*]}] 3.000 -set_max_delay -datapath_only -from [get_clocks RXDataCLK] -to [get_cells FitGbtPrg/RxData_ClkSync_comp/RX_IS_DATA_DATACLK_reg] 3.000 +set_max_delay -datapath_only -from [get_clocks RXDataCLK] -to [get_cells {FitGbtPrg/RxData_ClkSync_comp/RX_DATA_sysclk_reg[*]}] 3.000 +set_max_delay -datapath_only -from [get_clocks RXDataCLK] -to [get_cells {FitGbtPrg/RxData_ClkSync_comp/RX_IS_DATA_sysclk_reg*}] 3.000 set_max_delay -datapath_only -from [get_clocks RXDataCLK] -to [get_cells FitGbtPrg/RxData_ClkSync_comp/RX_CLK_from00_reg] 2.000 +set_property ASYNC_REG true [get_cells FitGbtPrg/RxData_ClkSync_comp/RX_CLK_from00_reg] +set_property ASYNC_REG true [get_cells FitGbtPrg/RxData_ClkSync_comp/RX_CLK_from01_reg] +set_multicycle_path 8 -setup -from [get_clocks TX_CLK] -to [get_pins FitGbtPrg/RxData_ClkSync_comp/rx_error_reset_sclk_reg/D] +set_multicycle_path 7 -hold -end -from [get_clocks TX_CLK] -to [get_pins FitGbtPrg/RxData_ClkSync_comp/rx_error_reset_sclk_reg/D] set_false_path -from [get_clocks -include_generated_clocks MCLKA] -to [get_clocks RXDataCLK] -set_false_path -from [get_clocks RXDataCLK] -to [get_cells {rout_buf_reg[*]}] +set_false_path -from [get_clocks RXDataCLK] -to [get_cells rout_buf_reg[*]] diff --git a/firmware/FT0/TCM/hdl/BC_correlator.vhd b/firmware/FT0/TCM_v1/hdl/BC_correlator.vhd similarity index 74% rename from firmware/FT0/TCM/hdl/BC_correlator.vhd rename to firmware/FT0/TCM_v1/hdl/BC_correlator.vhd index b350f1b..0d80133 100644 --- a/firmware/FT0/TCM/hdl/BC_correlator.vhd +++ b/firmware/FT0/TCM_v1/hdl/BC_correlator.vhd @@ -47,8 +47,7 @@ end BC_correlator; architecture RTL of BC_correlator is -signal ack0, clr_mem, clr_req, inc_i : STD_LOGIC; -signal wea : STD_LOGIC_vector (0 downto 0); +signal ack0, clr_mem, clr_req, wea : STD_LOGIC; signal m_rd, m_wr : STD_LOGIC_vector (31 downto 0); COMPONENT BC_corr_mem @@ -69,32 +68,26 @@ END COMPONENT; begin -m0 : BC_corr_mem PORT MAP (clka => clk320, wea => wea, addra => BC_cou, dina => m_wr, douta => m_rd, clkb => ipb_clk, web => "0", addrb => addr, dinb => (others=>'0'), doutb => data); +m0 : BC_corr_mem PORT MAP (clka => clk320, wea(0) => wea, addra => BC_cou, dina => m_wr, douta => m_rd, clkb => ipb_clk, web => "0", addrb => addr, dinb => (others=>'0'), doutb => data); -m_wr<= x"0000000" & "000" & inc_i when (clr_mem='1') else m_rd+1; + +wea<= '1' when ((clr_mem='1') or (inc='1')) and (mt_cou="110") else '0'; process(clk320) begin if (clk320'event and clk320='1') then - if (clr='1') then clr_req<='1'; else - if (clr_req='1') and (BC_cou=0) and (mt_cou="010") then clr_req<='0'; end if; - end if; - -if (BC_cou=0) and (mt_cou="010") then clr_mem<=clr_req; end if; - -if (mt_cou="011") then - - inc_i<= inc; - - if (clr_mem='1') or (inc='1') then wea(0)<= '1'; end if; - -else - wea(0)<= '0'; +if (clr='1') then clr_req<='1'; clr_mem<='0'; + elsif (BC_cou=0) and (mt_cou="010") then + clr_req<='0'; clr_mem<=clr_req; end if; - +if (mt_cou="101") then + if (clr_mem='1') then m_wr<= x"0000000" & "000" & inc; + elsif (m_rd/=x"FFFFFFFF") then m_wr<= m_rd+1; + end if; +end if; end if; end process; diff --git a/firmware/FT0/TCM/hdl/Flash_prog.vhd b/firmware/FT0/TCM_v1/hdl/Flash_prog.vhd similarity index 100% rename from firmware/FT0/TCM/hdl/Flash_prog.vhd rename to firmware/FT0/TCM_v1/hdl/Flash_prog.vhd diff --git a/firmware/FT0/TCM/hdl/HDMIRX.vhd b/firmware/FT0/TCM_v1/hdl/HDMIRX.vhd similarity index 94% rename from firmware/FT0/TCM/hdl/HDMIRX.vhd rename to firmware/FT0/TCM_v1/hdl/HDMIRX.vhd index 8b034da..e7fd8db 100644 --- a/firmware/FT0/TCM/hdl/HDMIRX.vhd +++ b/firmware/FT0/TCM_v1/hdl/HDMIRX.vhd @@ -58,7 +58,8 @@ entity hdmirx is bp_stable : out STD_LOGIC; dl_low : out STD_LOGIC; dl_high : out STD_LOGIC; - mast_dl_err : out STD_LOGIC; + mast_dl_low : out STD_LOGIC; + mast_dl_high : out STD_LOGIC; mast_stable : out STD_LOGIC; dly_ctrl_ena : in STD_LOGIC; syn_err : out STD_LOGIC; @@ -68,6 +69,7 @@ end hdmirx; architecture RTL of hdmirx is +type vect19_arr is array (3 downto 0) of std_logic_vector (18 downto 0); type vect8_arr is array (3 downto 0) of std_logic_vector (7 downto 0); type vect6_arr is array (3 downto 0) of std_logic_vector (5 downto 0); type vect5_arr is array (3 downto 0) of std_logic_vector (4 downto 0); @@ -76,7 +78,8 @@ type vect4_arr is array (3 downto 0) of std_logic_vector (3 downto 0); signal CLK320B, clk320_90B, lock, TD_eq, TD_bits, TD_idle, l_rdy, bitpos_ok_i : STD_LOGIC; signal dly_clr, dl_ce0, dl_inc0, link_ok, link_lost, dly_clr0, dly_clr1, dly_ctrl_ena0, dly_ctrl_ena1, dl_low0, dl_high0, dl_low1, dl_high1, mast_stable_i : STD_LOGIC; -signal sample, sig_loss_cou, TTsr : vect8_arr; +signal sig_loss_cou : vect19_arr; +signal sample, TTsr : vect8_arr; signal sig_stable_cou : vect6_arr; signal dvalue, ph_cnt : vect5_arr; @@ -165,7 +168,7 @@ if (CLK320'event and CLK320='1') then for i in 0 to 3 loop sample(i)(7 downto 4)<=sample(i)(3 downto 0); - if (edge(i)='1') then sig_loss_cou(i)<=x"00"; + if (edge(i)='1') then sig_loss_cou(i)<= (others=>'0'); else if (sig_lost(i)='0') then sig_loss_cou(i)<= sig_loss_cou(i)+1; end if; end if; @@ -187,7 +190,7 @@ if (dvalue(i)="11111") then dl_high_i(i)<= '1'; else dl_high_i(i)<='0'; end if; else if ( mast_stable_i='1') then if (edge(i)='1') then - if ((ph_cnt(i)="11111") and (el(i)='1') and (dl_high_i(i)='0')) or ((ph_cnt(i)="00000") and (el(i)='0') and (dl_low_i(i)='0')) then dl_ce(i)<='1'; dl_inc(i)<=el(i); ph_cnt(i)<="01111"; + if ((ph_cnt(i)="11110") and (el(i)='1') and (dl_high_i(i)='0')) or ((ph_cnt(i)=0) and (el(i)='0') and (dl_low_i(i)='0')) then dl_ce(i)<='1'; dl_inc(i)<=el(i); ph_cnt(i)<="01111"; else if (el(i)='1') then ph_cnt(i)<=ph_cnt(i)+1; else ph_cnt(i)<=ph_cnt(i)-1; end if; end if; @@ -210,7 +213,7 @@ if (dvalue(i)="11111") then dl_high_i(i)<= '1'; else dl_high_i(i)<='0'; end if; if (rst='1') or (sig_lost(0)='1') or (ena='0') or ((master='0') and (dly_ctrl_ena='0')) then ph_cnt(0)<="01111"; else if (edge(0)='1') then - if ((ph_cnt(0)="11111") and (el(0)='1') and (dl_high_i(0)='0')) or ((ph_cnt(0)="00000") and (el(0)='0') and (dl_low_i(0)='0')) then dl_ce0<='1'; + if ((ph_cnt(0)="11110") and (el(0)='1') and (dl_high_i(0)='0')) or ((ph_cnt(0)=0) and (el(0)='0') and (dl_low_i(0)='0')) then dl_ce0<='1'; dl_inc0<=el(0); ph_cnt(0)<="01111"; else if (el(0)='1') then ph_cnt(0)<=ph_cnt(0)+1; else ph_cnt(0)<=ph_cnt(0)-1; end if; @@ -274,7 +277,7 @@ edge(i)<= el(i) or ((not sample(i)(5)) and sample(i)(4)) or ((not sample(i)(4)) el(i)<= ((not sample(i)(7)) and sample(i)(6)) or ((not sample(i)(6)) and sample(i)(5)); -sig_lost(i)<= '1' when (sig_loss_cou(i)=x"FF") else '0'; +sig_lost(i)<= '1' when (sig_loss_cou(i)=320000) else '0'; sig_stable(i)<= '1' when (sig_stable_cou(i)="111111") else '0'; @@ -283,7 +286,7 @@ end generate; dl_low0<= ena when (dl_low_i(3 downto 1)/="000") or ((master='0') and (dl_low_i(0)='1')) else '0'; dl_high0<= ena when (dl_high_i(3 downto 1)/="000") or ((master='0') and (dl_high_i(0)='1')) else '0'; -mast_dl_err <= dl_low_i(0) or dl_high_i(0); +mast_dl_low <= dl_low_i(0); mast_dl_high <= dl_high_i(0); TLogic: for i in 0 to 7 generate TDV(i)<= (TTsr(0)(i) and TTsr(1)(i) and TTsr(2)(i) and TTsr(3)(i)); diff --git a/firmware/FT0/TCM/hdl/cnt_ctrl.vhd b/firmware/FT0/TCM_v1/hdl/cnt_ctrl.vhd similarity index 100% rename from firmware/FT0/TCM/hdl/cnt_ctrl.vhd rename to firmware/FT0/TCM_v1/hdl/cnt_ctrl.vhd diff --git a/firmware/FT0/TCM/hdl/counter32.vhd b/firmware/FT0/TCM_v1/hdl/counter32.vhd similarity index 100% rename from firmware/FT0/TCM/hdl/counter32.vhd rename to firmware/FT0/TCM_v1/hdl/counter32.vhd diff --git a/firmware/FT0/TCM/hdl/pm-spi.vhd b/firmware/FT0/TCM_v1/hdl/pm-spi.vhd similarity index 100% rename from firmware/FT0/TCM/hdl/pm-spi.vhd rename to firmware/FT0/TCM_v1/hdl/pm-spi.vhd diff --git a/firmware/FT0/TCM_v1/hdl/tcm.vhd b/firmware/FT0/TCM_v1/hdl/tcm.vhd index 0fcce6c..3db3fc0 100644 --- a/firmware/FT0/TCM_v1/hdl/tcm.vhd +++ b/firmware/FT0/TCM_v1/hdl/tcm.vhd @@ -159,14 +159,13 @@ type rdout_stat_arr is array (7 downto 0) of std_logic_vector (31 downto 0); signal HDMIA_P, HDMIA_N, HDMIC_P, HDMIC_N, TDA_P, TDA_N, TDC_P, TDC_N : HDMI_trig; signal TDA, TDC, TDC0, TDC1, TDC2 : Trgdat; -signal hdmia_config, hdmic_config, Status_A, Status_C, f_out, f_inp, l_mode, l_patt0, l_patt1, Orbit_ID, flash_data_out, t_stmp, rout_buf, mcu_ts, bc_corrl, bc_corrA, bc_corrC : STD_LOGIC_VECTOR (31 downto 0); +signal hdmia_config, hdmic_config, Status_A, Status_C, f_out, f_inp, l_mode, l_patt0, l_patt1, Orbit_ID, flash_data_out, t_stmp, rout_buf, mcu_ts, bc_corrl, bc_corrA, bc_corrC, bc_maskO : STD_LOGIC_VECTOR (31 downto 0); signal trig_mod: STD_LOGIC_VECTOR (14 downto 0); signal trg_r_wr : STD_LOGIC_VECTOR (4 downto 0); signal trg_r : Tout_arr; signal count_r : cou_arr; signal Tout_sel, Tmode_sel : STD_LOGIC; -signal CLK320A, CLK320C, Vertex, Vertex_0, OrA_i, OrC_i, OrA,S, OrC, SC, SC_0, C, C_0, B_rdy, B_rdy0, B_rdy1, B_rdy2, B_rdy3, OrC_B, OrC_B0, OrC_B1, OrC_B2, reset, rsti, lasi, irqi, mgtclk, clka, clkc, LCLK, LCLKI : STD_LOGIC; -signal clksys40 : std_logic; +signal CLK320A, CLK320C, Vertex, Vertex_0, OrA_i, OrC_i, OrA,S, OrC, SC, SC_0, C, C_0, B_rdy, B_rdy0, B_rdy1, B_rdy2, B_rdy3, OrA_B, OrC_B, OrC_B0, OrC_B1, OrC_B2, reset, rsti, lasi, irqi, mgtclk, clka, clkc, LCLK, LCLKI : STD_LOGIC; signal CSi, MOSIi, MISOi, SCKi : STD_LOGIC; signal bitcnt_A, bitcnt_C : STD_LOGIC_VECTOR (2 downto 0); signal Tcnt_cnt : STD_LOGIC_VECTOR (3 downto 0); @@ -201,13 +200,14 @@ signal SC_A, C_A, SC_C, C_C, Treg_data : STD_LOGIC_VECTOR (15 downto 0); signal AmplA, AmplC, AmplC0, AmplC1, AmplC2 : STD_LOGIC_VECTOR (16 downto 0); signal AmplS : STD_LOGIC_VECTOR (17 downto 0); signal Treg_addr : STD_LOGIC_VECTOR (2 downto 0); -signal TimeC, TimeC0, TimeC1, TimeC2, TimeA : STD_LOGIC_VECTOR (8 downto 0); +signal TimeC, TimeC0, TimeC1, TimeC2, TimeA, TimeA_rd, TimeC_rd : STD_LOGIC_VECTOR (8 downto 0); signal TimeA_o, TimeC_o : STD_LOGIC_VECTOR (15 downto 0); signal AvgA, AvgC : STD_LOGIC_VECTOR (13 downto 0); signal TresbM, TdiffM : STD_LOGIC_VECTOR (23 downto 0); -signal hdmiac_select, hdmicc_select, hdmias_select, hdmics_select, pll_lock_a, pll_lock_c, hdmis_ack, mul_ena, mul_enc, sideA_OK, sideC_OK, stat_clrA, stat_clrC, as_chg, cs_chg, rst_fl, as_blk, cs_blk, hdmi_to0, hdmi_to : STD_LOGIC; -signal PM_tcou : STD_LOGIC_VECTOR (23 downto 0); +signal hdmiac_select, hdmicc_select, hdmias_select, hdmics_select, pll_lock_a, pll_lock_c, hdmis_ack, mul_ena, mul_enc, sideA_OK, sideC_OK, stat_clr_cmd, as_chg, cs_chg, rst_fl, as_blk, cs_blk, hdmi_to0, hdmi_to : STD_LOGIC; +signal PM_tcou : STD_LOGIC_VECTOR (25 downto 0); signal dly_rst, cnt_rd, pm_adr_sel, pm_rdy, cnt_ctrl_sel, cnt_ctrl_rdy, ipb_locked, cnt_clr, cnt_lock, Tcnt_sel, Tcnt_0_rd, cnt_lock0, cnt_lock1, cnt_lock2, Tcnt_clr, cnt_clr0, cnt_clr1, cnt_clr2, Tcnt_ack, Tcnt_err : STD_LOGIC; +signal Ccnt_clr, Ccnt_clr0, Ccnt_clr1, Ccnt_clr2, CCcnt_clr : STD_LOGIC; signal fifo_sel, fifo_csel, f_rd, f_empty, f_wr, f_full, lclk160, lmode_sel, lpatt0_sel, lpatt1_sel, l_on, l_on0, l_on1, l_tg1, l_tg, l_fbin, l_fbout, a_t, a0_t, an_t : STD_LOGIC; signal l_cnt : STD_LOGIC_VECTOR (1 downto 0); signal f_cnt : STD_LOGIC_VECTOR (9 downto 0); @@ -217,24 +217,36 @@ signal lpatt_cnt, Nchan_A, Nchan_C, Nchan_C0, Nchan_C1, Nchan_C2 : STD_LOGIC_VEC signal lpatt_sreg : STD_LOGIC_VECTOR (63 downto 0); signal lfreq_cnt : STD_LOGIC_VECTOR (23 downto 0); signal BC_cou : STD_LOGIC_VECTOR(11 downto 0); -signal ldr : STD_LOGIC_VECTOR(3 downto 0); -signal Tmode : STD_LOGIC_VECTOR(7 downto 0); +signal ldr, ldrm : STD_LOGIC_VECTOR(3 downto 0); +signal Tmode : STD_LOGIC_VECTOR(9 downto 0); signal Rd_word, FIFO_in : STD_LOGIC_VECTOR(159 downto 0); -signal gbt_wr, gbt_empty, rdoutc_sel, rdoutc_ack, rdoutc_wr, rdouts_sel, RST_req : STD_LOGIC; ---signal readout_conf : rdout_conf_arr; ---signal readout_stat : rdout_stat_arr; -signal readout_conf : cntr_reg_addrreg_type; -signal readout_stat : status_reg_addrreg_type; +signal gbt_wr, gbt_empty, rdoutc_sel, rdoutc_ack, rdoutc_wr, rdouts_sel, rdouts_rdy, RST_req : STD_LOGIC; +signal rdouts_cnt, bc_mask : STD_LOGIC_VECTOR(1 DOWNTO 0); +signal readout_control_reg : ctrl_reg_t; +signal readout_status_reg : stat_reg_t; signal New_BCID : STD_LOGIC; -signal las_o, l_st, flshreg_sel, bkgndA, bkgndC, bkgndC0, bkgndC1, bkgndC2, bgA_inc, bgC_inc, bgOr, bgAnd, orA_str, orA_cnt, orC_cnt, Or_or, Or_and, Bg_Aclr, Bg_Cclr, Bg_Orclr, Bg_Andclr, sca, scc, ca, cc, scb, cb : STD_LOGIC; -signal tstamp_sel, d_rd, d_rdy, adc_sel, adc_sel1, rout_lock0, rout_lock1, rout_lock2, PM_rst, cctrl_rst, clk_src, clk_l, clk_frs, mcuts_sel, pmena_sel, pm_err, bccorr_sel, bccorr_ack, corr_inc, SC_str, CC_str, V_str : STD_LOGIC; -signal bccorrA_sel, bccorrC_sel, bccorr_ack0, bccorr_rd : STD_LOGIC; +signal las_o, l_st, l_st0, l_st1, flshreg_sel, NoiseA, NoiseC, NoiseC0, NoiseC1, NoiseC2, NoiseA_inc, NoiseC_inc, NoiseAll, orA_str, Interact, OrA_T, OrC_T, Interact_T, V_T, sca, scc, ca, cc, scb, cb, BG_A, BG_C : STD_LOGIC; +signal tstamp_sel, d_rd, d_rdy, adc_sel, adc_sel1, rout_lock0, rout_lock1, rout_lock2, PM_rst, cctrl_rst, clk_src, clk_l, clk_frs, mcuts_sel, pmena_sel, pm_err, bccorr_sel, bccorr_ack, corr_inc, SC_str, CC_str, V_str, inRst : STD_LOGIC; +signal bccorrA_sel, bccorrC_sel, bccorr_ack0, bccorr_rd, bc_mask_sel, corr_inc0 : STD_LOGIC; signal d_addr : STD_LOGIC_VECTOR(6 DOWNTO 0); signal d_sns : STD_LOGIC_VECTOR(15 DOWNTO 0); signal rx_phase_status : std_logic_vector(3 downto 0); -signal laser_t0, laser_t : std_logic; +signal laser_t, tr_valid, tblock_sel, tblock0, tblock, tblock1, tblock2, t_blk : std_logic; signal pm_ena : std_logic_vector(19 downto 0) := x"00000"; +signal tblock_md : std_logic_vector(7 downto 0); +signal tblock_dly : STD_LOGIC_VECTOR (65 downto 0); +signal tblock_mux : STD_LOGIC_VECTOR (2 downto 0); + +signal AmplAI, AmplAO : STD_LOGIC_VECTOR (15 downto 0); +signal nsca, nscc, nscb, sct, nt, irt, ort, ovtx, orct, sc_i, c_i, avgt_sel, avgt_lk0, avgt_lk, RX_err_ipb, GBT_rdy_ipb : STD_LOGIC; +signal Nchan_S : STD_LOGIC_VECTOR (7 downto 0); +signal TimeAavg, TimeCavg : STD_LOGIC_VECTOR (18 downto 0); + +signal lasbc : STD_LOGIC; + +signal rdout_errf_rd, rdout_errf_rd0, rdout_errf_rd1, rdout_errf_rd2, rdout_errc, rdout_errc0, rdout_errc1, rdout_errc2 : STD_LOGIC; + component tcm_side is Port (CLKA : in STD_LOGIC; @@ -260,7 +272,9 @@ component tcm_side is Avg_o : out STD_LOGIC_VECTOR (13 downto 0); Nchan : out STD_LOGIC_VECTOR (6 downto 0); req : out STD_LOGIC_VECTOR (9 downto 0); - bkgnd : out STD_LOGIC + bkgnd : out STD_LOGIC; + AmplI_o : out STD_LOGIC_VECTOR (15 downto 0); + AmplO_o : out STD_LOGIC_VECTOR (15 downto 0) ); end component; @@ -352,11 +366,12 @@ end component; -- ############################################### -- ######### GBT Readout ######################## -- ############################################### - signal FIT_GBT_status : FIT_GBT_status_type; - signal FIT_GBT_control : CONTROL_REGISTER_type; + signal readout_status : readout_status_t; + signal readout_control : readout_control_t; signal Data_from_FITrd : std_logic_vector(GBT_data_word_bitdepth-1 downto 0); signal IsData_from_FITrd : STD_LOGIC; + signal RxData_rxclk_from_GBT : std_logic_vector(GBT_data_word_bitdepth-1 downto 0); signal IsRxData_rxclk_from_GBT : STD_LOGIC; @@ -364,15 +379,12 @@ end component; signal TCM_data_toreadout : board_data_type; signal gbt_global_status : std_logic_vector(3 downto 0); - signal readout_laser_out, readout_laser_out_ff0, readout_laser_out_ff1 : std_logic; - - signal ipbus_control_reg : cntr_reg_addrreg_type; - signal ipbus_status_reg: status_reg_addrreg_type; - + signal readout_laser_out : std_logic; + signal readout_err_rden, err_report_fifo_rden : std_logic; component FIT_GBT_project is generic ( - GENERATE_GBT_BANK : integer := 1 + IS_SIMULATION : integer := 0 ); Port ( @@ -382,9 +394,15 @@ end component; MgtRefClk_I : in STD_LOGIC; -- 200MHz ref clock RxDataClk_I : in STD_LOGIC; -- 40MHz data clock in RX domain GBT_RxFrameClk_O : out STD_LOGIC; --Rx GBT frame clk 40MHz + FSM_Clocks_O : out rdclocks_t; + IPbusClk_I : in std_logic; -- IPbus clock for error fifo read + err_report_fifo_rden_i : in std_logic; -- IPbus error report fifo read enable + Board_data_I : in board_data_type; --PM or TCM data - Control_register_I : in CONTROL_REGISTER_type; + Control_register_I : in readout_control_t; + errors_rden_I : in std_logic; -- status register EA (errors) was read + MGT_RX_P_I : in STD_LOGIC; MGT_RX_N_I : in STD_LOGIC; @@ -405,11 +423,7 @@ end component; IsRxData_rxclk_from_GBT_O : out STD_LOGIC; -- FIT readour status, including BCOR_ID to PM/TCM - FIT_GBT_status_O : out FIT_GBT_status_type; - rx_ph320 : out std_logic_vector(2 downto 0); - ph_error320 : out std_logic - - --GPIO_O : out std_logic_vector(15 downto 0) + readout_status_o : out readout_status_t ); end component; -- ############################################### @@ -535,10 +549,29 @@ END COMPONENT; ); END COMPONENT; +COMPONENT Mask_mem + PORT ( + clka : IN STD_LOGIC; + wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0); + dina : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + douta : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + clkb : IN STD_LOGIC; + enb : IN STD_LOGIC; + web : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + addrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dinb : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) + ); +END COMPONENT; attribute IODELAY_GROUP : STRING; attribute IODELAY_GROUP of IDL1: label is "TCM_DLY"; +-- attribute mark_debug : string; +-- attribute mark_debug of Data_from_FITrd : signal is "true"; +-- attribute mark_debug of IsData_from_FITrd : signal is "true"; + begin HDMIA_P(0)<=HDMIA0_P; HDMIA_N(0)<=HDMIA0_N; HDMIC_P(0)<=HDMIC0_P; HDMIC_N(0)<=HDMIC0_N; @@ -707,10 +740,6 @@ ipbus_module: IPBUS_basex_infra port map( fl_upg: FLASH generic map (clk_freq => 31250 ) port map (rst=>ipb_rst, clk => ipb_clk, data_in =>ipb_data_out, data_out =>flash_data_out, A =>ipb_addr(1 downto 0), wr_flshreg =>ipb_iswr, rd_flshreg =>ipb_isrd, flshreg_sel=>flshreg_sel, FSEL =>FSEL, FMOSI =>FMOSI, FMISO =>FMISO); -TX_CLK<=clksys40; - - - -- ################################################################################################# -- ################# FIT GBT Readout ########################################################## @@ -738,19 +767,26 @@ TX_CLK<=clksys40; -- FIT GBT project ===================================== FitGbtPrg: FIT_GBT_project generic map( - GENERATE_GBT_BANK => 1 + IS_SIMULATION => 0 ) Port map( RESET_I => sreset, SysClk_I => CLK320A, - DataClk_I => clksys40, + DataClk_I => TX_CLK, MgtRefClk_I => MGTCLK, RxDataClk_I => RX_CLK, -- 40MHz data clock in RX domain (loop back) GBT_RxFrameClk_O => RX_CLK, + FSM_Clocks_O => open, + + -- not connected + IPbusClk_I => TX_CLK, + err_report_fifo_rden_i => err_report_fifo_rden, Board_data_I => TCM_data_toreadout, - Control_register_I => FIT_GBT_control, + Control_register_I => readout_control, + errors_rden_I => readout_err_rden, + MGT_RX_P_I => GBT_RX_P, MGT_RX_N_I => GBT_RX_N, @@ -767,18 +803,16 @@ FitGbtPrg: FIT_GBT_project RxData_rxclk_from_GBT_O => RxData_rxclk_from_GBT, IsRxData_rxclk_from_GBT_O => IsRxData_rxclk_from_GBT, - rx_ph320 => rx_phase_status(2 downto 0), - ph_error320 => rx_phase_status(3), - FIT_GBT_status_O => FIT_GBT_status + readout_status_o => readout_status -- GPIO_O => GPIO ); -- ===================================================== GBT_is_RXD <= IsRxData_rxclk_from_GBT; -GBTRX_ready <= FIT_GBT_status.GBT_status.gbtRx_Ready; -RX_err <= FIT_GBT_status.GBT_status.gbtRx_ErrorDet; +GBTRX_ready <= readout_status.GBT_status.gbtRx_Ready; +RX_err <= readout_status.GBT_status.gbtRx_ErrorDet; --PM_data_toreadout.is_header <= GBT_is_TXD; --PM_data_toreadout.is_data <= GBT_is_TXD; @@ -786,35 +820,32 @@ RX_err <= FIT_GBT_status.GBT_status.gbtRx_ErrorDet; --PM_data_toreadout.data_word <= GBT_TX_D; -FIT_GBT_control <= func_CNTRREG_getcntrreg(ipbus_control_reg); -ipbus_status_reg <= func_STATREG_getaddrreg(FIT_GBT_status); +readout_control <= func_CNTRREG_getcntrreg(readout_control_reg); +readout_status_reg <= func_STATREG_getaddrreg(readout_status); -ipbus_control_reg <= readout_conf; -readout_stat <= ipbus_status_reg; - -gbt_global_status(0) <= FIT_GBT_status.GBT_status.Rx_Phase_error; ---gbt_global_status(1) <= '1' when FIT_GBT_status.BCIDsync_Mode = mode_LOST else '0'; ---gbt_global_status(2) <= '1' when FIT_GBT_status.hits_rd_counter_selector.hits_skipped /= x"0000_0000" else '0'; +gbt_global_status(0) <= readout_status.Rx_Phase_error; +--gbt_global_status(1) <= '1' when readout_status.BCIDsync_Mode = mode_LOST else '0'; +--gbt_global_status(2) <= '1' when readout_status.hits_rd_counter_selector.hits_skipped /= x"0000_0000" else '0'; gbt_global_status(3) <= '0'; -process (clksys40) +process (TX_CLK) begin - if (clksys40'event and clksys40='1') then - if ( FIT_GBT_status.BCIDsync_Mode = mode_LOST) then + if (TX_CLK'event and TX_CLK='1') then + if ( readout_status.BCIDsync_Mode = mode_LOST) then gbt_global_status(1) <= '1'; else gbt_global_status(1) <= '0'; end if; - if ( FIT_GBT_status.hits_rd_counter_selector.hits_skipped = x"0000_0000") then + if ( readout_status.fsm_errors = x"00") then gbt_global_status(2) <= '0'; else gbt_global_status(2) <= '1'; end if; - if ( FIT_GBT_status.Trigger_from_CRU and FIT_GBT_control.Data_Gen.trigger_resp_mask ) /= 0 then + if readout_status.laser_start = '1' then readout_laser_out <= '1'; else readout_laser_out <= '0'; @@ -848,10 +879,21 @@ if (RESET='1') then sreset<='1'; rstcount<=(others=>'0'); dly_rst<='0'; else end if; end process; +readout_err_rden<='1' when (rdout_errc1='1') and (rdout_errc2='0') else '0'; +err_report_fifo_rden <= '1'when (rdout_errf_rd1='1') and (rdout_errf_rd2='0') else '0'; + process (TX_CLK) begin if (TX_CLK'event and TX_CLK='1') then +rout_lock2<=rout_lock1; rout_lock1<=rout_lock0; rout_lock0<=rdouts_sel and (not rdouts_rdy); + +rdout_errc2<=rdout_errc1; rdout_errc1<=rdout_errc0; rdout_errc0<=rdout_errc; +rdout_errf_rd2<=rdout_errf_rd1; rdout_errf_rd1<=rdout_errf_rd0; rdout_errf_rd0<=rdout_errf_rd; + +if (rout_lock1='1') and (rout_lock2='0') then rout_buf <=readout_status_reg(to_integer(unsigned(ipb_addr(5 downto 0)))-16#28#); end if; + + GBT_is_TXD<=IsData_from_FITrd; IsRXData0<=GBT_is_RXD; @@ -872,9 +914,36 @@ if t100ms='0' then cou_100ms<=cou_100ms+1; if (GBT_is_TXD='1') or (TXact='1') then txled0<='0'; else txled0<='1'; end if; if (IsRXData0='1') or (RXact='1') then rxled0<='0'; else rxled0<='1'; end if; end if; + + if (l_mode(31)='0') then lfreq_cnt<=(others=>'0'); lpatt_cnt<=(others=>'0'); + else + if ((lfreq_cnt(23 downto 11)=0) or (l_mode(24)='1')) and (lfreq_cnt(11 downto 0)=1) and ((lasbc='1') or (l_mode(24)='0')) and (lpatt_cnt(6 downto 1)=0) then lpatt_sreg<=l_patt1 & l_patt0; lpatt_cnt<="1000000"; + if (l_mode(24)='0') then lfreq_cnt<=l_mode(23 downto 0); + else + lfreq_cnt<=x"000" & l_mode(23 downto 12); + end if; + else + if (l_mode(24)='0') or (lasbc='1') then lfreq_cnt<=lfreq_cnt-1; end if; + if (lpatt_cnt/=0) then lpatt_cnt<=lpatt_cnt-1; lpatt_sreg<= '0' & lpatt_sreg(63 downto 1); end if; + end if; + + end if; + +laser_t<=l_st; +tblock_dly<= tblock_dly(64 downto 0) & l_st; tblock<=tblock0; end if; -end process; +end process; + +l_st<= '0' when (l_mode(30)='0') else + readout_laser_out when (l_mode(31)='0') else + lpatt_sreg(0); + +tblock_mux(0)<= tblock_dly(to_integer(unsigned(tblock_md(5 downto 0)))); +tblock_mux(1)<= tblock_dly(to_integer(unsigned(tblock_md(5 downto 0)))+1); +tblock_mux(2)<= tblock_dly(to_integer(unsigned(tblock_md(5 downto 0)))+2); + +tblock0<= '1' when ((tblock_md(7 downto 6)>="01") and (tblock_mux(0)='1')) or ((tblock_md(7 downto 6)>="10") and (tblock_mux(1)='1')) or ((tblock_md(7 downto 6)="11") and (tblock_mux(2)='1')) else '0'; t100ms <='1' when cou_100ms=3999999 else '0'; @@ -904,6 +973,8 @@ lmode_sel<= ipb_str when ipb_addr(31 downto 0)= x"0000001B" else '0'; lpatt0_sel<= ipb_str when ipb_addr(31 downto 0)= x"0000001C" else '0'; lpatt1_sel<= ipb_str when ipb_addr(31 downto 0)= x"0000001D" else '0'; pmena_sel<= ipb_str when ipb_addr(31 downto 0)= x"0000001E" else '0'; +tblock_sel<= ipb_str when ipb_addr(31 downto 0)= x"0000001F" else '0'; +avgt_sel <= ipb_str when ipb_addr(31 downto 0)= x"00000020" and (ipb_isrd='1') else '0'; hdmics_select <= ipb_str when (ipb_addr(31 downto 4)= x"0000003") and (ipb_addr(3 downto 0) open, DATA => t_stmp, DATAVALID => open ); SNS : SENSOR PORT MAP ( di_in => (others=>'0'), daddr_in => d_addr, den_in => d_rd, dwe_in => '0', drdy_out => d_rdy, do_out => d_sns, dclk_in => ipb_clk, @@ -1042,22 +1118,13 @@ process(CLKA) begin if (CLKA'event) and (CLKA='1') then -a_t<=not a_t; l_on1<=l_on0; l_on0 <= l_st; -readout_laser_out_ff0 <= readout_laser_out; -readout_laser_out_ff1 <= readout_laser_out_ff0; - if (l_mode(31)='0') then lfreq_cnt<=(others=>'0'); lpatt_cnt<=(others=>'0'); - else - if (lfreq_cnt=1) and (lpatt_cnt(6 downto 1)=0) then lfreq_cnt<=l_mode(23 downto 0); lpatt_sreg<=l_patt1 & l_patt0; lpatt_cnt<="1000000"; - else - lfreq_cnt<=lfreq_cnt-1; - if (lpatt_cnt/=0) then lpatt_cnt<=lpatt_cnt-1; lpatt_sreg<=lpatt_sreg(62 downto 0) & '0'; end if; - end if; - end if; +a_t<=not a_t; l_on1<=l_on0; l_on0 <= l_st1; l_st1 <= l_st0; l_st0 <= laser_t; + end if; end process; -l_st<= readout_laser_out_ff1 when (l_mode(31)='0') else lpatt_sreg(63); +ldrm<=ldr-1; process (LCLK160) begin @@ -1076,8 +1143,8 @@ a0_t<=an_t; l_tg1<=l_tg; if (a0_t XOR an_t)='1' then l_cnt<="10"; else l_cnt<=l_cnt+1; end if; if (ldr(1 downto 0)=l_cnt) then - case ldr(3 downto 2) is - when "00" => l_on<= l_st; + case ldrm(3 downto 2) is + when "00" => l_on<= l_st1; when "01" => l_on<= l_on0; when "10" => l_on<= l_on1; when others => l_on<='0'; @@ -1096,11 +1163,11 @@ lasi<=las_o; end if; end process; -tcma: tcm_side port map(CLKA=>CLKA, RST=>reset, SRST=>sreset, TD_P=>TDA_P, TD_N=>TDA_N, Config=>hdmia_config, Status=>Status_a, stat_adr=> ipb_addr(3 downto 0), stat_clr=>stat_clrA, stat_chg=>as_blk, side_OK=>sideA_OK, TDD=>TDA, rd_lock=> rd_lock_a, - Or_o=>OrA_i, CLK320_o=>CLK320A, clksys40_o => clksys40, pll_lock=> pll_lock_a, mt_cou_o=>bitcnt_A, Time_o=>TimeA_o, Avg_o=>AvgA, Ampl_O=>AmplA, Nchan=> Nchan_A, req=> reqA, bkgnd=> bkgndA); +tcma: tcm_side port map(CLKA=>CLKA, RST=>reset, SRST=>sreset, TD_P=>TDA_P, TD_N=>TDA_N, Config=>hdmia_config, Status=>Status_a, stat_adr=> ipb_addr(3 downto 0), stat_clr=>stat_clr_cmd, stat_chg=>as_blk, side_OK=>sideA_OK, TDD=>TDA, rd_lock=> rd_lock_a, + Or_o=>OrA_B, CLK320_o=>CLK320A, clksys40_o => TX_CLK, pll_lock=> pll_lock_a, mt_cou_o=>bitcnt_A, Time_o=>TimeA_o, Avg_o=>AvgA, Ampl_O=>AmplA, Nchan=> Nchan_A, req=> reqA, bkgnd=> NoiseA, AmplI_O=> AmplAI, AmplO_O=> AmplAO ); -tcmc: tcm_side port map(CLKA=>CLKC, RST=>reset, SRST=>sreset, TD_P=>TDC_P, TD_N=>TDC_N, Config=>hdmic_config, Status=>Status_C, stat_adr=> ipb_addr(3 downto 0), stat_clr=>stat_clrC, stat_chg=>cs_blk, side_OK=>sideC_OK, TDD=>TDC0, rd_lock=> rd_lock_c, - Or_o=>OrC_B, CLK320_o=>CLK320C, clksys40_o=> open, pll_lock=> pll_lock_c, mt_cou_o=>bitcnt_c, Time_o=>TimeC_o, Avg_o=>AvgC, Ampl_o=>AmplC0, Nchan=> Nchan_C0, req=> reqC, bkgnd=> bkgndC0); +tcmc: tcm_side port map(CLKA=>CLKC, RST=>reset, SRST=>sreset, TD_P=>TDC_P, TD_N=>TDC_N, Config=>hdmic_config, Status=>Status_C, stat_adr=> ipb_addr(3 downto 0), stat_clr=>stat_clr_cmd, stat_chg=>cs_blk, side_OK=>sideC_OK, TDD=>TDC0, rd_lock=> rd_lock_c, + Or_o=>OrC_B, CLK320_o=>CLK320C, clksys40_o=> open, pll_lock=> pll_lock_c, mt_cou_o=>bitcnt_c, Time_o=>TimeC_o, Avg_o=>AvgC, Ampl_o=>AmplC0, Nchan=> Nchan_C0, req=> reqC, bkgnd=> NoiseC0, AmplI_O=> open, AmplO_O=> open); TresbM<=TimeC(8) & TimeC & "00000000000000"; Tdiff<=TdiffM(23 downto 14); @@ -1158,7 +1225,7 @@ if (SCKi'event and SCKi='1') then when 3 => SPI_DATA<= SC_C; when 4 => SPI_DATA<= C_A; when 5 => SPI_DATA<= C_C; - when 6 => SPI_DATA<=x"00" & Tmode; + when 6 => SPI_DATA<="000000" & Tmode; when 16#10# to 16#17# => SPI_DATA<=spi_buf_out; when 16#18# => SPI_DATA<= x"000" & ldr; @@ -1189,15 +1256,22 @@ irqi<= dcs_irq or IPB_chg or GBT_chg or GBTRXerr or RST_req when (irq_cnt="11") PM_rst <= rst_spi2 and (not rst_spi1); -bccorr_rd<= bccorr_sel or bccorrA_sel or bccorrC_sel; bccorr_ack<=bccorr_ack0 and bccorr_rd; +bccorr_rd<= bccorr_sel or bccorrA_sel or bccorrC_sel or (bc_mask_sel and ipb_isrd); bccorr_ack<=bccorr_ack0 and bccorr_rd; -hdmi_to0<='1' when (PM_tcou/=15625000) else '0'; +hdmi_to0<='1' when (PM_tcou/=31250000) else '0'; as_blk<=as_chg or hdmi_to; cs_blk<=cs_chg or hdmi_to; +rdouts_rdy<='1' when (rdouts_cnt="10") else '0'; + process(ipb_clk) begin if (ipb_clk'event and ipb_clk='1') then +if (rdouts_sel='0') or (rdouts_rdy='1') then rdouts_cnt<= (others=>'0'); else rdouts_cnt<=rdouts_cnt+1; end if; + +if (ipb_addr(4 downto 0)="01010") and (rdouts_sel='1') and (rdouts_rdy='0') then rdout_errc<='1'; else rdout_errc<='0'; end if; +if (ipb_addr(4 downto 0)="10010") and (rdouts_sel='1') and (rdouts_rdy='0') then rdout_errf_rd<='1'; else rdout_errf_rd<='0'; end if; + if (bccorr_ack0='0') and (bccorr_rd='1') then bccorr_ack0<='1'; else bccorr_ack0<='0'; end if; adc_sel1<=adc_sel and not d_rdy; @@ -1225,26 +1299,36 @@ IPB_rdy0<=ipb_leds(0); if (rst_spi1='1') then RST_req<='0'; clk_frs<='0'; else if (tcmr_select='1') and (ipb_iswr='1') and (ipb_addr(2 downto 0)=7) then - if (ipb_data_out(11)='1') then RST_req<='1'; end if; + if (ipb_data_out(11)='1') then RST_req<='1'; inRst<='1'; end if; if (ipb_data_out(10)='1') and (ipb_data_out(11)='1') then clk_frs<='1'; end if; end if; end if; + + if (ipb_rst='1') then hdmia_config<=(others=>'0'); hdmic_config<=(others=>'0'); else hdmi_to<=hdmi_to0; - if (PM_rst='1') then PM_tcou<=(others=>'0'); + if (rst_spi1='1') or (RST_req='1') then PM_tcou<=(others=>'0'); else - if (hdmi_to0='1') then PM_tcou<=PM_tcou+1; end if; + if (hdmi_to0='1') then PM_tcou<=PM_tcou+1; + else + if (inRst='1') then inRst<='0'; end if; + end if; end if; if (hdmiac_select='1') and (ipb_iswr='1') then hdmia_config<=ipb_data_out; as_chg<='1'; end if; if (hdmicc_select='1') and (ipb_iswr='1') then hdmic_config<=ipb_data_out; cs_chg<='1'; end if; end if; +if (ipb_rst='1') then tblock_md<=(others=>'0'); + else + if (tblock_sel='1') and (ipb_iswr='1') then tblock_md<=ipb_data_out(7 downto 0); end if; +end if; + if (as_chg='1') then as_chg<='0'; end if; if (cs_chg='1') then cs_chg<='0'; end if; if (Tmode_sel='1') and (ipb_iswr='1') then trig_mod<=ipb_data_out(14 downto 0); end if; -if (rst_spi1='1') then l_mode<=(others=>'0'); +if (rst_spi1='1') then l_mode(30)<='0'; else if (lmode_sel='1') and (ipb_iswr='1') then l_mode<=ipb_data_out(31 downto 0); end if; end if; @@ -1252,14 +1336,11 @@ if (lpatt0_sel='1') and (ipb_iswr='1') then l_patt0<=ipb_data_out(31 downto 0); if (lpatt1_sel='1') and (ipb_iswr='1') then l_patt1<=ipb_data_out(31 downto 0); end if; if (pmena_sel='1') and (ipb_iswr='1') then pm_ena<=ipb_data_out(19 downto 0); end if; -if (rst_spi1='1') or ((GBTRX_ready2='1') and (GBTRX_ready1='0')) then readout_conf(0)(22)<='1'; - else - if (rdoutc_sel='1') and (ipb_iswr='1') then - if (ipb_addr(7 downto 0)=16#D8#) then readout_conf(0)<= ipb_data_out(31 downto 23) & (ipb_data_out(22) or not GBTRX_ready1) & ipb_data_out(21 downto 0); +if (rdoutc_sel='1') and (ipb_iswr='1') then + if (ipb_addr(7 downto 0)=16#D8#) then readout_control_reg(0)<= ipb_data_out; else - readout_conf(to_integer(unsigned(ipb_addr(7 downto 0)))-16#D8#)<=ipb_data_out(31 downto 0); - end if; - end if; + readout_control_reg(to_integer(unsigned(ipb_addr(7 downto 0)))-16#D8#)<=ipb_data_out(31 downto 0); + end if; end if; if (ipb_leds(0)/=IPB_rdy0) then IPB_chg<='1'; @@ -1267,12 +1348,14 @@ if (ipb_leds(0)/=IPB_rdy0) then IPB_chg<='1'; if (stat_clr1='1') and (stat_clr='0') then IPB_chg<='0'; end if; end if; -if (GBTRX_ready/=GBTRX_ready0) then GBT_chg<='1'; +if (GBTRX_ready1/=GBTRX_ready2) then GBT_chg<='1'; else if (stat_clr1='1') and (stat_clr='0') then GBT_chg<='0'; end if; end if; -if (GBTRX_ready='1') and (RX_err='1') and (GBT_rdy='1') then GBTRXerr<='1'; GBTRXerr_ipb<='1'; +RX_err_ipb <=RX_err; GBT_rdy_ipb <= GBT_rdy; + +if (GBTRX_ready1='1') and (RX_err_ipb='1') and (GBT_rdy_ipb='1') then GBTRXerr<='1'; GBTRXerr_ipb<='1'; else if (stat_clr1='1') and (stat_clr='0') then GBTRXerr<='0'; end if; if (ipb_stat_rd='1') then GBTRXerr_ipb<='0'; end if; @@ -1280,7 +1363,7 @@ end if; if (rst_spi1='1') then rst_fl<='1'; else - if (ipb_stat_rd='1') then rst_fl<='0'; end if; + if (stat_clr_cmd='1') then rst_fl<='0'; end if; end if; if (stat_clr1='1') and (stat_clr='0') then irq_cnt<="00"; @@ -1323,7 +1406,7 @@ spi_wr2<=spi_wr1; spi_wr1<=spi_wr0; spi_wr0<=spi_wr_rdy; when "011" => SC_C<=Treg_data; when "100" => C_A<=Treg_data; when "101" => C_C<=Treg_data; - when "110" => Tmode<=Treg_data(7 downto 0); + when "110" => Tmode<=Treg_data(9 downto 0); when others => null; end case; @@ -1360,55 +1443,62 @@ C_SC : trigger_out port map ( clk320 => clk320A, T_in=>SC_0, T_out =>SC, mode C_FC : trigger_out port map ( clk320 => clk320A, T_in=>C_0, T_out =>C, mode=>trig_mod(11 downto 9), ipb_clk=>ipb_clk, DI=>ipb_data_out, DO=>trg_r(3), CO=>count_r(3), A=>ipb_addr(0), wr=>trg_r_wr(3), c_rd=>cnt_lock, c_clr=>cnt_clr, mt_cnt=>bitcnt_A, T_r=>trigs(3)); C_vertex : trigger_out port map ( clk320 => clk320A, T_in=>Vertex_0, T_out =>Vertex, mode=>trig_mod(14 downto 12), ipb_clk=>ipb_clk, DI=>ipb_data_out, CO=>count_r(4), DO=>trg_r(4), A=>ipb_addr(0), wr=>trg_r_wr(4), c_rd=>cnt_lock, c_clr=>cnt_clr, mt_cnt=>bitcnt_A, T_r=>trigs(4)); -bgA_inc<= '1' when (bkgndA='1') and (bitcnt_A="011") else '0'; -bgC_inc<= '1' when (bkgndC='1') and (bitcnt_A="011") else '0'; -bgAnd<= bgA_inc and bgC_inc; -bgOr<= bgA_inc or bgC_inc; - -orA_cnt<= '1' when (orA_str='1') and (bitcnt_A="011") else '0'; -orC_cnt<= '1' when (OrC_i='1') and (bitcnt_A="011") else '0'; - -Or_or<= orA_cnt or orC_cnt; -Or_and<= orA_cnt and orC_cnt; -Bg_Aclr<= bgA_inc and not orA_cnt; -Bg_Cclr<= bgC_inc and not orC_cnt; -Bg_Orclr<= Bg_Aclr or Bg_Cclr; -Bg_Andclr<= Bg_Aclr and Bg_Cclr; - -cou_bA: counter32 port map (clk320=> clk320A, cout=> count_r(5), rd=> cnt_lock, clr=> cnt_clr, inc=> bgA_inc); -cou_bC: counter32 port map (clk320=> clk320A, cout=> count_r(6), rd=> cnt_lock, clr=> cnt_clr, inc=> bgC_inc); -cou_bAnd: counter32 port map (clk320=> clk320A, cout=> count_r(7), rd=> cnt_lock, clr=> cnt_clr, inc=> bgAnd); -cou_bor: counter32 port map (clk320=> clk320A, cout=> count_r(8), rd=> cnt_lock, clr=> cnt_clr, inc=> bgOr); -cou_oror: counter32 port map (clk320=> clk320A, cout=> count_r(9), rd=> cnt_lock, clr=> cnt_clr, inc=> Or_or); -cou_orand: counter32 port map (clk320=> clk320A, cout=> count_r(10), rd=> cnt_lock, clr=> cnt_clr, inc=> Or_and); -cou_AC: counter32 port map (clk320=> clk320A, cout=> count_r(11), rd=> cnt_lock, clr=> cnt_clr, inc=> bg_Aclr); -cou_CC: counter32 port map (clk320=> clk320A, cout=> count_r(12), rd=> cnt_lock, clr=> cnt_clr, inc=> bg_Cclr); -cou_orc: counter32 port map (clk320=> clk320A, cout=> count_r(13), rd=> cnt_lock, clr=> cnt_clr, inc=> bg_Orclr); -cou_andc: counter32 port map (clk320=> clk320A, cout=> count_r(14), rd=> cnt_lock, clr=> cnt_clr, inc=> bg_Andclr); - -with Tmode(7 downto 4) select corr_inc<= +NoiseA_inc<= t_blk when (NoiseA='1') and (orA_str='0') and (bitcnt_A="011") else '0'; +NoiseC_inc<= t_blk when (NoiseC='1') and (orCt='0') and (Tmode(9)='0') and (bitcnt_A="011") else '0'; +NoiseAll<= NoiseA_inc or NoiseC_inc; + +Interact<= '1' when (orA_str='1') and (OrCt='1') and (bitcnt_A="011") else '0'; + +cou_NA: counter32 port map (clk320=> clk320A, cout=> count_r(5), rd=> cnt_lock, clr=> cnt_clr, inc=> NoiseA_inc); +cou_NC: counter32 port map (clk320=> clk320A, cout=> count_r(6), rd=> cnt_lock, clr=> cnt_clr, inc=> NoiseC_inc); +cou_NAll: counter32 port map (clk320=> clk320A, cout=> count_r(7), rd=> cnt_lock, clr=> cnt_clr, inc=> NoiseAll); + +bc_m: Mask_mem PORT MAP (clka => clk320A, wea => "0", addra => BC_cou, dina => (others=>'0'), douta => bc_mask, clkb => ipb_clk, enb => bc_mask_sel, web(0) => ipb_wr, addrb => ipb_addr(7 downto 0), dinb => ipb_data_out, doutb => bc_maskO); + +OrA_T<= '1' when (OrA_str='1') and (bc_mask="11") and (bitcnt_A="100") else '0'; +OrC_T<= '1' when (OrCt='1') and (bc_mask="11") and (bitcnt_A="100") else '0'; +Interact_T<= '1' when (OrCt='1') and (OrA_str='1') and (bc_mask="11") and (bitcnt_A="100") else '0'; +V_T<= '1' when (V_str='1') and (bc_mask="11") and (bitcnt_A="100") else '0'; +BG_A<= '1' when (OrCt='1') and (bc_mask="01") and (bitcnt_A="100") else '0'; +BG_C<= '1' when (OrA_str='1') and (bc_mask="10") and (bitcnt_A="100") else '0'; + +AT: counter32 port map (clk320=> clk320A, cout=> count_r(8), rd=> cnt_lock, clr=> cnt_clr, inc=> OrA_T); +CT: counter32 port map (clk320=> clk320A, cout=> count_r(9), rd=> cnt_lock, clr=> cnt_clr, inc=> OrC_T); +cou_int: counter32 port map (clk320=> clk320A, cout=> count_r(10), rd=> cnt_lock, clr=> cnt_clr, inc=> Interact); +IT: counter32 port map (clk320=> clk320A, cout=> count_r(11), rd=> cnt_lock, clr=> cnt_clr, inc=> Interact_T); +VT: counter32 port map (clk320=> clk320A, cout=> count_r(12), rd=> cnt_lock, clr=> cnt_clr, inc=> V_T); +BGA: counter32 port map (clk320=> clk320A, cout=> count_r(13), rd=> cnt_lock, clr=> cnt_clr, inc=> BG_A); +BGC: counter32 port map (clk320=> clk320A, cout=> count_r(14), rd=> cnt_lock, clr=> cnt_clr, inc=> BG_C); + +with Tmode(7 downto 4) select corr_inc0<= '0' when x"0", orA_str when x"1", orC_i when x"2", SC_str when x"3", CC_str when x"4", V_str when x"5", - bkgndA when x"6", - bkgndC when x"7", - bkgndA and bkgndC when x"8", - bkgndA or bkgndC when x"9", - orA_str and orC_i when x"A", - orA_str or orC_i when x"B", - bkgndA and not orA_str when x"C", - bkgndC and not orC_i when x"D", - (bkgndA and not orA_str) or (bkgndC and not orC_i) when x"E", - (bkgndA and not orA_str) and (bkgndC and not orC_i) when x"F"; - -m_cr: BC_correlator port map(clk320 =>CLK320A, BC_cou =>BC_COU, mt_cou =>bitcnt_A, inc =>corr_inc, clr =>cnt_clr, ipb_clk => ipb_clk, rd =>bccorr_sel, addr =>ipb_addr(11 downto 0), data =>bc_corrl); -m_crA: BC_correlator port map(clk320 =>CLK320A, BC_cou =>BC_COU, mt_cou =>bitcnt_A, inc =>orA_str, clr =>cnt_clr, ipb_clk => ipb_clk, rd =>bccorrA_sel, addr =>ipb_addr(11 downto 0), data =>bc_corrA); -m_crC: BC_correlator port map(clk320 =>CLK320A, BC_cou =>BC_COU, mt_cou =>bitcnt_A, inc =>orC_i, clr =>cnt_clr, ipb_clk => ipb_clk, rd =>bccorrC_sel, addr =>ipb_addr(11 downto 0), data =>bc_corrC); + NoiseA when x"6", + NoiseC when x"7", + NoiseA or NoiseC when x"8", + orA_str and bc_mask(0) and bc_mask(1) when x"9", + orCt and bc_mask(0) and bc_mask(1) when x"A", + orA_str and OrCt when x"B", + orA_str and orCt and bc_mask(0) and bc_mask(1) when x"C", + V_str and bc_mask(0) and bc_mask(1) when x"D", + orCt and bc_mask(0) and (not bc_mask(1)) when x"E", + orA_str and bc_mask(1) and (not bc_mask(0)) when x"F"; + +m_cr: BC_correlator port map(clk320 =>CLK320A, BC_cou =>BC_COU, mt_cou =>bitcnt_A, inc =>corr_inc, clr =>CCcnt_clr, ipb_clk => ipb_clk, rd =>bccorr_sel, addr =>ipb_addr(11 downto 0), data =>bc_corrl); +m_crA: BC_correlator port map(clk320 =>CLK320A, BC_cou =>BC_COU, mt_cou =>bitcnt_A, inc =>orA_str, clr =>CCcnt_clr, ipb_clk => ipb_clk, rd =>bccorrA_sel, addr =>ipb_addr(11 downto 0), data =>bc_corrA); +m_crC: BC_correlator port map(clk320 =>CLK320A, BC_cou =>BC_COU, mt_cou =>bitcnt_A, inc =>orC_i, clr =>CCcnt_clr, ipb_clk => ipb_clk, rd =>bccorrC_sel, addr =>ipb_addr(11 downto 0), data =>bc_corrC); -Vertex_0<= '1' when (signed(Tdiff)>=signed(Tlow)) and (signed(Tdiff)<=signed(Thigh)) and (OrA_i='1') and (OrC_i='1') else '0'; +Vertex_0<= ovtx and t_blk when Tmode(9)='0' else irt and t_blk; + +OrA_i<= ORA_B and t_blk; + +OrC_i<= OrCt and t_blk when Tmode(9)='0' else ort and t_blk; + +ovtx <= '1' when (signed(Tdiff)>=signed(Tlow)) and (signed(Tdiff)<=signed(Thigh)) and (OrA_B='1') and (OrCt='1') else '0'; AmplS<= (AmplA(16) & AmplA) + (AmplC(16) & AmplC); @@ -1418,40 +1508,58 @@ ca<= '1' when (unsigned(AmplA(15 downto 0))>unsigned(C_A & '0')) and (AmplA(16) cc<= '1' when (unsigned(AmplC(15 downto 0))>unsigned(C_C & '0')) and (AmplC(16)='0') else '0'; scb<= '1' when (unsigned(AmplS(16 downto 0))>unsigned(SC_A & '0')) and (AmplS(17)='0') else '0'; cb<= '1' when (unsigned(AmplS(16 downto 0))>unsigned(C_A & '0')) and (AmplS(17)='0') else '0'; + +Nchan_S<= ("0" & Nchan_A) + ("0" & Nchan_C); + +nsca <= '1' when (unsigned(Nchan_A) > unsigned(SC_A) ) else '0'; +nscc <= '1' when (unsigned(Nchan_C) > unsigned(SC_C) ) else '0'; +nscb <= '1' when (unsigned(Nchan_S) > unsigned(SC_A) ) else '0'; + +sct <= '1' when (((sca='1') or (Tmode(1)='1')) and ((scc='1') or (Tmode(2)='1') or (Tmode(9)='1')) and ((Tmode(2 downto 1)/="11") or (Tmode(9)='1'))) or ((scb='1') and (Tmode(2 downto 1)="11") and (Tmode(9)='0')) else '0'; +nt<= '1' when (((nsca='1') or (Tmode(1)='1')) and ((nscc='1') or (Tmode(2)='1') or (Tmode(9)='1')) and ((Tmode(2 downto 1)/="11") or (Tmode(9)='1'))) or ((nscb='1') and (Tmode(2 downto 1)="11") and (Tmode(9)='0')) else '0'; + +irt <= '1' when (unsigned(AmplAI(14 downto 0))>unsigned(SC_C & '0')) and (AmplAI(15)='0') else '0'; +ort <= '1' when (unsigned(AmplAO(14 downto 0))>unsigned(C_C & '0')) and (AmplAO(15)='0') else '0'; -SC_0<= not C_0 when (((sca='1') or (Tmode(1)='1')) and ((scc='1') or (Tmode(2)='1')) and (Tmode(2 downto 1)/="11")) or ((scb='1') and Tmode(2 downto 1)="11") else '0'; +SC_i<= (not C_0) and sct when (Tmode(8)='0') else nt and t_blk; SC_0<= SC_i and t_blk; -C_0<= '1' when (((ca='1') or (Tmode(1)='1')) and ((cc='1') or (Tmode(2)='1')) and (Tmode(2 downto 1)/="11")) or ((cb='1') and Tmode(2 downto 1)="11") else '0'; +C_i<= '1' when (((ca='1') or (Tmode(1)='1')) and ((cc='1') or (Tmode(2)='1') or (Tmode(9)='1')) and ((Tmode(2 downto 1)/="11") or (Tmode(9)='1'))) or ((cb='1') and (Tmode(2 downto 1)="11") and (Tmode(9)='0')) else '0'; +C_0<= C_i and t_blk; +tr_valid <= OrA_B or ORCt or SC_i or C_i or (Tmode(9) and (ort or irt)); -cnt_lock<=(cnt_lock1 and (not cnt_lock2)) or cnt_rd; cnt_clr<=cnt_clr1 and (not cnt_clr2); +cnt_lock<=(cnt_lock1 and (not cnt_lock2)) or cnt_rd; cnt_clr<=cnt_clr1 and (not cnt_clr2); CCcnt_clr<=(Ccnt_clr1 and (not Ccnt_clr2)) or cnt_clr; process (CLK320A) begin if (CLK320A'event and CLK320A='1') then -laser_t0<=l_on0; laser_t<=laser_t0; +corr_inc<=corr_inc0; - cnt_lock2<=cnt_lock1; cnt_lock1<=cnt_lock0; cnt_lock0<=Tcnt_0_rd; cnt_clr2<=cnt_clr1; cnt_clr1<=cnt_clr0; cnt_clr0<=Tcnt_clr; - rout_lock2<=rout_lock1; rout_lock1<=rout_lock0; rout_lock0<=rdouts_sel and ipb_clk; - - if (rout_lock1='1') and (rout_lock2='0') then rout_buf <=readout_stat(to_integer(unsigned(ipb_addr(5 downto 0)))-16#28#); end if; + rx_phase_status(2 downto 0) <= readout_status.rx_phase; + rx_phase_status(3) <= readout_status.Rx_Phase_error; + +cnt_lock2<=cnt_lock1; cnt_lock1<=cnt_lock0; cnt_lock0<=Tcnt_0_rd; cnt_clr2<=cnt_clr1; cnt_clr1<=cnt_clr0; cnt_clr0<=Tcnt_clr; Ccnt_clr2<=Ccnt_clr1; Ccnt_clr1<=Ccnt_clr0; Ccnt_clr0<=Ccnt_clr; +avgt_lk<= avgt_lk0; avgt_lk0<= avgt_sel; + B_rdy3<=B_rdy2; B_rdy2<=B_rdy1; B_rdy1<=B_rdy0; B_rdy0<=B_rdy; -if (B_rdy1='1') and (B_rdy2='0') then TimeC1<=TimeC0; AmplC1<=AmplC0; OrC_B1<=OrC_B; Nchan_C1<=Nchan_C0; bkgndC1<= bkgndC0; end if; +if (B_rdy1='1') and (B_rdy2='0') then TimeC1<=TimeC0; AmplC1<=AmplC0; OrC_B1<=OrC_B; Nchan_C1<=Nchan_C0; NoiseC1<= NoiseC0; end if; if (B_rdy2='1') and (B_rdy3='0') then TDC1<=TDC0; end if; if (bitcnt_A="000") then - + + t_blk<=not tblock; + if (Tmode(0)='1') then - if (B_rdy1='1') and (B_rdy2='0') then TimeC2<=TimeC0; AmplC2<=AmplC0; OrC_B2<=OrC_B; Nchan_C2<=Nchan_C0; bkgndC2<= bkgndC0; - else TimeC2<=TimeC1; AmplC2<=AmplC1; OrC_B2<=OrC_B1; Nchan_C2<=Nchan_C1; bkgndC2<= bkgndC1; + if (B_rdy1='1') and (B_rdy2='0') then TimeC2<=TimeC0; AmplC2<=AmplC0; OrC_B2<=OrC_B; Nchan_C2<=Nchan_C0; NoiseC2<= NoiseC0; + else TimeC2<=TimeC1; AmplC2<=AmplC1; OrC_B2<=OrC_B1; Nchan_C2<=Nchan_C1; NoiseC2<= NoiseC1; end if; - TimeC<=TimeC2; AmplC<=AmplC2; OrC_i<=OrC_B2; Nchan_C<=Nchan_C2; bkgndC<= bkgndC2; + TimeC<=TimeC2; AmplC<=AmplC2; OrCt<=OrC_B2; Nchan_C<=Nchan_C2; NoiseC<= NoiseC2; else - if (B_rdy1='1') and (B_rdy2='0') then TimeC<=TimeC0; AmplC<=AmplC0; ORC_i<=OrC_B; Nchan_C<=Nchan_C0; bkgndC<= bkgndC0; - else TimeC<=TimeC1; AmplC<=AmplC1; OrC_i<=OrC_B1; Nchan_C<=Nchan_C1; bkgndC<= bkgndC1; + if (B_rdy1='1') and (B_rdy2='0') then TimeC<=TimeC0; AmplC<=AmplC0; ORCt<=OrC_B; Nchan_C<=Nchan_C0; NoiseC<= NoiseC0; + else TimeC<=TimeC1; AmplC<=AmplC1; OrCt<=OrC_B1; Nchan_C<=Nchan_C1; NoiseC<= NoiseC1; end if; end if; end if; @@ -1459,7 +1567,7 @@ end if; if (bitcnt_A="001") then - if (New_BCID='1') then BC_COU<=FIT_GBT_status. BCID_from_CRU_corrected; Orbit_ID<=FIT_GBT_status. ORBIT_from_CRU_corrected; + if (New_BCID='1') then BC_COU<=readout_status. BCID_from_CRU_corrected; Orbit_ID<=readout_status. ORBIT_from_CRU_corrected; else if (BC_COU=x"DEB") then BC_cou<=x"000"; Orbit_ID<=Orbit_ID+1; else BC_cou<=BC_cou+1; end if; end if; @@ -1479,8 +1587,12 @@ if (Tmode(0)='1') then end if; if (bitcnt_A="010") then - if ((OrA_i or ORC_i or SC_0 or C_0 or laser_t)='1') then - Rd_Word<= x"F" & Tmode(3) &"001" & x"000000" & rx_phase_status & Orbit_ID & BC_COU & '0' & TimeC & '0' & TimeA & '0' & AmplC & '0' & AmplA & '0' & Nchan_C & '0' & Nchan_A & "00" & laser_t & trigs; + if (BC_COU=l_mode(11 downto 0)) then lasbc<='1'; else lasbc<='0'; end if; + if (trigs/=0) or (laser_t='1') or (tr_valid='1') then + Rd_Word(159 downto 80) <= x"F" & Tmode(3) &"001" & x"000000" & rx_phase_status & Orbit_ID & BC_COU; + Rd_word(79 downto 59) <= '0' & TimeC & '0' & TimeA & '0'; + if (Tmode(9)='0') then Rd_word(58 downto 42) <= AmplC; else Rd_word(58 downto 42) <= AmplAI(15) & AmplAI; end if; + Rd_word(41 downto 0) <= '0' & AmplA & '0' & Nchan_C & '0' & Nchan_A & tr_valid & (not t_blk) & laser_t & trigs; gbt_wr<='1'; end if; @@ -1489,6 +1601,12 @@ if (bitcnt_A="010") then end if; if (bitcnt_A="011") then + if (orA_str='1') and (OrCt='1') and (t_blk='1') and (Tmode(9)='0') then + TimeAavg<= TimeAavg - std_logic_vector(resize(signed(TimeAavg(18 downto 10)),19)) + std_logic_vector(resize(signed(Rd_Word(68 downto 60)),19)); + TimeCavg<= TimeCavg - std_logic_vector(resize(signed(TimeCavg(18 downto 10)),19)) + std_logic_vector(resize(signed(Rd_Word(78 downto 70)),19)); + end if; + if (avgt_lk='0') then TimeA_rd<= TimeAavg(18 downto 10); TimeC_rd<= TimeCavg(18 downto 10); end if; + if (Tmode(3)='0') then gbt_wr<='0'; end if; end if; @@ -1499,7 +1617,7 @@ end if; end if; end process; -New_BCID <= FIT_GBT_status.Start_run when (FIT_GBT_status.BCIDsync_Mode=mode_SYNC) else '0'; +New_BCID <= readout_status.bc_delay_apply; FIFO_in<= TDA(2)(15 downto 0) & TDA(1) & TDA(0) & TDA(4) & TDA(3) & TDA(2)(31 downto 16) when (bitcnt_A="100") and (gbt_wr='1') diff --git a/firmware/FT0/TCM/hdl/tcm_side.vhd b/firmware/FT0/TCM_v1/hdl/tcm_side.vhd similarity index 81% rename from firmware/FT0/TCM/hdl/tcm_side.vhd rename to firmware/FT0/TCM_v1/hdl/tcm_side.vhd index 7e1172b..c094be4 100644 --- a/firmware/FT0/TCM/hdl/tcm_side.vhd +++ b/firmware/FT0/TCM_v1/hdl/tcm_side.vhd @@ -68,7 +68,9 @@ entity tcm_side is Avg_o : out STD_LOGIC_VECTOR (13 downto 0); Nchan : out STD_LOGIC_VECTOR (6 downto 0); req : out STD_LOGIC_VECTOR (9 downto 0); - bkgnd : out STD_LOGIC + bkgnd : out STD_LOGIC; + AmplI_o : out STD_LOGIC_VECTOR (15 downto 0); + AmplO_o : out STD_LOGIC_VECTOR (15 downto 0) ); end tcm_side; @@ -87,7 +89,7 @@ signal TsumA_F : STD_LOGIC_VECTOR (3 downto 0); signal TcarryA_out,TcarryA, McarryA, T0sumA, T1sumA, Nchan0A, Nchan1A, Nchan2A, Nchan3A : STD_LOGIC_VECTOR (3 downto 0); signal TtimeA, MamplA : STD_LOGIC_VECTOR (17 downto 0); signal TSsumA, MSsumA : STD_LOGIC_VECTOR (1 downto 0); -signal Avg, Avg_0 : STD_LOGIC_VECTOR (13 downto 0); +signal Avg, Avg_i : STD_LOGIC_VECTOR (13 downto 0); signal TresA : STD_LOGIC_VECTOR (9 downto 0); signal Nchan00A, Nchan01A, Nchan02A, Nchan03A, Nchan10A, Nchan11A, Nchan12A, Nchan13A, T00sumA, T01sumA,T10sumA, T11sumA : STD_LOGIC_VECTOR (2 downto 0); @@ -98,13 +100,18 @@ signal inp_act : STD_LOGIC_VECTOR (9 downto 1); signal HDMI_status : Trgdat; signal clk320, clk320_90, trig_ena, done, done0, done_toggle, ena_dly, inc_dly, psen, ph_inc, link_OK, side_on, dly_inc, dly_dec, dly_err,dly_err_s, bitpos_ok, mdl_err, mdl_err_s, dly_ctrl_ena, stat_clr0, stat_clr1, stat_clr2 : STD_LOGIC; -signal rd_lock1, rd_lock0 : STD_LOGIC; +signal rd_lock1, rd_lock0, dly_ctrl_rdy : STD_LOGIC; signal idle_cou : STD_LOGIC_VECTOR (5 downto 0); signal mt_cou : STD_LOGIC_VECTOR (2 downto 0); -signal link_ena, link_OK_in, link_OK_act, master_sel, psen_o, ph_inc_o, is_idle, bp_stable, dl_low, dl_high, bitpos_ok_in, bitpos_ok_act, sig_empty, mast_dlerr, mast_stable, sync_err, sync_err_s: STD_LOGIC_VECTOR (9 downto 0); +signal link_ena, link_OK_in, link_OK_act, master_sel, psen_o, ph_inc_o, is_idle, bp_stable, dl_low, dl_high, bitpos_ok_in, bitpos_ok_act, sig_empty, mast_dl_low, mast_dl_high, mast_stable, sync_err, sync_err_s: STD_LOGIC_VECTOR (9 downto 0); signal bitpos : vect3_arr; signal master_n, N_empty0 : STD_LOGIC_VECTOR (3 downto 0); signal adj_count : STD_LOGIC_VECTOR (7 downto 0); +signal mast_delay: STD_LOGIC_VECTOR (17 downto 0); + +signal MsumAI_0, MsumAO_0 : STD_LOGIC_VECTOR (4 downto 0); +signal MsumAI_F, MsumAO_F : STD_LOGIC_VECTOR (3 downto 0); +signal MamplAI, MamplAO : STD_LOGIC_VECTOR (16 downto 0); component hdmirx is Port ( TD_P : in STD_LOGIC_VECTOR (3 downto 0); @@ -132,7 +139,8 @@ component hdmirx is bp_stable : out STD_LOGIC; dl_low : out STD_LOGIC; dl_high : out STD_LOGIC; - mast_dl_err : out STD_LOGIC; + mast_dl_low : out STD_LOGIC; + mast_dl_high : out STD_LOGIC; mast_stable : out STD_LOGIC; dly_ctrl_ena : in STD_LOGIC; syn_err : out STD_LOGIC; @@ -178,10 +186,10 @@ HDMIA: for i in 0 to 9 generate HDMI_RX: hdmirx port map(TD_P=>TD_P(i), TD_N=>TD_N(i), RST=>SRST, ena=>link_ena(i), link_rdy=>link_OK_in(i), trig_ena=>done, clk320=>clk320, clk320_90=>clk320_90, TDO=>HDMI_in(i), rd_lock=>rd_lock1, DATA_OUT=> TDD(i), status => HDMI_status(i), master=> master_sel(i), mt_cou=>mt_cou, bitpos=>bitpos(i), bitpos_ok=>bitpos_ok_in(i), ena_dly=>ena_dly, inc_dly=>inc_dly, ena_ph=>psen_o(i), inc_ph=>ph_inc_o(i), is_idle=>is_idle(i), bp_stable=>bp_stable(i), - dl_low=> dl_low(i), dl_high=> dl_high(i), mast_dl_err=>mast_dlerr(i), mast_stable=>mast_stable(i), dly_ctrl_ena=>dly_ctrl_ena, syn_err=>sync_err(i), PM_req=>req(i)); + dl_low=> dl_low(i), dl_high=> dl_high(i), mast_dl_low=>mast_dl_low(i), mast_dl_high=>mast_dl_high(i), mast_stable=>mast_stable(i), dly_ctrl_ena=>dly_ctrl_ena, syn_err=>sync_err(i), PM_req=>req(i)); end generate; -ROM1 : ROM7x15 PORT MAP (clka => CLK320, addra => Nchan_A, douta => Avg_0); +ROM1 : ROM7x15 PORT MAP (clka => CLK320, addra => Nchan_A, douta => Avg_i); master_n<=x"0" when config(0)='1' @@ -208,21 +216,28 @@ msel: for i in 0 to 9 generate side_on<='1' when (config(9 downto 0)/=0) else '0'; dly_dec<='1' when dl_high/=0 else '0'; dly_inc<='1' when dl_low/=0 else '0'; -dly_err<= (dly_inc and dly_dec) or mdl_err; +dly_err<= (dly_inc and dly_dec) or (mast_dl_low(to_integer(unsigned(master_n))) and dly_dec) or (mast_dl_high(to_integer(unsigned(master_n))) and dly_inc); link_OK<= '1' when (link_OK_act="1111111111") and (side_on='1') else '0'; bitpos_OK<= '1' when (bitpos_ok_act="1111111111") and (side_on='1') else '0'; -dly_ctrl_ena<='1' when (mast_stable="1111111111") else '0'; +dly_ctrl_rdy<='1' when (mast_stable="1111111111") else '0'; psen<= psen_o(to_integer(unsigned(master_n))) when (side_on='1') else '0'; ph_inc<= ph_inc_o(to_integer(unsigned(master_n))) when (side_on='1') else '0'; -mdl_err<= mast_dlerr(to_integer(unsigned(master_n))) when (side_on='1') else '0'; +mdl_err<= (mast_dl_low(to_integer(unsigned(master_n))) or mast_dl_high(to_integer(unsigned(master_n)))) when (side_on='1') and (dly_err='1') else '0'; process (clk320) begin if (clk320'event and clk320='1') then - + + if (dly_ctrl_rdy='0') then dly_ctrl_ena<='0'; mast_delay<=(others=>'0'); + else + if (mast_delay/="11" & x"FFFF") then mast_delay<=mast_delay+1; + else dly_ctrl_ena<='1'; + end if; + end if; + rd_lock1<=rd_lock0; rd_lock0<=rd_lock; stat_clr2<=stat_clr1; stat_clr1<=stat_clr0; stat_clr0<=stat_clr; done0<=done; @@ -234,8 +249,11 @@ mdl_err<= mast_dlerr(to_integer(unsigned(master_n))) when (side_on='1') else '0' end if; if mdl_err='1' then mdl_err_s<='1'; else if (stat_clr2='1') and (stat_clr1='0') then mdl_err_s<='0'; end if; - end if; + end if; + if (srst='1') then sync_err_s<=(others=>'0'); + + else for i in 0 to 9 loop link_ena(i)<=config(i) and not stat_chg ; @@ -243,7 +261,8 @@ link_ena(i)<=config(i) and not stat_chg ; if sync_err(i)='1' then sync_err_s(i)<='1'; else if (stat_clr2='1') and (stat_clr1='0') then sync_err_s(i)<='0'; end if; end if; - end loop; + end loop; + end if; if (idle_cou="111111") and (done='0') and (side_on='1') then mt_cou<="111"-bitpos(to_integer(unsigned(master_n))); idle_cou<="000000"; else mt_cou<=mt_cou+1; end if; @@ -263,16 +282,15 @@ if (side_on='1') and (srst='0') then else if (done='0') and (bitpos_OK='1') and (idle_cou>"010000") then done<='1'; end if; end if; -if (link_OK_in(to_integer(unsigned(master_n)))='1') and (dly_err='0') then - if (adj_count/=x"FF") then adj_count<=adj_count+1; - else - if (dly_inc or dly_dec)='1' then adj_count<=x"00"; ena_dly<=dly_ctrl_ena; inc_dly<=dly_inc; end if; - end if; - else adj_count<=x"00"; - end if; - - if (ena_dly='1') then ena_dly<='0'; end if; - else done<='0'; idle_cou<="000000"; adj_count<=x"00"; + if (link_OK_in(to_integer(unsigned(master_n)))='1') and (dly_err='0') and ((dly_inc or dly_dec)='1') then + adj_count<=adj_count+1; + if (adj_count=x"FF") then ena_dly<='1'; inc_dly<=dly_inc; + else ena_dly<='0'; + end if; + else adj_count<=x"00"; ena_dly<='0'; + end if; + + else ena_dly<='0'; end if; @@ -288,7 +306,7 @@ process (CLK320) begin if (CLK320'event and CLK320='1') then -Avg<=Avg_0; +Avg<=Avg_i; if (mt_cou="001") then @@ -298,10 +316,10 @@ if HDMI_in(i)>x"C" then NC(i)<="0000"; else NC(i)<=HDMI_in(i); end if; end loop; - TtimeA(17 downto 14) <="0000"; MamplA(17 downto 14) <="0000"; + TtimeA(17 downto 14) <="0000"; MamplA(17 downto 14) <="0000"; MamplAI(16 downto 14) <="000"; MamplAO(16 downto 14) <="000"; else - TtimeA<=TsumA_0 & TtimeA(13 downto 2) ; - MamplA<=MsumA_0 & MamplA(13 downto 2) ; + TtimeA<=TsumA_0 & TtimeA(13 downto 2); + MamplA<=MsumA_0 & MamplA(13 downto 2); MamplAI<=MsumAI_0 & MamplAI(13 downto 2); MamplAO<=MsumAO_0 & MamplAO(13 downto 2) ; end if; @@ -312,7 +330,7 @@ if (mt_cou="110") then Nchan_A<=Nchan_A0; end if; if (mt_cou="000") then Time_o<=TsumA_F & TtimeA(13 downto 2); -Ampl_o<= MsumA_F & MamplA(13 downto 2); +Ampl_o<= MsumA_F & MamplA(13 downto 2); AmplI_o<= MsumAI_F & MamplAI(13 downto 2); AmplO_o<= MsumAO_F & MamplAO(13 downto 2); bkgnd<=bkgnd_0; end if; @@ -327,8 +345,15 @@ M10sumA<= ("00"&HDMI_in(5)(2))+("00"&HDMI_in(6)(2))+("00"&HDMI_in(7)(2))+("00"&H M01sumA<= ("00"&HDMI_in(0)(3))+("00"&HDMI_in(1)(3))+("00"&HDMI_in(2)(3))+("00"&HDMI_in(3)(3))+("00"&HDMI_in(4)(3)); M11sumA<= ("00"&HDMI_in(5)(3))+("00"&HDMI_in(6)(3))+("00"&HDMI_in(7)(3))+("00"&HDMI_in(8)(3))+("00"&HDMI_in(9)(3)); +MsumAI_0<= ("00"&M00sumA) + ("0" & M01sumA&"0") + ("00"& MamplAI(16 downto 14)); +MsumAO_0<= ("00"&M10sumA) + ("0" & M11sumA&"0") + ("00"& MamplAO(16 downto 14)); + + +MsumA_0<= ("000"&M00sumA) + ("00" & M01sumA & "0") + ("000"&M10sumA) + ("00" & M11sumA & "0") + ("00"& MamplA(17 downto 14)); -MsumA_0<= ("000"&M00sumA) + ("00" & M01sumA&"0") + ("000"&M10sumA) + ("00" & M11sumA&"0") + ("00"& MamplA(17 downto 14)); +MsumAI_F<= ("0" & M00sumA) + (M01sumA&"0") + ("0" & MamplAI(16 downto 14)) + (M01sumA(1 downto 0) & "00") + (M01sumA(0) & "000"); +MsumAO_F<= ("0" & M10sumA) + (M11sumA&"0") + ("0" & MamplAO(16 downto 14)) + (M11sumA(1 downto 0) & "00") + (M11sumA(0) & "000"); + MsumA_F<= ("00" & M00sumA) + ("0" & M01sumA&"0") +("00" & M10sumA) + ("0" & M11sumA & "0") + ("0" & MamplA(17 downto 14)) + (M01sumA & "00") + (M11sumA & "00") + (M01sumA(1 downto 0) & "000") + (M11sumA(1 downto 0) & "000") + (M01sumA(0) & "0000") + ( M11sumA(0) & "0000"); diff --git a/firmware/FT0/TCM/hdl/trigger_out.vhd b/firmware/FT0/TCM_v1/hdl/trigger_out.vhd similarity index 98% rename from firmware/FT0/TCM/hdl/trigger_out.vhd rename to firmware/FT0/TCM_v1/hdl/trigger_out.vhd index e00e750..0af202c 100644 --- a/firmware/FT0/TCM/hdl/trigger_out.vhd +++ b/firmware/FT0/TCM_v1/hdl/trigger_out.vhd @@ -73,7 +73,7 @@ begin T_out<=T_o; -T_r <= T_in when (mode="100") else '0'; +T_r <= T_i; DO<=x"0000" & "00" & ts when (A='0') else '0' & rate; diff --git a/firmware/FT0/TCM_v1/ipcore_properties/BC_corr_mem.txt b/firmware/FT0/TCM_v1/ipcore_properties/BC_corr_mem.txt index 9b506f4..b9e155d 100644 --- a/firmware/FT0/TCM_v1/ipcore_properties/BC_corr_mem.txt +++ b/firmware/FT0/TCM_v1/ipcore_properties/BC_corr_mem.txt @@ -50,7 +50,7 @@ CONFIG.READ_LATENCY_B string false 1 CONFIG.RST.ARESETN.INSERT_VIP string false 0 CONFIG.Read_Width_A string false 32 CONFIG.Read_Width_B string false 32 -CONFIG.Register_PortA_Output_of_Memory_Core string false false +CONFIG.Register_PortA_Output_of_Memory_Core string false true CONFIG.Register_PortA_Output_of_Memory_Primitives string false false CONFIG.Register_PortB_Output_of_Memory_Core string false false CONFIG.Register_PortB_Output_of_Memory_Primitives string false false diff --git a/firmware/FT0/TCM_v1/ipcore_properties/Mask_mem.txt b/firmware/FT0/TCM_v1/ipcore_properties/Mask_mem.txt new file mode 100644 index 0000000..862de0a --- /dev/null +++ b/firmware/FT0/TCM_v1/ipcore_properties/Mask_mem.txt @@ -0,0 +1,78 @@ +Property Type Read-only Value +CONFIG.AXILITE_SLAVE_S_AXI.INSERT_VIP string false 0 +CONFIG.AXI_ID_Width string false 4 +CONFIG.AXI_SLAVE_S_AXI.INSERT_VIP string false 0 +CONFIG.AXI_Slave_Type string false Memory_Slave +CONFIG.AXI_Type string false AXI4_Full +CONFIG.Additional_Inputs_for_Power_Estimation string false false +CONFIG.Algorithm string false Minimum_Area +CONFIG.Assume_Synchronous_Clk string false false +CONFIG.Byte_Size string false 9 +CONFIG.CLK.ACLK.INSERT_VIP string false 0 +CONFIG.CTRL_ECC_ALGO string false NONE +CONFIG.Coe_File string false no_coe_file_loaded +CONFIG.Collision_Warnings string false ALL +CONFIG.Component_Name string false Mask_mem +CONFIG.Disable_Collision_Warnings string false false +CONFIG.Disable_Out_of_Range_Warnings string false false +CONFIG.ECC string false false +CONFIG.EN_DEEPSLEEP_PIN string false false +CONFIG.EN_ECC_PIPE string false false +CONFIG.EN_SAFETY_CKT string false false +CONFIG.EN_SHUTDOWN_PIN string false false +CONFIG.EN_SLEEP_PIN string false false +CONFIG.Enable_32bit_Address string false false +CONFIG.Enable_A string false Always_Enabled +CONFIG.Enable_B string false Use_ENB_Pin +CONFIG.Error_Injection_Type string false Single_Bit_Error_Injection +CONFIG.Fill_Remaining_Memory_Locations string false false +CONFIG.Interface_Type string false Native +CONFIG.Load_Init_File string false false +CONFIG.MEM_FILE string false no_mem_loaded +CONFIG.Memory_Type string false True_Dual_Port_RAM +CONFIG.Operating_Mode_A string false NO_CHANGE +CONFIG.Operating_Mode_B string false NO_CHANGE +CONFIG.Output_Reset_Value_A string false 0 +CONFIG.Output_Reset_Value_B string false 0 +CONFIG.PRIM_type_to_Implement string false BRAM +CONFIG.Pipeline_Stages string false 0 +CONFIG.Port_A_Clock string false 100 +CONFIG.Port_A_Enable_Rate string false 100 +CONFIG.Port_A_Write_Rate string false 50 +CONFIG.Port_B_Clock string false 100 +CONFIG.Port_B_Enable_Rate string false 100 +CONFIG.Port_B_Write_Rate string false 50 +CONFIG.Primitive string false 8kx2 +CONFIG.RD_ADDR_CHNG_A string false false +CONFIG.RD_ADDR_CHNG_B string false false +CONFIG.READ_LATENCY_A string false 1 +CONFIG.READ_LATENCY_B string false 1 +CONFIG.RST.ARESETN.INSERT_VIP string false 0 +CONFIG.Read_Width_A string false 2 +CONFIG.Read_Width_B string false 32 +CONFIG.Register_PortA_Output_of_Memory_Core string false false +CONFIG.Register_PortA_Output_of_Memory_Primitives string false true +CONFIG.Register_PortB_Output_of_Memory_Core string false false +CONFIG.Register_PortB_Output_of_Memory_Primitives string false false +CONFIG.Remaining_Memory_Locations string false 0 +CONFIG.Reset_Memory_Latch_A string false false +CONFIG.Reset_Memory_Latch_B string false false +CONFIG.Reset_Priority_A string false CE +CONFIG.Reset_Priority_B string false CE +CONFIG.Reset_Type string false SYNC +CONFIG.Use_AXI_ID string false false +CONFIG.Use_Byte_Write_Enable string false false +CONFIG.Use_Error_Injection_Pins string false false +CONFIG.Use_REGCEA_Pin string false false +CONFIG.Use_REGCEB_Pin string false false +CONFIG.Use_RSTA_Pin string false false +CONFIG.Use_RSTB_Pin string false false +CONFIG.Write_Depth_A string false 4096 +CONFIG.Write_Width_A string false 2 +CONFIG.Write_Width_B string false 32 +CONFIG.ecctype string false No_ECC +CONFIG.register_porta_input_of_softecc string false false +CONFIG.register_portb_output_of_softecc string false false +CONFIG.softecc string false false +CONFIG.use_bram_block string false Stand_Alone +IPDEF string true xilinx.com:ip:blk_mem_gen:8.4 diff --git a/firmware/FT0/TCM_v1/ipcore_properties/cntpck_fifo_comp.txt b/firmware/FT0/TCM_v1/ipcore_properties/cntpck_fifo_comp.txt index c22a96e..abb5b43 100644 --- a/firmware/FT0/TCM_v1/ipcore_properties/cntpck_fifo_comp.txt +++ b/firmware/FT0/TCM_v1/ipcore_properties/cntpck_fifo_comp.txt @@ -14,7 +14,7 @@ CONFIG.Clock_Type_AXI string false Common_Cl CONFIG.Component_Name string false cntpck_fifo_comp CONFIG.DATA_WIDTH string false 64 CONFIG.Data_Count string false false -CONFIG.Data_Count_Width string false 7 +CONFIG.Data_Count_Width string false 8 CONFIG.Disable_Timing_Violations string false false CONFIG.Disable_Timing_Violations_AXI string false false CONFIG.Dout_Reset_Value string false 0 @@ -60,14 +60,14 @@ CONFIG.FIFO_Implementation_wdch string false Common_Cl CONFIG.FIFO_Implementation_wrch string false Common_Clock_Block_RAM CONFIG.Fifo_Implementation string false Independent_Clocks_Block_RAM CONFIG.Full_Flags_Reset_Value string false 1 -CONFIG.Full_Threshold_Assert_Value string false 127 +CONFIG.Full_Threshold_Assert_Value string false 255 CONFIG.Full_Threshold_Assert_Value_axis string false 1023 CONFIG.Full_Threshold_Assert_Value_rach string false 1023 CONFIG.Full_Threshold_Assert_Value_rdch string false 1023 CONFIG.Full_Threshold_Assert_Value_wach string false 1023 CONFIG.Full_Threshold_Assert_Value_wdch string false 1023 CONFIG.Full_Threshold_Assert_Value_wrch string false 1023 -CONFIG.Full_Threshold_Negate_Value string false 126 +CONFIG.Full_Threshold_Negate_Value string false 254 CONFIG.HAS_ACLKEN string false false CONFIG.HAS_TKEEP string false false CONFIG.HAS_TSTRB string false false @@ -87,8 +87,8 @@ CONFIG.Inject_Sbit_Error_rdch string false false CONFIG.Inject_Sbit_Error_wach string false false CONFIG.Inject_Sbit_Error_wdch string false false CONFIG.Inject_Sbit_Error_wrch string false false -CONFIG.Input_Data_Width string false 160 -CONFIG.Input_Depth string false 128 +CONFIG.Input_Data_Width string false 128 +CONFIG.Input_Depth string false 256 CONFIG.Input_Depth_axis string false 1024 CONFIG.Input_Depth_rach string false 16 CONFIG.Input_Depth_rdch string false 1024 @@ -100,9 +100,9 @@ CONFIG.MASTER_ACLK.INSERT_VIP string false 0 CONFIG.M_AXI.INSERT_VIP string false 0 CONFIG.M_AXIS.INSERT_VIP string false 0 CONFIG.Master_interface_Clock_enable_memory_mapped string false false -CONFIG.Output_Data_Width string false 160 -CONFIG.Output_Depth string false 128 -CONFIG.Output_Register_Type string false Embedded_Reg +CONFIG.Output_Data_Width string false 128 +CONFIG.Output_Depth string false 256 +CONFIG.Output_Register_Type string false Fabric_Reg CONFIG.Overflow_Flag string false false CONFIG.Overflow_Flag_AXI string false false CONFIG.Overflow_Sense string false Active_High @@ -155,9 +155,9 @@ CONFIG.Underflow_Flag_AXI string false false CONFIG.Underflow_Sense string false Active_High CONFIG.Underflow_Sense_AXI string false Active_High CONFIG.Use_Dout_Reset string false true -CONFIG.Use_Embedded_Registers string false false +CONFIG.Use_Embedded_Registers string false true CONFIG.Use_Embedded_Registers_axis string false false -CONFIG.Use_Extra_Logic string false true +CONFIG.Use_Extra_Logic string false false CONFIG.Valid_Flag string false false CONFIG.Valid_Sense string false Active_High CONFIG.WRITE_CLK.FREQ_HZ string false 100000000 diff --git a/firmware/FT0/TCM_v1/ipcore_properties/err_report_fifo.txt b/firmware/FT0/TCM_v1/ipcore_properties/err_report_fifo.txt new file mode 100644 index 0000000..ae3e3d4 --- /dev/null +++ b/firmware/FT0/TCM_v1/ipcore_properties/err_report_fifo.txt @@ -0,0 +1,185 @@ +Property Type Read-only Value +CONFIG.ADDRESS_WIDTH string false 32 +CONFIG.ARUSER_Width string false 0 +CONFIG.AWUSER_Width string false 0 +CONFIG.Add_NGC_Constraint_AXI string false false +CONFIG.Almost_Empty_Flag string false false +CONFIG.Almost_Full_Flag string false false +CONFIG.BUSER_Width string false 0 +CONFIG.CORE_CLK.FREQ_HZ string false 100000000 +CONFIG.CORE_CLK.INSERT_VIP string false 0 +CONFIG.C_SELECT_XPM string false 0 +CONFIG.Clock_Enable_Type string false Slave_Interface_Clock_Enable +CONFIG.Clock_Type_AXI string false Common_Clock +CONFIG.Component_Name string false err_report_fifo +CONFIG.DATA_WIDTH string false 64 +CONFIG.Data_Count string false false +CONFIG.Data_Count_Width string false 11 +CONFIG.Disable_Timing_Violations string false false +CONFIG.Disable_Timing_Violations_AXI string false false +CONFIG.Dout_Reset_Value string false 0 +CONFIG.Empty_Threshold_Assert_Value string false 4 +CONFIG.Empty_Threshold_Assert_Value_axis string false 1022 +CONFIG.Empty_Threshold_Assert_Value_rach string false 1022 +CONFIG.Empty_Threshold_Assert_Value_rdch string false 1022 +CONFIG.Empty_Threshold_Assert_Value_wach string false 1022 +CONFIG.Empty_Threshold_Assert_Value_wdch string false 1022 +CONFIG.Empty_Threshold_Assert_Value_wrch string false 1022 +CONFIG.Empty_Threshold_Negate_Value string false 5 +CONFIG.Enable_Common_Overflow string false false +CONFIG.Enable_Common_Underflow string false false +CONFIG.Enable_Data_Counts_axis string false false +CONFIG.Enable_Data_Counts_rach string false false +CONFIG.Enable_Data_Counts_rdch string false false +CONFIG.Enable_Data_Counts_wach string false false +CONFIG.Enable_Data_Counts_wdch string false false +CONFIG.Enable_Data_Counts_wrch string false false +CONFIG.Enable_ECC string false false +CONFIG.Enable_ECC_Type string false Hard_ECC +CONFIG.Enable_ECC_axis string false false +CONFIG.Enable_ECC_rach string false false +CONFIG.Enable_ECC_rdch string false false +CONFIG.Enable_ECC_wach string false false +CONFIG.Enable_ECC_wdch string false false +CONFIG.Enable_ECC_wrch string false false +CONFIG.Enable_Reset_Synchronization string false true +CONFIG.Enable_Safety_Circuit string false false +CONFIG.Enable_TLAST string false false +CONFIG.Enable_TREADY string false true +CONFIG.FIFO_Application_Type_axis string false Data_FIFO +CONFIG.FIFO_Application_Type_rach string false Data_FIFO +CONFIG.FIFO_Application_Type_rdch string false Data_FIFO +CONFIG.FIFO_Application_Type_wach string false Data_FIFO +CONFIG.FIFO_Application_Type_wdch string false Data_FIFO +CONFIG.FIFO_Application_Type_wrch string false Data_FIFO +CONFIG.FIFO_Implementation_axis string false Common_Clock_Block_RAM +CONFIG.FIFO_Implementation_rach string false Common_Clock_Block_RAM +CONFIG.FIFO_Implementation_rdch string false Common_Clock_Block_RAM +CONFIG.FIFO_Implementation_wach string false Common_Clock_Block_RAM +CONFIG.FIFO_Implementation_wdch string false Common_Clock_Block_RAM +CONFIG.FIFO_Implementation_wrch string false Common_Clock_Block_RAM +CONFIG.Fifo_Implementation string false Common_Clock_Block_RAM +CONFIG.Full_Flags_Reset_Value string false 0 +CONFIG.Full_Threshold_Assert_Value string false 1023 +CONFIG.Full_Threshold_Assert_Value_axis string false 1023 +CONFIG.Full_Threshold_Assert_Value_rach string false 1023 +CONFIG.Full_Threshold_Assert_Value_rdch string false 1023 +CONFIG.Full_Threshold_Assert_Value_wach string false 1023 +CONFIG.Full_Threshold_Assert_Value_wdch string false 1023 +CONFIG.Full_Threshold_Assert_Value_wrch string false 1023 +CONFIG.Full_Threshold_Negate_Value string false 1022 +CONFIG.HAS_ACLKEN string false false +CONFIG.HAS_TKEEP string false false +CONFIG.HAS_TSTRB string false false +CONFIG.ID_WIDTH string false 0 +CONFIG.INTERFACE_TYPE string false Native +CONFIG.Inject_Dbit_Error string false false +CONFIG.Inject_Dbit_Error_axis string false false +CONFIG.Inject_Dbit_Error_rach string false false +CONFIG.Inject_Dbit_Error_rdch string false false +CONFIG.Inject_Dbit_Error_wach string false false +CONFIG.Inject_Dbit_Error_wdch string false false +CONFIG.Inject_Dbit_Error_wrch string false false +CONFIG.Inject_Sbit_Error string false false +CONFIG.Inject_Sbit_Error_axis string false false +CONFIG.Inject_Sbit_Error_rach string false false +CONFIG.Inject_Sbit_Error_rdch string false false +CONFIG.Inject_Sbit_Error_wach string false false +CONFIG.Inject_Sbit_Error_wdch string false false +CONFIG.Inject_Sbit_Error_wrch string false false +CONFIG.Input_Data_Width string false 32 +CONFIG.Input_Depth string false 1024 +CONFIG.Input_Depth_axis string false 1024 +CONFIG.Input_Depth_rach string false 16 +CONFIG.Input_Depth_rdch string false 1024 +CONFIG.Input_Depth_wach string false 16 +CONFIG.Input_Depth_wdch string false 1024 +CONFIG.Input_Depth_wrch string false 16 +CONFIG.MASTER_ACLK.FREQ_HZ string false 100000000 +CONFIG.MASTER_ACLK.INSERT_VIP string false 0 +CONFIG.M_AXI.INSERT_VIP string false 0 +CONFIG.M_AXIS.INSERT_VIP string false 0 +CONFIG.Master_interface_Clock_enable_memory_mapped string false false +CONFIG.Output_Data_Width string false 32 +CONFIG.Output_Depth string false 1024 +CONFIG.Output_Register_Type string false Embedded_Reg +CONFIG.Overflow_Flag string false false +CONFIG.Overflow_Flag_AXI string false false +CONFIG.Overflow_Sense string false Active_High +CONFIG.Overflow_Sense_AXI string false Active_High +CONFIG.PROTOCOL string false AXI4 +CONFIG.Performance_Options string false First_Word_Fall_Through +CONFIG.Programmable_Empty_Type string false No_Programmable_Empty_Threshold +CONFIG.Programmable_Empty_Type_axis string false No_Programmable_Empty_Threshold +CONFIG.Programmable_Empty_Type_rach string false No_Programmable_Empty_Threshold +CONFIG.Programmable_Empty_Type_rdch string false No_Programmable_Empty_Threshold +CONFIG.Programmable_Empty_Type_wach string false No_Programmable_Empty_Threshold +CONFIG.Programmable_Empty_Type_wdch string false No_Programmable_Empty_Threshold +CONFIG.Programmable_Empty_Type_wrch string false No_Programmable_Empty_Threshold +CONFIG.Programmable_Full_Type string false No_Programmable_Full_Threshold +CONFIG.Programmable_Full_Type_axis string false No_Programmable_Full_Threshold +CONFIG.Programmable_Full_Type_rach string false No_Programmable_Full_Threshold +CONFIG.Programmable_Full_Type_rdch string false No_Programmable_Full_Threshold +CONFIG.Programmable_Full_Type_wach string false No_Programmable_Full_Threshold +CONFIG.Programmable_Full_Type_wdch string false No_Programmable_Full_Threshold +CONFIG.Programmable_Full_Type_wrch string false No_Programmable_Full_Threshold +CONFIG.READ_CLK.FREQ_HZ string false 100000000 +CONFIG.READ_CLK.INSERT_VIP string false 0 +CONFIG.READ_WRITE_MODE string false READ_WRITE +CONFIG.RUSER_Width string false 0 +CONFIG.Read_Clock_Frequency string false 1 +CONFIG.Read_Data_Count string false false +CONFIG.Read_Data_Count_Width string false 11 +CONFIG.Register_Slice_Mode_axis string false Fully_Registered +CONFIG.Register_Slice_Mode_rach string false Fully_Registered +CONFIG.Register_Slice_Mode_rdch string false Fully_Registered +CONFIG.Register_Slice_Mode_wach string false Fully_Registered +CONFIG.Register_Slice_Mode_wdch string false Fully_Registered +CONFIG.Register_Slice_Mode_wrch string false Fully_Registered +CONFIG.Reset_Pin string false true +CONFIG.Reset_Type string false Synchronous_Reset +CONFIG.SLAVE_ACLK.FREQ_HZ string false 100000000 +CONFIG.SLAVE_ACLK.INSERT_VIP string false 0 +CONFIG.SLAVE_ARESETN.INSERT_VIP string false 0 +CONFIG.S_AXI.INSERT_VIP string false 0 +CONFIG.S_AXIS.INSERT_VIP string false 0 +CONFIG.Slave_interface_Clock_enable_memory_mapped string false false +CONFIG.TDATA_NUM_BYTES string false 1 +CONFIG.TDEST_WIDTH string false 0 +CONFIG.TID_WIDTH string false 0 +CONFIG.TKEEP_WIDTH string false 1 +CONFIG.TSTRB_WIDTH string false 1 +CONFIG.TUSER_WIDTH string false 4 +CONFIG.Underflow_Flag string false false +CONFIG.Underflow_Flag_AXI string false false +CONFIG.Underflow_Sense string false Active_High +CONFIG.Underflow_Sense_AXI string false Active_High +CONFIG.Use_Dout_Reset string false true +CONFIG.Use_Embedded_Registers string false false +CONFIG.Use_Embedded_Registers_axis string false false +CONFIG.Use_Extra_Logic string false true +CONFIG.Valid_Flag string false false +CONFIG.Valid_Sense string false Active_High +CONFIG.WRITE_CLK.FREQ_HZ string false 100000000 +CONFIG.WRITE_CLK.INSERT_VIP string false 0 +CONFIG.WUSER_Width string false 0 +CONFIG.Write_Acknowledge_Flag string false false +CONFIG.Write_Acknowledge_Sense string false Active_High +CONFIG.Write_Clock_Frequency string false 1 +CONFIG.Write_Data_Count string false false +CONFIG.Write_Data_Count_Width string false 11 +CONFIG.asymmetric_port_width string false false +CONFIG.axis_type string false FIFO +CONFIG.dynamic_power_saving string false false +CONFIG.ecc_pipeline_reg string false false +CONFIG.enable_low_latency string false false +CONFIG.enable_read_pointer_increment_by2 string false false +CONFIG.rach_type string false FIFO +CONFIG.rdch_type string false FIFO +CONFIG.synchronization_stages string false 2 +CONFIG.synchronization_stages_axi string false 2 +CONFIG.use_dout_register string false false +CONFIG.wach_type string false FIFO +CONFIG.wdch_type string false FIFO +CONFIG.wrch_type string false FIFO +IPDEF string true xilinx.com:ip:fifo_generator:13.2 diff --git a/firmware/FT0/TCM_v1/ipcore_properties/raw_data_fifo.txt b/firmware/FT0/TCM_v1/ipcore_properties/raw_data_fifo.txt index 8629119..4837ca1 100644 --- a/firmware/FT0/TCM_v1/ipcore_properties/raw_data_fifo.txt +++ b/firmware/FT0/TCM_v1/ipcore_properties/raw_data_fifo.txt @@ -4,7 +4,7 @@ CONFIG.ARUSER_Width string false 0 CONFIG.AWUSER_Width string false 0 CONFIG.Add_NGC_Constraint_AXI string false false CONFIG.Almost_Empty_Flag string false false -CONFIG.Almost_Full_Flag string false false +CONFIG.Almost_Full_Flag string false true CONFIG.BUSER_Width string false 0 CONFIG.CORE_CLK.FREQ_HZ string false 100000000 CONFIG.CORE_CLK.INSERT_VIP string false 0 @@ -60,14 +60,14 @@ CONFIG.FIFO_Implementation_wdch string false Common_Cl CONFIG.FIFO_Implementation_wrch string false Common_Clock_Block_RAM CONFIG.Fifo_Implementation string false Common_Clock_Block_RAM CONFIG.Full_Flags_Reset_Value string false 0 -CONFIG.Full_Threshold_Assert_Value string false 4095 +CONFIG.Full_Threshold_Assert_Value string false 4000 CONFIG.Full_Threshold_Assert_Value_axis string false 1023 CONFIG.Full_Threshold_Assert_Value_rach string false 1023 CONFIG.Full_Threshold_Assert_Value_rdch string false 1023 CONFIG.Full_Threshold_Assert_Value_wach string false 1023 CONFIG.Full_Threshold_Assert_Value_wdch string false 1023 CONFIG.Full_Threshold_Assert_Value_wrch string false 1023 -CONFIG.Full_Threshold_Negate_Value string false 4094 +CONFIG.Full_Threshold_Negate_Value string false 3999 CONFIG.HAS_ACLKEN string false false CONFIG.HAS_TKEEP string false false CONFIG.HAS_TSTRB string false false @@ -102,7 +102,7 @@ CONFIG.M_AXIS.INSERT_VIP string false 0 CONFIG.Master_interface_Clock_enable_memory_mapped string false false CONFIG.Output_Data_Width string false 80 CONFIG.Output_Depth string false 4096 -CONFIG.Output_Register_Type string false Embedded_Reg +CONFIG.Output_Register_Type string false Fabric_Reg CONFIG.Overflow_Flag string false false CONFIG.Overflow_Flag_AXI string false false CONFIG.Overflow_Sense string false Active_High @@ -116,7 +116,7 @@ CONFIG.Programmable_Empty_Type_rdch string false No_Progra CONFIG.Programmable_Empty_Type_wach string false No_Programmable_Empty_Threshold CONFIG.Programmable_Empty_Type_wdch string false No_Programmable_Empty_Threshold CONFIG.Programmable_Empty_Type_wrch string false No_Programmable_Empty_Threshold -CONFIG.Programmable_Full_Type string false No_Programmable_Full_Threshold +CONFIG.Programmable_Full_Type string false Single_Programmable_Full_Threshold_Constant CONFIG.Programmable_Full_Type_axis string false No_Programmable_Full_Threshold CONFIG.Programmable_Full_Type_rach string false No_Programmable_Full_Threshold CONFIG.Programmable_Full_Type_rdch string false No_Programmable_Full_Threshold @@ -155,7 +155,7 @@ CONFIG.Underflow_Flag_AXI string false false CONFIG.Underflow_Sense string false Active_High CONFIG.Underflow_Sense_AXI string false Active_High CONFIG.Use_Dout_Reset string false true -CONFIG.Use_Embedded_Registers string false false +CONFIG.Use_Embedded_Registers string false true CONFIG.Use_Embedded_Registers_axis string false false CONFIG.Use_Extra_Logic string false true CONFIG.Valid_Flag string false false diff --git a/firmware/FT0/TCM_v1/ipcore_properties/slct_data_fifo.txt b/firmware/FT0/TCM_v1/ipcore_properties/slct_data_fifo.txt index 52b27f5..556b30a 100644 --- a/firmware/FT0/TCM_v1/ipcore_properties/slct_data_fifo.txt +++ b/firmware/FT0/TCM_v1/ipcore_properties/slct_data_fifo.txt @@ -14,7 +14,7 @@ CONFIG.Clock_Type_AXI string false Common_Cl CONFIG.Component_Name string false slct_data_fifo CONFIG.DATA_WIDTH string false 64 CONFIG.Data_Count string false false -CONFIG.Data_Count_Width string false 12 +CONFIG.Data_Count_Width string false 14 CONFIG.Disable_Timing_Violations string false false CONFIG.Disable_Timing_Violations_AXI string false false CONFIG.Dout_Reset_Value string false 0 @@ -60,14 +60,14 @@ CONFIG.FIFO_Implementation_wdch string false Common_Cl CONFIG.FIFO_Implementation_wrch string false Common_Clock_Block_RAM CONFIG.Fifo_Implementation string false Independent_Clocks_Block_RAM CONFIG.Full_Flags_Reset_Value string false 1 -CONFIG.Full_Threshold_Assert_Value string false 4095 +CONFIG.Full_Threshold_Assert_Value string false 16000 CONFIG.Full_Threshold_Assert_Value_axis string false 1023 CONFIG.Full_Threshold_Assert_Value_rach string false 1023 CONFIG.Full_Threshold_Assert_Value_rdch string false 1023 CONFIG.Full_Threshold_Assert_Value_wach string false 1023 CONFIG.Full_Threshold_Assert_Value_wdch string false 1023 CONFIG.Full_Threshold_Assert_Value_wrch string false 1023 -CONFIG.Full_Threshold_Negate_Value string false 4094 +CONFIG.Full_Threshold_Negate_Value string false 15999 CONFIG.HAS_ACLKEN string false false CONFIG.HAS_TKEEP string false false CONFIG.HAS_TSTRB string false false @@ -88,7 +88,7 @@ CONFIG.Inject_Sbit_Error_wach string false false CONFIG.Inject_Sbit_Error_wdch string false false CONFIG.Inject_Sbit_Error_wrch string false false CONFIG.Input_Data_Width string false 80 -CONFIG.Input_Depth string false 4096 +CONFIG.Input_Depth string false 16384 CONFIG.Input_Depth_axis string false 1024 CONFIG.Input_Depth_rach string false 16 CONFIG.Input_Depth_rdch string false 1024 @@ -101,8 +101,8 @@ CONFIG.M_AXI.INSERT_VIP string false 0 CONFIG.M_AXIS.INSERT_VIP string false 0 CONFIG.Master_interface_Clock_enable_memory_mapped string false false CONFIG.Output_Data_Width string false 80 -CONFIG.Output_Depth string false 4096 -CONFIG.Output_Register_Type string false Embedded_Reg +CONFIG.Output_Depth string false 16384 +CONFIG.Output_Register_Type string false Fabric_Reg CONFIG.Overflow_Flag string false false CONFIG.Overflow_Flag_AXI string false false CONFIG.Overflow_Sense string false Active_High @@ -116,7 +116,7 @@ CONFIG.Programmable_Empty_Type_rdch string false No_Progra CONFIG.Programmable_Empty_Type_wach string false No_Programmable_Empty_Threshold CONFIG.Programmable_Empty_Type_wdch string false No_Programmable_Empty_Threshold CONFIG.Programmable_Empty_Type_wrch string false No_Programmable_Empty_Threshold -CONFIG.Programmable_Full_Type string false No_Programmable_Full_Threshold +CONFIG.Programmable_Full_Type string false Single_Programmable_Full_Threshold_Constant CONFIG.Programmable_Full_Type_axis string false No_Programmable_Full_Threshold CONFIG.Programmable_Full_Type_rach string false No_Programmable_Full_Threshold CONFIG.Programmable_Full_Type_rdch string false No_Programmable_Full_Threshold @@ -129,7 +129,7 @@ CONFIG.READ_WRITE_MODE string false READ_WRIT CONFIG.RUSER_Width string false 0 CONFIG.Read_Clock_Frequency string false 1 CONFIG.Read_Data_Count string false true -CONFIG.Read_Data_Count_Width string false 13 +CONFIG.Read_Data_Count_Width string false 15 CONFIG.Register_Slice_Mode_axis string false Fully_Registered CONFIG.Register_Slice_Mode_rach string false Fully_Registered CONFIG.Register_Slice_Mode_rdch string false Fully_Registered @@ -155,7 +155,7 @@ CONFIG.Underflow_Flag_AXI string false false CONFIG.Underflow_Sense string false Active_High CONFIG.Underflow_Sense_AXI string false Active_High CONFIG.Use_Dout_Reset string false true -CONFIG.Use_Embedded_Registers string false false +CONFIG.Use_Embedded_Registers string false true CONFIG.Use_Embedded_Registers_axis string false false CONFIG.Use_Extra_Logic string false true CONFIG.Valid_Flag string false false @@ -167,7 +167,7 @@ CONFIG.Write_Acknowledge_Flag string false false CONFIG.Write_Acknowledge_Sense string false Active_High CONFIG.Write_Clock_Frequency string false 1 CONFIG.Write_Data_Count string false true -CONFIG.Write_Data_Count_Width string false 13 +CONFIG.Write_Data_Count_Width string false 15 CONFIG.asymmetric_port_width string false false CONFIG.axis_type string false FIFO CONFIG.dynamic_power_saving string false false diff --git a/firmware/FT0/TCM_v1/ipcore_properties/trg_fifo_comp.txt b/firmware/FT0/TCM_v1/ipcore_properties/trg_fifo_comp.txt index b59b93e..ba10aac 100644 --- a/firmware/FT0/TCM_v1/ipcore_properties/trg_fifo_comp.txt +++ b/firmware/FT0/TCM_v1/ipcore_properties/trg_fifo_comp.txt @@ -14,7 +14,7 @@ CONFIG.Clock_Type_AXI string false Common_Cl CONFIG.Component_Name string false trg_fifo_comp CONFIG.DATA_WIDTH string false 64 CONFIG.Data_Count string false false -CONFIG.Data_Count_Width string false 9 +CONFIG.Data_Count_Width string false 12 CONFIG.Disable_Timing_Violations string false false CONFIG.Disable_Timing_Violations_AXI string false false CONFIG.Dout_Reset_Value string false 0 @@ -60,14 +60,14 @@ CONFIG.FIFO_Implementation_wdch string false Common_Cl CONFIG.FIFO_Implementation_wrch string false Common_Clock_Block_RAM CONFIG.Fifo_Implementation string false Independent_Clocks_Block_RAM CONFIG.Full_Flags_Reset_Value string false 1 -CONFIG.Full_Threshold_Assert_Value string false 511 +CONFIG.Full_Threshold_Assert_Value string false 4095 CONFIG.Full_Threshold_Assert_Value_axis string false 1023 CONFIG.Full_Threshold_Assert_Value_rach string false 1023 CONFIG.Full_Threshold_Assert_Value_rdch string false 1023 CONFIG.Full_Threshold_Assert_Value_wach string false 1023 CONFIG.Full_Threshold_Assert_Value_wdch string false 1023 CONFIG.Full_Threshold_Assert_Value_wrch string false 1023 -CONFIG.Full_Threshold_Negate_Value string false 510 +CONFIG.Full_Threshold_Negate_Value string false 4094 CONFIG.HAS_ACLKEN string false false CONFIG.HAS_TKEEP string false false CONFIG.HAS_TSTRB string false false @@ -88,7 +88,7 @@ CONFIG.Inject_Sbit_Error_wach string false false CONFIG.Inject_Sbit_Error_wdch string false false CONFIG.Inject_Sbit_Error_wrch string false false CONFIG.Input_Data_Width string false 76 -CONFIG.Input_Depth string false 512 +CONFIG.Input_Depth string false 4096 CONFIG.Input_Depth_axis string false 1024 CONFIG.Input_Depth_rach string false 16 CONFIG.Input_Depth_rdch string false 1024 @@ -101,8 +101,8 @@ CONFIG.M_AXI.INSERT_VIP string false 0 CONFIG.M_AXIS.INSERT_VIP string false 0 CONFIG.Master_interface_Clock_enable_memory_mapped string false false CONFIG.Output_Data_Width string false 76 -CONFIG.Output_Depth string false 512 -CONFIG.Output_Register_Type string false Embedded_Reg +CONFIG.Output_Depth string false 4096 +CONFIG.Output_Register_Type string false Fabric_Reg CONFIG.Overflow_Flag string false false CONFIG.Overflow_Flag_AXI string false false CONFIG.Overflow_Sense string false Active_High @@ -129,7 +129,7 @@ CONFIG.READ_WRITE_MODE string false READ_WRIT CONFIG.RUSER_Width string false 0 CONFIG.Read_Clock_Frequency string false 1 CONFIG.Read_Data_Count string false true -CONFIG.Read_Data_Count_Width string false 10 +CONFIG.Read_Data_Count_Width string false 12 CONFIG.Register_Slice_Mode_axis string false Fully_Registered CONFIG.Register_Slice_Mode_rach string false Fully_Registered CONFIG.Register_Slice_Mode_rdch string false Fully_Registered @@ -155,9 +155,9 @@ CONFIG.Underflow_Flag_AXI string false false CONFIG.Underflow_Sense string false Active_High CONFIG.Underflow_Sense_AXI string false Active_High CONFIG.Use_Dout_Reset string false true -CONFIG.Use_Embedded_Registers string false false +CONFIG.Use_Embedded_Registers string false true CONFIG.Use_Embedded_Registers_axis string false false -CONFIG.Use_Extra_Logic string false true +CONFIG.Use_Extra_Logic string false false CONFIG.Valid_Flag string false false CONFIG.Valid_Sense string false Active_High CONFIG.WRITE_CLK.FREQ_HZ string false 100000000 @@ -167,7 +167,7 @@ CONFIG.Write_Acknowledge_Flag string false false CONFIG.Write_Acknowledge_Sense string false Active_High CONFIG.Write_Clock_Frequency string false 1 CONFIG.Write_Data_Count string false true -CONFIG.Write_Data_Count_Width string false 10 +CONFIG.Write_Data_Count_Width string false 12 CONFIG.asymmetric_port_width string false false CONFIG.axis_type string false FIFO CONFIG.dynamic_power_saving string false false diff --git a/firmware/FT0/TCM_v1/make.tcl b/firmware/FT0/TCM_v1/make.tcl index f690d7a..2b9192e 100644 --- a/firmware/FT0/TCM_v1/make.tcl +++ b/firmware/FT0/TCM_v1/make.tcl @@ -121,14 +121,14 @@ set obj [get_filesets sources_1] # Import local files from the original project set files [list \ [file normalize "${origin_dir}/hdl/tcm.vhd" ]\ - [file normalize "${origin_dir}/../TCM/hdl/counter32.vhd" ]\ - [file normalize "${origin_dir}/../TCM/hdl/Flash_prog.vhd" ]\ - [file normalize "${origin_dir}/../TCM/hdl/pm-spi.vhd" ]\ - [file normalize "${origin_dir}/../TCM/hdl/cnt_ctrl.vhd" ]\ - [file normalize "${origin_dir}/../TCM/hdl/trigger_out.vhd" ]\ - [file normalize "${origin_dir}/../TCM/hdl/tcm_side.vhd" ]\ - [file normalize "${origin_dir}/../TCM/hdl/HDMIRX.vhd" ]\ - [file normalize "${origin_dir}/../TCM/hdl/BC_correlator.vhd" ]\ + [file normalize "${origin_dir}/hdl/counter32.vhd" ]\ + [file normalize "${origin_dir}/hdl/Flash_prog.vhd" ]\ + [file normalize "${origin_dir}/hdl/pm-spi.vhd" ]\ + [file normalize "${origin_dir}/hdl/cnt_ctrl.vhd" ]\ + [file normalize "${origin_dir}/hdl/trigger_out.vhd" ]\ + [file normalize "${origin_dir}/hdl/tcm_side.vhd" ]\ + [file normalize "${origin_dir}/hdl/HDMIRX.vhd" ]\ + [file normalize "${origin_dir}/hdl/BC_correlator.vhd" ]\ [file normalize "${origin_dir}/../../common/ipbus/hdl/ipbus_core/udp_dualportram.vhd" ]\ [file normalize "${origin_dir}/../../common/ipbus/hdl/ipbus_core/udp_build_arp.vhd" ]\ [file normalize "${origin_dir}/../../common/ipbus/hdl/ipbus_core/udp_txtransactor_if_simple.vhd" ]\ @@ -219,21 +219,21 @@ set files [list \ [file normalize "${origin_dir}/../../common/gbt-fpga/hdl/gbt_bank/core_sources/gbt_bank.vhd" ]\ [file normalize "${origin_dir}/../../common/gbt-fpga/hdl/gbt_bank/core_sources/gbt_rx/gbt_rx_decoder_gbtframe_syndrom.vhd" ]\ [file normalize "${origin_dir}/../../common/gbt-readout/hdl/GBT_TXRX5.vhd"] \ - [file normalize "${origin_dir}/../../common/gbt-readout/hdl/DataCLK_strobe.vhd" ]\ [file normalize "${origin_dir}/../../common/gbt-readout/hdl/DataConverter_TCM.vhd" ]\ - [file normalize "${origin_dir}/../../common/gbt-readout/hdl/RX_Data_Decoder.vhd" ]\ - [file normalize "${origin_dir}/../../common/gbt-readout/hdl/BC_counter.vhd" ]\ + [file normalize "${origin_dir}/../../common/gbt-readout/hdl/ltu_rx_decoder.vhd" ]\ + [file normalize "${origin_dir}/../../common/gbt-readout/hdl/bc_indicator.vhd" ]\ [file normalize "${origin_dir}/../../common/gbt-readout/hdl/Reset_Generator.vhd" ]\ [file normalize "${origin_dir}/../../common/gbt-readout/hdl/fit_gbt_boardTCM_package.vhd" ]\ [file normalize "${origin_dir}/../../common/gbt-readout/hdl/FIT_GBT_project.vhd" ]\ [file normalize "${origin_dir}/../../common/gbt-readout/hdl/Module_Data_Gen_TCM.vhd" ]\ - [file normalize "${origin_dir}/../../common/gbt-readout/hdl/CRU_ORBC_Gen.vhd" ]\ + [file normalize "${origin_dir}/../../common/gbt-readout/hdl/cru_ltu_emu.vhd" ]\ [file normalize "${origin_dir}/../../common/gbt-readout/hdl/TX_Data_Gen.vhd" ]\ [file normalize "${origin_dir}/../../common/gbt-readout/hdl/Event_selector.vhd" ]\ [file normalize "${origin_dir}/../../common/gbt-readout/hdl/fit_gbt_common_package.vhd" ]\ [file normalize "${origin_dir}/../../common/gbt-readout/hdl/RXDataClkSync.vhd" ]\ [file normalize "${origin_dir}/../../common/gbt-readout/hdl/CRU_packet_Builder.vhd" ]\ - [file normalize "${origin_dir}/../../common/gbt-readout/hdl/Data_Packager.vhd" ]\ + [file normalize "${origin_dir}/../../common/gbt-readout/hdl/snapshot_fifo.vhd" ]\ + [file normalize "${origin_dir}/../../common/gbt-readout/hdl/error_report.vhd" ]\ ] #set imported_files [import_files -fileset sources_1 $files] add_files -norecurse -fileset sources_1 $files @@ -292,6 +292,9 @@ if {[string equal $proj_create "yes"]} { } #------------------------------------------------------------------------------- +#timing report strategy +config_webtalk -user off + # upgrade_ip [get_ips] generate_target synthesis [get_ips] -force @@ -372,7 +375,7 @@ current_run -synthesis [get_runs synth_1] # Create 'impl_1' run (if not found) if {[string equal [get_runs -quiet impl_1] ""]} { - create_run -name impl_1 -part ${part} -flow {Vivado Implementation 2019} -strategy "Performance_NetDelay_low" -report_strategy {No Reports} -constrset constrs_1 -parent_run synth_1 + create_run -name impl_1 -part ${part} -flow {Vivado Implementation 2019} -strategy "Performance_NetDelay_low" -report_strategy {Timing Closure Reports} -constrset constrs_1 -parent_run synth_1 } else { set_property strategy "Performance_NetDelay_low" [get_runs impl_1] set_property flow "Vivado Implementation 2019" [get_runs impl_1] @@ -416,6 +419,7 @@ set_property -name "steps.phys_opt_design.args.directive" -value "AggressiveExpl set_property -name "steps.route_design.args.directive" -value "NoTimingRelaxation" -objects $obj set_property -name "steps.write_bitstream.args.readback_file" -value "0" -objects $obj set_property -name "steps.write_bitstream.args.verbose" -value "0" -objects $obj +set_property -name "steps.write_bitstream.args.bin_file" -value "1" -objects $obj # set the current impl run current_run -implementation [get_runs impl_1] @@ -426,3 +430,5 @@ update_compile_order -fileset sources_1 reset_run -quiet synth_1 launch_runs impl_1 -to_step write_bitstream -jobs 7 wait_on_run impl_1 +open_run impl_1 +report_timing_summary -file impl_1_timing_summary.log diff --git a/firmware/FT0/TCM_v1/xdc/tcm.xdc b/firmware/FT0/TCM_v1/xdc/tcm.xdc index 2e04c98..bf82a78 100644 --- a/firmware/FT0/TCM_v1/xdc/tcm.xdc +++ b/firmware/FT0/TCM_v1/xdc/tcm.xdc @@ -1,115 +1,119 @@ -# Ethernet RefClk (125MHz) -create_clock -period 8.000 -name eth_refclk [get_ports ETHCLK_P] - -create_clock -period 12.500 -name LCLK [get_ports LCLK_P] - - -# Ethernet driven by Ethernet txoutclk (i.e. via transceiver) -create_generated_clock -name eth_clk_62_5 -source [get_pins ipbus_module/eth/mmcm/inst/mmcm_adv_inst/CLKIN1] [get_pins ipbus_module/eth/mmcm/inst/mmcm_adv_inst/CLKOUT0] -create_generated_clock -name eth_clk_125 -source [get_pins ipbus_module/eth/mmcm/inst/mmcm_adv_inst/CLKIN1] [get_pins ipbus_module/eth/mmcm/inst/mmcm_adv_inst/CLKOUT1] - -# Clocks derived from MMCM driven by Ethernet RefClk directly (i.e. not via transceiver) -create_generated_clock -name clk_ipb -source [get_pins ipbus_module/clocks/pll/inst/plle2_adv_inst/CLKIN1] [get_pins ipbus_module/clocks/pll/inst/plle2_adv_inst/CLKOUT0] -create_generated_clock -name free_clk -source [get_pins ipbus_module/clocks/pll/inst/plle2_adv_inst/CLKIN1] [get_pins ipbus_module/clocks/pll/inst/plle2_adv_inst/CLKOUT1] -create_generated_clock -name dly_clk -source [get_pins ipbus_module/clocks/pll/inst/plle2_adv_inst/CLKIN1] [get_pins ipbus_module/clocks/pll/inst/plle2_adv_inst/CLKOUT2] - -create_clock -period 5.000 -name MGTCLK [get_ports MGTCLK_P] -create_clock -period 8.333 -name RxWordCLK [get_pins {FitGbtPrg/gbt_bank_gen.gbtBankDsgn/gbtBank/mgt_param_package_src_gen.mgt/mgtLatOpt_gen.mgtLatOpt/gtxLatOpt_gen[1].xlx_k7v7_mgt_std_i/U0/xlx_k7v7_mgt_ip_i/gt0_xlx_k7v7_mgt_ip_i/gtxe2_i/RXOUTCLK}] -create_clock -period 8.333 -name TxWordCLK [get_pins {FitGbtPrg/gbt_bank_gen.gbtBankDsgn/gbtBank/mgt_param_package_src_gen.mgt/mgtLatOpt_gen.mgtLatOpt/gtxLatOpt_gen[1].xlx_k7v7_mgt_std_i/U0/xlx_k7v7_mgt_ip_i/gt0_xlx_k7v7_mgt_ip_i/gtxe2_i/TXOUTCLK}] -create_generated_clock -name RXDataCLK [get_pins FitGbtPrg/gbt_bank_gen.gbtBankDsgn/gbtBank_rxFrmClkPhAlgnr/latOpt_phalgnr_gen.mmcm_inst/pll/inst/mmcm_adv_inst/CLKOUT0] - -create_clock -period 25.000 -name MCLKA -waveform {0.000 12.500} [get_ports CLKA_P] -create_clock -period 25.000 -name MCLKC -waveform {0.000 12.500} [get_ports CLKC_P] - -create_clock -period 100.000 -name SPI [get_ports SCK] - -#clock groups for standalone progect -#for integrated use spetial groups -###################################### -#set_clock_groups -name ASYNC_CLOCKS0 -asynchronous -group [get_clocks {RxWordCLK RXDataCLK}] -group [get_clocks TxWordCLK] -set_clock_groups -name ASYNC_CLOCKS1 -asynchronous -group [get_clocks TxWordCLK] -group [get_clocks -include_generated_clocks MCLKA] -set_clock_groups -name ASYNC_CLOCKS2 -asynchronous -group [get_clocks RxWordCLK] -group [get_clocks -include_generated_clocks MCLKA] - -set_clock_groups -name ASYNC_CLOCIPB -asynchronous -group [get_clocks -include_generated_clocks eth_refclk] -set_clock_groups -asynchronous -group [get_clocks -include_generated_clocks ipbus_module/eth/phy/*/gtxe2_i/TXOUTCLK] -group [get_clocks -include_generated_clocks ipbus_module/eth/phy/*/gtxe2_i/RXOUTCLK] - -#set_clock_groups -asynchronous -group [get_clocks free_clk] -#set_clock_groups -asynchronous -group [get_clocks dly_clk] - -set_clock_groups -name SPI_ASYNC -asynchronous -group [get_clocks SPI] - -set_input_delay -clock [get_clocks SPI] -clock_fall -min 5.000 [get_ports MOSI] -set_input_delay -clock [get_clocks SPI] -clock_fall -max 10.000 [get_ports MOSI] -set_input_delay -clock [get_clocks SPI] -clock_fall -min 5.000 [get_ports CS] -set_input_delay -clock [get_clocks SPI] -clock_fall -max 10.000 [get_ports CS] -set_output_delay -clock [get_clocks SPI] -max 5.000 [get_ports MISO] -set_output_delay -clock [get_clocks SPI] -min 0.000 [get_ports MISO] - -set_input_delay -clock [get_clocks clk_ipb] -min 5.000 [get_ports {MISO?[?]}] -set_input_delay -clock [get_clocks clk_ipb] -max 10.000 [get_ports {MISO?[?]}] -set_output_delay -clock [get_clocks clk_ipb] -max 5.000 [get_ports {{MOSI?[?]} {SEL?[?]} {SCK?[?]}}] -set_output_delay -clock [get_clocks clk_ipb] -min 0.000 [get_ports {{MOSI?[?]} {SEL?[?]} {SCK?[?]}}] - - -set_property ASYNC_REG true [get_cells spi_wr0_reg] -set_property ASYNC_REG true [get_cells spi_wr1_reg] -set_property ASYNC_REG true [get_cells cnt_lock0_reg] -set_property ASYNC_REG true [get_cells cnt_lock1_reg] -set_property ASYNC_REG true [get_cells cnt_clr0_reg] -set_property ASYNC_REG true [get_cells cnt_clr1_reg] -set_property ASYNC_REG true [get_cells {rout_lock0_reg rout_lock1_reg}] - -create_generated_clock -name CLKA320 -source [get_pins tcma/PLL1/inst/mmcm_adv_inst/CLKIN1] -master_clock MCLKA [get_pins tcma/PLL1/inst/mmcm_adv_inst/CLKOUT0] -create_generated_clock -name CLKC320 -source [get_pins tcmc/PLL1/inst/mmcm_adv_inst/CLKIN1] -master_clock MCLKC [get_pins tcmc/PLL1/inst/mmcm_adv_inst/CLKOUT0] - -create_generated_clock -name CLKsys40 -source [get_pins tcma/PLL1/inst/mmcm_adv_inst/CLKIN1] -master_clock MCLKA [get_pins tcma/PLL1/inst/mmcm_adv_inst/CLKOUT2] -#readout_laser_out_ff -set_property ASYNC_REG true [get_cells readout_laser_out_ff?_reg] - - -set_property IOB TRUE [get_cells -hierarchical T_o_reg] -set_property IOB TRUE [get_cells lasi_reg] -set_property ASYNC_REG true [get_cells {l_on0_reg l_on_reg}] -set_property ASYNC_REG true [get_cells {laser_t0_reg laser_t_reg}] - -set_property ASYNC_REG true [get_cells B_rdy0_reg] -set_property ASYNC_REG true [get_cells B_rdy1_reg] - - -set_property ASYNC_REG true [get_cells spibuf_wr0_reg] -set_property ASYNC_REG true [get_cells spibuf_wr1_reg] -set_property ASYNC_REG true [get_cells spibuf_rd0_reg] -set_property ASYNC_REG true [get_cells spibuf_rd1_reg] -set_property ASYNC_REG true [get_cells buf_lock0_reg] -set_property ASYNC_REG true [get_cells buf_lock1_reg] -set_property ASYNC_REG true [get_cells rst_spi0_reg] -set_property ASYNC_REG true [get_cells rst_spi1_reg] - - -set_property BEL MMCME2_ADV [get_cells FitGbtPrg/gbt_bank_gen.gbtBankDsgn/gbtBank_rxFrmClkPhAlgnr/latOpt_phalgnr_gen.mmcm_inst/pll/inst/mmcm_adv_inst] -set_property LOC MMCME2_ADV_X0Y4 [get_cells FitGbtPrg/gbt_bank_gen.gbtBankDsgn/gbtBank_rxFrmClkPhAlgnr/latOpt_phalgnr_gen.mmcm_inst/pll/inst/mmcm_adv_inst] - -set_property BEL MMCME2_ADV [get_cells tcma/PLL1/inst/mmcm_adv_inst] -set_property LOC MMCME2_ADV_X1Y1 [get_cells tcma/PLL1/inst/mmcm_adv_inst] - -set_property BEL PLLE2_ADV [get_cells Lclk0/inst/plle2_adv_inst] -set_property LOC PLLE2_ADV_X1Y1 [get_cells Lclk0/inst/plle2_adv_inst] - - -set_property IOB TRUE [get_cells -hierarchical {TDi_reg[?]}] -set_property ASYNC_REG true [get_cells -hierarchical {rd_lock0_reg rd_lock1_reg}] -set_property ASYNC_REG true [get_cells -hierarchical {stat_clr0_reg stat_clr1_reg}] -set_property ASYNC_REG true [get_cells -hierarchical {GBTRX_ready0_reg GBTRX_ready1_reg}] - -set_property ASYNC_REG true [get_cells {{reqA1_reg[?]} {reqA0_reg[?]} {reqC1_reg[?]} {reqC0_reg[?]}}] - - -# GBT readout -##################################################################### - -# Reset generator multipath ------------------------------------- -#set_false_path -from [get_cells FitGbtPrg/Reset_Generator_comp/GenRes_DataClk_ff*_reg] -to [all_registers] - -# RX Sync comp ------------------------------------- -set_property ASYNC_REG true [get_cells FitGbtPrg/RxData_ClkSync_comp/RX_CLK_from00_reg] -set_property ASYNC_REG true [get_cells FitGbtPrg/RxData_ClkSync_comp/RX_CLK_from01_reg] +# Ethernet RefClk (125MHz) +create_clock -period 8.000 -name eth_refclk [get_ports ETHCLK_P] + +create_clock -period 12.500 -name LCLK [get_ports LCLK_P] + + +# Ethernet driven by Ethernet txoutclk (i.e. via transceiver) +create_generated_clock -name eth_clk_62_5 -source [get_pins ipbus_module/eth/mmcm/inst/mmcm_adv_inst/CLKIN1] [get_pins ipbus_module/eth/mmcm/inst/mmcm_adv_inst/CLKOUT0] +create_generated_clock -name eth_clk_125 -source [get_pins ipbus_module/eth/mmcm/inst/mmcm_adv_inst/CLKIN1] [get_pins ipbus_module/eth/mmcm/inst/mmcm_adv_inst/CLKOUT1] + +# Clocks derived from MMCM driven by Ethernet RefClk directly (i.e. not via transceiver) +create_generated_clock -name clk_ipb -source [get_pins ipbus_module/clocks/pll/inst/plle2_adv_inst/CLKIN1] [get_pins ipbus_module/clocks/pll/inst/plle2_adv_inst/CLKOUT0] +create_generated_clock -name free_clk -source [get_pins ipbus_module/clocks/pll/inst/plle2_adv_inst/CLKIN1] [get_pins ipbus_module/clocks/pll/inst/plle2_adv_inst/CLKOUT1] +create_generated_clock -name dly_clk -source [get_pins ipbus_module/clocks/pll/inst/plle2_adv_inst/CLKIN1] [get_pins ipbus_module/clocks/pll/inst/plle2_adv_inst/CLKOUT2] + +create_clock -period 5.000 -name MGTCLK [get_ports MGTCLK_P] +create_clock -period 8.333 -name RxWordCLK [get_pins {FitGbtPrg/gbt_bank_gen.gbtBankDsgn/gbtBank/mgt_param_package_src_gen.mgt/mgtLatOpt_gen.mgtLatOpt/gtxLatOpt_gen[1].xlx_k7v7_mgt_std_i/U0/xlx_k7v7_mgt_ip_i/gt0_xlx_k7v7_mgt_ip_i/gtxe2_i/RXOUTCLK}] +create_clock -period 8.333 -name TxWordCLK [get_pins {FitGbtPrg/gbt_bank_gen.gbtBankDsgn/gbtBank/mgt_param_package_src_gen.mgt/mgtLatOpt_gen.mgtLatOpt/gtxLatOpt_gen[1].xlx_k7v7_mgt_std_i/U0/xlx_k7v7_mgt_ip_i/gt0_xlx_k7v7_mgt_ip_i/gtxe2_i/TXOUTCLK}] + +create_generated_clock -name RXDataCLK [get_pins FitGbtPrg/gbt_bank_gen.gbtBankDsgn/gbtBank_rxFrmClkPhAlgnr/latOpt_phalgnr_gen.mmcm_inst/pll/inst/mmcm_adv_inst/CLKOUT0] + +create_clock -period 25.000 -name MCLKA -waveform {0.000 12.500} [get_ports CLKA_P] +create_clock -period 25.000 -name MCLKC -waveform {0.000 12.500} [get_ports CLKC_P] + +create_clock -period 100.000 -name SPI [get_ports SCK] + +#clock groups for standalone progect +#for integrated use spetial groups +###################################### +#set_clock_groups -name ASYNC_CLOCKS0 -asynchronous -group [get_clocks {RxWordCLK RXDataCLK}] -group [get_clocks TxWordCLK] +set_clock_groups -name ASYNC_CLOCKS1 -asynchronous -group [get_clocks TxWordCLK] -group [get_clocks -include_generated_clocks MCLKA] +set_clock_groups -name ASYNC_CLOCKS2 -asynchronous -group [get_clocks RxWordCLK] -group [get_clocks -include_generated_clocks MCLKA] + +set_clock_groups -name ASYNC_CLOCIPB -asynchronous -group [get_clocks -include_generated_clocks eth_refclk] +set_clock_groups -asynchronous -group [get_clocks -include_generated_clocks ipbus_module/eth/phy/*/gtxe2_i/TXOUTCLK] -group [get_clocks -include_generated_clocks ipbus_module/eth/phy/*/gtxe2_i/RXOUTCLK] + +#set_clock_groups -asynchronous -group [get_clocks free_clk] +#set_clock_groups -asynchronous -group [get_clocks dly_clk] + +set_clock_groups -name SPI_ASYNC -asynchronous -group [get_clocks SPI] + +set_input_delay -clock [get_clocks SPI] -clock_fall -min 5.000 [get_ports MOSI] +set_input_delay -clock [get_clocks SPI] -clock_fall -max 10.000 [get_ports MOSI] +set_input_delay -clock [get_clocks SPI] -clock_fall -min 5.000 [get_ports CS] +set_input_delay -clock [get_clocks SPI] -clock_fall -max 10.000 [get_ports CS] +set_output_delay -clock [get_clocks SPI] -max 5.000 [get_ports MISO] +set_output_delay -clock [get_clocks SPI] -min 0.000 [get_ports MISO] + +set_input_delay -clock [get_clocks clk_ipb] -min 5.000 [get_ports {MISO?[?]}] +set_input_delay -clock [get_clocks clk_ipb] -max 10.000 [get_ports {MISO?[?]}] +set_output_delay -clock [get_clocks clk_ipb] -max 5.000 [get_ports {{MOSI?[?]} {SEL?[?]} {SCK?[?]}}] +set_output_delay -clock [get_clocks clk_ipb] -min 0.000 [get_ports {{MOSI?[?]} {SEL?[?]} {SCK?[?]}}] + + +set_property ASYNC_REG true [get_cells spi_wr0_reg] +set_property ASYNC_REG true [get_cells spi_wr1_reg] +set_property ASYNC_REG true [get_cells cnt_lock0_reg] +set_property ASYNC_REG true [get_cells cnt_lock1_reg] +set_property ASYNC_REG true [get_cells cnt_clr0_reg] +set_property ASYNC_REG true [get_cells cnt_clr1_reg] +set_property ASYNC_REG true [get_cells {rout_lock0_reg rout_lock1_reg}] +set_property ASYNC_REG true [get_cells {rdout_errc0_reg rdout_errc1_reg}] +set_property ASYNC_REG true [get_cells {rdout_errf_rd0_reg rdout_errf_rd1_reg}] + +set_property ASYNC_REG true [get_cells {Ccnt_clr0_reg Ccnt_clr1_reg}] + +create_generated_clock -name CLKA320 -source [get_pins tcma/PLL1/inst/mmcm_adv_inst/CLKIN1] -master_clock MCLKA [get_pins tcma/PLL1/inst/mmcm_adv_inst/CLKOUT0] +create_generated_clock -name CLKC320 -source [get_pins tcmc/PLL1/inst/mmcm_adv_inst/CLKIN1] -master_clock MCLKC [get_pins tcmc/PLL1/inst/mmcm_adv_inst/CLKOUT0] + +create_generated_clock -name TX_CLK -source [get_pins tcma/PLL1/inst/mmcm_adv_inst/CLKIN1] -master_clock MCLKA [get_pins tcma/PLL1/inst/mmcm_adv_inst/CLKOUT2] + +set_property IOB TRUE [get_cells -hierarchical T_o_reg] +set_property IOB TRUE [get_cells lasi_reg] + +set_property ASYNC_REG true [get_cells {l_st0_reg l_st1_reg}] + +set_property ASYNC_REG true [get_cells {avgt_lk0_reg avgt_lk_reg}] + +set_property ASYNC_REG true [get_cells B_rdy0_reg] +set_property ASYNC_REG true [get_cells B_rdy1_reg] + + +set_property ASYNC_REG true [get_cells spibuf_wr0_reg] +set_property ASYNC_REG true [get_cells spibuf_wr1_reg] +set_property ASYNC_REG true [get_cells spibuf_rd0_reg] +set_property ASYNC_REG true [get_cells spibuf_rd1_reg] +set_property ASYNC_REG true [get_cells buf_lock0_reg] +set_property ASYNC_REG true [get_cells buf_lock1_reg] +set_property ASYNC_REG true [get_cells rst_spi0_reg] +set_property ASYNC_REG true [get_cells rst_spi1_reg] + +set_property BEL MMCME2_ADV [get_cells FitGbtPrg/gbt_bank_gen.gbtBankDsgn/gbtBank_rxFrmClkPhAlgnr/latOpt_phalgnr_gen.mmcm_inst/pll/inst/mmcm_adv_inst] +set_property LOC MMCME2_ADV_X0Y4 [get_cells FitGbtPrg/gbt_bank_gen.gbtBankDsgn/gbtBank_rxFrmClkPhAlgnr/latOpt_phalgnr_gen.mmcm_inst/pll/inst/mmcm_adv_inst] + +set_property BEL MMCME2_ADV [get_cells tcma/PLL1/inst/mmcm_adv_inst] +set_property LOC MMCME2_ADV_X1Y1 [get_cells tcma/PLL1/inst/mmcm_adv_inst] + +set_property BEL PLLE2_ADV [get_cells Lclk0/inst/plle2_adv_inst] +set_property LOC PLLE2_ADV_X1Y1 [get_cells Lclk0/inst/plle2_adv_inst] + +set_property IOB TRUE [get_cells -hierarchical {TDi_reg[?]}] +set_property ASYNC_REG true [get_cells -hierarchical {rd_lock0_reg rd_lock1_reg}] +set_property ASYNC_REG true [get_cells -hierarchical {stat_clr0_reg stat_clr1_reg}] +set_property ASYNC_REG true [get_cells -hierarchical {GBTRX_ready0_reg GBTRX_ready1_reg}] + +set_property ASYNC_REG true [get_cells {{reqA1_reg[?]} {reqA0_reg[?]} {reqC1_reg[?]} {reqC0_reg[?]}}] + + +# GBT readout +##################################################################### + +# Reset generator multipath ------------------------------------- +#set_false_path -from [get_cells FitGbtPrg/Reset_Generator_comp/GenRes_DataClk_ff*_reg] -to [all_registers] + +# RX Sync comp ------------------------------------- +set_property ASYNC_REG true [get_cells FitGbtPrg/RxData_ClkSync_comp/RX_CLK_from00_reg] +set_property ASYNC_REG true [get_cells FitGbtPrg/RxData_ClkSync_comp/RX_CLK_from01_reg] + + diff --git a/firmware/FT0/TCM_v1/xdc/timing.xdc b/firmware/FT0/TCM_v1/xdc/timing.xdc index 47b6d4d..8fc344b 100644 --- a/firmware/FT0/TCM_v1/xdc/timing.xdc +++ b/firmware/FT0/TCM_v1/xdc/timing.xdc @@ -1,61 +1,129 @@ -set_false_path -through [get_pins ipbus_module/clocks/nuke_i_reg/Q] - -set_max_delay -datapath_only -from [get_clocks *] -to [get_ports {LA?[*] LAC* LED*}] 15.000 - -set_false_path -from [get_clocks RXDataCLK] -to [get_cells {FitGbtPrg/gbt_bank_gen.gbtBankDsgn/GBT_Status_O_reg[gbtRx_ErrorDet] FitGbtPrg/gbt_bank_gen.gbtBankDsgn/GBT_Status_O_reg[gbtRx_Ready] IsRXData0_reg}] - -set_max_delay -from [get_cells las_o_reg] -to [get_clocks LCLK] 2.900 - -## GBT RX: -##-------- - -## Comment: The period of RX_FRAMECLK is 25ns but "TS_GBTRX_GEARBOX_TO_DESCRAMBLER" is set to 20ns, providing 5ns for setup margin. -#set_max_delay -datapath_only -from [get_pins -hier -filter {NAME =~ */*/*/rxGearbox/*/C}] -to [get_pins -hier -filter {NAME =~ */*/*/descrambler/*/D}] 20.000 - -set_multicycle_path -setup -start -from [get_clocks RxWordCLK] -to [get_cells {FitGbtPrg/gbt_bank_gen.gbtBankDsgn/gbtBank/gbtRx_param_package_src_gen.gbtRx_gen[1].gbtRx/descrambler/*_O_reg - FitGbtPrg/gbt_bank_gen.gbtBankDsgn/gbtBank/gbtRx_param_package_src_gen.gbtRx_gen[1].gbtRx/descrambler/gbtFrameOrWideBus_gen.gbtRxDescrambler84bit_gen[?].gbtRxDescrambler21bit/RX_DATA_O_reg[*] - FitGbtPrg/gbt_bank_gen.gbtBankDsgn/gbtBank/gbtRx_param_package_src_gen.gbtRx_gen[1].gbtRx/descrambler/gbtFrameOrWideBus_gen.gbtRxDescrambler84bit_gen[?].gbtRxDescrambler21bit/feedbackRegister_reg[*]}] 3 -set_multicycle_path -hold -start -from [get_clocks RxWordCLK] -to [get_cells {FitGbtPrg/gbt_bank_gen.gbtBankDsgn/gbtBank/gbtRx_param_package_src_gen.gbtRx_gen[1].gbtRx/descrambler/*_O_reg - FitGbtPrg/gbt_bank_gen.gbtBankDsgn/gbtBank/gbtRx_param_package_src_gen.gbtRx_gen[1].gbtRx/descrambler/gbtFrameOrWideBus_gen.gbtRxDescrambler84bit_gen[?].gbtRxDescrambler21bit/RX_DATA_O_reg[*] - FitGbtPrg/gbt_bank_gen.gbtBankDsgn/gbtBank/gbtRx_param_package_src_gen.gbtRx_gen[1].gbtRx/descrambler/gbtFrameOrWideBus_gen.gbtRxDescrambler84bit_gen[?].gbtRxDescrambler21bit/feedbackRegister_reg[*]}] 2 - -#set_false_path -hold -from [get_clocks RXDataCLK] -to [get_pins {FitGbtPrg/gbtBankDsgn/gbtBank_rxFrmClkPhAlgnr/latOpt_phalgnr_gen.phase_computing_inst/serialToParallel_reg[0]/D}] -#et_max_delay -datapath_only -from [get_clocks RXDataCLK] -to [get_pins {FitGbtPrg/gbtBankDsgn/gbtBank_rxFrmClkPhAlgnr/latOpt_phalgnr_gen.phase_computing_inst/serialToParallel_reg[0]/D}] 1.000 - -set_max_delay -datapath_only -from [get_clocks CLKsys40] -to [get_pins readout_laser_out_ff0_reg/D] 3.000 - -set_multicycle_path -setup -from [get_clocks CLKA320] -to [get_cells {{C_vertex/T_?_reg} {Rd_word_reg[*]} V_str_reg}] 2 -set_multicycle_path -hold -from [get_clocks CLKA320] -to [get_cells {{C_vertex/T_?_reg} {Rd_word_reg[*]} V_str_reg}] 1 - - -set_multicycle_path -setup -from [get_cells {tcma/NC_reg[?][?]}] -to [get_clocks CLKA320] 2 -set_multicycle_path -hold -from [get_cells {tcma/NC_reg[?][?]}] -to [get_clocks CLKA320] 1 -set_multicycle_path -setup -from [get_cells {tcmc/NC_reg[?][?]}] -to [get_clocks CLKC320] 2 -set_multicycle_path -hold -from [get_cells {tcmc/NC_reg[?][?]}] -to [get_clocks CLKC320] 1 - -set_multicycle_path -setup -from [get_cells {{tcma/Ampl_o_reg[*]} {AmplC_reg[*]}}] -to [get_cells {C_FC/T_?_reg C_SC/T_?_reg {Rd_word_reg[*]} gbt_wr_reg SC_str_reg CC_str_reg}] 2 -set_multicycle_path -hold -from [get_cells {{tcma/Ampl_o_reg[*]} {AmplC_reg[*]}}] -to [get_cells {C_FC/T_?_reg C_SC/T_?_reg {Rd_word_reg[*]} gbt_wr_reg SC_str_reg CC_str_reg}] 1 - -set_multicycle_path -setup -from [get_cells -hierarchical -filter { PRIMITIVE_TYPE =~ BMEM.bram.* && NAME =~ "m_cr*/m0/*"}] -to [get_clocks CLKA320] 2 -set_multicycle_path -hold -from [get_cells -hierarchical -filter { PRIMITIVE_TYPE =~ BMEM.bram.* && NAME =~ "m_cr*/m0/*"}] -to [get_clocks CLKA320] 1 - -set_max_delay -datapath_only -from [get_clocks CLKC320] -to [get_clocks CLKA320] 3.000 - -set_false_path -from [get_ports RST] -set_false_path -from [get_cells sreset_reg -include_replicated_objects] - -# GBT readout -##################################################################### - -# Reset generator multipath ------------------------------------- -#set_false_path -from [get_cells FitGbtPrg/Reset_Generator_comp/GenRes_DataClk_ff*_reg] -to [all_registers] - -# RX Sync comp ------------------------------------- -set_max_delay -datapath_only -from [get_clocks RXDataCLK] -to [get_cells {FitGbtPrg/RxData_ClkSync_comp/RX_DATA_DATACLK_reg[*]}] 3.000 -set_max_delay -datapath_only -from [get_clocks RXDataCLK] -to [get_cells FitGbtPrg/RxData_ClkSync_comp/RX_IS_DATA_DATACLK_reg] 3.000 -set_max_delay -datapath_only -from [get_clocks RXDataCLK] -to [get_cells FitGbtPrg/RxData_ClkSync_comp/RX_CLK_from00_reg] 2.000 - -set_false_path -from [get_clocks -include_generated_clocks MCLKA] -to [get_clocks RXDataCLK] - -set_false_path -from [get_clocks RXDataCLK] -to [get_cells rout_buf_reg[*]] - +set_false_path -through [get_pins ipbus_module/clocks/nuke_i_reg/Q] + +set_max_delay -datapath_only -from [get_clocks *] -to [get_ports {LA?[*] LAC* LED*}] 15.000 + +set_false_path -from [get_clocks RXDataCLK] -to [get_cells {FitGbtPrg/gbt_bank_gen.gbtBankDsgn/gbtRx_ErrorDet_ff_reg FitGbtPrg/gbt_bank_gen.gbtBankDsgn/GBT_Status_O_reg[*] IsRXData0_reg}] +set_false_path -from [get_clocks RXDataCLK] -to [get_cells {FitGbtPrg/gbt_bank_gen.gbtBankDsgn/gbtRx_ErrorDet_ff_reg FitGbtPrg/gbt_bank_gen.gbtBankDsgn/gbtRx_ErrorDet_ff*}] +set_false_path -from [get_clocks RXDataCLK] -to [get_cells {FitGbtPrg/gbt_bank_gen.gbtBankDsgn/gbtRx_ErrorDet_ff_reg FitGbtPrg/gbt_bank_gen.gbtBankDsgn/Rx_Ready_ff*}] + +set_max_delay -from [get_cells las_o_reg] -to [get_clocks LCLK] 2.900 + +## GBT RX: +##-------- + +## Comment: The period of RX_FRAMECLK is 25ns but "TS_GBTRX_GEARBOX_TO_DESCRAMBLER" is set to 20ns, providing 5ns for setup margin. +#set_max_delay -datapath_only -from [get_pins -hier -filter {NAME =~ */*/*/rxGearbox/*/C}] -to [get_pins -hier -filter {NAME =~ */*/*/descrambler/*/D}] 20.000 + +set_multicycle_path -setup -start -from [get_clocks RxWordCLK] -to [get_cells {FitGbtPrg/gbt_bank_gen.gbtBankDsgn/gbtBank/gbtRx_param_package_src_gen.gbtRx_gen[1].gbtRx/descrambler/*_O_reg + FitGbtPrg/gbt_bank_gen.gbtBankDsgn/gbtBank/gbtRx_param_package_src_gen.gbtRx_gen[1].gbtRx/descrambler/gbtFrameOrWideBus_gen.gbtRxDescrambler84bit_gen[?].gbtRxDescrambler21bit/RX_DATA_O_reg[*] + FitGbtPrg/gbt_bank_gen.gbtBankDsgn/gbtBank/gbtRx_param_package_src_gen.gbtRx_gen[1].gbtRx/descrambler/gbtFrameOrWideBus_gen.gbtRxDescrambler84bit_gen[?].gbtRxDescrambler21bit/feedbackRegister_reg[*]}] 3 +set_multicycle_path -hold -start -from [get_clocks RxWordCLK] -to [get_cells {FitGbtPrg/gbt_bank_gen.gbtBankDsgn/gbtBank/gbtRx_param_package_src_gen.gbtRx_gen[1].gbtRx/descrambler/*_O_reg + FitGbtPrg/gbt_bank_gen.gbtBankDsgn/gbtBank/gbtRx_param_package_src_gen.gbtRx_gen[1].gbtRx/descrambler/gbtFrameOrWideBus_gen.gbtRxDescrambler84bit_gen[?].gbtRxDescrambler21bit/RX_DATA_O_reg[*] + FitGbtPrg/gbt_bank_gen.gbtBankDsgn/gbtBank/gbtRx_param_package_src_gen.gbtRx_gen[1].gbtRx/descrambler/gbtFrameOrWideBus_gen.gbtRxDescrambler84bit_gen[?].gbtRxDescrambler21bit/feedbackRegister_reg[*]}] 2 + +#set_false_path -hold -from [get_clocks RXDataCLK] -to [get_pins {FitGbtPrg/gbtBankDsgn/gbtBank_rxFrmClkPhAlgnr/latOpt_phalgnr_gen.phase_computing_inst/serialToParallel_reg[0]/D}] +#et_max_delay -datapath_only -from [get_clocks RXDataCLK] -to [get_pins {FitGbtPrg/gbtBankDsgn/gbtBank_rxFrmClkPhAlgnr/latOpt_phalgnr_gen.phase_computing_inst/serialToParallel_reg[0]/D}] 1.000 + + + +#set_max_delay -datapath_only -from [get_clocks MCLKA] -to [get_clocks CLKA320] 3.000 + +set_multicycle_path -setup -from [get_clocks CLKA320] -to [get_cells {{*/T_?_reg} *_str_reg gbt_wr_reg}] 2 +set_multicycle_path -hold -from [get_clocks CLKA320] -to [get_cells {{*/T_?_reg} *_str_reg gbt_wr_reg}] 1 + +set_multicycle_path -setup -from [get_cells {{tcma/Ampl_o_reg[*]} {tcma/AmplI_o_reg[*]} {tcma/Nchan_A_reg[*]} {tcma/Time_o_reg[*]} {tcma/Avg_reg[*]} {AmplC_reg[*]} {Nchan_C_reg[*]} {TimeC_reg[*]} t_blk_reg}] -to [get_cells {Rd_word_reg[*]}] 2 +set_multicycle_path -hold -from [get_cells {{tcma/Ampl_o_reg[*]} {tcma/AmplI_o_reg[*]} {tcma/Nchan_A_reg[*]} {tcma/Time_o_reg[*]} {tcma/Avg_reg[*]} {AmplC_reg[*]} {Nchan_C_reg[*]} {TimeC_reg[*]} t_blk_reg}] -to [get_cells {Rd_word_reg[*]}] 1 + +set_multicycle_path -setup -from [get_clocks TX_CLK] -to [get_cells {BC_cou_reg[*] Orbit_ID_reg[*]}] 2 +set_multicycle_path -hold -end -from [get_clocks TX_CLK] -to [get_cells {BC_cou_reg[*] Orbit_ID_reg[*]}] 1 + +set_multicycle_path -setup -from [get_cells {tcma/NC_reg[?][?]}] -to [get_clocks CLKA320] 2 +set_multicycle_path -hold -from [get_cells {tcma/NC_reg[?][?]}] -to [get_clocks CLKA320] 1 +set_multicycle_path -setup -from [get_cells {tcmc/NC_reg[?][?]}] -to [get_clocks CLKC320] 2 +set_multicycle_path -hold -from [get_cells {tcmc/NC_reg[?][?]}] -to [get_clocks CLKC320] 1 + + +#set_multicycle_path -setup -from [get_cells -hierarchical -filter { PRIMITIVE_TYPE =~ BMEM.bram.* && NAME =~ "m_cr*/m0/*"}] -to [get_clocks CLKA320] 2 +#set_multicycle_path -hold -from [get_cells -hierarchical -filter { PRIMITIVE_TYPE =~ BMEM.bram.* && NAME =~ "m_cr*/m0/*"}] -to [get_clocks CLKA320] 1 + +set_max_delay -datapath_only -from [get_clocks CLKC320] -to [get_clocks CLKA320] 3.000 + +set_false_path -from [get_ports RST] +set_false_path -from [get_cells sreset_reg -include_replicated_objects] + +# GBT readout +##################################################################### +# TOP +set_multicycle_path 8 -setup -from [get_clocks TX_CLK] -to [get_pins {gbt_global_status_reg[*]/D}] +set_multicycle_path 7 -hold -end -from [get_clocks TX_CLK] -to [get_pins {gbt_global_status_reg[*]/D}] +set_multicycle_path 8 -setup -from [get_clocks TX_CLK] -to [get_pins {rx_phase_status_reg[*]/D}] +set_multicycle_path 7 -hold -end -from [get_clocks TX_CLK] -to [get_pins {rx_phase_status_reg[*]/D}] + +# Reset_Generator ---------------------------------- +set_multicycle_path 8 -setup -from [get_clocks TX_CLK] -to [get_pins FitGbtPrg/Reset_Generator_comp/reset_sclk_reg/D] +set_multicycle_path 7 -hold -end -from [get_clocks TX_CLK] -to [get_pins FitGbtPrg/Reset_Generator_comp/reset_sclk_reg/D] +set_multicycle_path 8 -setup -from [get_clocks TX_CLK] -to [get_pins FitGbtPrg/Reset_Generator_comp/DataClk_qff00_sysclk_reg/D] +set_multicycle_path 7 -hold -end -from [get_clocks TX_CLK] -to [get_pins FitGbtPrg/Reset_Generator_comp/DataClk_qff00_sysclk_reg/D] +set_false_path -from [get_clocks TX_CLK] -to [get_pins {FitGbtPrg/Reset_Generator_comp/Reset_SClk_O*/D}] +set_false_path -from [get_clocks TX_CLK] -to [get_pins {FitGbtPrg/Reset_Generator_comp/count_ready_reg*/D}] + +# RXDATA_CLKSync ---------------------------------- +set_max_delay -datapath_only -from [get_clocks RXDataCLK] -to [get_cells {FitGbtPrg/RxData_ClkSync_comp/RX_DATA_sysclk_reg[*]}] 3.000 +set_max_delay -datapath_only -from [get_clocks RXDataCLK] -to [get_cells {FitGbtPrg/RxData_ClkSync_comp/RX_IS_DATA_sysclk_reg*}] 3.000 +set_max_delay -datapath_only -from [get_clocks RXDataCLK] -to [get_cells FitGbtPrg/RxData_ClkSync_comp/RX_CLK_from00_reg] 2.000 + +set_multicycle_path 8 -setup -from [get_clocks TX_CLK] -to [get_pins FitGbtPrg/RxData_ClkSync_comp/rx_error_reset_sclk_reg/D] +set_multicycle_path 7 -hold -end -from [get_clocks TX_CLK] -to [get_pins FitGbtPrg/RxData_ClkSync_comp/rx_error_reset_sclk_reg/D] + + +# Module_Data_Gen ---------------------------------- +set_multicycle_path 8 -setup -from [get_clocks TX_CLK] -to [get_pins FitGbtPrg/Module_Data_Gen_comp/using_generator_sc_reg/D] +set_multicycle_path 7 -hold -end -from [get_clocks TX_CLK] -to [get_pins FitGbtPrg/Module_Data_Gen_comp/using_generator_sc_reg/D] +set_multicycle_path 8 -setup -from [get_clocks TX_CLK] -to [get_pins FitGbtPrg/Module_Data_Gen_comp/event_orbit_sc_reg[*]/D] +set_multicycle_path 7 -hold -end -from [get_clocks TX_CLK] -to [get_pins FitGbtPrg/Module_Data_Gen_comp/event_orbit_sc_reg[*]/D] +set_multicycle_path 8 -setup -from [get_clocks TX_CLK] -to [get_pins FitGbtPrg/Module_Data_Gen_comp/event_bc_sc_reg[*]/D] +set_multicycle_path 7 -hold -end -from [get_clocks TX_CLK] -to [get_pins FitGbtPrg/Module_Data_Gen_comp/event_bc_sc_reg[*]/D] +set_multicycle_path 8 -setup -from [get_clocks TX_CLK] -to [get_pins FitGbtPrg/Module_Data_Gen_comp/event_rx_ph_err_reg/D] +set_multicycle_path 7 -hold -end -from [get_clocks TX_CLK] -to [get_pins FitGbtPrg/Module_Data_Gen_comp/event_rx_ph_err_reg/D] +set_multicycle_path 8 -setup -from [get_clocks TX_CLK] -to [get_pins FitGbtPrg/Module_Data_Gen_comp/event_rx_ph_reg[*]/D] +set_multicycle_path 7 -hold -end -from [get_clocks TX_CLK] -to [get_pins FitGbtPrg/Module_Data_Gen_comp/event_rx_ph_reg[*]/D] + +# Module_Data_Gen ---------------------------------- +set_multicycle_path 8 -setup -from [get_clocks TX_CLK] -to [get_pins FitGbtPrg/Event_Selector_comp/curr_orbit_sc_reg[*]/D] +set_multicycle_path 7 -hold -end -from [get_clocks TX_CLK] -to [get_pins FitGbtPrg/Event_Selector_comp/curr_orbit_sc_reg[*]/D] +set_multicycle_path 8 -setup -from [get_clocks TX_CLK] -to [get_pins FitGbtPrg/Event_Selector_comp/curr_bc_sc_reg[*]/D] +set_multicycle_path 7 -hold -end -from [get_clocks TX_CLK] -to [get_pins FitGbtPrg/Event_Selector_comp/curr_bc_sc_reg[*]/D] +set_multicycle_path 8 -setup -from [get_clocks TX_CLK] -to [get_pins FitGbtPrg/Event_Selector_comp/data_enabled_sc_reg/D] +set_multicycle_path 7 -hold -end -from [get_clocks TX_CLK] -to [get_pins FitGbtPrg/Event_Selector_comp/data_enabled_sc_reg/D] +set_multicycle_path 8 -setup -from [get_clocks TX_CLK] -to [get_pins FitGbtPrg/Event_Selector_comp/is_readout_sc_reg/D] +set_multicycle_path 7 -hold -end -from [get_clocks TX_CLK] -to [get_pins FitGbtPrg/Event_Selector_comp/is_readout_sc_reg/D] +set_multicycle_path 8 -setup -from [get_clocks TX_CLK] -to [get_pins FitGbtPrg/Event_Selector_comp/is_readout_ff3_sc_reg/D] +set_multicycle_path 7 -hold -end -from [get_clocks TX_CLK] -to [get_pins FitGbtPrg/Event_Selector_comp/is_readout_ff3_sc_reg/D] +set_multicycle_path 8 -setup -from [get_clocks TX_CLK] -to [get_pins FitGbtPrg/Event_Selector_comp/start_of_run_reg/D] +set_multicycle_path 7 -hold -end -from [get_clocks TX_CLK] -to [get_pins FitGbtPrg/Event_Selector_comp/start_of_run_reg/D] +set_multicycle_path 8 -setup -from [get_clocks TX_CLK] -to [get_pins FitGbtPrg/Event_Selector_comp/trigger_select_val_sc_reg[*]/D] +set_multicycle_path 7 -hold -end -from [get_clocks TX_CLK] -to [get_pins FitGbtPrg/Event_Selector_comp/trigger_select_val_sc_reg[*]/D] +set_multicycle_path 8 -setup -from [get_clocks TX_CLK] -to [get_pins FitGbtPrg/Event_Selector_comp/reset_dt_counters_sc_reg/D] +set_multicycle_path 7 -hold -end -from [get_clocks TX_CLK] -to [get_pins FitGbtPrg/Event_Selector_comp/reset_dt_counters_sc_reg/D] +set_multicycle_path 8 -setup -from [get_clocks TX_CLK] -to [get_pins FitGbtPrg/Event_Selector_comp/hb_rdh_response_reg/D] +set_multicycle_path 7 -hold -end -from [get_clocks TX_CLK] -to [get_pins FitGbtPrg/Event_Selector_comp/hb_rdh_response_reg/D] +set_multicycle_path 8 -setup -from [get_clocks TX_CLK] -to [get_pins FitGbtPrg/Event_Selector_comp/start_of_run_reg/D] +set_multicycle_path 7 -hold -end -from [get_clocks TX_CLK] -to [get_pins FitGbtPrg/Event_Selector_comp/start_of_run_reg/D] +set_multicycle_path 8 -setup -from [get_clocks TX_CLK] -to [get_pins FitGbtPrg/Event_Selector_comp/readout_bypass_reg/D] +set_multicycle_path 7 -hold -end -from [get_clocks TX_CLK] -to [get_pins FitGbtPrg/Event_Selector_comp/readout_bypass_reg/D] +set_multicycle_path 8 -setup -from [get_clocks TX_CLK] -to [get_pins FitGbtPrg/Event_Selector_comp/hb_reject_reg/D] +set_multicycle_path 7 -hold -end -from [get_clocks TX_CLK] -to [get_pins FitGbtPrg/Event_Selector_comp/hb_reject_reg/D] + +# bc_indicator ---------------------------------- +set_multicycle_path 8 -setup -from [get_clocks TX_CLK] -to [get_pins FitGbtPrg/bc_indicator_data_comp/reset_reg/D] +set_multicycle_path 7 -hold -end -from [get_clocks TX_CLK] -to [get_pins FitGbtPrg/bc_indicator_data_comp/reset_reg/D] + +# DataConverter ---------------------------------- +set_multicycle_path 8 -setup -from [get_clocks TX_CLK] -to [get_pins FitGbtPrg/DataConverter_comp/reset_drop_counters_reg/D] +set_multicycle_path 7 -hold -end -from [get_clocks TX_CLK] -to [get_pins FitGbtPrg/DataConverter_comp/reset_drop_counters_reg/D] +set_multicycle_path 8 -setup -from [get_clocks TX_CLK] -to [get_pins FitGbtPrg/DataConverter_comp/start_of_run_reg/D] +set_multicycle_path 7 -hold -end -from [get_clocks TX_CLK] -to [get_pins FitGbtPrg/DataConverter_comp/start_of_run_reg/D] +set_multicycle_path 8 -setup -from [get_clocks TX_CLK] -to [get_pins FitGbtPrg/DataConverter_comp/readout_bypass_reg/D] +set_multicycle_path 7 -hold -end -from [get_clocks TX_CLK] -to [get_pins FitGbtPrg/DataConverter_comp/readout_bypass_reg/D] +set_multicycle_path 8 -setup -from [get_clocks TX_CLK] -to [get_pins FitGbtPrg/DataConverter_comp/data_enabled_sclk_reg/D] +set_multicycle_path 7 -hold -end -from [get_clocks TX_CLK] -to [get_pins FitGbtPrg/DataConverter_comp/data_enabled_sclk_reg/D] diff --git a/firmware/FT0/bits/FIT_TESTMODULE_v2.bin b/firmware/FT0/bits/FIT_TESTMODULE_v2.bin deleted file mode 100644 index f5bfbd3..0000000 Binary files a/firmware/FT0/bits/FIT_TESTMODULE_v2.bin and /dev/null differ diff --git a/firmware/FT0/bits/FIT_TESTMODULE_v2.bit b/firmware/FT0/bits/FIT_TESTMODULE_v2.bit deleted file mode 100644 index 4b9e596..0000000 Binary files a/firmware/FT0/bits/FIT_TESTMODULE_v2.bit and /dev/null differ diff --git a/firmware/FT0/bits/PM.bin b/firmware/FT0/bits/PM.bin deleted file mode 100644 index cd4aca2..0000000 Binary files a/firmware/FT0/bits/PM.bin and /dev/null differ diff --git a/firmware/FT0/bits/PM.bit b/firmware/FT0/bits/PM.bit deleted file mode 100644 index aa3e5d5..0000000 Binary files a/firmware/FT0/bits/PM.bit and /dev/null differ diff --git a/firmware/FT0/bits/tcm.bin b/firmware/FT0/bits/tcm.bin deleted file mode 100644 index 08e3d33..0000000 Binary files a/firmware/FT0/bits/tcm.bin and /dev/null differ diff --git a/firmware/FT0/bits/tcm.bit b/firmware/FT0/bits/tcm.bit deleted file mode 100644 index 57fa309..0000000 Binary files a/firmware/FT0/bits/tcm.bit and /dev/null differ diff --git a/firmware/common/ftm/hdl/FIT_TESTMODULE_IPBUS_sender.vhd b/firmware/common/ftm/hdl/FIT_TESTMODULE_IPBUS_sender.vhd deleted file mode 100644 index 3c8d9cd..0000000 --- a/firmware/common/ftm/hdl/FIT_TESTMODULE_IPBUS_sender.vhd +++ /dev/null @@ -1,358 +0,0 @@ ----------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 11.10.2018 15:55:10 --- Design Name: --- Module Name: FIT_GBT_IPBUS_control - Behavioral --- Project Name: --- Target Devices: --- Tool Versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- - - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; -use IEEE.NUMERIC_STD.ALL; - - -library work; -use work.fit_gbt_common_package.all; - -entity FIT_TESTMODULE_IPBUS_sender is - Port ( - FSM_Clocks_I : in FSM_Clocks_type; - - FIT_GBT_status_I : in FIT_GBT_status_type; - Control_register_O : out CONTROL_REGISTER_type; - - GBTRX_IsData_rxclk_I : in STD_LOGIC; - GBTRX_Data_rxclk_I : in std_logic_vector(GBT_data_word_bitdepth-1 downto 0); - - hdmi_fifo_datain_I : in std_logic_vector(GBT_data_word_bitdepth-1 downto 0); - hdmi_fifo_wren_I : in std_logic; - hdmi_fifo_wrclk_I : in std_logic; - - IPBUS_rst_I : in std_logic; - IPBUS_data_out_O : out STD_LOGIC_VECTOR (31 downto 0); - IPBUS_data_in_I : in STD_LOGIC_VECTOR (31 downto 0); - IPBUS_addr_sel_I : in STD_LOGIC; - IPBUS_addr_I : in STD_LOGIC_VECTOR(11 downto 0); - IPBUS_iswr_I : in std_logic; - IPBUS_isrd_I : in std_logic; - IPBUS_ack_O : out std_logic; - IPBUS_err_O : out std_logic; - IPBUS_base_addr_I : in STD_LOGIC_VECTOR(11 downto 0) - ); -end FIT_TESTMODULE_IPBUS_sender; - -architecture Behavioral of FIT_TESTMODULE_IPBUS_sender is - - signal ipbus_di, ipbus_do, ipbus_do_next : STD_LOGIC_VECTOR (31 downto 0); - signal ipbus_ack, ipbus_err :std_logic; - signal hdmi_fifo_rden, hdmi_fifo_isempty : STD_LOGIC; - signal hdmi_fifo_dataout : std_logic_vector(GBT_data_word_bitdepth-1 downto 0); - - -- | DataClk_I | IPBUS clock | - -- -|> FIT_GBT_status_I -#-> ipbus_status_reg_map -> ipbus_status_reg_map_dc -|-> ipbus_status_reg_ipbclk -> IBBUS | - - -- <|- Control_register_reg_dc <-|- Control_register_reg_map_ipbclk <-#- ipbus_control_reg <- IBBUS | - -- -|> Control_register_reg_dc -#-> Control_register_rdmap_dc -|-> Control_register_rdmap_ipbclk -> IBBUS | - - signal FIT_GBT_status : FIT_GBT_status_type; - signal Control_register_reg_map_ipbclk, Control_register_reg_dc : CONTROL_REGISTER_type; - signal ipbus_control_reg, Control_register_rdmap_dc, Control_register_rdmap_ipbclk : cntr_reg_addrreg_type; - signal ipbus_status_reg_map, ipbus_status_reg_map_dc, ipbus_status_reg_ipbclk : status_reg_addrreg_type; - signal ipbus_arrd_int : integer := 0; - signal ipbus_base_arrd_int : integer := 0; - - signal data_fifo_datain : std_logic_vector(GBT_data_word_bitdepth+16-1 downto 0); - signal data_fifo_count : std_logic_vector(slctfifo_count_bitdepth-1 downto 0); - signal data_fifo_wren : std_logic; - signal data_fifo_full : std_logic; - - signal DATA_from_FIFO : std_logic_vector(159+32 downto 0); - signal GBT_cntr_data : std_logic_vector(95 downto 0); - signal DATA_FIFO_empty : std_logic; - signal FIFO_RDEN : std_logic; - - - type array32_type is array (natural range <>) of std_logic_vector(31 downto 0); - signal Data_FIFO_160bit_map, Data_FIFO_160bit_map_ff : array32_type(0 to 5); - - signal Data_FIFO_map_counter_ff, Data_FIFO_map_counter_ff_next : integer; - signal Is_DATA_Readign : std_logic; - - signal gbt_word_counter, gbt_word_counter_next : std_logic_vector(15 downto 0); - - signal rst_ipbus_ff, rst_ipbus_ff_next, rst_dclk : std_logic; - signal rst_counter, rst_counter_next : std_logic_vector(3 downto 0); - - - -- test debug signals - signal debug_ipb_rst :std_logic; - signal debug_ipb_iswr :std_logic; - signal debug_ipb_isrd :std_logic; - signal debug_ipb_ack :std_logic; - signal debug_ipb_err :std_logic; - signal debug_ipb_data_O : std_logic_vector (31 downto 0); - signal debug_ipb_data_I :std_logic_vector (31 downto 0); - signal debug_ipb_addr :std_logic_vector (11 downto 0); - - signal debug_data_fifo_out : std_logic_vector(159 downto 0); - signal debug_data_fifo_empty :std_logic; - signal debug_data_fifo_rden :std_logic; - - attribute mark_debug : string; - --- attribute MARK_DEBUG of Control_register_reg_dc : signal is "true"; --- attribute MARK_DEBUG of FIT_GBT_status : signal is "true"; - --- attribute MARK_DEBUG of data_fifo_datain : signal is "true"; --- attribute MARK_DEBUG of data_fifo_wren : signal is "true"; - - -begin --- FSM_Clocks_I.Reset --- FSM_Clocks_I.Data_Clk --- FSM_Clocks_I.System_Clk --- FSM_Clocks_I.System_Counter --- FSM_Clocks_I.GBT_RX_Clk --- FSM_Clocks_I.IPBUS_Data_Clk - --- debug signal assignement - debug_ipb_rst <= IPBUS_rst_I; - debug_ipb_iswr <= IPBUS_iswr_I; - debug_ipb_isrd <= IPBUS_isrd_I; - debug_ipb_ack <= ipbus_ack; - debug_ipb_err <= ipbus_err; - debug_ipb_data_O <= ipbus_do; - debug_ipb_data_I <= IPBUS_data_in_I; - debug_ipb_addr <= IPBUS_addr_I; - debug_data_fifo_empty <= DATA_FIFO_empty; - - -ipbus_di <= IPBUS_data_in_I; -IPBUS_data_out_O <= ipbus_do; -IPBUS_ack_O <= ipbus_ack; -IPBUS_err_O <= ipbus_err; -Control_register_O <= Control_register_reg_dc; - - FIT_GBT_status.GBT_status <= FIT_GBT_status_I.GBT_status; - FIT_GBT_status.Readout_Mode <= FIT_GBT_status_I.Readout_Mode; - FIT_GBT_status.CRU_Readout_Mode <= FIT_GBT_status_I.CRU_Readout_Mode; - FIT_GBT_status.BCIDsync_Mode <= FIT_GBT_status_I.BCIDsync_Mode; - FIT_GBT_status.Start_run <= FIT_GBT_status_I.Start_run; - FIT_GBT_status.Stop_run <= FIT_GBT_status_I.Stop_run; - - FIT_GBT_status.Trigger_from_CRU <= FIT_GBT_status_I.Trigger_from_CRU; - FIT_GBT_status.BCID_from_CRU <= FIT_GBT_status_I.BCID_from_CRU; - FIT_GBT_status.ORBIT_from_CRU <= FIT_GBT_status_I.ORBIT_from_CRU; - FIT_GBT_status.BCID_from_CRU_corrected <= FIT_GBT_status_I.BCID_from_CRU_corrected; - FIT_GBT_status.ORBIT_from_CRU_corrected <= FIT_GBT_status_I.ORBIT_from_CRU_corrected; - - FIT_GBT_status.fifo_status.raw_fifo_count <= FIT_GBT_status_I.fifo_status.raw_fifo_count; - FIT_GBT_status.fifo_status.slct_fifo_count <= FIT_GBT_status_I.fifo_status.slct_fifo_count; - FIT_GBT_status.fifo_status.ftmipbus_fifo_count <= data_fifo_count; - FIT_GBT_status.fifo_status.trg_fifo_count <= FIT_GBT_status_I.fifo_status.trg_fifo_count; - FIT_GBT_status.fifo_status.cntr_fifo_count <= FIT_GBT_status_I.fifo_status.cntr_fifo_count; - FIT_GBT_status.hits_rd_counter_converter <= FIT_GBT_status_I.hits_rd_counter_converter; - FIT_GBT_status.hits_rd_counter_selector <= FIT_GBT_status_I.hits_rd_counter_selector; - FIT_GBT_status.rx_phase <= FIT_GBT_status_I.rx_phase; - - - -Control_register_reg_map_ipbclk <= func_CNTRREG_getcntrreg(ipbus_control_reg); -Control_register_rdmap_dc <= func_CNTRREG_getaddrreg(Control_register_reg_dc); -ipbus_status_reg_map <= func_STATREG_getaddrreg(FIT_GBT_status); - -ipbus_arrd_int <= to_integer(unsigned(IPBUS_addr_I)); -ipbus_base_arrd_int <= to_integer(unsigned(IPBUS_base_addr_I)); - - - --- DATA FIFO 160 bit mapping to 32 bit words -Data_FIFO_160bit_map(5) <= DATA_from_FIFO(31 downto 0); -Data_FIFO_160bit_map(4) <= DATA_from_FIFO(63 downto 32); -Data_FIFO_160bit_map(3) <= DATA_from_FIFO(95 downto 64); - -Data_FIFO_160bit_map(2) <= DATA_from_FIFO(127 downto 96); -Data_FIFO_160bit_map(1) <= DATA_from_FIFO(159 downto 128); -Data_FIFO_160bit_map(0) <= DATA_from_FIFO(191 downto 160); - -Control_register_reg_dc <= Control_register_reg_map_ipbclk; -ipbus_status_reg_map_dc <= ipbus_status_reg_map; - - - - --- HDMI FIFO =========================================== -hdmi_fifo_rden <= '1' when (GBTRX_IsData_rxclk_I = '0') and (hdmi_fifo_isempty = '0') else '0'; - -hdmi_fifo_comp : entity work.hdmi_data_fifo - PORT MAP ( - rst => FSM_Clocks_I.Reset, - wr_clk => hdmi_fifo_wrclk_I, - rd_clk => FSM_Clocks_I.GBT_RX_Clk, - din => hdmi_fifo_datain_I, - wr_en => hdmi_fifo_wren_I, - rd_en => hdmi_fifo_rden, - dout => hdmi_fifo_dataout, - full => open, - empty => hdmi_fifo_isempty, - rd_data_count => open, - wr_rst_busy => open, - rd_rst_busy => open - ); --- ===================================================== - --- DATA FIFO =========================================== -GBT_cntr_data <= gbt_word_counter & GBTRX_Data_rxclk_I; -data_fifo_datain <= GBT_cntr_data when (GBTRX_IsData_rxclk_I = '1') else gbt_word_counter & hdmi_fifo_dataout; -data_fifo_wren <= '1' when (GBTRX_IsData_rxclk_I = '1') or (hdmi_fifo_rden = '1') else '0'; - -ipbus_data_fifo_comp : entity work.ipbus_data_fifo - PORT MAP ( - rst => FSM_Clocks_I.Reset, - wr_clk => FSM_Clocks_I.GBT_RX_Clk, - rd_clk => FSM_Clocks_I.IPBUS_Data_Clk, - din => data_fifo_datain, - wr_en => data_fifo_wren, - rd_en => FIFO_RDEN, - dout => DATA_from_FIFO, - full => data_fifo_full, - empty => DATA_FIFO_empty, - rd_data_count => data_fifo_count, - wr_rst_busy => open, - rd_rst_busy => open - ); - --- GBT counter *********************************** - PROCESS (FSM_Clocks_I.GBT_RX_Clk) - BEGIN - IF(FSM_Clocks_I.GBT_RX_Clk'EVENT and FSM_Clocks_I.GBT_RX_Clk = '1') THEN - - IF(FSM_Clocks_I.Reset = '1') THEN - gbt_word_counter <= (others => '0'); - ELSE - gbt_word_counter <= gbt_word_counter_next; - END IF; - - END IF; - END PROCESS; - - gbt_word_counter_next <= (others => '0') WHEN (FSM_Clocks_I.Reset = '1') ELSE - gbt_word_counter WHEN (data_fifo_wren = '0') ELSE - (others => '0') WHEN (gbt_word_counter = x"ffff") ELSE - gbt_word_counter + 1; --- *************************************************** - --- ===================================================== - - - - - - --- IP-BUS register *********************************** - PROCESS (FSM_Clocks_I.IPBUS_Data_Clk) - BEGIN - IF(FSM_Clocks_I.IPBUS_Data_Clk'EVENT and FSM_Clocks_I.IPBUS_Data_Clk = '1') THEN - - ipbus_status_reg_ipbclk <= ipbus_status_reg_map_dc; - Control_register_rdmap_ipbclk <= Control_register_rdmap_dc; - Data_FIFO_160bit_map_ff <= Data_FIFO_160bit_map; - - rst_ipbus_ff <= rst_ipbus_ff_next; - rst_counter <= rst_counter_next; - - IF(IPBUS_rst_I = '1') THEN - Data_FIFO_map_counter_ff <= 0; - -- gbt_word_counter <= (others => '0'); - ipbus_control_reg <= func_CNTRREG_getaddrreg(test_CONTROL_REG); - - ELSIF (IPBUS_addr_sel_I = '0') THEN - - ELSIF (IPBUS_isrd_I = '1') THEN - Data_FIFO_map_counter_ff <= Data_FIFO_map_counter_ff_next; - -- gbt_word_counter <= gbt_word_counter_next; - - ELSIF (IPBUS_iswr_I = '1') THEN - - if(ipbus_ack = '1') then - ipbus_control_reg(ipbus_arrd_int - ipbus_base_arrd_int) <= ipbus_di; - end if; - - ELSE - - END IF; - - END IF; - END PROCESS; --- *************************************************** - - --- FSM *********************************************** -ipbus_err <= '0'; - -Is_DATA_Readign <= '1' WHEN (IPBUS_isrd_I = '1') and (IPBUS_addr_sel_I = '1') and (ipbus_arrd_int = (ipbus_base_arrd_int + cntr_reg_n_32word + status_reg_n_32word)) ELSE '0'; - -ipbus_ack <='0' WHEN (IPBUS_rst_I = '1') ELSE - '0' WHEN (IPBUS_addr_sel_I = '0') else - '0' WHEN (ipbus_arrd_int < ipbus_base_arrd_int ) ELSE - '1' WHEN (IPBUS_isrd_I = '1') and (ipbus_arrd_int < (ipbus_base_arrd_int + cntr_reg_n_32word + status_reg_n_32word) ) ELSE - '1' WHEN (IPBUS_iswr_I = '1') and (ipbus_arrd_int < (ipbus_base_arrd_int + cntr_reg_n_32word) ) ELSE - '1' WHEN (Is_DATA_Readign = '1') ELSE - '0'; - - -ipbus_do <= (others => '0') WHEN (IPBUS_rst_I = '1') ELSE - (others => '0') WHEN ( ipbus_ack = '0') ELSE - Control_register_rdmap_ipbclk(ipbus_arrd_int - ipbus_base_arrd_int) WHEN (ipbus_arrd_int < ipbus_base_arrd_int + cntr_reg_n_32word) ELSE - ipbus_status_reg_ipbclk(ipbus_arrd_int - ipbus_base_arrd_int - cntr_reg_n_32word) WHEN (ipbus_arrd_int < (ipbus_base_arrd_int + cntr_reg_n_32word + status_reg_n_32word) ) ELSE - --- DATA READOUT ========================================== - x"aaaa_aaaa" WHEN (Is_DATA_Readign = '1') and (DATA_FIFO_empty = '1') ELSE - Data_FIFO_160bit_map_ff(Data_FIFO_map_counter_ff) WHEN (Is_DATA_Readign = '1') ELSE - x"ffff_ffff"; - -FIFO_RDEN <= '1' WHEN (Is_DATA_Readign = '1') and (Data_FIFO_map_counter_ff = 4) else '0'; -debug_data_fifo_rden <= '1' WHEN (Is_DATA_Readign = '1') and (Data_FIFO_map_counter_ff = 4) else '0'; - - - - -Data_FIFO_map_counter_ff_next <= 0 WHEN (Is_DATA_Readign = '0') ELSE - --Data_FIFO_map_counter_ff WHEN (Is_DATA_Readign = '0') ELSE - 0 WHEN (DATA_FIFO_empty = '1') ELSE - 0 WHEN (Data_FIFO_map_counter_ff = 5) ELSE - Data_FIFO_map_counter_ff + 1; - --- gbt_word_counter_next <= (others => '0') WHEN (IPBUS_rst_I = '1') ELSE - -- gbt_word_counter WHEN (Data_FIFO_map_counter_ff /= 5) ELSE - -- (others => '0') WHEN (gbt_word_counter = x"ffff") ELSE - -- gbt_word_counter + 1; - - -rst_counter_next <= x"0" WHEN (IPBUS_rst_I = '1') ELSE - x"f" when (rst_counter = x"f") ELSE - rst_counter + 1; - -rst_ipbus_ff_next <= '1' WHEN (IPBUS_rst_I = '1') ELSE - '1' WHEN (rst_counter < x"f") ELSE - '0' WHEN (rst_counter = x"f") ELSE - '0'; - -end Behavioral; - - - diff --git a/firmware/common/ftm/hdl/FIT_TESTMODULE_core.vhd b/firmware/common/ftm/hdl/FIT_TESTMODULE_core.vhd deleted file mode 100644 index 6506c78..0000000 --- a/firmware/common/ftm/hdl/FIT_TESTMODULE_core.vhd +++ /dev/null @@ -1,404 +0,0 @@ ----------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 14:40:15 01/30/2017 --- Design Name: --- Module Name: TX_Data_Gen - Behavioral --- Project Name: --- Target Devices: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use ieee.numeric_std.all; -use ieee.std_logic_unsigned.all ; - -use work.fit_gbt_common_package.all; -use work.fit_gbt_board_package.all; - -entity FIT_TESTMODULE_core is - Port ( - FSM_Clocks_I : in FSM_Clocks_type; - - GBTRX_IsData_rxclk_I : in STD_LOGIC; - GBTRX_Data_rxclk_I : in std_logic_vector(GBT_data_word_bitdepth-1 downto 0); - - GBTTX_IsData_dataclk_O : out STD_LOGIC; - GBTTX_Data_dataclk_O : out std_logic_vector(GBT_data_word_bitdepth-1 downto 0); - - hdmi_fifo_datain_I : in std_logic_vector(GBT_data_word_bitdepth-1 downto 0); - hdmi_fifo_wren_I : in std_logic; - hdmi_fifo_wrclk_I : in std_logic; - - GBT_Status_I : in Type_GBT_status; - - TESTM_status_O : out FIT_GBT_status_type; - Control_register_O : out CONTROL_REGISTER_type; - - IPBUS_rst_I : in std_logic; - IPBUS_data_out_O : out STD_LOGIC_VECTOR (31 downto 0); - IPBUS_data_in_I : in STD_LOGIC_VECTOR (31 downto 0); - IPBUS_addr_sel_I : in STD_LOGIC; - IPBUS_addr_I : in STD_LOGIC_VECTOR(11 downto 0); - IPBUS_iswr_I : in std_logic; - IPBUS_isrd_I : in std_logic; - IPBUS_ack_O : out std_logic; - IPBUS_err_O : out std_logic; - IPBUS_base_addr_I : in STD_LOGIC_VECTOR(11 downto 0) - ); -end FIT_TESTMODULE_core; - -architecture Behavioral of FIT_TESTMODULE_core is - - - -signal TESTM_control : CONTROL_REGISTER_type; -signal TESTM_status : FIT_GBT_status_type; - - -signal Module_data_from_gen : board_data_type; -signal CRU_ORBC_RXData_from_gen : std_logic_vector(GBT_data_word_bitdepth-1 downto 0); -signal CRU_ORBC_IsRXData_from_gen : std_logic; -signal Data_from_TXgen : std_logic_vector(GBT_data_word_bitdepth-1 downto 0); -signal IsData_from_TXgen : std_logic; - -signal FIFO_WE_from_cnvr : STD_LOGIC; -signal FIFO_data_word_from_cnvr : std_logic_vector(fifo_data_bitdepth-1 downto 0); - -signal DATA_from_FIFO : std_logic_vector(159+32 downto 0); -signal GBT_cntr_data : std_logic_vector(95 downto 0); -signal DATA_FIFO_empty : std_logic; -signal FIFO_RDEN : std_logic; - -signal is_space_for_packet_from_dtsndr : STD_LOGIC; - - -signal raw_data_fifo_words_count_rd : std_logic_vector(rawfifo_count_bitdepth-1 downto 0); -signal raw_data_fifo_words_count_wr : std_logic_vector(rawfifo_count_bitdepth-1 downto 0); -signal raw_data_fifo_data_tofifo : std_logic_vector(fifo_data_bitdepth-1 downto 0); -signal raw_data_fifo_data_fromfifo : std_logic_vector(fifo_data_bitdepth-1 downto 0); -signal raw_data_fifo_isempty : std_logic; -signal raw_data_fifo_wren : std_logic; -signal raw_data_fifo_rden : std_logic; -signal raw_data_fifo_space_is_for_packet : STD_LOGIC; -signal raw_data_fifo_reset : std_logic; - -signal data_fifo_datain : std_logic_vector(GBT_data_word_bitdepth+16-1 downto 0); -signal data_fifo_count : std_logic_vector(10 downto 0); -signal data_fifo_wren : std_logic; -signal data_fifo_full : std_logic; - -signal hdmi_fifo_dataout : std_logic_vector(GBT_data_word_bitdepth-1 downto 0); -signal hdmi_fifo_datain : std_logic_vector(GBT_data_word_bitdepth-1 downto 0); -signal hdmi_fifo_rden : std_logic; -signal hdmi_fifo_wren : std_logic; -signal hdmi_fifo_isempty : std_logic; - -signal gbt_word_counter, gbt_word_counter_next : std_logic_vector(15 downto 0); - - -attribute keep : string; -attribute keep of FIFO_RDEN : signal is "true"; -attribute keep of DATA_from_FIFO : signal is "true"; -attribute keep of TESTM_control : signal is "true"; -attribute keep of TESTM_status : signal is "true"; - -attribute keep of raw_data_fifo_wren : signal is "true"; -attribute keep of raw_data_fifo_rden : signal is "true"; -attribute keep of raw_data_fifo_isempty : signal is "true"; -attribute keep of raw_data_fifo_data_tofifo : signal is "true"; -attribute keep of raw_data_fifo_data_fromfifo : signal is "true"; - -attribute keep of gbt_word_counter : signal is "true"; - - -attribute mark_debug : string; -attribute MARK_DEBUG of data_fifo_datain : signal is "TRUE"; -attribute MARK_DEBUG of data_fifo_wren : signal is "TRUE"; -attribute MARK_DEBUG of FIFO_RDEN : signal is "TRUE"; -attribute MARK_DEBUG of DATA_from_FIFO : signal is "TRUE"; -attribute MARK_DEBUG of gbt_word_counter : signal is "TRUE"; -attribute MARK_DEBUG of data_fifo_count : signal is "TRUE"; -attribute MARK_DEBUG of data_fifo_full : signal is "TRUE"; - - - - - COMPONENT fifo_generator_0 PORT ( - rst : IN STD_LOGIC; - wr_clk : IN STD_LOGIC; - rd_clk : IN STD_LOGIC; - din : IN STD_LOGIC_VECTOR(95 DOWNTO 0); - wr_en : IN STD_LOGIC; - rd_en : IN STD_LOGIC; - dout : OUT STD_LOGIC_VECTOR(191 DOWNTO 0); - full : OUT STD_LOGIC; - empty : OUT STD_LOGIC; - rd_data_count : OUT STD_LOGIC_VECTOR(12 DOWNTO 0); - wr_rst_busy : OUT STD_LOGIC; - rd_rst_busy : OUT STD_LOGIC - ); - END COMPONENT; - - - - - -begin - -Control_register_O <= TESTM_control; - --- status not produced in FTM -TESTM_status_O <= TESTM_status; -TESTM_status.BCIDsync_Mode <= mode_SYNC; -TESTM_status.Readout_Mode <= mode_CNT; - -TESTM_status.BCID_from_CRU_corrected <= TESTM_status.BCID_from_CRU; -TESTM_status.ORBIT_from_CRU_corrected <= TESTM_status.ORBIT_from_CRU; - -TESTM_status.GBT_Status <= GBT_Status_I; - -raw_data_fifo_space_is_for_packet <= '1' when (unsigned(raw_data_fifo_words_count_wr) <= rawfifo_depth-total_data_words-1) else - '0'; - - - ---raw_data_fifo_wren <= GBTRX_IsData_rxclk_I; ---raw_data_fifo_data_tofifo <= GBTRX_Data_rxclk_I; - - - --- DATA GENERATOR ===================================== -Module_Data_Gen_comp : entity work.Module_Data_Gen - - Port map( - FSM_Clocks_I => FSM_Clocks_I, - - FIT_GBT_status_I => TESTM_status, - Control_register_I => TESTM_control, - - Board_data_I => board_data_test_const, - Board_data_O => Module_data_from_gen - ); --- ===================================================== - --- Data Converter =============================================== -DataConverter_comp: entity work.DataConverter - port map( - FSM_Clocks_I => FSM_Clocks_I, - - FIT_GBT_status_I => TESTM_status, - Control_register_I => TESTM_control, - - Board_data_I => Module_data_from_gen, - - FIFO_is_space_for_packet_I => is_space_for_packet_from_dtsndr, - - FIFO_WE_O => FIFO_WE_from_cnvr, - FIFO_data_word_O => FIFO_data_word_from_cnvr, - - hits_rd_counter_converter_O => TESTM_status.hits_rd_counter_converter - ); --- =========================================================== - - ----- Raw_data_fifo ============================================= ---raw_data_fifo_comp : entity work.raw_data_fifo ---port map( --- wr_clk => FSM_Clocks_I.System_Clk, --- rd_clk => FSM_Clocks_I.Data_Clk, --- wr_data_count => raw_data_fifo_words_count_wr, --- rd_data_count => raw_data_fifo_words_count_rd, --- rst => raw_data_fifo_reset, --- WR_EN => raw_data_fifo_wren, --- RD_EN => raw_data_fifo_rden, --- DIN => raw_data_fifo_data_tofifo, --- DOUT => raw_data_fifo_data_fromfifo, --- FULL => open, --- EMPTY => raw_data_fifo_isempty --- ); ----- =========================================================== - - - --- GBT data sender =========================================== -GBT_DATA_sender_comp : entity work.GBT_DATA_sender -port map( - FSM_Clocks_I => FSM_Clocks_I, - - FIT_GBT_status_I => TESTM_status, - Control_register_I => TESTM_control, - - Is_spade_for_packet_O => is_space_for_packet_from_dtsndr, - - RX_IsData_ORBCgen_I => CRU_ORBC_IsRXData_from_gen, - RX_Data_ORBCgen_I => CRU_ORBC_RXData_from_gen, - - DATA_converter_I => FIFO_data_word_from_cnvr, - FIFO_WE_converter_I => FIFO_WE_from_cnvr, - - IsData_O => GBTTX_IsData_dataclk_O, - Data_O => GBTTX_Data_dataclk_O - ); --- =========================================================== - --- TX Data Gen =============================================== -TX_Data_Gen_comp : entity work.TX_Data_Gen -port map( - FSM_Clocks_I => FSM_Clocks_I, - - FIT_GBT_status_I => TESTM_status, - Control_register_I => TESTM_control, - - TX_IsData_I => '0', - TX_Data_I => (others => '0'), - - RAWFIFO_data_word_I => (others => '0'), - RAWFIFO_Is_Empty_I => '1', - RAWFIFO_RE_O => open, - - TX_IsData_O => IsData_from_TXgen, - TX_Data_O => Data_from_TXgen - ); --- =========================================================== - - --- CRU ORBC GENERATOR ================================== -CRU_ORBC_Gen_comp : entity work.CRU_ORBC_Gen - - Port map( - FSM_Clocks_I => FSM_Clocks_I, - - FIT_GBT_status_I => TESTM_status, - Control_register_I => TESTM_control, - - RX_IsData_I => IsData_from_TXgen, - RX_Data_I => Data_from_TXgen, - - RX_IsData_O => CRU_ORBC_IsRXData_from_gen, - RX_Data_O => CRU_ORBC_RXData_from_gen, - - Current_BCID_from_O => TESTM_status.BCID_from_CRU, - Current_ORBIT_from_O=> TESTM_status.ORBIT_from_CRU, - Current_Trigger_from_O => TESTM_status.Trigger_from_CRU - - ); --- ===================================================== - --- HDMI FIFO =========================================== - hdmi_fifo_datain <= hdmi_fifo_datain_I; - hdmi_fifo_wren <= hdmi_fifo_wren_I; ---hdmi_fifo_wren <= '1' when (gbt_word_counter(7 downto 4) = x"f") else '0'; ---hdmi_fifo_datain <= x"daf0000000000000" & gbt_word_counter; - - -hdmi_fifo_rden <= '1' when (GBTRX_IsData_rxclk_I = '0') and (hdmi_fifo_isempty = '0') else '0'; - -hdmi_fifo_comp : entity work.raw_data_fifo - PORT MAP ( - rst => FSM_Clocks_I.Reset, - wr_clk => hdmi_fifo_wrclk_I, - rd_clk => FSM_Clocks_I.GBT_RX_Clk, - din => hdmi_fifo_datain, - wr_en => hdmi_fifo_wren, - rd_en => hdmi_fifo_rden, - dout => hdmi_fifo_dataout, - full => open, - empty => hdmi_fifo_isempty, - rd_data_count => open, - wr_rst_busy => open, - rd_rst_busy => open - ); --- ===================================================== - - --- DATA FIFO =========================================== -GBT_cntr_data <= gbt_word_counter & GBTRX_Data_rxclk_I; -data_fifo_datain <= GBT_cntr_data when (GBTRX_IsData_rxclk_I = '1') else gbt_word_counter & hdmi_fifo_dataout; -data_fifo_wren <= '1' when (GBTRX_IsData_rxclk_I = '1') or (hdmi_fifo_rden = '1') else '0'; - -fifo_generator_0_comp : fifo_generator_0 - PORT MAP ( - rst => FSM_Clocks_I.Reset, - wr_clk => FSM_Clocks_I.GBT_RX_Clk, - rd_clk => FSM_Clocks_I.IPBUS_Data_Clk, - din => data_fifo_datain, - wr_en => data_fifo_wren, - rd_en => FIFO_RDEN, - dout => DATA_from_FIFO, - full => data_fifo_full, - empty => DATA_FIFO_empty, - rd_data_count => TESTM_status.fifo_status.slct_fifo_count, - wr_rst_busy => open, - rd_rst_busy => open - ); - -- TESTM_status.fifo_status.slct_fifo_count(10 downto 0) <= data_fifo_count; - --TESTM_status.fifo_status.slct_fifo_count(slctfifo_count_bitdepth-1 downto 11) <= (others => '0'); - - -- GBT counter *********************************** - PROCESS (FSM_Clocks_I.GBT_RX_Clk) - BEGIN - IF(FSM_Clocks_I.GBT_RX_Clk'EVENT and FSM_Clocks_I.GBT_RX_Clk = '1') THEN - - IF(FSM_Clocks_I.Reset = '1') THEN - gbt_word_counter <= (others => '0'); - ELSE - gbt_word_counter <= gbt_word_counter_next; - END IF; - - END IF; - END PROCESS; - - gbt_word_counter_next <= (others => '0') WHEN (FSM_Clocks_I.Reset = '1') ELSE - gbt_word_counter WHEN (data_fifo_wren = '0') ELSE - (others => '0') WHEN (gbt_word_counter = x"ffff") ELSE - gbt_word_counter + 1; - - -- *************************************************** - --- ===================================================== - - - - - - - --- IP-BUS data sender ================================== -FIT_TESTMODULE_IPBUS_sender_comp : entity work.FIT_TESTMODULE_IPBUS_sender - Port map( - FSM_Clocks_I => FSM_Clocks_I, - - FIT_GBT_status_I => TESTM_status, - Control_register_O => TESTM_control, - - FIFO_Data_ibclk_I => DATA_from_FIFO, - FIFO_empty_I => DATA_FIFO_empty, - FIFO_RDEN_O => FIFO_RDEN, - - IPBUS_rst_I => IPBUS_rst_I, - IPBUS_data_out_O => IPBUS_data_out_O, - IPBUS_data_in_I => IPBUS_data_in_I, - IPBUS_addr_sel_I => IPBUS_addr_sel_I, - IPBUS_addr_I => IPBUS_addr_I, - IPBUS_iswr_I => IPBUS_iswr_I, - IPBUS_isrd_I => IPBUS_isrd_I, - IPBUS_ack_O => IPBUS_ack_O, - IPBUS_err_O => IPBUS_err_O, - IPBUS_base_addr_I => IPBUS_base_addr_I - ); --- ===================================================== - - -end Behavioral; - diff --git a/firmware/common/ftm/hdl/FIT_TESTMODULE_v2.vhd b/firmware/common/ftm/hdl/FIT_TESTMODULE_v2.vhd index c8c4528..3c7280d 100644 --- a/firmware/common/ftm/hdl/FIT_TESTMODULE_v2.vhd +++ b/firmware/common/ftm/hdl/FIT_TESTMODULE_v2.vhd @@ -1,25 +1,16 @@ ---------------------------------------------------------------------------------- --- Company: INR RAS Moscow --- Engineer: Finogeev D.A. (dmitry-finogeev@yandex.ru) +-- Company: INR RAS +-- Engineer: Finogeev D. A. dmitry-finogeev@yandex.ru -- --- Create Date: 14:00:14 12/22/2016 --- Design Name: FIT - GBT project --- Module Name: FIT_GBT_kc705_designe - Behavioral --- Project Name: --- Target Devices: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: +-- Create Date: 2017 +-- Description: TOP FTM module -- +-- Revision: 07/2021 ---------------------------------------------------------------------------------- + library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; +use IEEE.STD_LOGIC_1164.all; +use IEEE.STD_LOGIC_UNSIGNED.all; use ieee.std_logic_arith.all; use ieee.numeric_std.all; @@ -27,105 +18,105 @@ library unisim; use unisim.vcomponents.all; library work; -use work.ipbus.ALL; +use work.ipbus.all; use work.fit_gbt_common_package.all; use work.fit_gbt_board_package.all; entity FIT_TESTMODULE_v2 is - Port( - RESET : in STD_LOGIC; - - SYS_CLK_P : in STD_LOGIC; - SYS_CLK_N : in STD_LOGIC; - USER_CLK_P : in STD_LOGIC; - USER_CLK_N : in STD_LOGIC; - SMA_MGT_CLK_P : in STD_LOGIC; - SMA_MGT_CLK_N : in STD_LOGIC; - - eth_clk_p: in std_logic; -- 125MHz MGT clock - eth_clk_n: in std_logic; - - SFP_RX_P : in STD_LOGIC; - SFP_RX_N : in STD_LOGIC; - SFP_TX_P : out STD_LOGIC; - SFP_TX_N : out STD_LOGIC; - SFP_TX_DSBL : out STD_LOGIC; - - - - GPIO_SMA_J13 : out STD_LOGIC; - GPIO_SMA_J14 : out STD_LOGIC; - - GPIO_LED_0 : out STD_LOGIC; - GPIO_LED_1 : out STD_LOGIC; - GPIO_LED_2 : out STD_LOGIC; - GPIO_LED_3 : out STD_LOGIC; - GPIO_LED_4 : out STD_LOGIC; - GPIO_LED_5 : out STD_LOGIC; - GPIO_LED_6 : out STD_LOGIC; - GPIO_LED_7 : out STD_LOGIC; - GPIO_BUTTON_SW_C: in STD_LOGIC; - GPIO_DIP_SW0 : in STD_LOGIC; - - -- FTM V1.0 - LAS_EN : out STD_LOGIC; - LAS_D_P : out STD_LOGIC; - LAS_D_N : out STD_LOGIC; - SCOPE : out STD_LOGIC; - - FMC_HPC_clk_A_p : in STD_LOGIC; - FMC_HPC_clk_A_n : in STD_LOGIC; - FMC_HPC_clk_200_p : in STD_LOGIC; - FMC_HPC_clk_200_n : in STD_LOGIC; - - eth_rx_p: in std_logic; -- Ethernet MGT input - eth_rx_n: in std_logic; - eth_tx_p: out std_logic; -- Ethernet MGT output - eth_tx_n: out std_logic; - - sfp_los: in std_logic; - sfp_rate_sel: out std_logic_vector(1 downto 0); -- SFP rate select - - spi_ss: out std_logic; - spi_mosi: out std_logic; - spi_miso: in std_logic; - spi_sclk: out std_logic; - - TCM_SPI_MOSI : out std_logic; - TCM_SPI_MISO : in std_logic; - TCM_SPI_SCK : out std_logic; - TCM_SPI_SEL : out std_logic; - - TCM_TT0_P : in std_logic; - TCM_TT0_N : in std_logic; - TCM_TT1_P : in std_logic; - TCM_TT1_N : in std_logic; - TCM_TA0_P : in std_logic; - TCM_TA0_N : in std_logic; - TCM_TA1_P : in std_logic; - TCM_TA1_N : in std_logic; - - PM_SPI_MOSI : in std_logic; - PM_SPI_MISO : out std_logic; - PM_SPI_SCK : in std_logic; - PM_SPI_SEL : in std_logic; - - PM_TT0_P : out std_logic; - PM_TT0_N : out std_logic; - PM_TT1_P : out std_logic; - PM_TT1_N : out std_logic; - PM_TA0_P : out std_logic; - PM_TA0_N : out std_logic; - PM_TA1_P : out std_logic; - PM_TA1_N : out std_logic; - CLKPM_P : in std_logic; - CLKPM_N : in std_logic; - - LA : out std_logic_vector (15 downto 0) - - ); + port( + RESET : in std_logic; + + SYS_CLK_P : in std_logic; + SYS_CLK_N : in std_logic; + USER_CLK_P : in std_logic; + USER_CLK_N : in std_logic; + SMA_MGT_CLK_P : in std_logic; + SMA_MGT_CLK_N : in std_logic; + + eth_clk_p : in std_logic; -- 125MHz MGT clock + eth_clk_n : in std_logic; + + SFP_RX_P : in std_logic; + SFP_RX_N : in std_logic; + SFP_TX_P : out std_logic; + SFP_TX_N : out std_logic; + SFP_TX_DSBL : out std_logic; + + + + GPIO_SMA_J13 : out std_logic; + GPIO_SMA_J14 : out std_logic; + + GPIO_LED_0 : out std_logic; + GPIO_LED_1 : out std_logic; + GPIO_LED_2 : out std_logic; + GPIO_LED_3 : out std_logic; + GPIO_LED_4 : out std_logic; + GPIO_LED_5 : out std_logic; + GPIO_LED_6 : out std_logic; + GPIO_LED_7 : out std_logic; + GPIO_BUTTON_SW_C : in std_logic; + GPIO_DIP_SW0 : in std_logic; + + -- FTM V1.0 + LAS_EN : out std_logic; + LAS_D_P : out std_logic; + LAS_D_N : out std_logic; + SCOPE : out std_logic; + + FMC_HPC_clk_A_p : in std_logic; + FMC_HPC_clk_A_n : in std_logic; + FMC_HPC_clk_200_p : in std_logic; + FMC_HPC_clk_200_n : in std_logic; + + eth_rx_p : in std_logic; -- Ethernet MGT input + eth_rx_n : in std_logic; + eth_tx_p : out std_logic; -- Ethernet MGT output + eth_tx_n : out std_logic; + + sfp_los : in std_logic; + sfp_rate_sel : out std_logic_vector(1 downto 0); -- SFP rate select + + spi_ss : out std_logic; + spi_mosi : out std_logic; + spi_miso : in std_logic; + spi_sclk : out std_logic; + + TCM_SPI_MOSI : out std_logic; + TCM_SPI_MISO : in std_logic; + TCM_SPI_SCK : out std_logic; + TCM_SPI_SEL : out std_logic; + + TCM_TT0_P : in std_logic; + TCM_TT0_N : in std_logic; + TCM_TT1_P : in std_logic; + TCM_TT1_N : in std_logic; + TCM_TA0_P : in std_logic; + TCM_TA0_N : in std_logic; + TCM_TA1_P : in std_logic; + TCM_TA1_N : in std_logic; + + PM_SPI_MOSI : in std_logic; + PM_SPI_MISO : out std_logic; + PM_SPI_SCK : in std_logic; + PM_SPI_SEL : in std_logic; + + PM_TT0_P : out std_logic; + PM_TT0_N : out std_logic; + PM_TT1_P : out std_logic; + PM_TT1_N : out std_logic; + PM_TA0_P : out std_logic; + PM_TA0_N : out std_logic; + PM_TA1_P : out std_logic; + PM_TA1_N : out std_logic; + CLKPM_P : in std_logic; + CLKPM_N : in std_logic; + + LA : out std_logic_vector (15 downto 0) + + ); end FIT_TESTMODULE_v2; @@ -133,816 +124,776 @@ end FIT_TESTMODULE_v2; architecture Behavioral of FIT_TESTMODULE_v2 is -- Reset signals - signal reset_to_syscount : std_logic; - signal Is_SysClkCounter_ready : std_logic; - signal reset_aft_pllready : std_logic; - signal SDclk_pll_ready, clk200_rdy : std_logic; - signal gbt_reset, reset_to_syscount40 :std_logic; - --- generators cloks - signal SYSCLK_gen : std_logic; - signal SMA_MGT_CLK : std_logic; - signal USERCLK_gen : std_logic; - signal source_gen : std_logic; - --- CDM clocks - signal CDM_clk_A : std_logic; - signal CDM_clk_200 : std_logic; - signal CDM_pll_SysClk : std_logic; - signal CDM_pll_clk_A : std_logic; - - --- FIT PM clocks - signal SysClk_pll : std_logic; - signal DataClk_pll : std_logic; - signal MgtRefClk_pll : std_logic; - --- CLOCK to FIT_GBT - signal SysClk_to_FIT_GBT : std_logic; - signal DataClk_to_FIT_GBT : std_logic; - signal MgtRefClk_to_FIT_GBT : std_logic; - signal GBT_RxFrameClk : STD_LOGIC; - - + signal reset_logic, reset_pll : std_logic; + signal SDclk_pll_ready, clk200_rdy : std_logic; + signal gbt_reset, reset_to_syscount40 : std_logic; + +-- cloks + signal SYSCLK_gen : std_logic; + signal SMA_MGT_CLK : std_logic; + signal USERCLK_gen : std_logic; + signal source_gen : std_logic; + signal CDM_clk_A : std_logic; + signal CDM_clk_200 : std_logic; + signal CDM_pll_SysClk : std_logic; + signal CDM_pll_clk_A : std_logic; + signal SysClk_pll : std_logic; + signal DataClk_pll : std_logic; + signal MgtRefClk_pll : std_logic; + signal SysClk_to_FIT_GBT : std_logic; + signal DataClk_to_FIT_GBT : std_logic; + signal MgtRefClk_to_FIT_GBT : std_logic; + signal GBT_RxFrameClk : std_logic; + signal fsm_clocks : rdclocks_t; + + -- GBT signals - signal Data_from_FITrd : std_logic_vector(GBT_data_word_bitdepth-1 downto 0); - signal IsData_from_FITrd : STD_LOGIC; - - signal RxData_rxclk_from_GBT : std_logic_vector(GBT_data_word_bitdepth-1 downto 0); - signal IsRxData_rxclk_from_GBT : STD_LOGIC; - - signal from_gbt_bank_prj_GBT_status : Type_GBT_status; - - attribute mark_debug : string; - attribute mark_debug of RxData_rxclk_from_GBT : signal is "true"; - attribute mark_debug of IsRxData_rxclk_from_GBT : signal is "true"; - attribute mark_debug of Data_from_FITrd : signal is "true"; - attribute mark_debug of IsData_from_FITrd : signal is "true"; - - + signal Data_from_FITrd : std_logic_vector(GBT_data_word_bitdepth-1 downto 0); + signal IsData_from_FITrd : std_logic; + signal RxData_rxclk_from_GBT : std_logic_vector(GBT_data_word_bitdepth-1 downto 0); + signal IsRxData_rxclk_from_GBT : std_logic; + signal readout_status : readout_status_t; + signal readout_control : readout_control_t; + signal Laser_Signal_out : std_logic; + + -- attribute mark_debug : string; + -- attribute mark_debug of RxData_rxclk_from_GBT : signal is "true"; + -- attribute mark_debug of IsRxData_rxclk_from_GBT : signal is "true"; + -- attribute mark_debug of Data_from_FITrd : signal is "true"; + -- attribute mark_debug of IsData_from_FITrd : signal is "true"; + + -- IP-BUS signals - signal ipb_clk, ipb_rst : std_logic; - signal ipb_data_in, ipb_data_in_tm, ipb_data_out, spi_data_r, pm_spi_data, tcm_sc_data, loc_data : STD_LOGIC_VECTOR (31 downto 0); - signal ipb_addr : STD_LOGIC_VECTOR(31 downto 0); - signal ipb_iswr, ipb_isrd, ipb_wr, ipb_str, spi_sel, spi_err, spi_ack, tm_sel, ipb_ack_tm, ipb_err_tm, loc_rdy : std_logic; - signal ipb_out: ipb_wbus; - signal ipb_in: ipb_rbus; - signal bus_select : STD_LOGIC_VECTOR(4 downto 0); - signal LAI : STD_LOGIC_VECTOR(15 downto 0); - signal clk200, dly_rdy : STD_LOGIC; - signal SCOPE_I : std_logic; - - signal mac_addr: std_logic_vector(47 downto 0); - signal ip_addr: std_logic_vector(31 downto 0); - - signal HDMI0_P, HDMI0_N, HDMI0_o : std_logic_vector(3 downto 0); - signal HDMI0_d, HDMI0_s, t_stmp, HDMI0_d_sysclk : std_logic_vector(31 downto 0); - signal HDMI_clkout_320, HDMI_clk40 : std_logic; - signal rd_status, st_rq, st_rq_cmd, hdmi_ready, hdmi_ready0, hdmi_ready1, hdmi_ready2, hdmi_ready_sysclk, PM_req, PM_req0, PM_req1, PM_req2, PM_rq, rq_irq0, rq_irq1, rq_irq2, rq_irq : std_logic; - signal d_addr : STD_LOGIC_VECTOR(6 DOWNTO 0); - signal d_sns : STD_LOGIC_VECTOR(15 DOWNTO 0); - signal d_rd, d_rdy, adc_sel, adc_sel1 : std_logic; - + signal ipb_clk, ipb_rst : std_logic; + signal ipb_data_in, ipb_data_in_tm, ipb_data_out, spi_data_r, pm_spi_data, tcm_sc_data, loc_data : std_logic_vector (31 downto 0); + signal ipb_addr : std_logic_vector(31 downto 0); + signal ipb_iswr, ipb_isrd, ipb_wr, ipb_str, spi_sel, spi_err, spi_ack, tm_sel, ipb_ack_tm, ipb_err_tm, loc_rdy : std_logic; + signal ipb_out : ipb_wbus; + signal ipb_in : ipb_rbus; + signal bus_select : std_logic_vector(4 downto 0); + signal LAI : std_logic_vector(15 downto 0); + signal clk200, dly_rdy : std_logic; + signal SCOPE_I : std_logic; + signal mac_addr : std_logic_vector(47 downto 0); + signal ip_addr : std_logic_vector(31 downto 0); + signal ipb_leds : std_logic_vector(1 downto 0); + + -- TEST Module signals - signal FSM_Clocks : FSM_Clocks_type; - signal TESTM_status : FIT_GBT_status_type; - signal TESTM_control : CONTROL_REGISTER_type; - signal Laser_Signal_out, Laser_Signal_out_ff : std_logic; - - signal tt0_p, tt0_n, tt1_p, tt1_n, ta0_p, ta0_n, ta1_p, ta1_n, PM_TT0, PM_TT1, PM_TA0, PM_TA1, CLK_PM, CLK_PMi : std_logic; - signal tcm_sel, tcm_sck, tcm_miso, tcm_mosi, pm_spi_rdy, tcm_sc_rdy, clk320_tcm, pm_sel, pm_sck, pm_miso, pm_mosi, PM_rst, addr_sw : std_logic; - signal cnt_rd, t40, t40_0, t40_1 : std_logic; - signal TCM_bitcnt : std_logic_vector(2 downto 0); - signal TAmpl, TTime : std_logic_vector(13 downto 0); - signal T_cnt : std_logic_vector(15 downto 0); - signal B_cnt : std_logic_vector(16 downto 0); - signal Nchan : std_logic_vector(3 downto 0); - signal T0, T1, A0, A1 : std_logic_vector(7 downto 0); - - - signal ipb_leds : std_logic_vector(1 downto 0); - - - --- TESTs - signal Data_Clk_strobe : STD_LOGIC; - - - COMPONENT PmClockPll PORT( - RESET: in std_logic; - CLK_IN1_200: in std_logic; - CLK_OUT1_200: out std_logic; - CLK_OUT2_40: out std_logic; - CLK_OUT3_320: out std_logic - ); - END COMPONENT; - - COMPONENT CDM_Clk_pll PORT( - RESET: in std_logic; - CLK_IN1_40: in std_logic; - CLK_OUT1_40: out std_logic; - CLK_OUT2_320: out std_logic; - LOCKED : out std_logic - ); - END COMPONENT; - - - component pm_spi is - Port ( CLK : in STD_LOGIC; - RST : in STD_LOGIC; - DI : in STD_LOGIC_VECTOR (31 downto 0); - DO : out STD_LOGIC_VECTOR (31 downto 0); - A : in STD_LOGIC_VECTOR (8 downto 0); - wr : in STD_LOGIC; - rd : in STD_LOGIC; - cs : in STD_LOGIC; - rdy : out STD_LOGIC; - spi_sel : out STD_LOGIC; - spi_clk : out STD_LOGIC; - spi_mosi : out STD_LOGIC; - spi_miso : in STD_LOGIC; - cnt_rd : in STD_LOGIC; - PM_rst : in STD_LOGIC - ); - - end component; - - component tcm_sc is - Port (CLK : in STD_LOGIC; - RST : in STD_LOGIC; - DI : in STD_LOGIC_VECTOR (31 downto 0); - DO : out STD_LOGIC_VECTOR (31 downto 0); - A : in STD_LOGIC_VECTOR (8 downto 0); - wr : in STD_LOGIC; - rd : in STD_LOGIC; - cs : in STD_LOGIC; - rdy : out STD_LOGIC; - cnt_rd : out STD_LOGIC - ); - end component; - - component tcm_sync is - Port ( CLKA : in STD_LOGIC; - TD_P : in STD_LOGIC_VECTOR (3 downto 0); - TD_N : in STD_LOGIC_VECTOR (3 downto 0); - RST : in STD_LOGIC; - pllrdy : out STD_LOGIC; - rdy : out STD_LOGIC; - clkout : out STD_LOGIC; - clkout_90 : out STD_LOGIC; - bitcnt : out STD_LOGIC_VECTOR (2 downto 0); - TDO : out STD_LOGIC_VECTOR (3 downto 0); - Dready : out STD_LOGIC; - rd_lock : in STD_LOGIC; - DATA_OUT : out STD_LOGIC_VECTOR (31 downto 0); - status : out STD_LOGIC_VECTOR (31 downto 0); - PM_req : out STD_LOGIC - ); - end component; - - component TCM_SPI is - Port ( sck : in STD_LOGIC; - sel : in STD_LOGIC; - mosi : in STD_LOGIC; - miso : out STD_LOGIC); - end component; - - - component TCM_PLL320 - port - (-- Clock in ports - -- Clock out ports - clk_out1 : out std_logic; - -- Status and control signals - reset : in std_logic; - locked : out std_logic; - clk_in1 : in std_logic + signal HDMI0_P, HDMI0_N, HDMI0_o : std_logic_vector(3 downto 0); + signal HDMI0_d, HDMI0_s, t_stmp, HDMI0_d_sysclk : std_logic_vector(31 downto 0); + signal HDMI_clkout_320, HDMI_clk40 : std_logic; + signal rd_status, st_rq, st_rq_cmd, hdmi_ready, hdmi_ready0, hdmi_ready1, hdmi_ready2, hdmi_ready_sysclk, PM_req, PM_req0, PM_req1, PM_req2, PM_rq, rq_irq0, rq_irq1, rq_irq2, rq_irq : std_logic; + signal d_addr : std_logic_vector(6 downto 0); + signal d_sns : std_logic_vector(15 downto 0); + signal d_rd, d_rdy, adc_sel, adc_sel1 : std_logic; + signal tt0_p, tt0_n, tt1_p, tt1_n, ta0_p, ta0_n, ta1_p, ta1_n, PM_TT0, PM_TT1, PM_TA0, PM_TA1, CLK_PM, CLK_PMi : std_logic; + signal tcm_sel, tcm_sck, tcm_miso, tcm_mosi, pm_spi_rdy, tcm_sc_rdy, clk320_tcm, pm_sel, pm_sck, pm_miso, pm_mosi, PM_rst, addr_sw : std_logic; + signal cnt_rd, t40, t40_0, t40_1 : std_logic; + signal TCM_bitcnt : std_logic_vector(2 downto 0); + signal TAmpl, TTime : std_logic_vector(13 downto 0); + signal T_cnt : std_logic_vector(15 downto 0); + signal B_cnt : std_logic_vector(16 downto 0); + signal Nchan : std_logic_vector(3 downto 0); + signal T0, T1, A0, A1 : std_logic_vector(7 downto 0); + + component PmClockPll port( + RESET : in std_logic; + CLK_IN1_200 : in std_logic; + CLK_OUT1_200 : out std_logic; + CLK_OUT2_40 : out std_logic; + CLK_OUT3_320 : out std_logic ); - end component; - - COMPONENT SENSOR - PORT ( - di_in : IN STD_LOGIC_VECTOR(15 DOWNTO 0); - daddr_in : IN STD_LOGIC_VECTOR(6 DOWNTO 0); - den_in : IN STD_LOGIC; - dwe_in : IN STD_LOGIC; - drdy_out : OUT STD_LOGIC; - do_out : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); - dclk_in : IN STD_LOGIC; - reset_in : IN STD_LOGIC; - vp_in : IN STD_LOGIC; - vn_in : IN STD_LOGIC; - channel_out : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); - eoc_out : OUT STD_LOGIC; - alarm_out : OUT STD_LOGIC; - eos_out : OUT STD_LOGIC; - busy_out : OUT STD_LOGIC - ); - END COMPONENT; - - - -attribute IODELAY_GROUP : STRING; -attribute IODELAY_GROUP of IDL1: label is "TCM_DLY"; - - -begin + end component; + + component CDM_Clk_pll port( + RESET : in std_logic; + CLK_IN1_40 : in std_logic; + CLK_OUT1_40 : out std_logic; + CLK_OUT2_320 : out std_logic; + LOCKED : out std_logic + ); + end component; -sw0: IBUF port map (O => addr_sw, I =>GPIO_DIP_SW0); --- wiring ============================================== --- PLL clocking source -source_gen <= USERCLK_gen; + component pm_spi is + port (CLK : in std_logic; + RST : in std_logic; + DI : in std_logic_vector (31 downto 0); + DO : out std_logic_vector (31 downto 0); + A : in std_logic_vector (8 downto 0); + wr : in std_logic; + rd : in std_logic; + cs : in std_logic; + rdy : out std_logic; + spi_sel : out std_logic; + spi_clk : out std_logic; + spi_mosi : out std_logic; + spi_miso : in std_logic; + cnt_rd : in std_logic; + PM_rst : in std_logic + ); + + end component; + + component tcm_sc is + port (CLK : in std_logic; + RST : in std_logic; + DI : in std_logic_vector (31 downto 0); + DO : out std_logic_vector (31 downto 0); + A : in std_logic_vector (8 downto 0); + wr : in std_logic; + rd : in std_logic; + cs : in std_logic; + rdy : out std_logic; + cnt_rd : out std_logic + ); + end component; + + component tcm_sync is + port (CLKA : in std_logic; + TD_P : in std_logic_vector (3 downto 0); + TD_N : in std_logic_vector (3 downto 0); + RST : in std_logic; + pllrdy : out std_logic; + rdy : out std_logic; + clkout : out std_logic; + clkout_90 : out std_logic; + bitcnt : out std_logic_vector (2 downto 0); + TDO : out std_logic_vector (3 downto 0); + Dready : out std_logic; + rd_lock : in std_logic; + DATA_OUT : out std_logic_vector (31 downto 0); + status : out std_logic_vector (31 downto 0); + PM_req : out std_logic + ); + end component; + + component TCM_SPI is + port (sck : in std_logic; + sel : in std_logic; + mosi : in std_logic; + miso : out std_logic); + end component; + + + component TCM_PLL320 + port + ( -- Clock in ports + -- Clock out ports + clk_out1 : out std_logic; + -- Status and control signals + reset : in std_logic; + locked : out std_logic; + clk_in1 : in std_logic + ); + end component; + + component SENSOR + port ( + di_in : in std_logic_vector(15 downto 0); + daddr_in : in std_logic_vector(6 downto 0); + den_in : in std_logic; + dwe_in : in std_logic; + drdy_out : out std_logic; + do_out : out std_logic_vector(15 downto 0); + dclk_in : in std_logic; + reset_in : in std_logic; + vp_in : in std_logic; + vn_in : in std_logic; + channel_out : out std_logic_vector(4 downto 0); + eoc_out : out std_logic; + alarm_out : out std_logic; + eos_out : out std_logic; + busy_out : out std_logic + ); + end component; --- CLOCK to FIT_GBT --- SysClk_to_FIT_GBT <= SysClk_pll; --- DataClk_to_FIT_GBT <= DataClk_pll; --- MgtRefClk_to_FIT_GBT <= MgtRefClk_pll; -SysClk_to_FIT_GBT <= CDM_pll_SysClk; -DataClk_to_FIT_GBT <= CDM_pll_clk_A; ---DataClk_to_FIT_GBT <= CDM_clk_A; -MgtRefClk_to_FIT_GBT <= CDM_clk_200; -FSM_Clocks.Data_Clk <= DataClk_to_FIT_GBT; -FSM_Clocks.System_Clk <= SysClk_to_FIT_GBT; -FSM_Clocks.GBT_RX_Clk <= GBT_RxFrameClk; -FSM_Clocks.IPBUS_Data_Clk <= ipb_clk; + attribute IODELAY_GROUP : string; + attribute IODELAY_GROUP of IDL1 : label is "TCM_DLY"; - --- USER OUTPUTS --- GPIO_LED_0 <= TESTM_status.GBT_status.rxWordClkReady; -- from rxPgaseAlign_gen.rxBitSlipControl --- GPIO_LED_1 <= TESTM_status.GBT_status.rxFrameClkReady; -- from latOpt_phalgnr_gen.phase_conm_inst -GPIO_LED_2 <= TESTM_status.GBT_status.mgtLinkReady; -- from FitGbtPrg/gbtBankDsgn/gbtExmplDsgn_inst/gbtBank/mgt_param_package_src_gen.mgt/mgtLatOpt_gen.mgtLatOpt/gtxLatOpt_gen[1].xlx_k7v7_mgt_std_i/U0/gt0_txresetfsm_i -GPIO_LED_3 <= TESTM_status.GBT_status.gbtRx_Ready; -- FitGbtPrg/gbtBankDsgn/gbtExmplDsgn_inst/gbtBank/gbtRx_param_package_src_gen.gbtRx_gen[1].gbtRx/status/statusLatOpt_gen.RX_READY_O_reg --- GPIO_LED_4 <= TESTM_status.GBT_status.mgt_phalin_cplllock; -- CPLLLOCK from FitGbtPrg/gbtBankDsgn/gbtExmplDsgn_inst/gbtBank/mgt_param_package_src_gen.mgt/mgtLatOpt_gen.mgtLatOpt/gtxLatOpt_gen[1].xlx_k7v7_mgt_std_i/U0/xlx_k7v7_mgt_ip_i/gt0_xlx_k7v7_mgt_ip_i/gtxe2_i --- GPIO_LED_5 <= TESTM_status.GBT_status.tx_resetDone; -- TXRESETDONE from gtxe2_i --- GPIO_LED_6 <= TESTM_status.GBT_status.tx_fsmResetDone; -- gt0_txresetfsm_i -GPIO_LED_4 <= ipb_leds(0); -GPIO_LED_7 <= ipb_leds(1); +begin -SCOPE_I <= DataClk_to_FIT_GBT; + -- CLOCK & GPIO ##################################################################### + -- ################################################################################## + -- clocking + source_gen <= USERCLK_gen; + SysClk_to_FIT_GBT <= CDM_pll_SysClk; + DataClk_to_FIT_GBT <= CDM_pll_clk_A; + MgtRefClk_to_FIT_GBT <= CDM_clk_200; -GPIO_SMA_J13 <= DataClk_to_FIT_GBT; -GPIO_SMA_J14 <= GBT_RxFrameClk; --- ================================================ -Laser_Signal_out_ff <= '1' when (TESTM_status.Trigger_from_CRU and TESTM_control.Data_Gen.trigger_resp_mask) /= 0 else '0'; +-- USER OUTPUTS + GPIO_LED_0 <= SDclk_pll_ready; + GPIO_LED_1 <= reset_logic; + GPIO_LED_2 <= clk200; + GPIO_LED_3 <= GBT_RxFrameClk; + GPIO_LED_4 <= '0'; + GPIO_LED_5 <= ipb_leds(0); + GPIO_LED_6 <= ipb_leds(1); + GPIO_LED_7 <= '0'; + + SCOPE_I <= GBT_RxFrameClk; + GPIO_SMA_J13 <= DataClk_to_FIT_GBT; + GPIO_SMA_J14 <= GBT_RxFrameClk; + -- ################################################################################## + -- ################################################################################## + - process (FSM_Clocks.Data_Clk) - begin - if (FSM_Clocks.Data_Clk'event and FSM_Clocks.Data_Clk='1') then - Laser_Signal_out <= Laser_Signal_out_ff; - end if; - end process; + -- BUFFERS & PLLs ################################################################### + -- ################################################################################## -- Clocking Buffers & Pll ============================== + sw0 : IBUF port map (O => addr_sw, I => GPIO_DIP_SW0); + -- SYSCLK IBUFGDS - sysClockIbufgds: ibufds - generic map ( - DIFF_TERM => FALSE, -- Differential Termination - IBUF_LOW_PWR => FALSE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards - IOSTANDARD => "LVDS_25") - port map ( - O => SYSCLK_gen, - I => SYS_CLK_P, - IB => SYS_CLK_N + sysClockIbufgds : ibufds + generic map ( + DIFF_TERM => false, -- Differential Termination + IBUF_LOW_PWR => false, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards + IOSTANDARD => "LVDS_25") + port map ( + O => SYSCLK_gen, + I => SYS_CLK_P, + IB => SYS_CLK_N ); -- USER CLK - userClockIbufgds: ibufds - generic map ( - IBUF_LOW_PWR => FALSE, - IOSTANDARD => "LVDS_25") - port map ( - O => USERCLK_gen, - I => USER_CLK_P, - IB => USER_CLK_N + userClockIbufgds : ibufds + generic map ( + IBUF_LOW_PWR => false, + IOSTANDARD => "LVDS_25") + port map ( + O => USERCLK_gen, + I => USER_CLK_P, + IB => USER_CLK_N ); -- FMC HPC CLK A - CDM_clk_A_Ibufgds: ibufds - generic map ( - DIFF_TERM => TRUE, - IBUF_LOW_PWR => FALSE, - IOSTANDARD => "LVDS_25") - port map ( - O => CDM_clk_A, - I => FMC_HPC_clk_A_p, - IB => FMC_HPC_clk_A_n + CDM_clk_A_Ibufgds : ibufds + generic map ( + DIFF_TERM => true, + IBUF_LOW_PWR => false, + IOSTANDARD => "LVDS_25") + port map ( + O => CDM_clk_A, + I => FMC_HPC_clk_A_p, + IB => FMC_HPC_clk_A_n ); -- Laser signal - LAS_EN <= '1'; - - Laser_Obufgds: obufds - generic map ( - --DIFF_TERM => FALSE, + LAS_EN <= '1'; + + Laser_Obufgds : obufds + generic map ( + --DIFF_TERM => FALSE, -- IBUF_LOW_PWR => FALSE, - IOSTANDARD => "LVDS_25") - port map ( - I => Laser_Signal_out, - O => LAS_D_P, - OB => LAS_D_N + IOSTANDARD => "LVDS_25") + port map ( + I => Laser_Signal_out, + O => LAS_D_P, + OB => LAS_D_N ); - CDM_clk_200_IbufdsGtxe2: ibufds_gte2 - port map ( - O => CDM_clk_200, - ODIV2 => open, - CEB => '0', - I => FMC_HPC_clk_200_p, - IB => FMC_HPC_clk_200_n - ); - - + CDM_clk_200_IbufdsGtxe2 : ibufds_gte2 + port map ( + O => CDM_clk_200, + ODIV2 => open, + CEB => '0', + I => FMC_HPC_clk_200_p, + IB => FMC_HPC_clk_200_n + ); + + -- IBUFGDS SMA MGT - smaMgtRefClkIbufdsGtxe2: ibufds_gte2 - port map ( - O => SMA_MGT_CLK, - ODIV2 => open, - CEB => '0', - I => SMA_MGT_CLK_P, - IB => SMA_MGT_CLK_N - ); - -TT0i_buf: obufds generic map (IOSTANDARD => "LVDS_25") - port map (I=> PM_TT0, O=> PM_TT0_P, OB=> PM_TT0_N); + smaMgtRefClkIbufdsGtxe2 : ibufds_gte2 + port map ( + O => SMA_MGT_CLK, + ODIV2 => open, + CEB => '0', + I => SMA_MGT_CLK_P, + IB => SMA_MGT_CLK_N + ); + + TT0i_buf : obufds generic map (IOSTANDARD => "LVDS_25") + port map (I => PM_TT0, O => PM_TT0_P, OB => PM_TT0_N); + + TT1i_buf : obufds generic map (IOSTANDARD => "LVDS_25") + port map (I => PM_TT1, O => PM_TT1_P, OB => PM_TT1_N); + + TA0i_buf : obufds generic map (IOSTANDARD => "LVDS_25") + port map (I => PM_TA0, O => PM_TA0_P, OB => PM_TA0_N); + + TA1i_buf : obufds generic map (IOSTANDARD => "LVDS_25") + port map (I => PM_TA1, O => PM_TA1_P, OB => PM_TA1_N); -TT1i_buf: obufds generic map (IOSTANDARD => "LVDS_25") - port map (I=> PM_TT1, O=> PM_TT1_P, OB=> PM_TT1_N); + CLKi_buf : ibufds_diff_out generic map (DIFF_TERM => true, IBUF_LOW_PWR => false, IOSTANDARD => "LVDS_25") + port map (O => CLK_PMi, OB => open, I => CLKPM_P, IB => CLKPM_N); -TA0i_buf: obufds generic map (IOSTANDARD => "LVDS_25") - port map (I=> PM_TA0, O=> PM_TA0_P, OB=> PM_TA0_N); + TCM_PLL : TCM_PLL320 port map (clk_out1 => clk320_TCM, reset => RESET, locked => open, clk_in1 => CLK_PM); -TA1i_buf: obufds generic map (IOSTANDARD => "LVDS_25") - port map (I=> PM_TA1, O=> PM_TA1_P, OB=> PM_TA1_N); + MCLKB1 : BUFG + port map (O => CLK_PM, I => CLK_PMi); -CLKi_buf: ibufds_diff_out generic map (DIFF_TERM =>TRUE, IBUF_LOW_PWR => FALSE, IOSTANDARD => "LVDS_25") - port map (O=> CLK_PMi, OB=> open, I=> CLKPM_P, IB => CLKPM_N); + SCOPE_buf : OBUF + port map (O => SCOPE, I => SCOPE_I); -TCM_PLL : TCM_PLL320 port map (clk_out1 => clk320_TCM, reset => RESET, locked => open, clk_in1 => CLK_PM); + -- PLL by KC705 generator + PmClockPllcomp : PmClockPll + port map( + RESET => RESET, + CLK_IN1_200 => source_gen, + CLK_OUT1_200 => MgtRefClk_pll, + CLK_OUT2_40 => DataClk_pll, + CLK_OUT3_320 => SysClk_pll + ); + +-- PLL by CDM clock A + CDMClkpllcomp : CDM_Clk_pll + port map( + RESET => reset_pll, + locked => SDclk_pll_ready, + CLK_IN1_40 => CDM_clk_A, + CLK_OUT1_40 => CDM_pll_clk_A, + CLK_OUT2_320 => CDM_pll_SysClk + ); -MCLKB1: BUFG - port map (O => CLK_PM, I => CLK_PMi); + -- ################################################################################## + -- ################################################################################## -SCOPE_buf: OBUF - port map (O => SCOPE, I => SCOPE_I); - process (CLK_PM) + + + + -- FIT READOUT modules ############################################################## + -- ################################################################################## +-- IP-BUS module =============================================== + sfp_rate_sel(1 downto 0) <= B"00"; + mac_addr <= X"020ddba11503"; -- Careful here, arbitrary addresses do not always work + ip_addr <= X"c0a80029" when (addr_sw = '1') else -- 192.168.0.41 + X"ac144baf"; -- 172.20.75.175 + ipbus_module : entity work.IPBUS_basex_infra + generic map (USE_BUFG => 1) + + port map( + eth_clk_p => eth_clk_p, + eth_clk_n => eth_clk_n, + eth_tx_p => eth_tx_p, + eth_tx_n => eth_tx_n, + eth_rx_p => eth_rx_p, + eth_rx_n => eth_rx_n, + + clk_ipb_o => ipb_clk, + rst_ipb_o => ipb_rst, + + RESET => reset_logic, + + leds => ipb_leds, -- status LEDs + mac_addr => mac_addr, + + ip_addr => ip_addr, + ipb_in => ipb_in, + ipb_out => ipb_out, + clk200 => clk200, + locked => clk200_rdy + ); + + +-- ============================================================= + + +-- Reset_Generator =============================================== + PLL_Reset_Generator_comp : entity work.PLL_Reset_Generator + port map ( + + GRESET_I => RESET, + GDataClk_I => CDM_clk_A, + PLL_ready_I => SDclk_pll_ready, + + reset_lgc_o => reset_logic, + reset_pll_o => reset_pll + + ); +-- ============================================================= + + +-- IP-BUS data sender ================================== + ipbus_face_comp : entity work.ipbus_face + port map( + FSM_Clocks_I => fsm_clocks, + ipbus_clock_i => ipb_clk, + + FIT_GBT_status_I => readout_status, + Control_register_O => readout_control, + + GBTRX_IsData_rxclk_I => IsRxData_rxclk_from_GBT, + GBTRX_Data_rxclk_I => RxData_rxclk_from_GBT, + + hdmi_fifo_datain_I => x"E" & readout_status.ORBIT_from_CRU & readout_status.BCID_from_CRU & HDMI0_d_sysclk, + hdmi_fifo_wren_I => hdmi_ready_sysclk, + hdmi_fifo_wrclk_I => SysClk_to_FIT_GBT, + + IPBUS_rst_I => ipb_rst, + IPBUS_data_out_O => ipb_data_in_tm, + IPBUS_data_in_I => ipb_data_out, + IPBUS_addr_sel_I => bus_select(1), + IPBUS_addr_I => ipb_addr(11 downto 0), + IPBUS_iswr_I => ipb_iswr, + IPBUS_isrd_I => ipb_isrd, + IPBUS_ack_O => ipb_ack_tm, + IPBUS_err_O => ipb_err_tm, + IPBUS_base_addr_I => x"0D8" + ); +-- ===================================================== + + +-- FIT GBT project ===================================== + FitGbtPrg : entity work.FIT_GBT_project + generic map( + IS_SIMULATION => 0 + ) + + port map( + RESET_I => reset_logic, + SysClk_I => SysClk_to_FIT_GBT, + DataClk_I => DataClk_to_FIT_GBT, + MgtRefClk_I => MgtRefClk_to_FIT_GBT, + RxDataClk_I => GBT_RxFrameClk, -- 40MHz data clock in RX domain (loop back) + GBT_RxFrameClk_O => GBT_RxFrameClk, + FSM_Clocks_O => fsm_clocks, + + -- not connected + IPbusClk_I => '0', + err_report_fifo_rden_i => '0', + + Board_data_I => board_data_test_const, + Control_register_I => readout_control, + + MGT_RX_P_I => SFP_RX_P, + MGT_RX_N_I => SFP_RX_N, + MGT_TX_P_O => SFP_TX_P, + MGT_TX_N_O => SFP_TX_N, + MGT_TX_dsbl_O => open, + + RxData_rxclk_to_FITrd_I => RxData_rxclk_from_GBT, --loop back data + IsRxData_rxclk_to_FITrd_I => IsRxData_rxclk_from_GBT, --loop back data + Data_from_FITrd_O => Data_from_FITrd, + IsData_from_FITrd_O => IsData_from_FITrd, + Data_to_GBT_I => Data_from_FITrd, --loop back data + IsData_to_GBT_I => IsData_from_FITrd, --loop back data + + RxData_rxclk_from_GBT_O => RxData_rxclk_from_GBT, + IsRxData_rxclk_from_GBT_O => IsRxData_rxclk_from_GBT, + + readout_status_o => readout_status + ); +-- ===================================================== + -- ################################################################################## + -- ################################################################################## + + + + + + + + + + -- PM / TCM pard (D. Serebryakov) ################################################### + -- ################################################################################## + process (DataClk_to_FIT_GBT) begin - if (CLK_PM'event and CLK_PM='0') then - t40<=not t40; - end if; + if (DataClk_to_FIT_GBT'event and DataClk_to_FIT_GBT = '1') then + if readout_status.trg_match_resp_mask = '1' then Laser_Signal_out <= '1'; else Laser_Signal_out <= '0'; end if; + end if; end process; -TAmpl<= std_logic_vector(to_signed(500, 14)); -TTime(12 downto 0)<= std_logic_vector(to_signed(100, 13)); -Nchan<= std_logic_vector(to_unsigned(2, 4)); -TTime(13)<='1' when (B_cnt=0) else '0'; + process (CLK_PM) + begin + if (CLK_PM'event and CLK_PM = '0') then + t40 <= not t40; + end if; + end process; + + TAmpl <= std_logic_vector(to_signed(500, 14)); + TTime(12 downto 0) <= std_logic_vector(to_signed(100, 13)); + Nchan <= std_logic_vector(to_unsigned(2, 4)); - process (CLK320_TCM) + TTime(13) <= '1' when (B_cnt = 0) else '0'; + + process (CLK320_TCM) begin - if (CLK320_TCM'event and CLK320_TCM='1') then - - rq_irq2<=rq_irq1; rq_irq1<=rq_irq0; rq_irq0<=st_rq_cmd; - - if (rq_irq2='0') and (rq_irq1='1') and (rq_irq='0') then rq_irq<='1'; end if; - - t40_1<=t40_0; t40_0<=t40; - if (t40_1/=t40_0) then TCM_bitcnt<="000"; - else TCM_bitcnt<= TCM_bitcnt+1; end if; - - if (TCM_bitcnt="000") then - -if (T_cnt/=0) and (B_cnt/=0) then - T1<=x"02"; A0<=x"02"; A1<=x"02"; - if (rq_irq='0') then T0<=x"02"; else T0<=x"00"; rq_irq<='0'; end if; -else - if (T_cnt=0) then - T0<=TTime(12) &TTime(10) &TTime(8) &TTime(6) &TTime(4) &TTime(2) & TTime(0) & Nchan(0); - T1<=TTime(13) &TTime(11) &TTime(9) &TTime(7) &TTime(5) &TTime(1) & TTime(1) & Nchan(1); - A0<=TAmpl(12) &TAmpl(10) &TAmpl(8) &TAmpl(6) &TAmpl(4) &TAmpl(2) & TAmpl(0) & Nchan(2); - A1<=TAmpl(13) &TAmpl(11) &TAmpl(9) &TAmpl(7) &TAmpl(5) &TAmpl(1) & TAmpl(1) & Nchan(3); - else - T0<=x"01"; T1<=x"80"; A0<=x"01"; A1<=x"01"; - end if; - end if; - - if (T_cnt=0) then T_cnt<=std_logic_vector(to_unsigned(39999, 16)); - else T_cnt<=T_cnt-1; - end if; - - if (B_cnt=0) then B_cnt<=std_logic_vector(to_unsigned(59999, 17)); - else B_cnt<=B_cnt-1; - end if; - - else - - T0<='0'& T0(7 downto 1); T1<='0'& T1(7 downto 1); A0<='0'& A0(7 downto 1); A1<='0'& A1(7 downto 1); - - end if; - - PM_TT0<=T0(0); PM_TT1<=T1(0); PM_TA0<=A0(0); PM_TA1<=A1(0); - - end if; - end process; - -TT0_buf: ibufds_diff_out generic map (DIFF_TERM =>TRUE, IBUF_LOW_PWR => FALSE, IOSTANDARD => "LVDS_25") - port map (O=> HDMI0_P(0), OB=> HDMI0_N(0), I=> TCM_TT0_P, IB => TCM_TT0_N); - -TT1_buf: ibufds_diff_out generic map (DIFF_TERM =>TRUE, IBUF_LOW_PWR => FALSE, IOSTANDARD => "LVDS_25") - port map (O=> HDMI0_P(1), OB=> HDMI0_N(1), I=> TCM_TT1_P, IB => TCM_TT1_N); - -TA0_buf: ibufds_diff_out generic map (DIFF_TERM =>TRUE, IBUF_LOW_PWR => FALSE, IOSTANDARD => "LVDS_25") - port map (O=> HDMI0_P(2), OB=> HDMI0_N(2), I=> TCM_TA0_P, IB => TCM_TA0_N); - -TA1_buf: ibufds_diff_out generic map (DIFF_TERM =>TRUE, IBUF_LOW_PWR => FALSE, IOSTANDARD => "LVDS_25") - port map (O=> HDMI0_P(3), OB=> HDMI0_N(3), I=> TCM_TA1_P, IB => TCM_TA1_N); - -Tspi_sck : OBUF Port map (O =>TCM_SPI_SCK , I => tcm_sck); -Tspi_sel : OBUF Port map (O =>TCM_SPI_SEL , I => tcm_sel); -Tspi_mosi : OBUF Port map (O =>TCM_SPI_MOSI , I => tcm_mosi); -Tspi_miso : IBUF Port map (O =>tcm_miso , I =>TCM_SPI_MISO); - -Pspi_sck : IBUF Port map (O =>pm_sck, I => PM_SPI_SCK); -Pspi_sel : IBUF Port map (O => pm_sel, I => PM_SPI_SEL); -Pspi_mosi : IBUF Port map (O => pm_mosi, I => PM_SPI_MOSI); -Pspi_miso : OBUF Port map (O =>PM_SPI_MISO, I =>pm_miso); - -PSPI: TCM_SPI port map(sck=>pm_sck, sel=>pm_sel, mosi=>pm_mosi, miso=>pm_miso); - -ILA: for i in 0 to 15 generate -ILA0: OBUF - port map (O => LA(i), I => LAI(i) ); -end generate; - - --- PLL by KC705 generator -PmClockPllcomp : PmClockPll -port map( - RESET => RESET, - CLK_IN1_200 => source_gen, - CLK_OUT1_200 => MgtRefClk_pll, - CLK_OUT2_40 => DataClk_pll, - CLK_OUT3_320 => SysClk_pll -); + if (CLK320_TCM'event and CLK320_TCM = '1') then --- PLL by CDM clock A -CDMClkpllcomp : CDM_Clk_pll -port map( - RESET => RESET, - locked=> SDclk_pll_ready, - CLK_IN1_40 => CDM_clk_A, - CLK_OUT1_40 => CDM_pll_clk_A, - CLK_OUT2_320 => CDM_pll_SysClk -); --- ===================================================== + rq_irq2 <= rq_irq1; rq_irq1 <= rq_irq0; rq_irq0 <= st_rq_cmd; + + if (rq_irq2 = '0') and (rq_irq1 = '1') and (rq_irq = '0') then rq_irq <= '1'; end if; + + t40_1 <= t40_0; t40_0 <= t40; + if (t40_1 /= t40_0) then TCM_bitcnt <= "000"; + else TCM_bitcnt <= TCM_bitcnt+1; end if; + + if (TCM_bitcnt = "000") then + + if (T_cnt /= 0) and (B_cnt /= 0) then + T1 <= x"02"; A0 <= x"02"; A1 <= x"02"; + if (rq_irq = '0') then T0 <= x"02"; else T0 <= x"00"; rq_irq <= '0'; end if; + else + if (T_cnt = 0) then + T0 <= TTime(12) &TTime(10) &TTime(8) &TTime(6) &TTime(4) &TTime(2) & TTime(0) & Nchan(0); + T1 <= TTime(13) &TTime(11) &TTime(9) &TTime(7) &TTime(5) &TTime(1) & TTime(1) & Nchan(1); + A0 <= TAmpl(12) &TAmpl(10) &TAmpl(8) &TAmpl(6) &TAmpl(4) &TAmpl(2) & TAmpl(0) & Nchan(2); + A1 <= TAmpl(13) &TAmpl(11) &TAmpl(9) &TAmpl(7) &TAmpl(5) &TAmpl(1) & TAmpl(1) & Nchan(3); + else + T0 <= x"01"; T1 <= x"80"; A0 <= x"01"; A1 <= x"01"; + end if; + end if; + + if (T_cnt = 0) then T_cnt <= std_logic_vector(to_unsigned(39999, 16)); + else T_cnt <= T_cnt-1; + end if; + + if (B_cnt = 0) then B_cnt <= std_logic_vector(to_unsigned(59999, 17)); + else B_cnt <= B_cnt-1; + end if; + + else + + T0 <= '0'& T0(7 downto 1); T1 <= '0'& T1(7 downto 1); A0 <= '0'& A0(7 downto 1); A1 <= '0'& A1(7 downto 1); + + end if; + + PM_TT0 <= T0(0); PM_TT1 <= T1(0); PM_TA0 <= A0(0); PM_TA1 <= A1(0); + + end if; + end process; + + TT0_buf : ibufds_diff_out generic map (DIFF_TERM => true, IBUF_LOW_PWR => false, IOSTANDARD => "LVDS_25") + port map (O => HDMI0_P(0), OB => HDMI0_N(0), I => TCM_TT0_P, IB => TCM_TT0_N); + + TT1_buf : ibufds_diff_out generic map (DIFF_TERM => true, IBUF_LOW_PWR => false, IOSTANDARD => "LVDS_25") + port map (O => HDMI0_P(1), OB => HDMI0_N(1), I => TCM_TT1_P, IB => TCM_TT1_N); + + TA0_buf : ibufds_diff_out generic map (DIFF_TERM => true, IBUF_LOW_PWR => false, IOSTANDARD => "LVDS_25") + port map (O => HDMI0_P(2), OB => HDMI0_N(2), I => TCM_TA0_P, IB => TCM_TA0_N); + + TA1_buf : ibufds_diff_out generic map (DIFF_TERM => true, IBUF_LOW_PWR => false, IOSTANDARD => "LVDS_25") + port map (O => HDMI0_P(3), OB => HDMI0_N(3), I => TCM_TA1_P, IB => TCM_TA1_N); + + Tspi_sck : OBUF port map (O => TCM_SPI_SCK, I => tcm_sck); + Tspi_sel : OBUF port map (O => TCM_SPI_SEL, I => tcm_sel); + Tspi_mosi : OBUF port map (O => TCM_SPI_MOSI, I => tcm_mosi); + Tspi_miso : IBUF port map (O => tcm_miso, I => TCM_SPI_MISO); + + Pspi_sck : IBUF port map (O => pm_sck, I => PM_SPI_SCK); + Pspi_sel : IBUF port map (O => pm_sel, I => PM_SPI_SEL); + Pspi_mosi : IBUF port map (O => pm_mosi, I => PM_SPI_MOSI); + Pspi_miso : OBUF port map (O => PM_SPI_MISO, I => pm_miso); + + PSPI : TCM_SPI port map(sck => pm_sck, sel => pm_sel, mosi => pm_mosi, miso => pm_miso); + + ILA : for i in 0 to 15 generate + ILA0 : OBUF + port map (O => LA(i), I => LAI(i)); + end generate; + + IDL1 : IDELAYCTRL + port map ( + RDY => dly_rdy, -- 1-bit output: Ready output + REFCLK => clk200, -- 1-bit input: Reference clock input + RST => (RESET and (not clk200_rdy)) -- 1-bit input: Active high reset input + ); + + + + HDMI0 : tcm_sync + port map( + CLKA => CDM_clk_A, + TD_P => HDMI0_P, + TD_N => HDMI0_N, + RST => RESET and (not dly_rdy), + pllrdy => open, + rdy => open, + clkout => HDMI_clkout_320, + clkout_90 => open, + bitcnt => open, + TDO => HDMI0_o, + Dready => hdmi_ready, -- wren + + rd_lock => rd_status, + DATA_OUT => HDMI0_d, -- to fifo + status => HDMI0_s, + PM_req => PM_req + ); - IDL1 : IDELAYCTRL - port map ( - RDY => dly_rdy, -- 1-bit output: Ready output - REFCLK => clk200, -- 1-bit input: Reference clock input - RST => (RESET and (not clk200_rdy)) -- 1-bit input: Active high reset input - ); - - - -HDMI0: tcm_sync - port map( - CLKA => CDM_clk_A, - TD_P=>HDMI0_P, - TD_N=>HDMI0_N, - RST=>RESET and (not dly_rdy), - pllrdy =>open, - rdy=>open, - clkout=>HDMI_clkout_320, - clkout_90=>open, - bitcnt=>open, - TDO=>HDMI0_o, - Dready=>hdmi_ready, -- wren - - rd_lock=>rd_status, - DATA_OUT=> HDMI0_d, -- to fifo - status => HDMI0_s, - PM_req => PM_req - ); - - process (HDMI_clkout_320) begin - if (HDMI_clkout_320'event and HDMI_clkout_320='1') then - - LAI(3 downto 0)<=HDMI0_o; - end if; + if (HDMI_clkout_320'event and HDMI_clkout_320 = '1') then + + LAI(3 downto 0) <= HDMI0_o; + end if; end process; process (SysClk_to_FIT_GBT) begin - if ( SysClk_to_FIT_GBT'event and SysClk_to_FIT_GBT='1') then - - hdmi_ready2 <=hdmi_ready1; hdmi_ready1 <=hdmi_ready0; hdmi_ready0 <=hdmi_ready; - if (hdmi_ready_sysclk='1') then HDMI0_d_sysclk <=HDMI0_d; end if; + if (SysClk_to_FIT_GBT'event and SysClk_to_FIT_GBT = '1') then - end if; + hdmi_ready2 <= hdmi_ready1; hdmi_ready1 <= hdmi_ready0; hdmi_ready0 <= hdmi_ready; + if (hdmi_ready_sysclk = '1') then HDMI0_d_sysclk <= HDMI0_d; end if; + + end if; end process; - - hdmi_ready_sysclk<=(not hdmi_ready2) and hdmi_ready1; + hdmi_ready_sysclk <= (not hdmi_ready2) and hdmi_ready1; --- IP-BUS module =============================================== + bus_select(0) <= ipb_str when ipb_addr(31 downto 3) = x"0000200" & '0' else '0'; + bus_select(1) <= ipb_str when ipb_addr(31 downto 12) = x"00001" else '0'; + bus_select(2) <= ipb_str when ipb_addr(31 downto 9) = x"00000" & "000" else '0'; + bus_select(3) <= ipb_str when ipb_addr(31 downto 9) = x"00000" & "001" else '0'; + bus_select(4) <= ipb_str when ipb_addr(31 downto 9) = x"00000" & "010" else '0'; -sfp_rate_sel(1 downto 0) <= B"00"; -mac_addr <= X"020ddba11503"; -- Careful here, arbitrary addresses do not always work ---ip_addr <= X"ac144baf"; -- 172.20.75.175 ---ip_addr <= X"ac144b5f"; -- 172.20.75.95 -ip_addr <= X"c0a80029" when (addr_sw='1') else -- 192.168.0.41 - X"ac144baf"; -- 172.20.75.175 - -ipbus_module: entity work.IPBUS_basex_infra -generic map (USE_BUFG => 1) - -port map( - eth_clk_p => eth_clk_p, - eth_clk_n => eth_clk_n, - eth_tx_p => eth_tx_p, - eth_tx_n => eth_tx_n, - eth_rx_p => eth_rx_p, - eth_rx_n => eth_rx_n, - - clk_ipb_o => ipb_clk, - rst_ipb_o => ipb_rst, - - RESET => FSM_Clocks.Reset, - - leds => ipb_leds, -- status LEDs - mac_addr => mac_addr, - - ip_addr => ip_addr, - ipb_in => ipb_in, - ipb_out => ipb_out, - clk200 => clk200, - locked=> clk200_rdy -); + ipb_data_out <= ipb_out.ipb_wdata; ipb_addr <= ipb_out.ipb_addr; + ipb_in.ipb_rdata <= ipb_data_in; + ipb_iswr <= ipb_out.ipb_write and ipb_out.ipb_strobe; ipb_isrd <= (not ipb_out.ipb_write) and ipb_out.ipb_strobe; --- ============================================================= -bus_select(0) <= ipb_str when ipb_addr(31 downto 3)= x"0000200" & '0' else '0'; -bus_select(1) <= ipb_str when ipb_addr(31 downto 12)= x"00001" else '0'; -bus_select(2) <= ipb_str when ipb_addr(31 downto 9)= x"00000" & "000" else '0'; -bus_select(3) <= ipb_str when ipb_addr(31 downto 9)= x"00000" & "001" else '0'; -bus_select(4) <= ipb_str when ipb_addr(31 downto 9)= x"00000" & "010" else '0'; - -ipb_data_out<=ipb_out.ipb_wdata; ipb_addr<=ipb_out.ipb_addr; - ipb_in.ipb_rdata<=ipb_data_in; - - ipb_iswr<=ipb_out.ipb_write and ipb_out.ipb_strobe; ipb_isrd<=(not ipb_out.ipb_write) and ipb_out.ipb_strobe; + ipb_str <= ipb_out.ipb_strobe; ipb_wr <= ipb_out.ipb_write; -ipb_str<=ipb_out.ipb_strobe; ipb_wr<= ipb_out.ipb_write; + rd_status <= '1' when (bus_select(4) = '1') and (ipb_addr(8 downto 0) = '0' & x"00") and (ipb_wr = '0') else '0'; + st_rq <= '1' when (bus_select(4) = '1') and (ipb_addr(8 downto 0) = '0' & x"02") else '0'; + st_rq_cmd <= '1' when (bus_select(4) = '1') and (ipb_addr(8 downto 0) = '0' & x"02") and (ipb_wr = '1') and (ipb_data_out(1) = '1') else '0'; + PM_rst <= '1' when (bus_select(4) = '1') and (ipb_addr(8 downto 0) = '0' & x"02") and (ipb_wr = '1') and (ipb_data_out(2) = '1') else '0'; -rd_status <= '1' when (bus_select(4)='1') and (ipb_addr(8 downto 0)='0' & x"00") and (ipb_wr='0') else '0'; -st_rq <= '1' when (bus_select(4)='1') and (ipb_addr(8 downto 0)='0' & x"02") else '0'; -st_rq_cmd <= '1' when (bus_select(4)='1') and (ipb_addr(8 downto 0)='0' & x"02") and (ipb_wr='1') and (ipb_data_out(1)='1') else '0'; -PM_rst <= '1' when (bus_select(4)='1') and (ipb_addr(8 downto 0)='0' & x"02") and (ipb_wr='1') and (ipb_data_out(2)='1') else '0'; - - process (ipb_clk) + process (ipb_clk) begin - if (ipb_clk'event and ipb_clk='1') then - - adc_sel1<=adc_sel and not d_rdy; - -PM_req2<=PM_req1; PM_req1<=PM_req0; PM_req0<=PM_req; -if (PM_req2='0') and (PM_req1='1') then PM_rq<='1'; - else - if (st_rq='1') and (ipb_wr='0') then PM_rq<='0'; end if; -end if; - - end if; + if (ipb_clk'event and ipb_clk = '1') then + + adc_sel1 <= adc_sel and not d_rdy; + + PM_req2 <= PM_req1; PM_req1 <= PM_req0; PM_req0 <= PM_req; + if (PM_req2 = '0') and (PM_req1 = '1') then PM_rq <= '1'; + else + if (st_rq = '1') and (ipb_wr = '0') then PM_rq <= '0'; end if; + end if; + + end if; end process; - -UA2 : USR_ACCESSE2 port map (CFGCLK => open, DATA => t_stmp, DATAVALID => open ); - -SNS : SENSOR PORT MAP ( di_in => (others=>'0'), daddr_in => d_addr, den_in => d_rd, dwe_in => '0', drdy_out => d_rdy, do_out => d_sns, dclk_in => ipb_clk, - reset_in => ipb_rst, vp_in => '0', vn_in => '0', channel_out => open, eoc_out => open, alarm_out => open, eos_out => open, busy_out => open); - -d_addr<="00000" & ipb_addr(1 downto 0); - -adc_sel<= '1' when bus_select(4)='1' and ipb_addr(8 downto 2)="0000001" and ipb_addr(1 downto 0)/="11" and (ipb_wr='0') else '0'; - -d_rd<= adc_sel and not adc_sel1; - -loc_rdy<= d_rdy when adc_sel='1' else '1'; - - -loc_data<= HDMI0_s when ipb_addr(8 downto 0) = '0' & x"00" else - HDMI0_d when ipb_addr(8 downto 0) = '0' & x"01" else - x"0000000" & "000" & PM_rq when ipb_addr(8 downto 0) = '0' & x"02" else - t_stmp when ipb_addr(8 downto 0) = '0' & x"03" else - x"0000" & d_sns when adc_sel='1' else - x"00000000"; - - - -with bus_select select -ipb_in.ipb_ack<= spi_ack when "00001", - ipb_ack_tm when "00010", - pm_spi_rdy when "00100", - tcm_sc_rdy when "01000", - loc_rdy when "10000", - '0' when others; - - -ipb_in.ipb_err<= spi_err or ipb_err_tm; - -with bus_select select - ipb_data_in<= spi_data_r when "00001", - ipb_data_in_tm when "00010", - pm_spi_data when "00100", - tcm_sc_data when "01000", - loc_data when "10000", - x"00000000" when others; - - - -slave_spi: entity work.ipbus_spi - port map( - clk => ipb_clk, - rst => ipb_rst, - ipb_data_w => ipb_data_out, - ipb_data_r => spi_data_r, - ipb_spi_adr =>ipb_addr(2 downto 0), - ipb_sel=> bus_select(0), - ipb_wr=> ipb_wr, - ss => spi_ss, - ipb_err=> spi_err, - ipb_ack=> spi_ack, - mosi => spi_mosi, - miso => spi_miso, - sclk => spi_sclk - ); - -pm_sc: pm_spi - Port map ( CLK => ipb_clk, - RST => ipb_rst, - DI => ipb_data_out, - DO => pm_spi_data, - A => ipb_addr(8 downto 0), - wr => ipb_iswr, - rd => ipb_isrd, - cs => bus_select(2), - rdy => pm_spi_rdy, - spi_sel =>tcm_sel, - spi_clk =>tcm_sck, - spi_mosi =>tcm_mosi, - spi_miso =>tcm_miso, - cnt_rd => cnt_rd, - PM_rst => PM_rst - ); - - LAI(7) <= tcm_sel; - LAI(6) <= tcm_sck; - LAI(5) <= tcm_mosi; - LAI(4) <= not tcm_miso; - - LAI(8) <= reset_aft_pllready; - LAI(9) <= FSM_Clocks.Reset; - - -tcm_sc1: tcm_sc - Port map ( CLK => ipb_clk, - RST => ipb_rst, - DI => ipb_data_out, - DO => tcm_sc_data, - A => ipb_addr(8 downto 0), - wr => ipb_iswr, - rd => ipb_isrd, - cs => bus_select(3), - rdy => tcm_sc_rdy, - cnt_rd => cnt_rd - ); ---LAI(0)<=cnt_rd; + UA2 : USR_ACCESSE2 port map (CFGCLK => open, DATA => t_stmp, DATAVALID => open); + SNS : SENSOR port map (di_in => (others => '0'), daddr_in => d_addr, den_in => d_rd, dwe_in => '0', drdy_out => d_rdy, do_out => d_sns, dclk_in => ipb_clk, + reset_in => ipb_rst, vp_in => '0', vn_in => '0', channel_out => open, eoc_out => open, alarm_out => open, eos_out => open, busy_out => open); --- Reset_Generator =============================================== -PLL_Reset_Generator_comp : entity work.PLL_Reset_Generator -port map ( - - GRESET_I => RESET, - GDataClk_I => CDM_clk_A, - PLL_ready_I => SDclk_pll_ready, - - RESET_O => reset_aft_pllready -); --- ============================================================= + d_addr <= "00000" & ipb_addr(1 downto 0); + adc_sel <= '1' when bus_select(4) = '1' and ipb_addr(8 downto 2) = "0000001" and ipb_addr(1 downto 0) /= "11" and (ipb_wr = '0') else '0'; --- Reset FSM ================================================= -Reset_Generator_comp: entity work.Reset_Generator -port map( - RESET_I => RESET, - SysClk_I => FSM_Clocks.System_Clk, - DataClk_I => FSM_Clocks.Data_Clk, - Sys_Cntr_ready_I => Is_SysClkCounter_ready, - Reset_DClk_O => reset_to_syscount, - General_reset_O => FSM_Clocks.Reset, - Reset_DClk40_O => reset_to_syscount40, - General_reset40_O => FSM_Clocks.Reset40 - ); --- =========================================================== - --- Data Clk strobe =========================================== -DataClk_I_strobe_comp: entity work.DataClk_strobe -port map( - RESET_I => reset_to_syscount, - RESET40_I => FSM_Clocks.Reset40, - SysClk_I => FSM_Clocks.System_Clk, - DataClk_I => FSM_Clocks.Data_Clk, - SysClk_count_O => FSM_Clocks.System_Counter, - Counter_ready_O => Is_SysClkCounter_ready - ); - --- =========================================================== + d_rd <= adc_sel and not adc_sel1; + loc_rdy <= d_rdy when adc_sel = '1' else '1'; --- IP-BUS data sender ================================== -FIT_TESTMODULE_IPBUS_sender_comp : entity work.FIT_TESTMODULE_IPBUS_sender - Port map( - FSM_Clocks_I => FSM_Clocks, - - FIT_GBT_status_I => TESTM_status, - Control_register_O => TESTM_control, - - GBTRX_IsData_rxclk_I => IsRxData_rxclk_from_GBT, - GBTRX_Data_rxclk_I => RxData_rxclk_from_GBT, - - hdmi_fifo_datain_I => x"E" & TESTM_status.ORBIT_from_CRU & TESTM_status.BCID_from_CRU & HDMI0_d_sysclk, - hdmi_fifo_wren_I => hdmi_ready_sysclk, - hdmi_fifo_wrclk_I => SysClk_to_FIT_GBT, - - IPBUS_rst_I => ipb_rst, - IPBUS_data_out_O => ipb_data_in_tm, - IPBUS_data_in_I => ipb_data_out, - IPBUS_addr_sel_I => bus_select(1), - IPBUS_addr_I => ipb_addr(11 downto 0), - IPBUS_iswr_I => ipb_iswr, - IPBUS_isrd_I => ipb_isrd, - IPBUS_ack_O => ipb_ack_tm, - IPBUS_err_O => ipb_err_tm, - IPBUS_base_addr_I => (others => '0') - ); --- ===================================================== + loc_data <= HDMI0_s when ipb_addr(8 downto 0) = '0' & x"00" else + HDMI0_d when ipb_addr(8 downto 0) = '0' & x"01" else + x"0000000" & "000" & PM_rq when ipb_addr(8 downto 0) = '0' & x"02" else + t_stmp when ipb_addr(8 downto 0) = '0' & x"03" else + x"0000" & d_sns when adc_sel = '1' else + x"00000000"; --- FIT GBT project ===================================== -FitGbtPrg: entity work.FIT_GBT_project - generic map( - GENERATE_GBT_BANK => 1 - ) - - Port map( - RESET_I => reset_to_syscount, - SysClk_I => FSM_Clocks.System_Clk, - DataClk_I => FSM_Clocks.Data_Clk, - MgtRefClk_I => MgtRefClk_to_FIT_GBT, - RxDataClk_I => GBT_RxFrameClk, -- 40MHz data clock in RX domain (loop back) - GBT_RxFrameClk_O => GBT_RxFrameClk, - - Board_data_I => board_data_test_const, - Control_register_I => TESTM_control, - - MGT_RX_P_I => SFP_RX_P, - MGT_RX_N_I => SFP_RX_N, - MGT_TX_P_O => SFP_TX_P, - MGT_TX_N_O => SFP_TX_N, - MGT_TX_dsbl_O => open, - - RxData_rxclk_to_FITrd_I => RxData_rxclk_from_GBT, --loop back data - IsRxData_rxclk_to_FITrd_I => IsRxData_rxclk_from_GBT, --loop back data - Data_from_FITrd_O => Data_from_FITrd, - IsData_from_FITrd_O => IsData_from_FITrd, - Data_to_GBT_I => Data_from_FITrd, --loop back data - IsData_to_GBT_I => IsData_from_FITrd, --loop back data - - RxData_rxclk_from_GBT_O => RxData_rxclk_from_GBT, - IsRxData_rxclk_from_GBT_O => IsRxData_rxclk_from_GBT, - rx_ph320 => open, - ph_error320 => open, - - FIT_GBT_status_O => TESTM_status - ); --- ===================================================== + with bus_select select + ipb_in.ipb_ack <= spi_ack when "00001", + ipb_ack_tm when "00010", + pm_spi_rdy when "00100", + tcm_sc_rdy when "01000", + loc_rdy when "10000", + '0' when others; + + + ipb_in.ipb_err <= spi_err or ipb_err_tm; + + with bus_select select + ipb_data_in <= spi_data_r when "00001", + ipb_data_in_tm when "00010", + pm_spi_data when "00100", + tcm_sc_data when "01000", + loc_data when "10000", + x"00000000" when others; + + + + slave_spi : entity work.ipbus_spi + port map( + clk => ipb_clk, + rst => ipb_rst, + ipb_data_w => ipb_data_out, + ipb_data_r => spi_data_r, + ipb_spi_adr => ipb_addr(2 downto 0), + ipb_sel => bus_select(0), + ipb_wr => ipb_wr, + ss => spi_ss, + ipb_err => spi_err, + ipb_ack => spi_ack, + mosi => spi_mosi, + miso => spi_miso, + sclk => spi_sclk + ); + + pm_sc : pm_spi + port map (CLK => ipb_clk, + RST => ipb_rst, + DI => ipb_data_out, + DO => pm_spi_data, + A => ipb_addr(8 downto 0), + wr => ipb_iswr, + rd => ipb_isrd, + cs => bus_select(2), + rdy => pm_spi_rdy, + spi_sel => tcm_sel, + spi_clk => tcm_sck, + spi_mosi => tcm_mosi, + spi_miso => tcm_miso, + cnt_rd => cnt_rd, + PM_rst => PM_rst + ); + + LAI(7) <= tcm_sel; + LAI(6) <= tcm_sck; + LAI(5) <= tcm_mosi; + LAI(4) <= not tcm_miso; + + LAI(8) <= reset_logic; + LAI(9) <= '0'; + + + tcm_sc1 : tcm_sc + port map (CLK => ipb_clk, + RST => ipb_rst, + DI => ipb_data_out, + DO => tcm_sc_data, + A => ipb_addr(8 downto 0), + wr => ipb_iswr, + rd => ipb_isrd, + cs => bus_select(3), + rdy => tcm_sc_rdy, + cnt_rd => cnt_rd + ); + +--LAI(0)<=cnt_rd; + -- ################################################################################## + -- ################################################################################## diff --git a/firmware/common/ftm/hdl/GBT_DATA_sender.vhd b/firmware/common/ftm/hdl/GBT_DATA_sender.vhd deleted file mode 100644 index 1bebe80..0000000 --- a/firmware/common/ftm/hdl/GBT_DATA_sender.vhd +++ /dev/null @@ -1,127 +0,0 @@ ----------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 24.05.2019 11:51:36 --- Design Name: --- Module Name: GBT_DATA_sender - Behavioral --- Project Name: --- Target Devices: --- Tool Versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- - - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use ieee.numeric_std.all; -use ieee.std_logic_unsigned.all ; - -use work.fit_gbt_common_package.all; -use work.fit_gbt_board_package.all; - -entity GBT_DATA_sender is - Port ( - - FSM_Clocks_I : in FSM_Clocks_type; - - FIT_GBT_status_I : in FIT_GBT_status_type; - Control_register_I : in CONTROL_REGISTER_type; - - - RX_IsData_ORBCgen_I : in STD_LOGIC; - RX_Data_ORBCgen_I : in std_logic_vector(GBT_data_word_bitdepth-1 downto 0); - - DATA_converter_I : in std_logic_vector(fifo_data_bitdepth-1 downto 0); - FIFO_WE_converter_I : in std_logic; - - Is_spade_for_packet_O : out STD_LOGIC; - IsData_O : out STD_LOGIC; - Data_O : out std_logic_vector(GBT_data_word_bitdepth-1 downto 0) - ); - -end GBT_DATA_sender; - -architecture Behavioral of GBT_DATA_sender is - - - -signal send_data_fifo_words_count_rd : std_logic_vector(rawfifo_count_bitdepth-1 downto 0); -signal send_data_fifo_words_count_wr : std_logic_vector(rawfifo_count_bitdepth-1 downto 0); -signal send_data_fifo_data_tofifo : std_logic_vector(fifo_data_bitdepth-1 downto 0); -signal send_data_fifo_data_fromfifo : std_logic_vector(fifo_data_bitdepth-1 downto 0); -signal send_data_fifo_isempty : std_logic; -signal send_data_fifo_wren : std_logic; -signal send_data_fifo_rden : std_logic; -signal send_data_fifo_space_is_for_packet : STD_LOGIC; -signal send_data_fifo_reset : std_logic; - -attribute keep : string; - -attribute keep of send_data_fifo_wren : signal is "true"; -attribute keep of send_data_fifo_rden : signal is "true"; -attribute keep of send_data_fifo_isempty : signal is "true"; -attribute keep of send_data_fifo_data_tofifo : signal is "true"; -attribute keep of send_data_fifo_data_fromfifo : signal is "true"; - -begin - - -Data_O <= send_data_fifo_data_fromfifo WHEN (Control_register_I.Data_Gen.usage_generator = use_MAIN_generator) ELSE RX_Data_ORBCgen_I; -IsData_O <= send_data_fifo_rden WHEN (Control_register_I.Data_Gen.usage_generator = use_MAIN_generator) ELSE RX_IsData_ORBCgen_I; - -Is_spade_for_packet_O <= '1' when (unsigned(send_data_fifo_words_count_wr) <= rawfifo_depth-total_data_words-1) else - '0'; - - -send_data_fifo_data_tofifo <= DATA_converter_I; -send_data_fifo_wren <= FIFO_WE_converter_I; -send_data_fifo_reset <= '1' WHEN (Control_register_I.Data_Gen.usage_generator /= use_MAIN_generator) or (FSM_Clocks_I.Reset = '1') ELSE '0'; - -send_data_fifo_rden <= not send_data_fifo_isempty; - - --- data_fifo ============================================= -send_data_fifo_comp : entity work.raw_data_fifo -port map( - wr_clk => FSM_Clocks_I.System_Clk, - rd_clk => FSM_Clocks_I.Data_Clk, - wr_data_count => send_data_fifo_words_count_wr, - rd_data_count => send_data_fifo_words_count_rd, - rst => send_data_fifo_reset, - WR_EN => send_data_fifo_wren, - RD_EN => send_data_fifo_rden, - DIN => send_data_fifo_data_tofifo, - DOUT => send_data_fifo_data_fromfifo, - FULL => open, - EMPTY => send_data_fifo_isempty - ); --- =========================================================== - - --- Data ff data clk ********************************** --- process (FSM_Clocks_I.Data_Clk) --- begin - --- IF(rising_edge(FSM_Clocks_I.Data_Clk) )THEN --- IF (FSM_Clocks_I.Reset = '1') THEN --- send_data_fifo_rden <= '0'; --- ELSE --- send_data_fifo_rden <= not send_data_fifo_isempty; --- END IF; --- END IF; - --- end process; --- *************************************************** - - - - -end Behavioral; diff --git a/firmware/common/ftm/hdl/PLL_Reset_Generator.vhd b/firmware/common/ftm/hdl/PLL_Reset_Generator.vhd index 5b56125..3b4199e 100644 --- a/firmware/common/ftm/hdl/PLL_Reset_Generator.vhd +++ b/firmware/common/ftm/hdl/PLL_Reset_Generator.vhd @@ -2,90 +2,72 @@ -- Company: INR RAS -- Engineer: Finogeev D. A. dmitry-finogeev@yandex.ru -- --- Create Date: 09/11/2017 --- Design Name: --- Module Name: RXDATA_CLKSync - Behavioral --- Project Name: --- Target Devices: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision --- Additional Comments: +-- Create Date: 2017 +-- Description: reset logic after PLL ready -- +-- Revision: 08/2021 ---------------------------------------------------------------------------------- library IEEE; -use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_1164.all; use work.fit_gbt_common_package.all; -use ieee.std_logic_unsigned.all ; +use ieee.std_logic_unsigned.all; entity PLL_Reset_Generator is - Port ( - GRESET_I : in STD_LOGIC; - GDataClk_I : in STD_LOGIC; - PLL_ready_I : in STD_LOGIC; - - RESET_O : out std_logic - ); + port ( + GRESET_I : in std_logic; + GDataClk_I : in std_logic; + PLL_ready_I : in std_logic; + + reset_pll_o : out std_logic; + reset_lgc_o : out std_logic + ); end PLL_Reset_Generator; architecture Behavioral of PLL_Reset_Generator is - signal delay_cntr, delay_cntr_next : std_logic_vector(3 downto 0); - - signal pll_ready_ff0, pll_ready_ff1 : std_logic; - signal out_reset, out_reset_ff, out_reset_next : std_logic; + signal reset_in, reset_lgc, reset_pll : std_logic; - attribute keep : string; - attribute keep of delay_cntr : signal is "true"; - attribute keep of pll_ready_ff0 : signal is "true"; - attribute keep of pll_ready_ff1 : signal is "true"; - attribute keep of out_reset_ff : signal is "true"; - -begin - -RESET_O <= out_reset_ff; + type FSM_STATE_T is (s0_reset, s1_waitpll, s2_ready); + signal FSM_STATE : FSM_STATE_T; + signal reset_cnt : natural range 0 to 15 := 0; + signal pll_ready : std_logic; + -- attribute mark_debug : string; + -- attribute mark_debug of reset_in : signal is "true"; + -- attribute mark_debug of reset_cnt : signal is "true"; + -- attribute mark_debug of fsm_state : signal is "true"; + -- attribute mark_debug of reset_pll : signal is "true"; + -- attribute mark_debug of reset_lgc : signal is "true"; + -- attribute mark_debug of pll_ready : signal is "true"; --- Data clk *********************************** - PROCESS (GDataClk_I, GRESET_I) - BEGIN - IF(GRESET_I = '1') THEN - - delay_cntr <= (others => '0'); - pll_ready_ff0 <= '0'; - pll_ready_ff1 <= '0'; - - out_reset <= '1'; - out_reset_ff <= '1'; - else +begin - IF rising_edge(GDataClk_I)THEN - - delay_cntr <= delay_cntr_next; - pll_ready_ff0 <= PLL_ready_I; - pll_ready_ff1 <= pll_ready_ff0; - - out_reset <= out_reset_next; - out_reset_ff <= out_reset; - - END IF; - END IF; - END PROCESS; --- ******************************************** + process (GDataClk_I) + begin + if rising_edge(GDataClk_I)then + reset_in <= GRESET_I; + pll_ready <= PLL_ready_I; + reset_lgc_o <= reset_lgc; + reset_pll_o <= reset_pll; + if(reset_in = '1') then + fsm_state <= s0_reset; + elsif fsm_state = s0_reset then + fsm_state <= s1_waitpll; + reset_cnt <= 0; + reset_pll <= '1'; + reset_lgc <= '1'; + elsif fsm_state = s1_waitpll then + if reset_cnt < 15 then reset_cnt <= reset_cnt+1; else reset_pll <= '0'; end if; + if reset_cnt = 15 and pll_ready = '1' then fsm_state <= s2_ready; end if; + elsif fsm_state = s2_ready then + reset_lgc <= '0'; + end if; --- FSM *********************************************** -delay_cntr_next <= x"0" WHEN (pll_ready_ff0 = '0') or (pll_ready_ff1 = '0') ELSE - x"f" WHEN (delay_cntr = x"f") ELSE - delay_cntr+1; + end if; + end process; -out_reset_next <= '0' WHEN delay_cntr = x"f" ELSE - out_reset; end Behavioral; diff --git a/firmware/common/ftm/hdl/ipbus_face.vhd b/firmware/common/ftm/hdl/ipbus_face.vhd new file mode 100644 index 0000000..d639362 --- /dev/null +++ b/firmware/common/ftm/hdl/ipbus_face.vhd @@ -0,0 +1,275 @@ +---------------------------------------------------------------------------------- +-- Company: INR RAS +-- Engineer: Finogeev D. A. dmitry-finogeev@yandex.ru +-- +-- Create Date: 2017 +-- Description: IPBus interface for : FIT readout status/control, hdmi data, GBT data readout +-- +-- Revision: 07/2021 +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.STD_LOGIC_UNSIGNED.all; +use IEEE.NUMERIC_STD.all; + + +library work; +use work.fit_gbt_common_package.all; + +entity ipbus_face is + port ( + FSM_Clocks_I : in rdclocks_t; + ipbus_clock_i : in std_logic; + + FIT_GBT_status_I : in readout_status_t; + Control_register_O : out readout_control_t; + + GBTRX_IsData_rxclk_I : in std_logic; + GBTRX_Data_rxclk_I : in std_logic_vector(GBT_data_word_bitdepth-1 downto 0); + + hdmi_fifo_datain_I : in std_logic_vector(GBT_data_word_bitdepth-1 downto 0); + hdmi_fifo_wren_I : in std_logic; + hdmi_fifo_wrclk_I : in std_logic; + + IPBUS_rst_I : in std_logic; + IPBUS_data_out_O : out std_logic_vector (31 downto 0); + IPBUS_data_in_I : in std_logic_vector (31 downto 0); + IPBUS_addr_sel_I : in std_logic; + IPBUS_addr_I : in std_logic_vector(11 downto 0); + IPBUS_iswr_I : in std_logic; + IPBUS_isrd_I : in std_logic; + IPBUS_ack_O : out std_logic; + IPBUS_err_O : out std_logic; + IPBUS_base_addr_I : in std_logic_vector(11 downto 0) + ); +end ipbus_face; + +architecture Behavioral of ipbus_face is + + signal rx_reset, ipb_reset : std_logic; + + signal hdmi_fifo_rden, hdmi_fifo_isempty : std_logic; + signal hdmi_fifo_dout : std_logic_vector(GBT_data_word_bitdepth-1 downto 0); + + signal data_fifo_din : std_logic_vector(95 downto 0); + signal data_fifo_dout : std_logic_vector(191 downto 0); + signal data_fifo_count : std_logic_vector(13 downto 0); + signal data_fifo_wren, data_fifo_rden, data_fifo_full, data_fifo_empty : std_logic; + + type array32_type is array (natural range <>) of std_logic_vector(31 downto 0); + signal fifo_to_ipbus_data_map : array32_type(0 to 5); + signal fifo_to_ipbus_data_out : std_logic_vector(31 downto 0); + signal data_map_counter : natural range 0 to 5 := 0; + signal gbt_word_counter : std_logic_vector(15 downto 0) := x"0000"; + signal read_from_fifo_sgn, read_from_fifo_cmd : std_logic; + + signal ctrl_reg : ctrl_reg_t; + signal stat_reg, stat_reg_ipbclk : stat_reg_t; + signal readout_control : readout_control_t; + signal readout_status, readout_status_ff : readout_status_t; + + signal ipbus_addr_int, ipbus_base_addr_int : natural range 0 to 4095; + + -- ipbus fsm + signal ipbus_di, ipbus_do : std_logic_vector (31 downto 0); + signal ipbus_ack, ipbus_err : std_logic; + + -- test debug signals + signal debug_ipb_rst : std_logic; + signal debug_ipb_iswr : std_logic; + signal debug_ipb_isrd : std_logic; + signal debug_ipb_ack : std_logic; + signal debug_ipb_data_O : std_logic_vector (31 downto 0); + signal debug_ipb_data_I : std_logic_vector (31 downto 0); + signal debug_ipb_addr : std_logic_vector (11 downto 0); + + -- attribute mark_debug : string; + -- attribute MARK_DEBUG of debug_ipb_rst : signal is "true"; + -- attribute MARK_DEBUG of debug_ipb_iswr : signal is "true"; + -- attribute MARK_DEBUG of debug_ipb_isrd : signal is "true"; + -- attribute MARK_DEBUG of debug_ipb_ack : signal is "true"; + -- attribute MARK_DEBUG of debug_ipb_data_O : signal is "true"; + -- attribute MARK_DEBUG of debug_ipb_data_I : signal is "true"; + -- attribute MARK_DEBUG of debug_ipb_addr : signal is "true"; + -- attribute MARK_DEBUG of readout_control : signal is "true"; + -- attribute MARK_DEBUG of readout_status_ff : signal is "true"; + -- attribute MARK_DEBUG of data_fifo_dout : signal is "true"; + -- attribute MARK_DEBUG of data_fifo_rden : signal is "true"; + -- attribute MARK_DEBUG of data_map_counter : signal is "true"; + -- attribute MARK_DEBUG of fifo_to_ipbus_data_out : signal is "true"; + -- attribute MARK_DEBUG of data_fifo_count : signal is "true"; + -- attribute MARK_DEBUG of ipbus_addr_int : signal is "true"; + -- attribute MARK_DEBUG of stat_reg_ipbclk : signal is "true"; + -- attribute MARK_DEBUG of ctrl_reg : signal is "true"; + -- attribute MARK_DEBUG of ipbus_base_addr_int : signal is "true"; + + +begin + +-- debug signal assignement + debug_ipb_rst <= IPBUS_rst_I; + debug_ipb_iswr <= IPBUS_iswr_I; + debug_ipb_isrd <= IPBUS_isrd_I; + debug_ipb_ack <= ipbus_ack; + debug_ipb_data_O <= ipbus_do; + debug_ipb_data_I <= IPBUS_data_in_I; + debug_ipb_addr <= IPBUS_addr_I; + +-- ipbus wiring + ipbus_di <= IPBUS_data_in_I; + IPBUS_data_out_O <= ipbus_do; + IPBUS_ack_O <= ipbus_ack; + IPBUS_err_O <= '0'; + + +-- DATA FIFO 192 bit mapping to 6X32 bit words + fifo_to_ipbus_data_map(5) <= data_fifo_dout(31 downto 0); + fifo_to_ipbus_data_map(4) <= data_fifo_dout(63 downto 32); + fifo_to_ipbus_data_map(3) <= data_fifo_dout(95 downto 64); + fifo_to_ipbus_data_map(2) <= data_fifo_dout(127 downto 96); + fifo_to_ipbus_data_map(1) <= data_fifo_dout(159 downto 128); + fifo_to_ipbus_data_map(0) <= data_fifo_dout(191 downto 160); + +-- address constants + ipbus_base_addr_int <= to_integer(unsigned(IPBUS_base_addr_I)); + ipbus_addr_int <= to_integer(unsigned(IPBUS_addr_I)) - ipbus_base_addr_int; + +-- ctrl / stat registers + Control_register_O <= readout_control; + + -- reassign status to add ipbus count and data + readout_status.GBT_status <= FIT_GBT_status_I.GBT_status; + readout_status.Readout_Mode <= FIT_GBT_status_I.Readout_Mode; + readout_status.CRU_Readout_Mode <= FIT_GBT_status_I.CRU_Readout_Mode; + readout_status.BCIDsync_Mode <= FIT_GBT_status_I.BCIDsync_Mode; + readout_status.BCID_from_CRU <= FIT_GBT_status_I.BCID_from_CRU; + readout_status.ORBIT_from_CRU <= FIT_GBT_status_I.ORBIT_from_CRU; + readout_status.Trigger_from_CRU <= FIT_GBT_status_I.Trigger_from_CRU; + readout_status.bcind_trg <= FIT_GBT_status_I.bcind_trg; + readout_status.bcind_evt <= FIT_GBT_status_I.bcind_evt; + readout_status.Stop_run <= FIT_GBT_status_I.Stop_run; + readout_status.Start_run <= FIT_GBT_status_I.Start_run; + readout_status.rx_phase <= FIT_GBT_status_I.rx_phase; + readout_status.cnv_fifo_max <= FIT_GBT_status_I.cnv_fifo_max; + readout_status.cnv_drop_cnt <= FIT_GBT_status_I.cnv_drop_cnt; + readout_status.sel_fifo_max <= FIT_GBT_status_I.sel_fifo_max; + readout_status.sel_drop_cnt <= FIT_GBT_status_I.sel_drop_cnt; + readout_status.gbt_data_cnt <= FIT_GBT_status_I.gbt_data_cnt; + readout_status.fsm_errors <= FIT_GBT_status_I.fsm_errors; + readout_status.ipbusrd_fifo_cnt <= "00"&data_fifo_count; + readout_status.ipbusrd_fifo_out <= fifo_to_ipbus_data_out; + + + + +-- HDMI FIFO =========================================== + hdmi_fifo_comp : entity work.hdmi_data_fifo + port map ( + rst => FSM_Clocks_I.Reset_sclk, + wr_clk => hdmi_fifo_wrclk_I, + rd_clk => FSM_Clocks_I.GBT_RX_Clk, + din => hdmi_fifo_datain_I, + wr_en => hdmi_fifo_wren_I, + rd_en => hdmi_fifo_rden, + dout => hdmi_fifo_dout, + full => open, + empty => hdmi_fifo_isempty, + rd_data_count => open, + wr_rst_busy => open, + rd_rst_busy => open + ); + + hdmi_fifo_rden <= '1' when (GBTRX_IsData_rxclk_I = '0') and (hdmi_fifo_isempty = '0') else '0'; +-- ===================================================== + + + +-- DATA FIFO =========================================== + ipbus_data_fifo_comp : entity work.ipbus_data_fifo + port map ( + rst => ipb_reset, + wr_clk => FSM_Clocks_I.GBT_RX_Clk, + rd_clk => ipbus_clock_i, + din => data_fifo_din, + wr_en => data_fifo_wren, + rd_en => data_fifo_rden, + dout => data_fifo_dout, + full => data_fifo_full, + empty => data_fifo_empty, + rd_data_count => data_fifo_count, + wr_rst_busy => open, + rd_rst_busy => open + ); + + data_fifo_din <= gbt_word_counter & GBTRX_Data_rxclk_I when (GBTRX_IsData_rxclk_I = '1') else gbt_word_counter & hdmi_fifo_dout; + data_fifo_wren <= '1' when (GBTRX_IsData_rxclk_I = '1') or (hdmi_fifo_rden = '1') else '0'; + data_fifo_rden <= '1' when read_from_fifo_sgn = '1' and data_map_counter = 5 else '0'; + read_from_fifo_sgn <= '1' when read_from_fifo_cmd = '1' and data_fifo_empty = '0' else '0'; + read_from_fifo_cmd <= '1' when ipbus_addr_int = ipbusrd_fifo_out_addr else '0'; + fifo_to_ipbus_data_out <= fifo_to_ipbus_data_map(data_map_counter) when data_fifo_empty = '0' else x"aaaa_aaaa"; + + + process (FSM_Clocks_I.GBT_RX_Clk) + begin + if(rising_edge(FSM_Clocks_I.GBT_RX_Clk))then + rx_reset <= FSM_Clocks_I.Reset_dclk; + if rx_reset = '1' or (gbt_word_counter = x"ffff") then gbt_word_counter <= (others => '0'); + elsif (data_fifo_wren = '1') then gbt_word_counter <= gbt_word_counter +1; end if; + end if; + end process; +-- ===================================================== + + -- status and control by data clock + process (FSM_Clocks_I.Data_Clk) + begin + if(rising_edge(FSM_Clocks_I.Data_Clk))then + readout_control <= func_CNTRREG_getcntrreg(ctrl_reg); + -- extra latch for ila + readout_status_ff <= readout_status; + stat_reg <= func_STATREG_getaddrreg(readout_status_ff); + end if; + end process; + + +-- IPbus clock ***************************************** + process (ipbus_clock_i) + begin + if(rising_edge(ipbus_clock_i))then + ipb_reset <= IPBUS_rst_I; + stat_reg_ipbclk <= stat_reg; + + if (ipb_reset = '1') then + + data_map_counter <= 0; + ctrl_reg <= (others => (others => '0')); + + else + + if read_from_fifo_sgn = '1' then + if data_map_counter < 5 then data_map_counter <= data_map_counter+1; else data_map_counter <= 0; end if; + end if; + + if(IPBUS_iswr_I = '1') and (ipbus_addr_int < ctrl_reg_size) then ctrl_reg(ipbus_addr_int) <= ipbus_di; end if; + + + end if; + end if; + + end process; +-- *************************************************** + ipbus_ack <= '1' when (IPBUS_isrd_I = '1') and (ipbus_addr_int < ipbusrd_stat_addr_offset + stat_reg_size) else -- reading + '1' when (IPBUS_iswr_I = '1') and (ipbus_addr_int < ctrl_reg_size) else -- writing + '0'; + + + ipbus_do <= (others => '0') when (ipbus_ack = '0') or (IPBUS_isrd_I = '0') else + ctrl_reg(ipbus_addr_int) when (ipbus_addr_int < ctrl_reg_size) else + stat_reg_ipbclk(ipbus_addr_int-ipbusrd_stat_addr_offset) when (ipbus_addr_int >= ipbusrd_stat_addr_offset) and (ipbus_addr_int < ipbusrd_stat_addr_offset + stat_reg_size) else + x"00000000"; + +end Behavioral; + + + diff --git a/firmware/common/gbt-readout/hdl/BC_counter.vhd b/firmware/common/gbt-readout/hdl/BC_counter.vhd deleted file mode 100644 index 518d4cb..0000000 --- a/firmware/common/gbt-readout/hdl/BC_counter.vhd +++ /dev/null @@ -1,103 +0,0 @@ ----------------------------------------------------------------------------------- --- Company: INR RAS --- Engineer: Finogeev D. A. dmitry-finogeev@yandex.ru --- --- Create Date: 06/11/2017 --- Design Name: --- Module Name: RXDATA_CLKSync - Behavioral --- Project Name: --- Target Devices: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision --- Additional Comments: --- ----------------------------------------------------------------------------------- - - - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use ieee.numeric_std.all; -use ieee.std_logic_unsigned.all ; - -use work.fit_gbt_common_package.all; - -entity BC_counter is -Port ( - RESET_I : in STD_LOGIC; - DATA_CLK_I : in STD_LOGIC; -- 40MHz board clk - - IS_INIT_I : in STD_LOGIC; - ORBC_ID_INIT_I : in std_logic_vector(Orbit_id_bitdepth + BC_id_bitdepth-1 downto 0); - - ORBC_ID_COUNT_O : out std_logic_vector(Orbit_id_bitdepth + BC_id_bitdepth-1 downto 0); - IS_Orbit_trg_O : out std_logic - ); -end BC_counter; - -architecture Behavioral of BC_counter is - - signal ORBC_ID_COUNT_ff, ORBC_ID_COUNT_ff_next : std_logic_vector(Orbit_id_bitdepth + BC_id_bitdepth-1 downto 0); - signal IS_Orbit_trg_ff, IS_Orbit_trg_ff_next : std_logic; - - signal Orbit_ID : std_logic_vector(Orbit_id_bitdepth-1 downto 0); - signal Orbit_ID_max : std_logic_vector(Orbit_id_bitdepth-1 downto 0); - signal BC_ID : std_logic_vector(BC_id_bitdepth-1 downto 0); - signal BC_ID_start : std_logic_vector(BC_id_bitdepth-1 downto 0); - -begin - --- flip-flop connecting ****************************** - Orbit_ID_max <= (others => '1'); - BC_ID_start <= (others => '0'); - - ORBC_ID_COUNT_O <= ORBC_ID_COUNT_ff; - IS_Orbit_trg_O <= IS_Orbit_trg_ff; - Orbit_ID <= ORBC_ID_COUNT_ff(Orbit_id_bitdepth + BC_id_bitdepth - 1 downto BC_id_bitdepth); - BC_ID <= ORBC_ID_COUNT_ff(BC_id_bitdepth - 1 downto 0); --- *************************************************** - - - --- Data ff data clk ********************************** - PROCESS (DATA_CLK_I) - BEGIN - IF(DATA_CLK_I'EVENT and DATA_CLK_I = '1') THEN - IF(RESET_I = '1') THEN - ORBC_ID_COUNT_ff <= (others => '0'); - IS_Orbit_trg_ff <= '0'; - ELSE - ORBC_ID_COUNT_ff <= ORBC_ID_COUNT_ff_next; - IS_Orbit_trg_ff <= IS_Orbit_trg_ff_next; - END IF; - END IF; - END PROCESS; --- *************************************************** - - - - - --- FSM *********************************************** -ORBC_ID_COUNT_ff_next <= (others => '0') WHEN (RESET_I = '1') ELSE - ORBC_ID_INIT_I WHEN (IS_INIT_I = '1') ELSE - - (others => '0') WHEN (Orbit_ID = Orbit_ID_max) ELSE - ( (Orbit_ID + 1) & BC_ID_start) WHEN (BC_ID = (LHC_BCID_max + BC_ID_start)) ELSE - ( Orbit_ID & (BC_ID+1) ); - -IS_Orbit_trg_ff_next <= '0' WHEN (RESET_I = '1') ELSE - '1' WHEN (Orbit_ID = Orbit_ID_max) ELSE - '1' WHEN (BC_ID = (LHC_BCID_max + BC_ID_start)) ELSE - '0'; --- *************************************************** - - - -end Behavioral; - diff --git a/firmware/common/gbt-readout/hdl/CRU_ORBC_Gen.vhd b/firmware/common/gbt-readout/hdl/CRU_ORBC_Gen.vhd deleted file mode 100644 index d447612..0000000 --- a/firmware/common/gbt-readout/hdl/CRU_ORBC_Gen.vhd +++ /dev/null @@ -1,361 +0,0 @@ ----------------------------------------------------------------------------------- --- Company: INR RAS --- Engineer: Finogeev D. A. dmitry-finogeev@yandex.ru --- --- Create Date: 07/11/2017 --- Design Name: --- Module Name: RXDATA_CLKSync - Behavioral --- Project Name: --- Target Devices: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision --- Additional Comments: --- ----------------------------------------------------------------------------------- - - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use ieee.numeric_std.all; -use ieee.std_logic_unsigned.all ; - -use work.fit_gbt_common_package.all; -use work.fit_gbt_board_package.all; - - -entity CRU_ORBC_Gen is - Port ( - FSM_Clocks_I : in FSM_Clocks_type; - - FIT_GBT_status_I : in FIT_GBT_status_type; - Control_register_I : in CONTROL_REGISTER_type; - - RX_IsData_I : in STD_LOGIC; - RX_Data_I : in std_logic_vector(GBT_data_word_bitdepth-1 downto 0); - - RX_IsData_O : out STD_LOGIC; - RX_Data_O : out std_logic_vector(GBT_data_word_bitdepth-1 downto 0); - - Current_BCID_from_O : out std_logic_vector(BC_id_bitdepth-1 downto 0); -- BC ID from CRUS - Current_ORBIT_from_O: out std_logic_vector(Orbit_id_bitdepth-1 downto 0); -- ORBIT from CRUS - Current_Trigger_from_O : out std_logic_vector(Trigger_bitdepth-1 downto 0) - ); -end CRU_ORBC_Gen; - -architecture Behavioral of CRU_ORBC_Gen is - - signal RX_Data_gen_ff, RX_Data_gen_ff_next : std_logic_vector(GBT_data_word_bitdepth-1 downto 0); - signal RX_IsData_gen_ff, RX_IsData_gen_ff_next : STD_LOGIC; - - signal EV_ID_counter_set : std_logic; - signal EV_ID_counter : std_logic_vector(Orbit_id_bitdepth + BC_id_bitdepth-1 downto 0); - signal IS_Orbit_trg_counter : std_logic; - - - type readout_trg_type is (s0_idle, s1_trg_SOC, s1_trg_SOT, s1_trg_EOC, s1_trg_EOT); - signal rd_trg_send_mode, rd_trg_send_mode_next : readout_trg_type; - signal is_rd_trg_send : std_logic; - signal readout_command_ff, readout_command_ff1 : Readout_command_type := idle; - signal runType_mode, running_mode : std_logic_vector(Trigger_bitdepth-1 downto 0); - - - signal is_trigger_sending : std_logic; -- emulating CRU trigger messages - signal TRG_evid : std_logic_vector(Trigger_bitdepth-1 downto 0); - signal TRG_readout_command : std_logic_vector(Trigger_bitdepth-1 downto 0); - signal TRG_readout_state : std_logic_vector(Trigger_bitdepth-1 downto 0); - signal TRG_result : std_logic_vector(Trigger_bitdepth-1 downto 0); - signal isTRG_valid : std_logic; - - - -- single trigger - signal is_send_single_trg : std_logic; - signal single_trg_val, single_trg_val_ff, single_trg_send_val : std_logic_vector(Trigger_bitdepth-1 downto 0); - - -- continious trigger - signal cont_trg_value, cont_trg_send : std_logic_vector(Trigger_bitdepth-1 downto 0); - signal cont_trg_bunch_mask : std_logic_vector(64 downto 0); - signal cont_trg_bunch_mask_comp : std_logic; - -- type cont_trg_bunch_mask_mux_type is array (0 to 64) of std_logic; - -- signal cont_trg_bunch_mask_mux : cont_trg_bunch_mask_mux_type; - signal bunch_freq : std_logic_vector(15 downto 0); - signal bunch_freq_hboffset : std_logic_vector(BC_id_bitdepth-1 downto 0); - signal reset_offset : std_logic; - - signal bfreq_counter, bfreq_counter_next : std_logic_vector(15 downto 0); - signal bpattern_counter, bpattern_counter_next : integer := 0; - signal is_boffset_sync, is_boffset_sync_next : std_logic; - signal is_sentd_cont_trg : std_logic; - - -- single trigger - signal trigger_single_val : std_logic_vector(Trigger_bitdepth-1 downto 0); -- send this trigger (once then moved from 0->1) - - - attribute mark_debug : string; - attribute mark_debug of rd_trg_send_mode : signal is "true"; - attribute mark_debug of bpattern_counter : signal is "true"; - attribute mark_debug of cont_trg_send : signal is "true"; - attribute mark_debug of is_sentd_cont_trg : signal is "true"; - attribute mark_debug of cont_trg_bunch_mask_comp : signal is "true"; - attribute mark_debug of TRG_result : signal is "true"; - attribute mark_debug of is_trigger_sending : signal is "true"; - attribute mark_debug of is_send_single_trg : signal is "true"; - attribute mark_debug of single_trg_send_val : signal is "true"; - attribute mark_debug of EV_ID_counter : signal is "true"; - attribute mark_debug of is_boffset_sync : signal is "true"; - - - - -begin - trigger_single_val <= Control_register_I.Trigger_Gen.trigger_single_val; - cont_trg_value <= Control_register_I.Trigger_Gen.trigger_cont_value; - cont_trg_bunch_mask <= '0' & Control_register_I.Trigger_Gen.trigger_pattern; - bunch_freq <= Control_register_I.Trigger_Gen.bunch_freq; -- first packet in bunch = bunch_freq_hboffset + delay - bunch_freq_hboffset <= Control_register_I.Trigger_Gen.bunch_freq_hboffset; - - single_trg_val <= Control_register_I.Trigger_Gen.trigger_single_val; - readout_command_ff <= Control_register_I.Trigger_Gen.Readout_command; - --- *************************************************** - RX_Data_O <= RX_Data_I WHEN (Control_register_I.Trigger_Gen.usage_generator = use_NO_generator) ELSE RX_Data_gen_ff; - RX_IsData_O <= RX_IsData_I WHEN (Control_register_I.Trigger_Gen.usage_generator = use_NO_generator) ELSE RX_IsData_gen_ff; --- *************************************************** - -Current_BCID_from_O <= EV_ID_counter(BC_id_bitdepth-1 downto 0); -Current_ORBIT_from_O <= EV_ID_counter(Orbit_id_bitdepth + BC_id_bitdepth-1 downto BC_id_bitdepth); -Current_Trigger_from_O <= TRG_result; - - --- BC Counter ================================================== - BC_counter_datagen_comp : entity work.BC_counter - port map ( - RESET_I => FSM_Clocks_I.Reset40, - DATA_CLK_I => FSM_Clocks_I.Data_Clk, - - IS_INIT_I => EV_ID_counter_set, - ORBC_ID_INIT_I => (others => '0'), - - ORBC_ID_COUNT_O => EV_ID_counter, - IS_Orbit_trg_O => IS_Orbit_trg_counter - ); --- ============================================================= - - --- MUX ========================================================= - -- process is - -- begin - - -- for i in 0 to 63 loop - -- cont_trg_bunch_mask_mux(i) <= cont_trg_bunch_mask(i); - -- end loop; - -- wait; - - -- end process; - -- cont_trg_bunch_mask_mux(64) <= '0'; --- cont_trg_bunch_mask(64) <= '0'; - cont_trg_bunch_mask_comp <= cont_trg_bunch_mask(bpattern_counter); --- ============================================================= - - --- Data ff data clk ********************************** - process (FSM_Clocks_I.Data_Clk) - begin - - IF(rising_edge(FSM_Clocks_I.Data_Clk) )THEN - IF (FSM_Clocks_I.Reset40 = '1') THEN - RX_Data_gen_ff <= (others => '0'); - RX_IsData_gen_ff <= '0'; --- phtrg_counter_ff <= (others => '0'); - rd_trg_send_mode <= s0_idle; - - bfreq_counter <= (others => '0'); - bpattern_counter <= 0; - is_boffset_sync <= '0'; - - single_trg_val_ff <= (others => '0'); - - readout_command_ff1 <= idle; - - ELSE - RX_Data_gen_ff <= RX_Data_gen_ff_next; - RX_IsData_gen_ff <= RX_IsData_gen_ff_next; --- phtrg_counter_ff <= phtrg_counter_ff_next; - rd_trg_send_mode <= rd_trg_send_mode_next; - - bfreq_counter <= bfreq_counter_next; - bpattern_counter <= bpattern_counter_next; - is_boffset_sync <= is_boffset_sync_next; - - - single_trg_val_ff <= single_trg_val; - readout_command_ff1 <= readout_command_ff; - END IF; - END IF; - - end process; --- *************************************************** - - - --- *************************************************** - - - ----------- Counters --------------------------------- -reset_offset <= Control_register_I.reset_gen_offset; --- phtrg_counter_ff_next <= (others => '0') WHEN (FSM_Clocks_I.Reset = '1') ELSE - -- (others => '0') WHEN (phtrg_counter_ff = Control_register_I.Trigger_Gen.trigger_rate) ELSE - -- phtrg_counter_ff + 1; - -bfreq_counter_next <= (others => '0') WHEN (FSM_Clocks_I.Reset = '1') ELSE - (others => '0') WHEN (bfreq_counter = bunch_freq-1) ELSE - (others => '0') WHEN (bunch_freq = 0) ELSE - (others => '0') WHEN (is_boffset_sync = '0') ELSE - x"0001" WHEN (EV_ID_counter(11 downto 0) = bunch_freq_hboffset) and (FIT_GBT_status_I.BCIDsync_Mode = mode_SYNC) ELSE - bfreq_counter + 1; - -is_boffset_sync_next <= '0' WHEN (FSM_Clocks_I.Reset = '1') ELSE - '0' WHEN (reset_offset = '1') ELSE - '1' WHEN (is_boffset_sync = '0') and (EV_ID_counter(11 downto 0) = bunch_freq_hboffset) and (FIT_GBT_status_I.BCIDsync_Mode = mode_SYNC) ELSE - is_boffset_sync; - - -bpattern_counter_next <= 0 WHEN (FSM_Clocks_I.Reset = '1') ELSE - 0 WHEN (bfreq_counter >= bunch_freq-1) ELSE - 64 WHEN (is_boffset_sync = '0') ELSE - 64 WHEN (bpattern_counter = 64) ELSE - bpattern_counter + 1; - -is_sentd_cont_trg <= '0' WHEN (FSM_Clocks_I.Reset = '1') ELSE - '0' WHEN (FIT_GBT_status_I.BCIDsync_Mode /= mode_SYNC) ELSE - '0' WHEN cont_trg_bunch_mask_comp = '0' ELSE - '1' WHEN cont_trg_bunch_mask_comp = '1'; - -cont_trg_send <= (others => '0') WHEN (FSM_Clocks_I.Reset = '1') ELSE - (others => '0') WHEN is_sentd_cont_trg = '0' ELSE - cont_trg_value; - --- Event ID counter start -EV_ID_counter_set <= '1' WHEN (bpattern_counter < 2) and (EV_ID_counter = x"00000000_000") ELSE - '0'; - ----------- CRU TX data gen ------------------------- -TRG_result <= TRG_readout_command or TRG_readout_state or TRG_evid or cont_trg_send or single_trg_send_val; -is_trigger_sending <= IS_Orbit_trg_counter or is_rd_trg_send or is_sentd_cont_trg or is_send_single_trg; -isTRG_valid <= is_trigger_sending; - - - - --- RX data -TRG_evid <= (TRG_const_HB) WHEN (IS_Orbit_trg_counter = '1') ELSE - (others => '0'); - - -RX_Data_gen_ff_next <= (others => '0') WHEN (FSM_Clocks_I.Reset = '1') ELSE - (others => '0') WHEN (is_trigger_sending = '0') ELSE --- "000" & isTRG_valid & EV_ID_counter(Orbit_id_bitdepth + BC_id_bitdepth-1 downto BC_id_bitdepth) & EV_ID_counter(BC_id_bitdepth-1 downto 0) & TRG_result; --- new versions of LTU GBT word, corrected on 18/11/2020 - EV_ID_counter(Orbit_id_bitdepth + BC_id_bitdepth-1 downto BC_id_bitdepth) & x"0" & EV_ID_counter(BC_id_bitdepth-1 downto 0) & TRG_result; - -RX_IsData_gen_ff_next <= '0' WHEN (FSM_Clocks_I.Reset = '1') ELSE - '1' WHEN (is_trigger_sending = '1') ELSE - '0'; - - - --- single trigger -is_send_single_trg <= '0' WHEN (FSM_Clocks_I.Reset = '1') ELSE - '1' WHEN (single_trg_val /= x"00000000") and (single_trg_val_ff = x"00000000") ELSE - '0'; - -single_trg_send_val <= (others => '0') WHEN (FSM_Clocks_I.Reset = '1') ELSE - single_trg_val WHEN (single_trg_val /= x"00000000") and (single_trg_val_ff = x"00000000") ELSE - (others => '0'); - - - - - --- Readout trigger send -is_rd_trg_send <= '1' WHEN (TRG_readout_command /= TRG_const_void) ELSE - '0'; - -TRG_readout_command <= TRG_const_SOT WHEN (rd_trg_send_mode = s1_trg_SOT) and (IS_Orbit_trg_counter = '1') ELSE - TRG_const_EOT WHEN (rd_trg_send_mode = s1_trg_EOT) and (IS_Orbit_trg_counter = '1') ELSE - TRG_const_SOC WHEN (rd_trg_send_mode = s1_trg_SOC) and (IS_Orbit_trg_counter = '1') ELSE - TRG_const_EOC WHEN (rd_trg_send_mode = s1_trg_EOC) and (IS_Orbit_trg_counter = '1') ELSE - (others => '0'); - - - --- type readout_trg_type is (s0_idle, s1_trg_SOC, s1_trg_SOT, s1_trg_EOC, s1_trg_EOT); --- type Readout_command_type is (idle, continious, trigger); -rd_trg_send_mode_next <= s0_idle WHEN (FSM_Clocks_I.Reset = '1') ELSE - s1_trg_SOC WHEN ((Control_register_I.Trigger_Gen.Readout_command = continious) and (readout_command_ff1 = idle)) ELSE - s1_trg_EOC WHEN ((Control_register_I.Trigger_Gen.Readout_command = idle) and (readout_command_ff1 = continious)) ELSE - s1_trg_SOT WHEN ((Control_register_I.Trigger_Gen.Readout_command = trigger) and (readout_command_ff1 = idle)) ELSE - s1_trg_EOT WHEN ((Control_register_I.Trigger_Gen.Readout_command = idle) and (readout_command_ff1 = trigger)) ELSE - s0_idle WHEN (is_rd_trg_send = '1') ELSE - rd_trg_send_mode; - -runType_mode <= TRG_const_RT WHEN (readout_command_ff1 = continious) and (rd_trg_send_mode = s0_idle) ELSE (others => '0'); -running_mode <= TRG_const_RS WHEN ((readout_command_ff1 = continious) or (readout_command_ff1 = trigger)) and (rd_trg_send_mode = s0_idle) ELSE (others => '0'); ---TRG_readout_state <= runType_mode or running_mode WHEN (IS_Orbit_trg_counter = '1') ELSE (others => '0'); -TRG_readout_state <= runType_mode or running_mode; --- *************************************************** - -end Behavioral; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/firmware/common/gbt-readout/hdl/CRU_packet_Builder.vhd b/firmware/common/gbt-readout/hdl/CRU_packet_Builder.vhd index 2a06533..18a50ce 100644 --- a/firmware/common/gbt-readout/hdl/CRU_packet_Builder.vhd +++ b/firmware/common/gbt-readout/hdl/CRU_packet_Builder.vhd @@ -19,9 +19,9 @@ ---------------------------------------------------------------------------------- library IEEE; -use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_1164.all; use ieee.numeric_std.all; -use ieee.std_logic_unsigned.all ; +use ieee.std_logic_unsigned.all; -- use ieee.STD_LOGIC_ARITH.all; use work.fit_gbt_common_package.all; @@ -29,219 +29,159 @@ use work.fit_gbt_board_package.all; entity CRU_packet_Builder is - Port ( - FSM_Clocks_I : in FSM_Clocks_type; - - FIT_GBT_status_I : in FIT_GBT_status_type; - Control_register_I : in CONTROL_REGISTER_type; - - SLCTFIFO_data_word_I : in std_logic_vector(fifo_data_bitdepth-1 downto 0); - SLCTFIFO_Is_Empty_I : in STD_LOGIC; - SLCTFIFO_RE_O : out STD_LOGIC; - - CNTPTFIFO_data_word_I : in std_logic_vector(cntpckfifo_data_bitdepth-1 downto 0); - CNTPFIFO_Is_Empty_I : in STD_LOGIC; - CNTPFIFO_RE_O : out STD_LOGIC; - - Is_Data_O : out STD_LOGIC; - Data_O : out std_logic_vector(GBT_data_word_bitdepth-1 downto 0) - ); + port ( + FSM_Clocks_I : in rdclocks_t; + + Status_register_I : in readout_status_t; + Control_register_I : in readout_control_t; + + SLCTFIFO_data_word_I : in std_logic_vector(GBT_data_word_bitdepth-1 downto 0); + SLCTFIFO_Is_Empty_I : in std_logic; + SLCTFIFO_RE_O : out std_logic; + + CNTPTFIFO_data_word_I : in std_logic_vector(127 downto 0); + CNTPFIFO_Is_Empty_I : in std_logic; + CNTPFIFO_RE_O : out std_logic; + + Is_Data_O : out std_logic; + Data_O : out std_logic_vector(GBT_data_word_bitdepth-1 downto 0); + + -- errors indicate unexpected FSM state, should be reset and debugged + -- 0 - slct_fifo is empty while reading data + errors_o : out std_logic_vector(0 downto 0) + ); end CRU_packet_Builder; architecture Behavioral of CRU_packet_Builder is - - constant nwords_in_SOP : integer := 5; - constant nwords_in_EOP : integer := 1; - - type SOP_format_type is array (0 to nwords_in_SOP-1) of std_logic_vector(GBT_data_word_bitdepth downto 0); - type EOP_format_type is array (0 to nwords_in_EOP-1) of std_logic_vector(GBT_data_word_bitdepth downto 0); - signal SOP_format : SOP_format_type; - signal EOP_format : EOP_format_type; - - - type FSM_STATE_T is (s0_start, s1_sop, s2_data, s3_eop); - signal FSM_STATE, FSM_STATE_NEXT : FSM_STATE_T; - - signal Word_Count, Word_Count_next : std_logic_vector(GEN_count_bitdepth-1 downto 0); - signal cont_packet_count, cont_packet_count_next : std_logic_vector(63 downto 0); - signal header_payload : std_logic_vector(GEN_count_bitdepth-1 downto 0); - signal dwords_payload : std_logic_vector(GEN_count_bitdepth-1 downto 0); - signal trailer_payload : std_logic_vector(GEN_count_bitdepth-1 downto 0); - signal data_payload_bytes : integer; - - signal is_close_frame : std_logic; - signal header_size : std_logic_vector(7 downto 0); - signal block_lenght : std_logic_vector(15 downto 0); - signal pages_counter : std_logic_vector(RDH_pages_counter_bitdepth-1 downto 0); - signal HB_Orbit : std_logic_vector(Orbit_id_bitdepth-1 downto 0); - signal HB_BC : std_logic_vector(BC_id_bitdepth-1 downto 0); - signal TRG_Orbit : std_logic_vector(Orbit_id_bitdepth-1 downto 0); - signal TRG_BC : std_logic_vector(BC_id_bitdepth-1 downto 0); - signal TRG_Type : std_logic_vector(Trigger_bitdepth-1 downto 0); - signal Link_ID : std_logic_vector(7 downto 0); - signal System_ID : std_logic_vector(7 downto 0); - signal Memory_size : std_logic_vector(15 downto 0); - - - signal Data_ff, Data_ff_next : std_logic_vector(GBT_data_word_bitdepth-1 downto 0); - signal IsData_ff, IsData_ff_next : STD_LOGIC; - - -- signal dataheader_ff, dataheader_ff_next : std_logic_vector(GBT_data_word_bitdepth-1 downto 0); --header for first event in packets - - - attribute keep : string; - attribute keep of Data_ff : signal is "true"; - attribute keep of IsData_ff : signal is "true"; - attribute keep of cont_packet_count : signal is "true"; + + -- control + signal readout_bypass : boolean; + + -- PACKET format + constant nwords_in_SOP : natural := 5; + constant nwords_in_EOP : natural := 1; + type SOP_format_type is array (0 to nwords_in_SOP-1) of std_logic_vector(GBT_data_word_bitdepth downto 0); + type EOP_format_type is array (0 to nwords_in_EOP-1) of std_logic_vector(GBT_data_word_bitdepth downto 0); + signal SOP_format : SOP_format_type; + signal EOP_format : EOP_format_type; + + -- header data + constant rdh_header_version : std_logic_vector(7 downto 0) := x"07"; + constant rdh_header_size : std_logic_vector(7 downto 0) := x"40"; + constant rdh_detector_field : std_logic_vector(31 downto 0) := x"00000000"; + constant rdh_par : std_logic_vector(15 downto 0) := x"0000"; + constant rdh_data_format : std_logic_vector(7 downto 0) := x"00"; -- will be replaced by CRU + + signal rdh_feeid : std_logic_vector(15 downto 0); + signal rdh_sysid : std_logic_vector(7 downto 0); + signal rdh_priority_bit : std_logic_vector(7 downto 0); + signal rdh_orbit : std_logic_vector(Orbit_id_bitdepth-1 downto 0); + signal rdh_bc : std_logic_vector(BC_id_bitdepth-1 downto 0); + signal rdh_trg : std_logic_vector(Trigger_bitdepth-1 downto 0); + signal rdh_stop : std_logic_vector(7 downto 0); + signal rdh_pages_counter : std_logic_vector(15 downto 0); + signal rdh_offset_new_packet : std_logic_vector(15 downto 0); + + -- FSM signals + type FSM_STATE_T is (s0_wait, s1_sop, s2_data, s3_eop); + signal FSM_STATE, FSM_STATE_NEXT : FSM_STATE_T; + signal word_counter, rdh_nwords : natural range 0 to 512+5+1 +1; + signal cntpck_fifo_re, slct_fifo_re : std_logic; + begin - Is_Data_O <= IsData_ff; - Data_O <= Data_ff; - - header_payload <= std_logic_vector(to_unsigned((nwords_in_SOP-1), GEN_count_bitdepth)); - dwords_payload <= func_CNTPCKword_npwords(CNTPTFIFO_data_word_I); - trailer_payload <= std_logic_vector(to_unsigned((nwords_in_EOP-1), GEN_count_bitdepth)); - - data_payload_bytes <= (to_integer(unsigned(dwords_payload)) + 4) * 16; - --- Data format *************************************** - is_close_frame <= func_CNTPCKword_isclf(CNTPTFIFO_data_word_I); - pages_counter <= func_CNTPCKword_pgcounter(CNTPTFIFO_data_word_I); --- header_size <= std_logic_vector(to_unsigned((nwords_in_SOP-1), 8)); --- header_size <= x"28"; - header_size <= x"40"; - block_lenght <= std_logic_vector(to_unsigned(( data_payload_bytes ), 16)); - HB_Orbit <= func_CNTPCKword_hborbit(CNTPTFIFO_data_word_I); - HB_BC <= func_CNTPCKword_hbbc(CNTPTFIFO_data_word_I); - TRG_Orbit <= func_CNTPCKword_trgorbit(CNTPTFIFO_data_word_I); - TRG_BC <= func_CNTPCKword_trgbc(CNTPTFIFO_data_word_I); - TRG_Type <= func_CNTPCKword_trigger(CNTPTFIFO_data_word_I); - Link_ID <= x"20"; - System_ID <= x"00"; - Memory_size <= x"0000"; - - -- is data - SOP_format(0) <= '0' & x"10000000000000000000"; -- SOP CRU - --SOP_format(0) <= '0' & x"00000000000000000001"; -- SOP G-RORC - --SOP_format(0) <= '0' & data_word_cnst_SOP; - - - -- v4 =================================================================================== - -- is data reserved priority bit FEE ID Block lenght header size header versions - --SOP_format(1) <= '1' & x"000000"& x"01"& Control_register_I.RDH_data.FEE_ID& block_lenght& header_size& x"04"; - - --SOP_format(2) <= '1' & x"0000"& HB_Orbit & TRG_Orbit; - - --SOP_format(3) <= '1' & x"0000"& TRG_Type & x"0"&HB_BC & x"0"&TRG_BC; - -- is data reserved pages counter stop bit PAR detector field - --SOP_format(4) <= '1' & x"000000"& pages_counter& "0000000"&is_close_frame& Control_register_I.RDH_data.PAR& Control_register_I.RDH_data.DET_Field; - -- ====================================================================================== - - - -- v6 =================================================================================== - -- is data reserved priority bit | FEE ID header versions - SOP_format(1) <= '1' & block_lenght& x"0000"& System_ID& x"01"& Control_register_I.RDH_data.FEE_ID& header_size& x"06"; - -- reserved - SOP_format(2) <= '1' & x"0000"& HB_Orbit & x"0000_0"& HB_BC; - -- reserved - SOP_format(3) <= '1' & x"0000"& x"00"& x"0"&"000"&is_close_frame & pages_counter & TRG_Type; - -- reserved - SOP_format(4) <= '1' & x"0000"& x"0000"& Control_register_I.RDH_data.PAR& x"0000"&Control_register_I.RDH_data.DET_Field; - -- ====================================================================================== - - - - - --EOP_format(0) <= '1' & x"ffff" & cont_packet_count; -- test trailer - EOP_format(0) <= '0' & x"20000000000000000000"; -- eop CRU --- *************************************************** - - - - - --- Data clock flip-flops ***************************** - PROCESS (FSM_Clocks_I.Data_Clk) - BEGIN - IF(FSM_Clocks_I.Data_Clk'EVENT and FSM_Clocks_I.Data_Clk = '1') THEN - IF(FSM_Clocks_I.Reset40 = '1') THEN - IsData_ff <= '0'; - Data_ff <= (others => '0'); --- dataheader_ff <= (others => '0'); - - FSM_STATE <= s0_start; - Word_Count <= (others => '0'); - cont_packet_count <= (others => '0'); - ELSE - IsData_ff <= IsData_ff_next; - Data_ff <= Data_ff_next; --- dataheader_ff <= dataheader_ff_next; - - FSM_STATE <= FSM_STATE_NEXT; - Word_Count <= Word_Count_next; - cont_packet_count <= cont_packet_count_next; - END IF; - END IF; - END PROCESS; --- *************************************************** - - - - --- FSM *********************************************** -FSM_STATE_NEXT <= s0_start WHEN (FSM_Clocks_I.Reset = '1') ELSE - s1_sop WHEN (FSM_STATE = s0_start) and (CNTPFIFO_Is_Empty_I = '0') ELSE - s3_eop WHEN (FSM_STATE = s1_sop) and (Word_Count = header_payload) and (dwords_payload = GEN_const_void) ELSE - s2_data WHEN (FSM_STATE = s1_sop) and (Word_Count = header_payload) ELSE - s3_eop WHEN (FSM_STATE = s2_data) and (Word_Count+1 = dwords_payload) ELSE - s0_start WHEN (FSM_STATE = s3_eop) and (Word_Count = trailer_payload) ELSE - FSM_STATE; - - -Word_Count_next <= (others => '0') WHEN (FSM_Clocks_I.Reset = '1') ELSE - (others => '0') WHEN (FSM_STATE = s0_start) ELSE - (others => '0') WHEN (FSM_STATE = s1_sop) and (Word_Count = header_payload) ELSE - (others => '0') WHEN (FSM_STATE = s2_data) and (Word_Count+1 = dwords_payload) ELSE - (others => '0') WHEN (FSM_STATE = s3_eop) and (Word_Count = trailer_payload) ELSE - Word_Count+1; - -cont_packet_count_next <= (others => '0') WHEN (FSM_Clocks_I.Reset = '1') ELSE - (others => '0') WHEN (FIT_GBT_status_I.Readout_Mode = mode_IDLE) ELSE - cont_packet_count+1 WHEN (FSM_STATE = s3_eop) and (Word_Count = trailer_payload) ELSE - cont_packet_count; - - --- dataheader_ff_next <= (others => '0') WHEN (FSM_Clocks_I.Reset = '1') ELSE - -- FIFO_data_word_I WHEN (FSM_STATE = s1_sop) and (Word_Count = 0) ELSE - -- dataheader_ff; - - -IsData_ff_next <= '0' WHEN (FSM_Clocks_I.Reset = '1') ELSE - SOP_format(to_integer(unsigned(Word_Count)))(GBT_data_word_bitdepth) WHEN (FSM_STATE = s1_sop) ELSE - '1' WHEN (FSM_STATE = s2_data) ELSE - EOP_format(to_integer(unsigned(Word_Count)))(GBT_data_word_bitdepth) WHEN (FSM_STATE = s3_eop) ELSE - '0'; - - -Data_ff_next <= (others => '0') WHEN (FSM_Clocks_I.Reset = '1') ELSE - SOP_format(to_integer(unsigned(Word_Count)))(GBT_data_word_bitdepth-1 downto 0) WHEN (FSM_STATE = s1_sop) ELSE - SLCTFIFO_data_word_I WHEN (FSM_STATE = s2_data) ELSE - EOP_format(to_integer(unsigned(Word_Count)))(GBT_data_word_bitdepth-1 downto 0) WHEN (FSM_STATE = s3_eop) ELSE - (others => '0'); - - -SLCTFIFO_RE_O <= '0' WHEN (FSM_Clocks_I.Reset = '1') ELSE - '1' WHEN (FSM_STATE = s2_data) ELSE - '0'; - -CNTPFIFO_RE_O <= '0' WHEN (FSM_Clocks_I.Reset = '1') ELSE - '1' WHEN (FSM_STATE = s3_eop) and (Word_Count = trailer_payload) ELSE - '0'; - --- *************************************************** - - - + -- continiosly reading select fifo in bypass mode + SLCTFIFO_RE_O <= slct_fifo_re when not readout_bypass else not SLCTFIFO_Is_Empty_I; + CNTPFIFO_RE_O <= cntpck_fifo_re; + + rdh_feeid <= Control_register_I.RDH_data.FEE_ID; + rdh_sysid <= Control_register_I.RDH_data.SYS_ID; + rdh_priority_bit <= Control_register_I.RDH_data.PRT_BIT; + rdh_offset_new_packet <= std_logic_vector(to_unsigned(((rdh_nwords+4)*16), 16)); -- will be replaced by CRU + + -- v6 =================================================================================== + SOP_format(0) <= '0' & x"10000000000000000000"; -- SOP CRU + -- RDH2[15 .. 0] RDH1[31 .. 0] RDH0 [31 .. 0] + SOP_format(1) <= '1' & rdh_offset_new_packet & x"0000" & rdh_sysid & rdh_priority_bit & rdh_feeid & rdh_header_size & rdh_header_version; + -- RDH6[15 .. 0] RDH5[31 .. 0] RDH4 [31 .. 0] + SOP_format(2) <= '1' & x"00" & rdh_data_format & rdh_orbit & x"0000_0" & rdh_bc; + -- RDH10[15 .. 0] RDH9[31 .. 0] RDH8 [31 .. 0] + SOP_format(3) <= '1' & x"0000_00" & rdh_stop & rdh_pages_counter & rdh_trg; + -- RDH14[15 .. 0] RDH13[31 .. 0] RDH12 [31 .. 0] + SOP_format(4) <= '1' & x"0000_0000" & rdh_par & rdh_detector_field; + EOP_format(0) <= '0' & x"20000000000000000000"; -- eop CRU + -- ====================================================================================== + + + -- Data ff data clk *********************************** + process (FSM_Clocks_I.Data_Clk) + begin + if(rising_edge(FSM_Clocks_I.Data_Clk))then + + if(FSM_Clocks_I.Reset_dclk = '1') then + + FSM_STATE <= s0_wait; + errors_o <= (others => '0'); + + else + + readout_bypass <= Control_register_I.readout_bypass = '1'; + + FSM_STATE <= FSM_STATE_NEXT; + + -- latching RDH info from fifo + if cntpck_fifo_re = '1' then + rdh_trg <= CNTPTFIFO_data_word_I(31 downto 0); + rdh_bc <= CNTPTFIFO_data_word_I(43 downto 32); + rdh_orbit <= CNTPTFIFO_data_word_I(75 downto 44); + rdh_nwords <= to_integer(unsigned(CNTPTFIFO_data_word_I(87 downto 76))); + rdh_pages_counter <= x"00" & CNTPTFIFO_data_word_I(95 downto 88); + rdh_stop <= "0000000" & CNTPTFIFO_data_word_I(96); + end if; + + -- word counter + if (FSM_STATE_NEXT = s1_sop) and ((FSM_STATE = s0_wait) or (FSM_STATE = s3_eop)) then word_counter <= 0; + elsif word_counter <= 512+5+1 +1 then word_counter <= word_counter + 1; end if; + + -- if select fifo becomes empty while reading data, raise error + if (FSM_STATE = s2_data) and SLCTFIFO_Is_Empty_I = '1' then errors_o(0) <= '1'; end if; + + + end if; + + end if; + end process; +-- **************************************************** + + FSM_STATE_NEXT <= s1_sop when (FSM_STATE = s0_wait) and (CNTPFIFO_Is_Empty_I = '0') else + s3_eop when (FSM_STATE = s1_sop) and (word_counter = nwords_in_SOP-1) and (rdh_nwords = 0) else + s2_data when (FSM_STATE = s1_sop) and (word_counter = nwords_in_SOP-1) else + s3_eop when (FSM_STATE = s2_data) and (word_counter = rdh_nwords + nwords_in_SOP-1) else + s0_wait when (FSM_STATE = s3_eop) and (word_counter = rdh_nwords + nwords_in_SOP + nwords_in_EOP-1) and (CNTPFIFO_Is_Empty_I = '1') else + s1_sop when (FSM_STATE = s3_eop) and (word_counter = rdh_nwords + nwords_in_SOP + nwords_in_EOP-1) and (CNTPFIFO_Is_Empty_I = '0') else + FSM_STATE; + + cntpck_fifo_re <= '1' when (FSM_STATE = s1_sop) and word_counter = 0 else '0'; + slct_fifo_re <= '1' when (FSM_STATE = s2_data) else '0'; + + Data_O <= SLCTFIFO_data_word_I when readout_bypass else + SOP_format(word_counter)(GBT_data_word_bitdepth-1 downto 0) when (FSM_STATE = s1_sop) else + SLCTFIFO_data_word_I when (FSM_STATE = s2_data) else + EOP_format(word_counter - rdh_nwords - nwords_in_SOP)(GBT_data_word_bitdepth-1 downto 0) when (FSM_STATE = s3_eop) else + (others => '0'); + + Is_Data_O <= not SLCTFIFO_Is_Empty_I when readout_bypass else + SOP_format(word_counter)(GBT_data_word_bitdepth) when (FSM_STATE = s1_sop) else + '1' when (FSM_STATE = s2_data) else + EOP_format(word_counter - rdh_nwords - nwords_in_SOP)(GBT_data_word_bitdepth) when (FSM_STATE = s3_eop) else + '0'; + + + + + + + end Behavioral; diff --git a/firmware/common/gbt-readout/hdl/DataCLK_strobe.vhd b/firmware/common/gbt-readout/hdl/DataCLK_strobe.vhd deleted file mode 100644 index d419b02..0000000 --- a/firmware/common/gbt-readout/hdl/DataCLK_strobe.vhd +++ /dev/null @@ -1,93 +0,0 @@ ----------------------------------------------------------------------------------- --- Company: INR RAS --- Engineer: Finogeev D. A. dmitry-finogeev@yandex.ru --- --- Create Date: 09/11/2017 --- Design Name: --- Module Name: RXDATA_CLKSync - Behavioral --- Project Name: --- Target Devices: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision --- Additional Comments: --- ----------------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use work.fit_gbt_common_package.all; -use ieee.std_logic_unsigned.all ; - -entity DataCLK_strobe is - Port ( - RESET_I : in STD_LOGIC; - RESET40_I : in STD_LOGIC; - SysClk_I : in STD_LOGIC; - DataClk_I : in STD_LOGIC; - SysClk_count_O : out std_logic_vector(3 downto 0); - Counter_ready_O : out STD_LOGIC - ); -end DataCLK_strobe; - -architecture Behavioral of DataCLK_strobe is - - signal DataClk_q_dataclk : std_logic := '0'; - signal DataClk_qff00_sysclk : std_logic; - signal DataClk_front_sysclk : std_logic; - - signal count_ready : std_logic; - signal sysclk_count_ff : std_logic_vector(2 downto 0); -begin - - SysClk_count_O <= '0' & sysclk_count_ff; - --- Data clk ********************************* -PROCESS(DataClk_I) -BEGIN - IF rising_edge(DataClk_I)THEN - - IF(RESET40_I = '1')THEN - Counter_ready_O <= '0'; - ELSE - Counter_ready_O <= count_ready; - DataClk_q_dataclk <= not DataClk_q_dataclk; - END IF; - - END IF; -END PROCESS; --- *************************************************** - - --- Clock clk ********************************* -PROCESS(SysClk_I) -BEGIN - IF rising_edge(SysClk_I)THEN - - IF(RESET_I = '1')THEN - count_ready <= '0'; - - ELSE - DataClk_qff00_sysclk <= DataClk_q_dataclk; - - if (DataClk_front_sysclk='1') then sysclk_count_ff <= "001"; count_ready <='1'; - else sysclk_count_ff <= sysclk_count_ff+1; - end if; - - END IF; - - END IF; -END PROCESS; --- *************************************************** - --- FSM *********************************************** -DataClk_front_sysclk <= DataClk_q_dataclk xor DataClk_qff00_sysclk; - - - -end Behavioral; - diff --git a/firmware/common/gbt-readout/hdl/DataConverter_PM.vhd b/firmware/common/gbt-readout/hdl/DataConverter_PM.vhd index 518cc77..8304262 100644 --- a/firmware/common/gbt-readout/hdl/DataConverter_PM.vhd +++ b/firmware/common/gbt-readout/hdl/DataConverter_PM.vhd @@ -2,233 +2,310 @@ -- Company: INR RAS -- Engineer: Finogeev D. A. dmitry-finogeev@yandex.ru -- --- Create Date: 07/11/2017 --- Design Name: --- Module Name: --- Project Name: --- Target Devices: --- Tool versions: --- Description: +-- Create Date: 2017 +-- Description: convert data from FEE to RDH format -- --- Dependencies: --- --- Revision: --- Revision --- Additional Comments: --- - --- TO DO: --- check packets from PM without space --- FIFO full --- FIFO reset --- 320 CLock - +-- Revision: 09/2021 ---------------------------------------------------------------------------------- library IEEE; -use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_1164.all; use ieee.numeric_std.all; -use ieee.std_logic_unsigned.all ; +use ieee.std_logic_unsigned.all; use work.fit_gbt_common_package.all; use work.fit_gbt_board_package.all; entity DataConverter is - Port ( - FSM_Clocks_I : in FSM_Clocks_type; - - FIT_GBT_status_I : in FIT_GBT_status_type; - Control_register_I : in CONTROL_REGISTER_type; - - Board_data_I : in board_data_type; - - FIFO_is_space_for_packet_I : in STD_LOGIC; - - FIFO_WE_O : out STD_LOGIC; - FIFO_data_word_O : out std_logic_vector(fifo_data_bitdepth-1 downto 0); - - hits_rd_counter_converter_O : out hit_rd_counter_type - ); + port ( + FSM_Clocks_I : in rdclocks_t; + + Status_register_I : in readout_status_t; + Control_register_I : in readout_control_t; + + Board_data_I : in board_data_type; + + header_fifo_data_o : out std_logic_vector(GBT_data_word_bitdepth-1 downto 0); + data_fifo_data_o : out std_logic_vector(GBT_data_word_bitdepth-1 downto 0); + header_fifo_rden_i : in std_logic; + data_fifo_rden_i : in std_logic; + header_fifo_empty_o : out std_logic; + data_fifo_empty_o : out std_logic; + no_data_o : out boolean; + + drop_ounter_o : out std_logic_vector(15 downto 0); + fifo_cnt_max_o : out std_logic_vector(15 downto 0); + + raw_data_o : out std_logic_vector(GBT_data_word_bitdepth-1 downto 0); + raw_isdata_o : out std_logic; + data_bcid_o : out std_logic_vector(BC_id_bitdepth-1 downto 0); + data_bcen_o : out std_logic; + + -- errors indicate unexpected FSM state, should be reset and debugged + -- 0 - data_fifo is not empty while start of run + -- 1 - header_fifo is not empty while start of run + -- 2 - tcm_data_fifo is full (for tcm only) + -- 3 - input packet corrupted: extra word + -- 4 - input packet corrupted: header too early + pm_data_shreg_o : out std_logic_vector(errrep_pmdat_len*80-1 downto 0); + rawdatfifo_wr_rate_o : out std_logic_vector(11 downto 0); + rawdatfifo_rd_rate_o : out std_logic_vector(11 downto 0); + errors_o : out std_logic_vector(4 downto 0) + ); end DataConverter; architecture Behavioral of DataConverter is - constant board_data_void_const : board_data_type := - ( - is_header => '0', - is_data => '0', - is_packet => '0', - data_word => (others => '0') - ); - - -- type FSM_STATE_T is (s0_wait_header, s1_sending_data); - -- signal FSM_STATE, FSM_STATE_NEXT : FSM_STATE_T; - - - signal Board_data_sysclkff, Board_data_sysclkff_next : Board_data_type; - signal FIFO_is_space_for_packet_ff, FIFO_is_space_for_packet_ff_next: std_logic; - --- signal word_counter_ff, word_counter_ff_next : std_logic_vector(n_pckt_wrds_bitdepth-1 downto 0); - constant counter_zero : std_logic_vector(n_pckt_wrds_bitdepth-1 downto 0) := (others => '0'); - signal packet_lenght_fromheader : std_logic_vector(n_pckt_wrds_bitdepth-1 downto 0); - --packet_lenght_ff, packet_lenght_ff_next : std_logic_vector(n_pckt_wrds_bitdepth-1 downto 0); - - signal header_orbit : std_logic_vector(Orbit_id_bitdepth-1 downto 0); - signal header_bc : std_logic_vector(BC_id_bitdepth-1 downto 0); - signal header_word, data_word : std_logic_vector(fifo_data_bitdepth-1 downto 0); - signal is_data_word_header : std_logic; - - signal sending_event, sending_event_next : std_logic; - signal FIFO_WE_ff, FIFO_WE_ff_next : STD_LOGIC; - signal FIFO_data_word_ff, FIFO_data_word_ff_next : std_logic_vector(fifo_data_bitdepth-1 downto 0); - - signal reset_drop_counters : std_logic; - signal is_dropping_event : std_logic;--, is_dropping_event_next : std_logic; - signal dropped_events, dropped_events_next : std_logic_vector(31 downto 0); - signal first_dropped_orbit, first_dropped_orbit_next : std_logic_vector(Orbit_id_bitdepth-1 downto 0); - signal first_dropped_bc, first_dropped_bc_next : std_logic_vector(BC_id_bitdepth-1 downto 0); - signal last_dropped_orbit, last_dropped_orbit_next : std_logic_vector(Orbit_id_bitdepth-1 downto 0); - signal last_dropped_bc, last_dropped_bc_next : std_logic_vector(BC_id_bitdepth-1 downto 0); - - - - attribute keep : string; - attribute keep of Board_data_sysclkff : signal is "true"; - attribute keep of reset_drop_counters : signal is "true"; - attribute keep of dropped_events : signal is "true"; - attribute keep of first_dropped_orbit : signal is "true"; - attribute keep of first_dropped_bc : signal is "true"; - attribute keep of last_dropped_orbit: signal is "true"; - attribute keep of last_dropped_bc: signal is "true"; - - -begin - + constant board_data_void_const : board_data_type := + ( + is_header => '0', + is_data => '0', + data_word => (others => '0') + ); + + signal header_pcklen, header_pcklen_ff, header_pcklen_latch, header_pcklen_latch_m1 : std_logic_vector(n_pckt_wrds_bitdepth-1 downto 0); + signal header_orbit : std_logic_vector(Orbit_id_bitdepth-1 downto 0); + signal header_bc : std_logic_vector(BC_id_bitdepth-1 downto 0); + signal header_word, header_word_latch, data_word : std_logic_vector(GBT_data_word_bitdepth-1 downto 0); + signal is_header, is_data : std_logic; + signal zero_pck : boolean; + + signal readout_bypass : boolean; + signal data_enabled, data_enabled_sclk, start_of_run : boolean; + signal reset_drop_counters : std_logic; + signal drop_counter : std_logic_vector(15 downto 0); + + signal data_rawfifo_cnt, rawfifo_cnt_max : std_logic_vector(12 downto 0); + signal header_rawfifo_full, data_rawfifo_full, rawfifo_full : std_logic; + + + signal sending_event, sending_event_dc : boolean; + signal word_counter : std_logic_vector(n_pckt_wrds_bitdepth-1 downto 0); + + signal header_fifo_din, data_fifo_din : std_logic_vector(GBT_data_word_bitdepth-1 downto 0); + signal header_fifo_we, data_fifo_we : std_logic; + signal header_fifo_empty, header_fifo_empty_dc, data_fifo_empty, data_fifo_empty_dc : std_logic; + + signal errors : std_logic_vector(1 downto 0); + signal err_extra_word, err_extra_header : std_logic; + + signal header_fifo_data : std_logic_vector(GBT_data_word_bitdepth-1 downto 0); + signal data_fifo_data : std_logic_vector(GBT_data_word_bitdepth-1 downto 0); + signal header_fifo_rden : std_logic; + signal data_fifo_rden : std_logic; + + signal pm_data_shreg, pm_data_shreg_dclk : std_logic_vector(errrep_pmdat_len*80-1 downto 0); + + signal rawdat_rate_cnt_cnt, rawdat_rate_cnt_wr, rawdat_rate_cnt_rd : std_logic_vector(11 downto 0); + signal rawdat_rate_wr, rawdat_rate_rd : std_logic_vector(11 downto 0); + signal rawdat_rate_wr_dc, rawdat_rate_rd_dc : std_logic_vector(11 downto 0); + + -- attribute mark_debug : string; + -- attribute mark_debug of reset_drop_counters : signal is "true"; + -- attribute mark_debug of header_fifo_din : signal is "true"; + -- attribute mark_debug of data_fifo_din : signal is "true"; + -- attribute mark_debug of header_fifo_we : signal is "true"; + -- attribute mark_debug of data_fifo_we : signal is "true"; + -- attribute mark_debug of word_counter : signal is "true"; + -- attribute mark_debug of sending_event : signal is "true"; + -- attribute mark_debug of header_word : signal is "true"; + -- attribute mark_debug of data_word : signal is "true"; + -- attribute mark_debug of is_data : signal is "true"; + -- attribute mark_debug of is_header : signal is "true"; + -- attribute mark_debug of header_pcklen_ff : signal is "true"; + -- attribute mark_debug of header_word_latch : signal is "true"; + -- attribute mark_debug of header_pcklen_latch : signal is "true"; + -- attribute mark_debug of header_fifo_empty : signal is "true"; + -- attribute mark_debug of data_fifo_empty : signal is "true"; + -- attribute mark_debug of header_rawfifo_full : signal is "true"; + -- attribute mark_debug of data_rawfifo_full : signal is "true"; + -- attribute mark_debug of header_fifo_data : signal is "true"; + -- attribute mark_debug of data_fifo_data : signal is "true"; + -- attribute mark_debug of header_fifo_rden : signal is "true"; + -- attribute mark_debug of data_fifo_rden : signal is "true"; + -- attribute mark_debug of pm_data_shreg : signal is "true"; + -- attribute mark_debug of err_extra_word : signal is "true"; + -- attribute mark_debug of err_extra_header : signal is "true"; +begin --- Wiring ******************************************** - FIFO_WE_O <= FIFO_WE_ff; - FIFO_data_word_O <= FIFO_data_word_ff; - - - hits_rd_counter_converter_O.hits_send_porbit <= (others => '0'); - hits_rd_counter_converter_O.hits_skipped <= dropped_events; - hits_rd_counter_converter_O.first_orbit_hdrop <= first_dropped_orbit; - hits_rd_counter_converter_O.first_bc_hdrop <= first_dropped_bc; - hits_rd_counter_converter_O.last_orbit_hdrop <= last_dropped_orbit; - hits_rd_counter_converter_O.last_bc_hdrop <= last_dropped_bc; - --- *************************************************** - --- Header format ************************************* - packet_lenght_fromheader <= func_PMHEADER_n_dwords( Board_data_sysclkff.data_word ); - header_orbit <=func_PMHEADER_getORBIT(Board_data_sysclkff.data_word); - header_bc <= func_PMHEADER_getBC(Board_data_sysclkff.data_word); - header_word <= func_FITDATAHD_get_header(packet_lenght_fromheader, header_orbit, header_bc, FIT_GBT_status_I.rx_phase, FIT_GBT_status_I.GBT_status.Rx_Phase_error, '0'); - data_word <= Board_data_sysclkff.data_word; --- *************************************************** - - --- Data ff data clk *********************************** - PROCESS (FSM_Clocks_I.System_Clk) - BEGIN - IF(FSM_Clocks_I.System_Clk'EVENT and FSM_Clocks_I.System_Clk = '1') THEN - IF(FSM_Clocks_I.Reset = '1') THEN - Board_data_sysclkff <= board_data_void_const; - sending_event <= '0'; - FIFO_is_space_for_packet_ff <= '0'; - - dropped_events <= (others => '0'); - first_dropped_orbit <= (others => '0'); - first_dropped_bc <= (others => '0'); - last_dropped_orbit <= (others => '0'); - last_dropped_bc <= (others => '0'); - FIFO_WE_ff <= '0'; - FIFO_data_word_ff <= (others => '0'); - - ELSE - Board_data_sysclkff <= Board_data_sysclkff_next; - sending_event <= sending_event_next; - FIFO_is_space_for_packet_ff <= FIFO_is_space_for_packet_ff_next; - FIFO_WE_ff <= FIFO_WE_ff_next; - FIFO_data_word_ff <= FIFO_data_word_ff_next; - - dropped_events <= dropped_events_next; - first_dropped_orbit <= first_dropped_orbit_next; - first_dropped_bc <= first_dropped_bc_next; - last_dropped_orbit <= last_dropped_orbit_next; - last_dropped_bc <= last_dropped_bc_next; - END IF; - - - END IF; + header_fifo_empty_o <= header_fifo_empty; + data_fifo_empty_o <= data_fifo_empty; + + header_pcklen <= func_PMHEADER_n_dwords(Board_data_I.data_word); + header_orbit <= func_PMHEADER_getORBIT(Board_data_I.data_word); + header_bc <= func_PMHEADER_getBC(Board_data_I.data_word); + + raw_data_o <= Board_data_I.data_word; + raw_isdata_o <= Board_data_I.is_data; + data_bcid_o <= header_bc; + data_bcen_o <= Board_data_I.is_header; + + header_fifo_data_o <= header_fifo_data; + data_fifo_data_o <= data_fifo_data; + header_fifo_rden <= header_fifo_rden_i; + data_fifo_rden <= data_fifo_rden_i; + + pm_data_shreg_o <= pm_data_shreg_dclk; + rawdatfifo_wr_rate_o <= rawdat_rate_wr_dc; + rawdatfifo_rd_rate_o <= rawdat_rate_rd_dc; + + +---- Raw_header_fifo ============================================= + raw_header_fifo_comp : entity work.raw_data_fifo + port map( + clk => FSM_Clocks_I.System_Clk, + srst => FSM_Clocks_I.Reset_sclk, + WR_EN => header_fifo_we, + RD_EN => header_fifo_rden, + DIN => header_fifo_din, + DOUT => header_fifo_data, + data_count => open, + prog_full => header_rawfifo_full, + FULL => open, + EMPTY => header_fifo_empty + ); +---- =========================================================== + + +---- Raw_data_fifo ============================================= + raw_data_fifo_comp : entity work.raw_data_fifo + port map( + clk => FSM_Clocks_I.System_Clk, + srst => FSM_Clocks_I.Reset_sclk, + WR_EN => data_fifo_we, + RD_EN => data_fifo_rden, + DIN => data_fifo_din, + DOUT => data_fifo_data, + data_count => data_rawfifo_cnt, + prog_full => data_rawfifo_full, + FULL => open, + EMPTY => data_fifo_empty + ); +---- =========================================================== + + rawfifo_full <= header_rawfifo_full or data_rawfifo_full; + + process (FSM_Clocks_I.Data_Clk) + begin + if(rising_edge(FSM_Clocks_I.Data_Clk))then + header_fifo_empty_dc <= header_fifo_empty; + data_fifo_empty_dc <= data_fifo_empty; + sending_event_dc <= sending_event; + + data_enabled <= Status_register_I.data_enable = '1'; + drop_ounter_o <= drop_counter; + fifo_cnt_max_o <= "000"&rawfifo_cnt_max; + errors_o <= err_extra_header&err_extra_word&'0'&errors; + no_data_o <= header_fifo_empty_dc = '1' and data_fifo_empty_dc = '1' and not sending_event_dc and not data_enabled; + + pm_data_shreg_dclk <= pm_data_shreg; + rawdat_rate_wr_dc <= rawdat_rate_wr; + rawdat_rate_rd_dc <= rawdat_rate_rd; + end if; + end process; + + +-- sys ff data clk *********************************** + process (FSM_Clocks_I.System_Clk) + begin + if(rising_edge(FSM_Clocks_I.System_Clk)) then + + reset_drop_counters <= Control_register_I.reset_data_counters; + start_of_run <= Status_register_I.Start_run = '1'; + readout_bypass <= Control_register_I.readout_bypass = '1'; + + + header_word <= func_FITDATAHD_get_header(header_pcklen, header_orbit, header_bc, Status_register_I.rx_phase, Status_register_I.Rx_Phase_error, '0'); + data_word <= Board_data_I.data_word; + is_data <= Board_data_I.is_data; + is_header <= Board_data_I.is_header; + header_pcklen_ff <= header_pcklen; + zero_pck <= false; + + data_enabled_sclk <= data_enabled; + + + if(FSM_Clocks_I.Reset_sclk = '1') then + + sending_event <= false; + drop_counter <= (others => '0'); + rawfifo_cnt_max <= (others => '0'); + word_counter <= (others => '1'); + errors <= (others => '0'); + err_extra_word <= '0'; + err_extra_header <= '0'; + + else + + if is_header = '1' then + + if (word_counter < header_pcklen_latch) then -- header is too early, skiping heade + err_extra_header <= '1'; + else -- header after prev packet - ok; or word_counter is max (start) + header_word_latch <= header_word; + header_pcklen_latch <= header_pcklen_ff; + header_pcklen_latch_m1 <= header_pcklen_ff-1; + zero_pck <= header_pcklen_ff = 0; + word_counter <= (others => '0'); + sending_event <= (rawfifo_full = '0') and data_enabled_sclk; + if (rawfifo_full = '1') and data_enabled_sclk and drop_counter /= x"ffff" then drop_counter <= drop_counter + 1; end if; + end if; + + elsif is_data = '1' then + + if (word_counter = header_pcklen_latch) and (err_extra_header = '0') then err_extra_word <= '1'; end if; + word_counter <= word_counter + 1; + + end if; + + -- turning off sending_event while idle without data for clear error 'ready for run' + if not data_enabled_sclk and header_fifo_empty = '1' and data_fifo_empty = '1' and is_data = '0' then + sending_event <= false; end if; + + if rawfifo_cnt_max < data_rawfifo_cnt then rawfifo_cnt_max <= data_rawfifo_cnt; end if; + + if reset_drop_counters = '1' then + drop_counter <= (others => '0'); + rawfifo_cnt_max <= (others => '0'); + end if; + + if start_of_run then errors <= (not header_fifo_empty) & (not data_fifo_empty); end if; + -- circle pm data buffer for error report + if (Board_data_I.is_data = '1') or (Board_data_I.is_header = '1') then + pm_data_shreg <= pm_data_shreg((errrep_pmdat_len-1)*80-1 downto 0)&Board_data_I.data_word; + end if; - END PROCESS; --- **************************************************** + -- raw fifo wr/rd rate + if rawdat_rate_cnt_cnt = x"3e8" then + rawdat_rate_rd <= rawdat_rate_cnt_rd; + rawdat_rate_wr <= rawdat_rate_cnt_wr; + rawdat_rate_cnt_rd <= (others => '0'); + rawdat_rate_cnt_wr <= (others => '0'); + rawdat_rate_cnt_cnt <= (others => '0'); + else + rawdat_rate_cnt_cnt <= rawdat_rate_cnt_cnt+1; + if data_fifo_we = '1' then rawdat_rate_cnt_wr <= rawdat_rate_cnt_wr+1; end if; + if data_fifo_rden = '1' then rawdat_rate_cnt_rd <= rawdat_rate_cnt_rd+1; end if; + end if; + end if; --- FSM ************************************************ -Board_data_sysclkff_next <= Board_data_I; -FIFO_is_space_for_packet_ff_next <= FIFO_is_space_for_packet_I; + end if; -reset_drop_counters <= Control_register_I.reset_drophit_counter; --- reset_drop_counters <= '1' WHEN (FSM_Clocks_I.Reset = '1') ELSE - -- '1' WHEN (FIT_GBT_status_I.Start_run = '1') ELSE - -- '0'; - -sending_event_next <= '0' WHEN (FSM_Clocks_I.Reset = '1') ELSE - '0' WHEN (Board_data_I.is_header = '1') and (FIFO_is_space_for_packet_ff = '0') ELSE - '1' WHEN (Board_data_I.is_header = '1') and (Control_register_I.readout_bypass='1') ELSE - '0' WHEN (Board_data_I.is_header = '1') and (FIT_GBT_status_I.Readout_Mode = mode_IDLE) ELSE - '1' WHEN (Board_data_I.is_header = '1') ELSE - sending_event; - -FIFO_data_word_ff_next <= (others => '0') WHEN (FSM_Clocks_I.Reset = '1') ELSE - header_word WHEN (sending_event = '1') and (Board_data_sysclkff.is_header = '1') ELSE - data_word WHEN (sending_event = '1') and (Board_data_sysclkff.is_data = '1') ELSE - (others => '0'); - -FIFO_WE_ff_next <= '0' WHEN (FSM_Clocks_I.Reset = '1') ELSE - '1' WHEN (Board_data_sysclkff.is_data = '1') and (sending_event = '1') ELSE - '0'; - --- Event counter ------------------------------------ - -is_dropping_event <= '0' WHEN (FSM_Clocks_I.Reset = '1') ELSE - '0' WHEN (FIT_GBT_status_I.Readout_Mode = mode_IDLE) ELSE - '1' WHEN (Board_data_sysclkff.is_header = '1') and (FIFO_is_space_for_packet_ff = '0') ELSE - '0'; - -dropped_events_next <= (others => '0') WHEN (FSM_Clocks_I.Reset = '1') ELSE - (others => '0') WHEN (reset_drop_counters = '1') ELSE - dropped_events + 1 WHEN (is_dropping_event = '1') ELSE - dropped_events; - -last_dropped_orbit_next <= (others => '0') WHEN (FSM_Clocks_I.Reset = '1') ELSE - (others => '0') WHEN (reset_drop_counters = '1') ELSE - header_orbit WHEN (is_dropping_event = '1') ELSE - last_dropped_orbit; - -last_dropped_bc_next <= (others => '0') WHEN (FSM_Clocks_I.Reset = '1') ELSE - (others => '0') WHEN (reset_drop_counters = '1') ELSE - header_bc WHEN (is_dropping_event = '1') ELSE - last_dropped_bc; - -first_dropped_orbit_next <= (others => '0') WHEN (FSM_Clocks_I.Reset = '1') ELSE - (others => '0') WHEN (reset_drop_counters = '1') ELSE - header_orbit WHEN (is_dropping_event = '1') and (last_dropped_orbit = ORBIT_const_void) ELSE - first_dropped_orbit; - -first_dropped_bc_next <= (others => '0') WHEN (FSM_Clocks_I.Reset = '1') ELSE - (others => '0') WHEN (reset_drop_counters = '1') ELSE - header_bc WHEN (is_dropping_event = '1') and (last_dropped_orbit = ORBIT_const_void) ELSE - first_dropped_bc; + end process; -- **************************************************** - + header_fifo_din <= header_word_latch; + header_fifo_we <= '0' when readout_bypass else + '1' when ((word_counter = header_pcklen_latch_m1) or zero_pck) and sending_event else '0'; + + data_fifo_din <= data_word; + data_fifo_we <= '0' when readout_bypass else + '1' when (is_data = '1' and is_header = '0') and (word_counter < header_pcklen_latch) and sending_event else '0'; end Behavioral; diff --git a/firmware/common/gbt-readout/hdl/DataConverter_TCM.vhd b/firmware/common/gbt-readout/hdl/DataConverter_TCM.vhd index 67d7dde..a62a703 100644 --- a/firmware/common/gbt-readout/hdl/DataConverter_TCM.vhd +++ b/firmware/common/gbt-readout/hdl/DataConverter_TCM.vhd @@ -2,272 +2,291 @@ -- Company: INR RAS -- Engineer: Finogeev D. A. dmitry-finogeev@yandex.ru -- --- Create Date: 07/11/2017 --- Design Name: --- Module Name: --- Project Name: --- Target Devices: --- Tool versions: --- Description: +-- Create Date: 2017 +-- Description: convert data from FEE to RDH format +-- Comparison to PM converter, additional FIFO 160 to 80 to convert TCM packages to PM format -- --- Dependencies: --- --- Revision: --- Revision --- Additional Comments: --- - --- TO DO: --- check packets from PM without space --- FIFO full --- FIFO reset --- 320 CLock - +-- Revision: 07/2021 ---------------------------------------------------------------------------------- library IEEE; -use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_1164.all; use ieee.numeric_std.all; -use ieee.std_logic_unsigned.all ; +use ieee.std_logic_unsigned.all; use work.fit_gbt_common_package.all; use work.fit_gbt_board_package.all; entity DataConverter is - Port ( - FSM_Clocks_I : in FSM_Clocks_type; - - FIT_GBT_status_I : in FIT_GBT_status_type; - Control_register_I : in CONTROL_REGISTER_type; - - Board_data_I : in board_data_type; - - FIFO_is_space_for_packet_I : in STD_LOGIC; - - FIFO_WE_O : out STD_LOGIC; - FIFO_data_word_O : out std_logic_vector(fifo_data_bitdepth-1 downto 0); --- FIFO_data_word_O : out std_logic_vector(160-1 downto 0); - - hits_rd_counter_converter_O : out hit_rd_counter_type - ); + port ( + FSM_Clocks_I : in rdclocks_t; + + Status_register_I : in readout_status_t; + Control_register_I : in readout_control_t; + + Board_data_I : in board_data_type; + + header_fifo_data_o : out std_logic_vector(GBT_data_word_bitdepth-1 downto 0); + data_fifo_data_o : out std_logic_vector(GBT_data_word_bitdepth-1 downto 0); + header_fifo_rden_i : in std_logic; + data_fifo_rden_i : in std_logic; + header_fifo_empty_o : out std_logic; + data_fifo_empty_o : out std_logic; + no_data_o : out boolean; + + drop_ounter_o : out std_logic_vector(15 downto 0); + fifo_cnt_max_o : out std_logic_vector(15 downto 0); + + raw_data_o : out std_logic_vector(GBT_data_word_bitdepth-1 downto 0); + raw_isdata_o : out std_logic; + data_bcid_o : out std_logic_vector(BC_id_bitdepth-1 downto 0); + data_bcen_o : out std_logic; + + -- errors indicate unexpected FSM state, should be reset and debugged + -- 0 - data_fifo is not empty while start of run + -- 1 - header_fifo is not empty while start of run + -- 2 - tcm_data_fifo is full + pm_data_shreg_o : out std_logic_vector(errrep_pmdat_len*80-1 downto 0); -- not used + rawdatfifo_wr_rate_o : out std_logic_vector(11 downto 0); + rawdatfifo_rd_rate_o : out std_logic_vector(11 downto 0); + errors_o : out std_logic_vector(4 downto 0) + ); end DataConverter; architecture Behavioral of DataConverter is - constant board_data_void_const : board_data_type := - ( - is_header => '0', - is_data => '0', - data_word => (others => '0') - ); - - -- type FSM_STATE_T is (s0_wait_header, s1_sending_data); - -- signal FSM_STATE, FSM_STATE_NEXT : FSM_STATE_T; - - signal data_fromfifo : std_logic_vector(fifo_data_bitdepth-1 downto 0); - signal is_header_from_fifo : std_logic; - signal is_data_from_fifo : std_logic; - signal raw_data_fifo_isempty : std_logic; - - - - signal Board_data_sysclkff, Board_data_sysclkff_next : Board_data_type; - signal FIFO_is_space_for_packet_ff, FIFO_is_space_for_packet_ff_next: std_logic; - --- signal word_counter_ff, word_counter_ff_next : std_logic_vector(n_pckt_wrds_bitdepth-1 downto 0); - constant counter_zero : std_logic_vector(n_pckt_wrds_bitdepth-1 downto 0) := (others => '0'); - signal packet_lenght_fromheader : std_logic_vector(n_pckt_wrds_bitdepth-1 downto 0); - --packet_lenght_ff, packet_lenght_ff_next : std_logic_vector(n_pckt_wrds_bitdepth-1 downto 0); - - signal header_orbit : std_logic_vector(Orbit_id_bitdepth-1 downto 0); - signal header_bc : std_logic_vector(BC_id_bitdepth-1 downto 0); - signal header_word, data_word : std_logic_vector(fifo_data_bitdepth-1 downto 0); - - signal sending_event, sending_event_next : std_logic; - signal FIFO_WE_ff, FIFO_WE_ff_next : STD_LOGIC; - signal FIFO_data_word_ff, FIFO_data_word_ff_next : std_logic_vector(fifo_data_bitdepth-1 downto 0); - - signal reset_drop_counters : std_logic; - signal is_dropping_event : std_logic;--, is_dropping_event_next : std_logic; - signal dropped_events, dropped_events_next : std_logic_vector(31 downto 0); - signal first_dropped_orbit, first_dropped_orbit_next : std_logic_vector(Orbit_id_bitdepth-1 downto 0); - signal first_dropped_bc, first_dropped_bc_next : std_logic_vector(BC_id_bitdepth-1 downto 0); - signal last_dropped_orbit, last_dropped_orbit_next : std_logic_vector(Orbit_id_bitdepth-1 downto 0); - signal last_dropped_bc, last_dropped_bc_next : std_logic_vector(BC_id_bitdepth-1 downto 0); - - - - attribute keep : string; - attribute keep of Board_data_sysclkff : signal is "true"; - attribute keep of reset_drop_counters : signal is "true"; - attribute keep of dropped_events : signal is "true"; - attribute keep of first_dropped_orbit : signal is "true"; - attribute keep of first_dropped_bc : signal is "true"; - attribute keep of last_dropped_orbit: signal is "true"; - attribute keep of last_dropped_bc: signal is "true"; - - + constant board_data_void_const : board_data_type := + ( + is_header => '0', + is_data => '0', + data_word => (others => '0') + ); + + signal board_data : board_data_type; + signal header_pcklen, header_pcklen_ff, header_pcklen_latch, header_pcklen_latch_m1 : std_logic_vector(n_pckt_wrds_bitdepth-1 downto 0); + signal header_orbit : std_logic_vector(Orbit_id_bitdepth-1 downto 0); + signal header_bc : std_logic_vector(BC_id_bitdepth-1 downto 0); + signal header_word, header_word_latch, data_word : std_logic_vector(GBT_data_word_bitdepth-1 downto 0); + signal is_header, is_data : std_logic; + + signal data_bcid : std_logic_vector(BC_id_bitdepth-1 downto 0); + signal data_bcen : std_logic; + + signal readout_bypass : boolean; + signal data_enabled, data_enabled_sclk, start_of_run : boolean; + signal reset_drop_counters : std_logic; + signal drop_counter : std_logic_vector(15 downto 0); + + signal data_rawfifo_cnt, rawfifo_cnt_max : std_logic_vector(12 downto 0); + signal header_rawfifo_full, data_rawfifo_full, rawfifo_full : std_logic; + + + signal sending_event, sending_event_dc : boolean; + signal word_counter : std_logic_vector(n_pckt_wrds_bitdepth-1 downto 0); + + signal tcm_data_fifo_empty, tcm_data_fifo_full, tcm_data_fifo_rden : std_logic; + signal tcm_data_fifo_dout : std_logic_vector(GBT_data_word_bitdepth-1 downto 0); + + signal header_fifo_din, data_fifo_din : std_logic_vector(GBT_data_word_bitdepth-1 downto 0); + signal header_fifo_we, data_fifo_we : std_logic; + signal header_fifo_empty, header_fifo_empty_dc, data_fifo_empty, data_fifo_empty_dc : std_logic; + + signal errors : std_logic_vector(2 downto 0); + + + -- attribute mark_debug : string; + -- attribute mark_debug of reset_drop_counters : signal is "true"; + -- attribute mark_debug of header_fifo_din : signal is "true"; + -- attribute mark_debug of data_fifo_din : signal is "true"; + -- attribute mark_debug of header_fifo_we : signal is "true"; + -- attribute mark_debug of data_fifo_we : signal is "true"; + -- attribute mark_debug of word_counter : signal is "true"; + -- attribute mark_debug of sending_event : signal is "true"; + -- attribute mark_debug of header_word : signal is "true"; + -- attribute mark_debug of data_word : signal is "true"; + -- attribute mark_debug of is_data : signal is "true"; + -- attribute mark_debug of is_header : signal is "true"; + -- attribute mark_debug of header_pcklen_ff : signal is "true"; + -- attribute mark_debug of header_word_latch : signal is "true"; + -- attribute mark_debug of header_pcklen_latch : signal is "true"; + begin + header_fifo_empty_o <= header_fifo_empty; + data_fifo_empty_o <= data_fifo_empty; + header_pcklen <= func_PMHEADER_n_dwords(tcm_data_fifo_dout); + header_orbit <= func_PMHEADER_getORBIT(tcm_data_fifo_dout); + header_bc <= func_PMHEADER_getBC(tcm_data_fifo_dout); + raw_data_o <= tcm_data_fifo_dout; + raw_isdata_o <= not tcm_data_fifo_empty; --- Wiring ******************************************** - FIFO_WE_O <= FIFO_WE_ff; - FIFO_data_word_O <= FIFO_data_word_ff; + pm_data_shreg_o <= (others => '0'); + rawdatfifo_wr_rate_o <= (others => '0'); + rawdatfifo_rd_rate_o <= (others => '0'); --- FIFO_WE_O <= Board_data_sysclkff.is_data; --- FIFO_data_word_O <= Board_data_sysclkff.data_word; - - - hits_rd_counter_converter_O.hits_send_porbit <= (others => '0'); - hits_rd_counter_converter_O.hits_skipped <= dropped_events; - hits_rd_counter_converter_O.first_orbit_hdrop <= first_dropped_orbit; - hits_rd_counter_converter_O.first_bc_hdrop <= first_dropped_bc; - hits_rd_counter_converter_O.last_orbit_hdrop <= last_dropped_orbit; - hits_rd_counter_converter_O.last_bc_hdrop <= last_dropped_bc; --- *************************************************** +-- tcm_data_160to80bit_fifo ============================================= + tcm_data_160to80bit_fifo_comp : entity work.tcm_data_160to80bit_fifo + port map( + clk => FSM_Clocks_I.System_Clk, + srst => FSM_Clocks_I.Reset_sclk, + WR_EN => board_data.is_data, + RD_EN => tcm_data_fifo_rden, + DIN => board_data.data_word, + DOUT => tcm_data_fifo_dout, + FULL => tcm_data_fifo_full, + EMPTY => tcm_data_fifo_empty, + rd_data_count => open + ); + tcm_data_fifo_rden <= not tcm_data_fifo_empty; +-- =========================================================== +---- Raw_header_fifo ============================================= + raw_header_fifo_comp : entity work.raw_data_fifo + port map( + clk => FSM_Clocks_I.System_Clk, + srst => FSM_Clocks_I.Reset_sclk, + WR_EN => header_fifo_we, + RD_EN => header_fifo_rden_i, + DIN => header_fifo_din, + DOUT => header_fifo_data_o, + data_count => open, + prog_full => header_rawfifo_full, + FULL => open, + EMPTY => header_fifo_empty + ); +---- =========================================================== + + +---- Raw_data_fifo ============================================= + raw_data_fifo_comp : entity work.raw_data_fifo + port map( + clk => FSM_Clocks_I.System_Clk, + srst => FSM_Clocks_I.Reset_sclk, + WR_EN => data_fifo_we, + RD_EN => data_fifo_rden_i, + DIN => data_fifo_din, + DOUT => data_fifo_data_o, + data_count => data_rawfifo_cnt, + prog_full => data_rawfifo_full, + FULL => open, + EMPTY => data_fifo_empty + ); +---- =========================================================== --- tcm_data_160to80bit_fifo ============================================= -tcm_data_160to80bit_fifo_comp : entity work.tcm_data_160to80bit_fifo -port map( - clk => FSM_Clocks_I.System_Clk, - srst => FSM_Clocks_I.Reset, - WR_EN => Board_data_I.is_data, - RD_EN => not raw_data_fifo_isempty, - DIN => Board_data_I.data_word, - DOUT => data_fromfifo, - FULL => open, - EMPTY => raw_data_fifo_isempty, - rd_data_count => open - ); - -is_header_from_fifo <= '1' when (data_fromfifo(79 downto 76) = "1111") else '0'; -is_data_from_fifo <= not raw_data_fifo_isempty; + rawfifo_full <= header_rawfifo_full or data_rawfifo_full; --- =========================================================== + process (FSM_Clocks_I.Data_Clk) + begin + if(rising_edge(FSM_Clocks_I.Data_Clk))then + header_fifo_empty_dc <= header_fifo_empty; + data_fifo_empty_dc <= data_fifo_empty; + sending_event_dc <= sending_event; --- Header format ************************************* - packet_lenght_fromheader <= func_PMHEADER_n_dwords( data_fromfifo ); - header_orbit <=func_PMHEADER_getORBIT(data_fromfifo); - header_bc <= func_PMHEADER_getBC(data_fromfifo); - header_word <= func_FITDATAHD_get_header(packet_lenght_fromheader, header_orbit, header_bc, FIT_GBT_status_I.rx_phase, FIT_GBT_status_I.GBT_status.Rx_Phase_error, '1'); - data_word <= data_fromfifo; --- *************************************************** - - - - --- Data ff data clk *********************************** - PROCESS (FSM_Clocks_I.System_Clk) - BEGIN - IF(FSM_Clocks_I.System_Clk'EVENT and FSM_Clocks_I.System_Clk = '1') THEN - IF(FSM_Clocks_I.Reset = '1') THEN - Board_data_sysclkff <= board_data_void_const; - sending_event <= '0'; - FIFO_is_space_for_packet_ff <= '0'; - - dropped_events <= (others => '0'); - first_dropped_orbit <= (others => '0'); - first_dropped_bc <= (others => '0'); - last_dropped_orbit <= (others => '0'); - last_dropped_bc <= (others => '0'); - FIFO_WE_ff <= '0'; - FIFO_data_word_ff <= (others => '0'); - - --is_data_from_fifo <= '0'; - - ELSE - Board_data_sysclkff <= Board_data_sysclkff_next; - sending_event <= sending_event_next; - FIFO_is_space_for_packet_ff <= FIFO_is_space_for_packet_ff_next; - FIFO_WE_ff <= FIFO_WE_ff_next; - --if (is_data_from_fifo = '1') and (sending_event = '1') then FIFO_WE_ff <= '1'; else FIFO_WE_ff <= '0'; end if; - FIFO_data_word_ff <= FIFO_data_word_ff_next; - - dropped_events <= dropped_events_next; - first_dropped_orbit <= first_dropped_orbit_next; - first_dropped_bc <= first_dropped_bc_next; - last_dropped_orbit <= last_dropped_orbit_next; - last_dropped_bc <= last_dropped_bc_next; - - --is_data_from_fifo <= not raw_data_fifo_isempty; - END IF; - - - END IF; - - - END PROCESS; --- **************************************************** + data_enabled <= Status_register_I.data_enable = '1'; + drop_ounter_o <= drop_counter; + fifo_cnt_max_o <= "000"&rawfifo_cnt_max; + errors_o <= "00"&errors; + no_data_o <= header_fifo_empty_dc = '1' and data_fifo_empty_dc = '1' and not sending_event_dc and not data_enabled; + end if; + end process; + + +-- sys ff data clk *********************************** + process (FSM_Clocks_I.System_Clk) + begin + if(rising_edge(FSM_Clocks_I.System_Clk)) then + + board_data <= Board_data_I; + reset_drop_counters <= Control_register_I.reset_data_counters; + start_of_run <= Status_register_I.Start_run = '1'; + readout_bypass <= Control_register_I.readout_bypass = '1'; + + header_word <= func_FITDATAHD_get_header(header_pcklen, header_orbit, header_bc, Status_register_I.rx_phase, Status_register_I.Rx_Phase_error, '1'); + data_word <= tcm_data_fifo_dout; + is_data <= not tcm_data_fifo_empty; + if tcm_data_fifo_dout(79 downto 76) = x"f" then is_header <= '1'; else is_header <= '0'; end if; + header_pcklen_ff <= header_pcklen; + + data_enabled_sclk <= data_enabled; + + if(FSM_Clocks_I.Reset_sclk = '1') then + + sending_event <= false; + drop_counter <= (others => '0'); + rawfifo_cnt_max <= (others => '0'); + word_counter <= (others => '1'); + errors <= (others => '0'); + + else + -- bcid output for BC indicator + data_bcid <= header_bc; + if tcm_data_fifo_dout(79 downto 76) = x"f" then data_bcen <= '1'; else data_bcen <= '0'; end if; + -- is muted for laser data + if tcm_data_fifo_dout(5) = '0' and data_bcen = '1' then + data_bcen_o <= data_bcen; + data_bcid_o <= data_bcid; + else + data_bcen_o <= '0'; + data_bcid_o <= (others => '0'); + end if; --- FSM ************************************************ ---Board_data_sysclkff_next <= Board_data_I; -FIFO_is_space_for_packet_ff_next <= FIFO_is_space_for_packet_I; - -reset_drop_counters <= Control_register_I.reset_drophit_counter; --- reset_drop_counters <= '1' WHEN (FSM_Clocks_I.Reset = '1') ELSE - -- '1' WHEN (FIT_GBT_status_I.Start_run = '1') ELSE - -- '0'; - - -sending_event_next <= '0' WHEN (FSM_Clocks_I.Reset = '1') ELSE - '0' WHEN (is_header_from_fifo = '1') and (FIFO_is_space_for_packet_ff = '0') ELSE --- '1' WHEN (is_header_from_fifo = '1') and (FIT_GBT_status_I.Readout_Mode = mode_IDLE) and (Control_register_I.readout_bypass='1') ELSE - '1' WHEN (is_header_from_fifo = '1') and (Control_register_I.readout_bypass='1') ELSE - '0' WHEN (is_header_from_fifo = '1') and (FIT_GBT_status_I.Readout_Mode = mode_IDLE) ELSE - '1' WHEN (is_header_from_fifo = '1') ELSE - sending_event; - -FIFO_data_word_ff_next <= (others => '0') WHEN (FSM_Clocks_I.Reset = '1') ELSE - header_word WHEN ((sending_event = '1')or(sending_event_next = '1')) and (is_header_from_fifo = '1') ELSE - data_word WHEN ((sending_event = '1')or(sending_event_next = '1')) and (is_data_from_fifo = '1') ELSE - (others => '0'); - -FIFO_WE_ff_next <= '0' WHEN (FSM_Clocks_I.Reset = '1') ELSE --- '1' WHEN (is_data_from_fifo = '1') and ((sending_event = '1')or(sending_event_next = '1')) ELSE - '1' WHEN (is_data_from_fifo = '1') and (sending_event_next = '1') ELSE - '0'; - --- Event counter ------------------------------------ - -is_dropping_event <= '0' WHEN (FSM_Clocks_I.Reset = '1') ELSE - '0' WHEN (FIT_GBT_status_I.Readout_Mode = mode_IDLE) ELSE - '1' WHEN (is_header_from_fifo = '1') and (FIFO_is_space_for_packet_ff = '0') ELSE - '0'; - -dropped_events_next <= (others => '0') WHEN (FSM_Clocks_I.Reset = '1') ELSE - (others => '0') WHEN (reset_drop_counters = '1') ELSE - dropped_events + 1 WHEN (is_dropping_event = '1') ELSE - dropped_events; - -last_dropped_orbit_next <= (others => '0') WHEN (FSM_Clocks_I.Reset = '1') ELSE - (others => '0') WHEN (reset_drop_counters = '1') ELSE - header_orbit WHEN (is_dropping_event = '1') ELSE - last_dropped_orbit; - -last_dropped_bc_next <= (others => '0') WHEN (FSM_Clocks_I.Reset = '1') ELSE - (others => '0') WHEN (reset_drop_counters = '1') ELSE - header_bc WHEN (is_dropping_event = '1') ELSE - last_dropped_bc; - -first_dropped_orbit_next <= (others => '0') WHEN (FSM_Clocks_I.Reset = '1') ELSE - (others => '0') WHEN (reset_drop_counters = '1') ELSE - header_orbit WHEN (is_dropping_event = '1') and (last_dropped_orbit = ORBIT_const_void) ELSE - first_dropped_orbit; - -first_dropped_bc_next <= (others => '0') WHEN (FSM_Clocks_I.Reset = '1') ELSE - (others => '0') WHEN (reset_drop_counters = '1') ELSE - header_bc WHEN (is_dropping_event = '1') and (last_dropped_orbit = ORBIT_const_void) ELSE - first_dropped_bc; + + if is_header = '1' then + + header_word_latch <= header_word; + header_pcklen_latch <= header_pcklen_ff; + header_pcklen_latch_m1 <= header_pcklen_ff-1; + word_counter <= (others => '0'); + + sending_event <= (rawfifo_full = '0') and data_enabled_sclk; + + if (rawfifo_full = '1') and data_enabled_sclk and drop_counter /= x"ffff" then + drop_counter <= drop_counter + 1; + end if; + + elsif is_data = '1' then + + word_counter <= word_counter + 1; + + end if; + + -- turning off sending_event while idle without data for clear error 'ready for run' + if not data_enabled_sclk and header_fifo_empty = '1' and data_fifo_empty = '1' and is_data = '0' then + sending_event <= false; end if; + + + if rawfifo_cnt_max < data_rawfifo_cnt then rawfifo_cnt_max <= data_rawfifo_cnt; end if; + + if reset_drop_counters = '1' then + drop_counter <= (others => '0'); + rawfifo_cnt_max <= (others => '0'); + end if; + + if start_of_run then errors(1 downto 0) <= (not header_fifo_empty) & (not data_fifo_empty); end if; + if tcm_data_fifo_full = '1' and data_enabled_sclk then errors(2) <= '1'; end if; + + + end if; + + end if; + + + end process; -- **************************************************** - + header_fifo_din <= header_word_latch; + header_fifo_we <= '0' when readout_bypass else + '1' when word_counter = header_pcklen_latch_m1 and sending_event else '0'; + + data_fifo_din <= data_word; + data_fifo_we <= '0' when readout_bypass else + '1' when is_data = '1' and is_header = '0' and sending_event else '0'; end Behavioral; diff --git a/firmware/common/gbt-readout/hdl/Data_Packager.vhd b/firmware/common/gbt-readout/hdl/Data_Packager.vhd deleted file mode 100644 index a05ef06..0000000 --- a/firmware/common/gbt-readout/hdl/Data_Packager.vhd +++ /dev/null @@ -1,293 +0,0 @@ ----------------------------------------------------------------------------------- --- Company: INR RAS --- Engineer: Finogeev D.A. dmitry-finogeev@yandex.ru --- --- Create Date: 12:03:02 01/09/2017 --- Design Name: FIT GBT --- Module Name: Data_Packager - Behavioral --- Project Name: --- Target Devices: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use work.fit_gbt_common_package.all; -use work.fit_gbt_board_package.all; - -use ieee.numeric_std.all; - - -entity Data_Packager is - Port ( - FSM_Clocks_I : in FSM_Clocks_type; - - FIT_GBT_status_I : in FIT_GBT_status_type; - Control_register_I : in CONTROL_REGISTER_type; - - Board_data_I : in board_data_type; - - fifo_status_O : out FIFO_STATUS_type; - hits_rd_counter_converter_O : out hit_rd_counter_type; - hits_rd_counter_selector_O : out hit_rd_counter_type; - - TX_Data_O : out std_logic_vector(GBT_data_word_bitdepth-1 downto 0); - TX_IsData_O : out STD_LOGIC --- GPIO_O : out std_logic_vector(15 downto 0) - - ); -end Data_Packager; - -architecture Behavioral of Data_Packager is - - signal data_from_cru_constructor : std_logic_vector(GBT_data_word_bitdepth-1 downto 0); - signal is_data_from_cru_constructor : STD_LOGIC; - - signal raw_data_fifo_words_count_rd : std_logic_vector(rawfifo_count_bitdepth-1 downto 0); - signal raw_data_fifo_words_count_wr : std_logic_vector(rawfifo_count_bitdepth-1 downto 0); - signal raw_data_fifo_data_tofifo : std_logic_vector(fifo_data_bitdepth-1 downto 0); - signal raw_data_fifo_data_fromfifo : std_logic_vector(fifo_data_bitdepth-1 downto 0); - signal raw_data_fifo_isempty : std_logic; - signal raw_data_fifo_wren : std_logic; - signal raw_data_fifo_rden_selector : std_logic; - signal raw_data_fifo_rden : std_logic; - signal raw_data_fifo_space_is_for_packet : STD_LOGIC; - signal raw_data_fifo_reset : std_logic; - signal raw_data_fifo_rden_txgenerator : std_logic; - signal readout_bypass_s : std_logic; - - - signal slct_data_fifo_words_count_wr : std_logic_vector(slctfifo_count_bitdepth-1 downto 0); - signal slct_data_fifo_data_tofifo : std_logic_vector(fifo_data_bitdepth-1 downto 0); - signal slct_data_fifo_data_fromfifo : std_logic_vector(fifo_data_bitdepth-1 downto 0); - signal slct_data_fifo_isempty : std_logic; - signal slct_data_fifo_is_space_for_packet : std_logic; - signal slct_data_fifo_wren : std_logic; - signal slct_data_fifo_rden : std_logic; - signal slct_data_fifo_space_is_for_packet : STD_LOGIC; - signal slct_data_fifo_reset : std_logic; - - signal trg_fifo_count : std_logic_vector(trgfifo_count_bitdepth-1 downto 0); - signal cntr_fifo_count : std_logic_vector(cntpckfifo_count_bitdepth-1 downto 0); - - signal cntpck_fifo_data_fromfifo : std_logic_vector(cntpckfifo_data_bitdepth-1 downto 0); - signal cntpck_fifo_isempty : std_logic; - signal cntpck_fifo_rden : std_logic; - - - attribute keep : string; - attribute keep of raw_data_fifo_data_fromfifo : signal is "true"; - attribute keep of raw_data_fifo_rden : signal is "true"; - attribute keep of slct_data_fifo_data_fromfifo : signal is "true"; - attribute keep of slct_data_fifo_rden : signal is "true"; - attribute keep of raw_data_fifo_data_tofifo : signal is "true"; - attribute keep of slct_data_fifo_data_tofifo : signal is "true"; - attribute keep of raw_data_fifo_isempty : signal is "true"; - attribute keep of slct_data_fifo_isempty : signal is "true"; - - - - -begin --- --Wiring ===================================================== --- TX_Data_O(83 downto 0) <= (others=>'0'); -- test generation ---raw_data_fifo_space_is_for_packet <= '1' when (unsigned(raw_data_fifo_words_count_wr) <= 150-total_data_words-1) else -raw_data_fifo_space_is_for_packet <= '1' when (unsigned(raw_data_fifo_words_count_wr) <= rawfifo_depth-total_data_words-1) else - '0'; - ---slct_data_fifo_is_space_for_packet <= '1' when (unsigned(slct_data_fifo_words_count_wr) <= 150-total_data_words-1) else -slct_data_fifo_is_space_for_packet <= '1' when (unsigned(slct_data_fifo_words_count_wr) <= slctfifo_depth-total_data_words-1) else - '0'; - -raw_data_fifo_reset <= FSM_Clocks_I.Reset; -slct_data_fifo_reset <= FSM_Clocks_I.Reset; - -fifo_status_O.raw_fifo_count <= raw_data_fifo_words_count_wr; -fifo_status_O.slct_fifo_count <= slct_data_fifo_words_count_wr; -fifo_status_O.trg_fifo_count <= trg_fifo_count; -fifo_status_O.cntr_fifo_count <= cntr_fifo_count; -fifo_status_O.ftmipbus_fifo_count <= (others => '0'); - - -process(FSM_Clocks_I.System_Clk) -begin -if (FSM_Clocks_I.System_Clk'event) and (FSM_Clocks_I.System_Clk='1') then - readout_bypass_s <=Control_register_I.readout_bypass; -end if; -end process; - --- -- =========================================================== - - - --- Data Converter =============================================== --- PM data already formed --- DataConverter_gen: if (Board_DataConversion_type = one_word) or (Board_DataConversion_type = one_word) generate - -DataConverter_comp: entity work.DataConverter - port map( - FSM_Clocks_I => FSM_Clocks_I, - - FIT_GBT_status_I => FIT_GBT_status_I, - Control_register_I => Control_register_I, - - Board_data_I => Board_data_I, - - FIFO_is_space_for_packet_I => raw_data_fifo_space_is_for_packet, - - FIFO_WE_O => raw_data_fifo_wren, - FIFO_data_word_O => raw_data_fifo_data_tofifo, - - hits_rd_counter_converter_O => hits_rd_counter_converter_O - - ); - --- end generate; --- =========================================================== - - - - - --- Raw_data_fifo ============================================= ---raw_data_fifo_comp : entity work.raw_data_fifo ---port map( --- wr_clk => FSM_Clocks_I.System_Clk, --- rd_clk => FSM_Clocks_I.System_Clk, --- wr_data_count => raw_data_fifo_words_count_wr, --- rd_data_count => raw_data_fifo_words_count_rd, --- rst => raw_data_fifo_reset, --- WR_EN => raw_data_fifo_wren, --- RD_EN => raw_data_fifo_rden, --- DIN => raw_data_fifo_data_tofifo, --- DOUT => raw_data_fifo_data_fromfifo, --- FULL => open, --- EMPTY => raw_data_fifo_isempty --- ); ---GPIO_O(15) <= raw_data_fifo_wren; ---GPIO_O(14) <= raw_data_fifo_rden; ---GPIO_O(4 downto 0) <= raw_data_fifo_words_count_rd(4 downto 0); - --- =========================================================== - ----- Raw_data_fifo ============================================= -raw_data_fifo_comp : entity work.raw_data_fifo -port map( - clk => FSM_Clocks_I.System_Clk, - data_count => raw_data_fifo_words_count_wr, - srst => raw_data_fifo_reset, - WR_EN => raw_data_fifo_wren, - RD_EN => raw_data_fifo_rden, - DIN => raw_data_fifo_data_tofifo, - DOUT => raw_data_fifo_data_fromfifo, - FULL => open, - EMPTY => raw_data_fifo_isempty - ); -raw_data_fifo_words_count_rd <= raw_data_fifo_words_count_wr; - -raw_data_fifo_rden <= raw_data_fifo_rden_txgenerator WHEN (readout_bypass_s = '1') - ELSE raw_data_fifo_rden_selector; - ----- =========================================================== - - - - --- Slc_data_fifo ============================================= -slct_data_fifo_comp : entity work.slct_data_fifo -port map( - wr_clk => FSM_Clocks_I.System_Clk, - rd_clk => FSM_Clocks_I.Data_Clk, - wr_data_count => slct_data_fifo_words_count_wr, - rst => slct_data_fifo_reset, - WR_EN => slct_data_fifo_wren, - RD_EN => slct_data_fifo_rden, - DIN => slct_data_fifo_data_tofifo, - DOUT => slct_data_fifo_data_fromfifo, - FULL => open, - EMPTY => slct_data_fifo_isempty - ); --- =========================================================== - --- Event Selector ====================================== -Event_Selector_comp : entity work.Event_Selector -port map ( - FSM_Clocks_I => FSM_Clocks_I, - - FIT_GBT_status_I => FIT_GBT_status_I, - Control_register_I => Control_register_I, - - RAWFIFO_data_word_I => raw_data_fifo_data_fromfifo, - RAWFIFO_Is_Empty_I => raw_data_fifo_isempty, - RAWFIFO_data_count_I => raw_data_fifo_words_count_rd, - RAWFIFO_RE_O => raw_data_fifo_rden_selector, - RAWFIFO_RESET_O => raw_data_fifo_reset, - - SLCTFIFO_data_word_O => slct_data_fifo_data_tofifo, - SLCTFIFO_Is_spacefpacket_I => slct_data_fifo_is_space_for_packet, - SLCTFIFO_WE_O => slct_data_fifo_wren, - SLCTFIFO_RESET_O => slct_data_fifo_reset, - - CNTPTFIFO_data_word_O => cntpck_fifo_data_fromfifo, - CNTPFIFO_Is_Empty_O => cntpck_fifo_isempty, - CNTPFIFO_count_O => cntr_fifo_count, - CNTPFIFO_RE_I => cntpck_fifo_rden, - - TRGFIFO_count_O => trg_fifo_count, - - hits_rd_counter_selector_O => hits_rd_counter_selector_O - ); --- =========================================================== - --- CRU Packet Constructer ====================================== -CRU_packet_Builder_comp : entity work.CRU_packet_Builder -port map ( - FSM_Clocks_I => FSM_Clocks_I, - - FIT_GBT_status_I => FIT_GBT_status_I, - Control_register_I => Control_register_I, - - SLCTFIFO_data_word_I => slct_data_fifo_data_fromfifo, - SLCTFIFO_Is_Empty_I => slct_data_fifo_isempty, - SLCTFIFO_RE_O => slct_data_fifo_rden, - - CNTPTFIFO_data_word_I => cntpck_fifo_data_fromfifo, - CNTPFIFO_Is_Empty_I => cntpck_fifo_isempty, - CNTPFIFO_RE_O => cntpck_fifo_rden, - - Is_Data_O => is_data_from_cru_constructor, - Data_O => data_from_cru_constructor - ); --- =========================================================== - - - --- TX Data Gen =============================================== -TX_Data_Gen_comp : entity work.TX_Data_Gen -port map( - FSM_Clocks_I => FSM_Clocks_I, - - Control_register_I => Control_register_I, - FIT_GBT_status_I => FIT_GBT_status_I, - - TX_IsData_I => is_data_from_cru_constructor, - TX_Data_I => data_from_cru_constructor, - - RAWFIFO_data_word_I => raw_data_fifo_data_fromfifo, - RAWFIFO_Is_Empty_I => raw_data_fifo_isempty, - RAWFIFO_RE_O => raw_data_fifo_rden_txgenerator, - - TX_IsData_O => TX_IsData_O, - TX_Data_O => TX_Data_O - ); --- =========================================================== - -end Behavioral; - diff --git a/firmware/common/gbt-readout/hdl/Data_Packager_tcm_temp.vhd b/firmware/common/gbt-readout/hdl/Data_Packager_tcm_temp.vhd deleted file mode 100644 index 60b3314..0000000 --- a/firmware/common/gbt-readout/hdl/Data_Packager_tcm_temp.vhd +++ /dev/null @@ -1,277 +0,0 @@ ----------------------------------------------------------------------------------- --- Company: INR RAS --- Engineer: Finogeev D.A. dmitry-finogeev@yandex.ru --- --- Create Date: 12:03:02 01/09/2017 --- Design Name: FIT GBT --- Module Name: Data_Packager - Behavioral --- Project Name: --- Target Devices: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use work.fit_gbt_common_package.all; -use work.fit_gbt_board_package.all; - -use ieee.numeric_std.all; - - -entity Data_Packager is - Port ( - FSM_Clocks_I : in FSM_Clocks_type; - - FIT_GBT_status_I : in FIT_GBT_status_type; - Control_register_I : in CONTROL_REGISTER_type; - - Board_data_I : in board_data_type; - - fifo_status_O : out FIFO_STATUS_type; - hits_rd_counter_converter_O : out hit_rd_counter_type; - hits_rd_counter_selector_O : out hit_rd_counter_type; - - TX_Data_O : out std_logic_vector(GBT_data_word_bitdepth-1 downto 0); - TX_IsData_O : out STD_LOGIC; - GPIO_O : out std_logic_vector(15 downto 0) - - ); -end Data_Packager; - -architecture Behavioral of Data_Packager is - - signal data_from_cru_constructor : std_logic_vector(GBT_data_word_bitdepth-1 downto 0); - signal is_data_from_cru_constructor : STD_LOGIC; - - signal raw_data_fifo_words_count_rd : std_logic_vector(rawfifo_count_bitdepth-1 downto 0); - signal raw_data_fifo_words_count_wr : std_logic_vector(rawfifo_count_bitdepth-1 downto 0); - signal raw_data_fifo_data_tofifo : std_logic_vector(160-1 downto 0); - signal raw_data_fifo_data_fromfifo : std_logic_vector(fifo_data_bitdepth-1 downto 0); - signal raw_data_fifo_isempty : std_logic; - signal raw_data_fifo_wren : std_logic; - signal raw_data_fifo_rden, readout_bypass_s : std_logic; - signal raw_data_fifo_rden_selector : std_logic; - signal raw_data_fifo_rden_txgenerator : std_logic; - signal raw_data_fifo_space_is_for_packet : STD_LOGIC; - signal raw_data_fifo_reset : std_logic; - - signal slct_data_fifo_words_count_wr : std_logic_vector(slctfifo_count_bitdepth-1 downto 0); - signal slct_data_fifo_data_tofifo : std_logic_vector(fifo_data_bitdepth-1 downto 0); - signal slct_data_fifo_data_fromfifo : std_logic_vector(fifo_data_bitdepth-1 downto 0); - signal slct_data_fifo_isempty : std_logic; - signal slct_data_fifo_is_space_for_packet : std_logic; - signal slct_data_fifo_wren : std_logic; - signal slct_data_fifo_rden : std_logic; - signal slct_data_fifo_space_is_for_packet : STD_LOGIC; - signal slct_data_fifo_reset : std_logic; - - signal trg_fifo_count : std_logic_vector(trgfifo_count_bitdepth-1 downto 0); - signal cntr_fifo_count : std_logic_vector(cntpckfifo_count_bitdepth-1 downto 0); - - signal cntpck_fifo_data_fromfifo : std_logic_vector(cntpckfifo_data_bitdepth-1 downto 0); - signal cntpck_fifo_isempty : std_logic; - signal cntpck_fifo_rden : std_logic; - - - attribute mark_debug : string; - attribute mark_debug of raw_data_fifo_data_fromfifo : signal is "true"; - attribute mark_debug of raw_data_fifo_rden : signal is "true"; - attribute mark_debug of raw_data_fifo_data_tofifo : signal is "true"; - attribute mark_debug of raw_data_fifo_wren : signal is "true"; - attribute mark_debug of raw_data_fifo_isempty : signal is "true"; - - attribute mark_debug of slct_data_fifo_data_fromfifo : signal is "true"; - attribute mark_debug of slct_data_fifo_rden : signal is "true"; - attribute mark_debug of slct_data_fifo_data_tofifo : signal is "true"; - attribute mark_debug of slct_data_fifo_isempty : signal is "true"; - - - - -begin --- --Wiring ===================================================== --- TX_Data_O(83 downto 0) <= (others=>'0'); -- test generation ---raw_data_fifo_space_is_for_packet <= '1' when (unsigned(raw_data_fifo_words_count_wr) <= 150-total_data_words-1) else -raw_data_fifo_space_is_for_packet <= '1' when (unsigned(raw_data_fifo_words_count_wr) <= rawfifo_depth-total_data_words-1) else - '0'; - ---slct_data_fifo_is_space_for_packet <= '1' when (unsigned(slct_data_fifo_words_count_wr) <= 150-total_data_words-1) else -slct_data_fifo_is_space_for_packet <= '1' when (unsigned(slct_data_fifo_words_count_wr) <= slctfifo_depth-total_data_words-1) else - '0'; - -process(FSM_Clocks_I.System_Clk) -begin -if (FSM_Clocks_I.System_Clk'event) and (FSM_Clocks_I.System_Clk='1') then - readout_bypass_s <=Control_register_I.readout_bypass; -end if; -end process; - -raw_data_fifo_reset <= FSM_Clocks_I.Reset; -slct_data_fifo_reset <= FSM_Clocks_I.Reset; - -fifo_status_O.raw_fifo_count <= raw_data_fifo_words_count_wr; -fifo_status_O.slct_fifo_count <= slct_data_fifo_words_count_wr; -fifo_status_O.trg_fifo_count <= trg_fifo_count; -fifo_status_O.cntr_fifo_count <= cntr_fifo_count; - --- -- =========================================================== - - - --- Data Converter =============================================== --- PM data already formed -DataConverter_gen: if (Board_DataConversion_type = one_word) or (Board_DataConversion_type = one_word) generate - -DataConverter_comp: entity work.DataConverter - port map( - FSM_Clocks_I => FSM_Clocks_I, - - FIT_GBT_status_I => FIT_GBT_status_I, - Control_register_I => Control_register_I, - - Board_data_I => Board_data_I, - - FIFO_is_space_for_packet_I => raw_data_fifo_space_is_for_packet, - - FIFO_WE_O => raw_data_fifo_wren, - FIFO_data_word_O => raw_data_fifo_data_tofifo, - - hits_rd_counter_converter_O => hits_rd_counter_converter_O - - ); - -end generate; --- =========================================================== - - - - - - --- Raw_data_fifo ============================================= -raw_data_fifo_comp : entity work.raw_data_fifo -port map( - clk => FSM_Clocks_I.System_Clk, - srst => raw_data_fifo_reset, - WR_EN => raw_data_fifo_wren, - RD_EN => raw_data_fifo_rden, - DIN => raw_data_fifo_data_tofifo, - DOUT => raw_data_fifo_data_fromfifo, - FULL => open, - EMPTY => raw_data_fifo_isempty, - rd_data_count => raw_data_fifo_words_count_wr - ); -raw_data_fifo_words_count_rd <= raw_data_fifo_words_count_wr; - -GPIO_O <= x"0000"; ---GPIO_O(15) <= raw_data_fifo_wren; ---GPIO_O(14) <= raw_data_fifo_rden; ---GPIO_O(4 downto 0) <= raw_data_fifo_words_count_rd(4 downto 0); - -raw_data_fifo_rden <= raw_data_fifo_rden_txgenerator WHEN (readout_bypass_s = '1') - ELSE raw_data_fifo_rden_selector; - - --- =========================================================== - - - - --- Slc_data_fifo ============================================= -slct_data_fifo_comp : entity work.slct_data_fifo -port map( - wr_clk => FSM_Clocks_I.System_Clk, - rd_clk => FSM_Clocks_I.Data_Clk, - wr_data_count => slct_data_fifo_words_count_wr, - rst => slct_data_fifo_reset, - WR_EN => slct_data_fifo_wren, - RD_EN => slct_data_fifo_rden, - DIN => slct_data_fifo_data_tofifo, - DOUT => slct_data_fifo_data_fromfifo, - FULL => open, - EMPTY => slct_data_fifo_isempty - ); --- =========================================================== - --- Event Selector ====================================== -Event_Selector_comp : entity work.Event_Selector -port map ( - FSM_Clocks_I => FSM_Clocks_I, - - FIT_GBT_status_I => FIT_GBT_status_I, - Control_register_I => Control_register_I, - - RAWFIFO_data_word_I => raw_data_fifo_data_fromfifo, - RAWFIFO_Is_Empty_I => raw_data_fifo_isempty, - RAWFIFO_data_count_I => raw_data_fifo_words_count_rd, - RAWFIFO_RE_O => raw_data_fifo_rden_selector, - RAWFIFO_RESET_O => open, --raw_data_fifo_reset, - - SLCTFIFO_data_word_O => slct_data_fifo_data_tofifo, - SLCTFIFO_Is_spacefpacket_I => slct_data_fifo_is_space_for_packet, - SLCTFIFO_WE_O => slct_data_fifo_wren, - SLCTFIFO_RESET_O => open, --slct_data_fifo_reset, - - CNTPTFIFO_data_word_O => cntpck_fifo_data_fromfifo, - CNTPFIFO_Is_Empty_O => cntpck_fifo_isempty, - CNTPFIFO_count_O => cntr_fifo_count, - CNTPFIFO_RE_I => cntpck_fifo_rden, - - TRGFIFO_count_O => trg_fifo_count, - - hits_rd_counter_selector_O => hits_rd_counter_selector_O - ); --- =========================================================== - --- CRU Packet Constructer ====================================== -CRU_packet_Builder_comp : entity work.CRU_packet_Builder -port map ( - FSM_Clocks_I => FSM_Clocks_I, - - FIT_GBT_status_I => FIT_GBT_status_I, - Control_register_I => Control_register_I, - - SLCTFIFO_data_word_I => slct_data_fifo_data_fromfifo, - SLCTFIFO_Is_Empty_I => slct_data_fifo_isempty, - SLCTFIFO_RE_O => slct_data_fifo_rden, - - CNTPTFIFO_data_word_I => cntpck_fifo_data_fromfifo, - CNTPFIFO_Is_Empty_I => cntpck_fifo_isempty, - CNTPFIFO_RE_O => cntpck_fifo_rden, - - Is_Data_O => is_data_from_cru_constructor, - Data_O => data_from_cru_constructor - ); --- =========================================================== - - - --- TX Data Gen =============================================== -TX_Data_Gen_comp : entity work.TX_Data_Gen -port map( - FSM_Clocks_I => FSM_Clocks_I, - - Control_register_I => Control_register_I, - FIT_GBT_status_I => FIT_GBT_status_I, - - TX_IsData_I => is_data_from_cru_constructor, - TX_Data_I => data_from_cru_constructor, - - RAWFIFO_data_word_I => raw_data_fifo_data_fromfifo, - RAWFIFO_Is_Empty_I => raw_data_fifo_isempty, - RAWFIFO_RE_O => raw_data_fifo_rden_txgenerator, - - TX_IsData_O => TX_IsData_O, - TX_Data_O => TX_Data_O - ); --- =========================================================== - -end Behavioral; - diff --git a/firmware/common/gbt-readout/hdl/Event_selector.vhd b/firmware/common/gbt-readout/hdl/Event_selector.vhd index 728dc2e..0733905 100644 --- a/firmware/common/gbt-readout/hdl/Event_selector.vhd +++ b/firmware/common/gbt-readout/hdl/Event_selector.vhd @@ -1,721 +1,512 @@ ---------------------------------------------------------------------------------- --- Company: --- Engineer: +-- Company: INR RAS +-- Engineer: Finogeev D. A. dmitry-finogeev@yandex.ru -- --- Create Date: 15:42:21 04/12/2017 --- Design Name: --- Module Name: Test_Generator - Behavioral --- Project Name: --- Target Devices: --- Tool versions: --- Description: +-- Create Date: 2017 +-- Description: Select detector data and collect it for RDH -- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- - +-- Revision: 07/2021 ---------------------------------------------------------------------------------- + library IEEE; -use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_1164.all; use ieee.numeric_std.all; -use ieee.std_logic_unsigned.all ; +use ieee.std_logic_unsigned.all; use work.fit_gbt_common_package.all; use work.fit_gbt_board_package.all; entity Event_selector is - Port ( - FSM_Clocks_I : in FSM_Clocks_type; - - FIT_GBT_status_I : in FIT_GBT_status_type; - Control_register_I : in CONTROL_REGISTER_type; - - RAWFIFO_data_word_I : in std_logic_vector(fifo_data_bitdepth-1 downto 0); - RAWFIFO_data_count_I :in std_logic_vector(rawfifo_count_bitdepth-1 downto 0); - RAWFIFO_Is_Empty_I : in STD_LOGIC; - RAWFIFO_RE_O : out STD_LOGIC; - RAWFIFO_RESET_O : out STD_LOGIC; - - SLCTFIFO_data_word_O : out std_logic_vector(fifo_data_bitdepth-1 downto 0); - SLCTFIFO_Is_spacefpacket_I : in STD_LOGIC; - SLCTFIFO_WE_O : out STD_LOGIC; - SLCTFIFO_RESET_O : out STD_LOGIC; - - CNTPTFIFO_data_word_O : out std_logic_vector(cntpckfifo_data_bitdepth-1 downto 0); - CNTPFIFO_Is_Empty_O : out STD_LOGIC; - CNTPFIFO_count_O : out std_logic_vector(cntpckfifo_count_bitdepth-1 downto 0); - CNTPFIFO_RE_I : in STD_LOGIC; - - TRGFIFO_count_O : out std_logic_vector(trgfifo_count_bitdepth-1 downto 0); - - hits_rd_counter_selector_O : out hit_rd_counter_type - - ); + port ( + FSM_Clocks_I : in rdclocks_t; + + Status_register_I : in readout_status_t; + Control_register_I : in readout_control_t; + + header_fifo_data_i : in std_logic_vector(GBT_data_word_bitdepth-1 downto 0); + data_fifo_data_i : in std_logic_vector(GBT_data_word_bitdepth-1 downto 0); + header_fifo_rden_o : out std_logic; + data_fifo_rden_o : out std_logic; + header_fifo_empty_i : in std_logic; + + -- raw data for readout bypass mode + raw_data_i : in std_logic_vector(GBT_data_word_bitdepth-1 downto 0); + raw_isdata_i : in std_logic; + + slct_fifo_dout_o : out std_logic_vector(GBT_data_word_bitdepth-1 downto 0); + slct_fifo_empty_o : out std_logic; + slct_fifo_rden_i : in std_logic; + + cntpck_fifo_dout_o : out std_logic_vector(127 downto 0); + cntpck_fifo_empty_o : out std_logic; + cntpck_fifo_rden_i : in std_logic; + + trg_fifo_empty_o : out std_logic; + + slct_fifo_cnt_o : out std_logic_vector(15 downto 0); + slct_fifo_cnt_max_o : out std_logic_vector(15 downto 0); + packets_dropped_o : out std_logic_vector(15 downto 0); + event_counter_o : out std_logic_vector(31 downto 0); + + no_data_o : out boolean; + + -- errors indicate unexpected FSM state, should be reset and debugged + -- 0 - slct_fifo is not empty when run starts + -- 1 - cntpck_fifo is not empty when run starts + -- 2 - trg_fifo is not empty when run starts + -- 3 - trg_fifo was full + errors_o : out std_logic_vector(3 downto 0) + ); end Event_selector; architecture Behavioral of Event_selector is - - -- trg fifo ------------------- - signal trgfifo_data_fromff : std_logic_vector(trgfifo_data_bitdepth-1 downto 0); - signal trgfifo_data_toff : std_logic_vector(trgfifo_data_bitdepth-1 downto 0); - signal trgfifo_we :std_logic; - signal trgfifo_we_ff01, trgfifo_we_ff02, trgfifo_we_ff03 :std_logic; - signal trgfifo_re :std_logic; - signal trgfifo_dcount_rd : std_logic_vector(trgfifo_count_bitdepth-1 downto 0); - signal trgfifo_empty :std_logic; - signal trgfifo_empty_real :std_logic; - signal trgfifo_reset :std_logic; - signal trgfifo_out_trigger : std_logic_vector(Trigger_bitdepth-1 downto 0); - signal trgfifo_out_orbit : std_logic_vector(Orbit_id_bitdepth-1 downto 0); - signal trgfifo_out_bc : std_logic_vector(BC_id_bitdepth-1 downto 0); - - signal is_trg_first_data_late : std_logic; - signal is_trg_eq_data : std_logic; - signal is_trg_late_data_first : std_logic; - signal is_hb_response, is_hb_response_s : std_logic; - - -- TRG from CRU comp ---------- - signal fromcru_orbit_ff, fromcru_dec_orbit_ff, fromcru_dec_orbit_ff_next : std_logic_vector(Orbit_id_bitdepth-1 downto 0); - signal fromcru_bc_ff, fromcru_dec_bc_ff, fromcru_dec_bc_ff_next : std_logic_vector(BC_id_bitdepth-1 downto 0); - signal is_trg_forrawdata_must_present : std_logic; - - - - -- raw fifo ------------------- - signal is_fullpacket_in_rawfifo : std_logic; - signal rawfifo_packet_ndwords, rawfifo_packet_ndwords_ff : std_logic_vector(n_pckt_wrds_bitdepth-1 downto 0); - signal rawfifo_packet_orbit, rawfifo_packet_orbit_ff : std_logic_vector(Orbit_id_bitdepth-1 downto 0); - signal rawfifo_packet_bc, rawfifo_packet_bc_ff: std_logic_vector(BC_id_bitdepth-1 downto 0); - - - - -- cntpck fifo ------------------- - signal cntpckfifo_data_fromff : std_logic_vector(cntpckfifo_data_bitdepth-1 downto 0); - signal cntpckfifo_data_toff : std_logic_vector(cntpckfifo_data_bitdepth-1 downto 0); - signal cntpckfifo_we :std_logic; - signal cntpckfifo_re :std_logic; - signal cntpckfifo_empty :std_logic; - signal cntpckfifo_reset :std_logic; - signal cntpckfifo_dcount_rd : std_logic_vector(cntpckfifo_count_bitdepth-1 downto 0); - - - - -- FSM --------------------- - signal Readout_Mode_ff00, Readout_Mode_ff00_syscl, Readout_Mode_ff01 : Type_Readout_Mode; -- delay for put EOC/EOT to trgfifo - signal Readout_Mode_manage, Readout_Mode_manage_DtClk, Readout_Mode_manage_next : Type_Readout_Mode; -- delay for put EOC/EOT to trgfifo - type FSM_STATE_T is (s0_DT_comp, s1_dread, s2_send_wpacket); - signal FSM_STATE, FSM_STATE_NEXT : FSM_STATE_T; - type rdata_state_T is (s0_start, s1_header, s2_data, s3_lastw); - signal rdata_state, rdata_state_next : rdata_state_T; - type cntpckws_state_T is (s0_simpl_pcw, s1_closefr_pcw); - signal cntpckws_state, cntpckws_state_next : cntpckws_state_T; - signal is_frame_open, is_frame_open_next : std_logic; - - - - -- data packet ------------- - signal current_hb_orbit, current_hb_orbit_next : std_logic_vector(Orbit_id_bitdepth-1 downto 0); - signal current_hb_bc, current_hb_bc_next : std_logic_vector(BC_id_bitdepth-1 downto 0); - - signal data_header_orbit_ff, data_header_orbit_ff_next : std_logic_vector(Orbit_id_bitdepth-1 downto 0); - signal data_header_bc_ff, data_header_bc_ff_next : std_logic_vector(BC_id_bitdepth-1 downto 0); - signal data_header_nwrd_ff, data_header_nwrd_ff_next : std_logic_vector(n_pckt_wrds_bitdepth-1 downto 0); - signal wcnt_inpck, wcnt_inpck_next : std_logic_vector(GEN_count_bitdepth-1 downto 0); - signal pages_counter, pages_counter_next : std_logic_vector(RDH_pages_counter_bitdepth-1 downto 0); - signal wcnt_fullpck, wcnt_fullpck_next, wcnt_fullpck_ff : std_logic_vector(GEN_count_bitdepth-1 downto 0); - signal max_data_packet_payload : std_logic_vector(GEN_count_bitdepth-1 downto 0); - signal crutrg_delay_comp : std_logic_vector(BC_id_bitdepth-1 downto 0); - - signal is_sending_packet_ff, is_sending_packet_ff_next : std_logic; - signal slck_fifo_we : std_logic; - - signal data_rate_counter, data_rate_counter_next : std_logic_vector(15 downto 0); - signal hits_send_porbit, hits_send_porbit_next : std_logic_vector(15 downto 0); - - -- data drop counter - signal reset_drop_counters : std_logic; - signal is_dropping_event : std_logic;--, is_dropping_event_next : std_logic; - signal dropped_events, dropped_events_next : std_logic_vector(31 downto 0); - signal first_dropped_orbit, first_dropped_orbit_next : std_logic_vector(Orbit_id_bitdepth-1 downto 0); - signal first_dropped_bc, first_dropped_bc_next : std_logic_vector(BC_id_bitdepth-1 downto 0); - signal last_dropped_orbit, last_dropped_orbit_next : std_logic_vector(Orbit_id_bitdepth-1 downto 0); - signal last_dropped_bc, last_dropped_bc_next : std_logic_vector(BC_id_bitdepth-1 downto 0); - - - - - - attribute keep : string; - attribute keep of Readout_Mode_manage : signal is "true"; - attribute keep of FSM_STATE : signal is "true"; - attribute keep of rdata_state : signal is "true"; - attribute keep of cntpckws_state : signal is "true"; - attribute keep of is_frame_open: signal is "true"; - attribute keep of pages_counter: signal is "true"; - - attribute keep of trgfifo_out_trigger : signal is "true"; - attribute keep of trgfifo_out_orbit : signal is "true"; - attribute keep of trgfifo_out_bc : signal is "true"; - - attribute keep of data_header_orbit_ff : signal is "true"; - attribute keep of data_header_bc_ff : signal is "true"; - - - attribute keep of current_hb_orbit : signal is "true"; - attribute keep of current_hb_bc : signal is "true"; - - attribute keep of is_trg_first_data_late : signal is "true"; - attribute keep of is_trg_eq_data : signal is "true"; - attribute keep of is_trg_late_data_first : signal is "true"; - attribute keep of is_hb_response : signal is "true"; - - attribute keep of fromcru_dec_orbit_ff : signal is "true"; - attribute keep of fromcru_dec_bc_ff : signal is "true"; - attribute keep of is_trg_forrawdata_must_present : signal is "true"; - - - attribute keep of trgfifo_empty : signal is "true"; - attribute keep of trgfifo_we : signal is "true"; - attribute keep of trgfifo_data_toff : signal is "true"; - - attribute keep of reset_drop_counters : signal is "true"; - attribute keep of dropped_events : signal is "true"; - attribute keep of first_dropped_orbit : signal is "true"; - attribute keep of first_dropped_bc : signal is "true"; - attribute keep of last_dropped_orbit: signal is "true"; - attribute keep of last_dropped_bc: signal is "true"; + + -- actual bcid is dalayed to take a chance to trigger go throught fifo + constant bcid_delay : natural := 32; + constant max_rdh_size : natural := 512 - (4+16); -- 492, 0x1ec + + signal data_ndwords, data_ndwords_cmd : std_logic_vector(n_pckt_wrds_bitdepth-1 downto 0); + signal data_orbit : std_logic_vector(Orbit_id_bitdepth-1 downto 0); + signal data_bc : std_logic_vector(BC_id_bitdepth-1 downto 0); + signal curr_orbit, curr_orbit_sc : std_logic_vector(Orbit_id_bitdepth-1 downto 0); + signal curr_orbit_p1, curr_orbit_p1_sc: std_logic_vector(Orbit_id_bitdepth-1 downto 0); + signal curr_bc, curr_bc_sc : std_logic_vector(BC_id_bitdepth-1 downto 0); + signal trigger_select_val_sc : std_logic_vector(Trigger_bitdepth-1 downto 0); + + signal trgfifo_dout, trgfifo_din : std_logic_vector(75 downto 0); + signal trgfifo_empty, trgfifo_re, trgfifo_we, trgfifo_full, trgfifo_full_latch : std_logic; + signal trgfifo_out_trigger : std_logic_vector(Trigger_bitdepth-1 downto 0); + signal trgfifo_out_orbit : std_logic_vector(Orbit_id_bitdepth-1 downto 0); + signal trgfifo_out_bc : std_logic_vector(BC_id_bitdepth-1 downto 0); + + signal slct_fifo_din, slct_fifo_din_ff : std_logic_vector(GBT_data_word_bitdepth-1 downto 0); + signal slct_fifo_count_rd, slct_fifo_count_wr, fifo_cnt_max : std_logic_vector(14 downto 0); + signal drop_counter : std_logic_vector(15 downto 0); + signal event_counter, event_counter_ff : std_logic_vector(31 downto 0); + signal event_counter_zero_counter : std_logic_vector(31 downto 0); + + signal slct_fifo_wren, slct_fifo_wren_ff, slct_fifo_busy, slct_fifo_full, slct_fifo_empty : std_logic; + + signal cntpck_fifo_din, cntpck_fifo_din_ff : std_logic_vector(127 downto 0); + signal cntpck_fifo_wren, cntpck_fifo_wren_ff, cntpck_fifo_full, cntpck_fifo_empty : std_logic; + + signal trgfifo_empty_dc, cntpck_fifo_empty_sc, slct_fifo_empty_sc : std_logic; + signal send_gear_rdh_dc, send_last_rdh_dc : boolean; + signal fifo_notempty_while_start : std_logic_vector(2 downto 0); + signal trgfifo_wr_busy : std_logic; + + type FSM_STATE_T is (s0_idle, s1_select, s2_dread); + signal FSM_STATE, FSM_STATE_NEXT : FSM_STATE_T; + signal select_timeout : natural range 0 to 7; -- min time between select states is 3 cycles to wait updated data from fifo. + + signal header_fifo_rd, data_fifo_rd : std_logic; + signal word_counter : std_logic_vector(n_pckt_wrds_bitdepth-1 downto 0); + signal rdh_size_counter, rdh_packet_counter : natural range 0 to max_rdh_size+2; + + signal rdh_trigger : std_logic_vector(Trigger_bitdepth-1 downto 0); + signal rdh_orbit : std_logic_vector(Orbit_id_bitdepth-1 downto 0); + signal rdh_bc : std_logic_vector(BC_id_bitdepth-1 downto 0); + + -- control options + signal hb_rdh_response, readout_bypass, hb_reject : boolean; + + -- cru readout states + signal data_enabled_sc, send_trg_mode_sc, start_of_run : boolean; + -- trg_fifo set 'not_empty' after 2 cycles, is_readout should be delayed. is_readout_sc - actual + signal is_readout_sc, is_readout_ff1, is_readout_ff2, is_readout_ff3, is_readout_ff3_sc : boolean; + -- data-trg comparison + signal is_hbtrg, is_hb_r_trg, is_sox, is_eox, is_hbtrg_cmd, is_sel_trg, read_data, read_trigger, start_select : boolean; + signal read_data_cmd, read_trigger_cmd, rdh_close_cmd, hb_reject_cmd : boolean; + signal data_not_actual, trg_not_actual, trg_eq_data, trg_later_data, data_later_trg : boolean; + -- packet reading states + signal reading_header, reading_last_word : boolean; + -- pushing data to select fifo by TRG/CNT mode + signal data_reject_cmd : boolean; + -- send_gear_rdh becames true after first BC while readout and false after first BC while idle, used to do not send firs RDH response + -- send_last_rdh used to send last RDH response after readout finished + signal send_gear_rdh, send_last_rdh : boolean; + -- dropping data when select fifo is full + signal dropping_data_cmd : boolean; + signal stop_bit : std_logic; + signal reset_dt_counters_sc : boolean; + + +-- attribute mark_debug : string; +-- attribute mark_debug of event_counter : signal is "true"; +-- attribute mark_debug of event_counter_zero_counter : signal is "true"; +-- attribute mark_debug of trgfifo_empty : signal is "true"; +-- attribute mark_debug of trgfifo_full : signal is "true"; +-- attribute mark_debug of trgfifo_full_latch : signal is "true"; +-- attribute mark_debug of cntpck_fifo_empty_sc : signal is "true"; +-- attribute mark_debug of slct_fifo_empty_sc : signal is "true"; +-- attribute mark_debug of send_gear_rdh : signal is "true"; +-- attribute mark_debug of send_last_rdh : signal is "true"; + +-- attribute mark_debug of FSM_STATE : signal is "true"; +-- attribute mark_debug of read_data_cmd : signal is "true"; +-- attribute mark_debug of read_trigger_cmd : signal is "true"; +-- attribute mark_debug of start_select : signal is "true"; +-- attribute mark_debug of select_timeout : signal is "true"; + +-- attribute mark_debug of curr_orbit_sc : signal is "true"; +-- attribute mark_debug of curr_bc_sc : signal is "true"; +-- attribute mark_debug of trgfifo_out_orbit : signal is "true"; +-- attribute mark_debug of trgfifo_out_bc : signal is "true"; +-- attribute mark_debug of trgfifo_we : signal is "true"; +-- attribute mark_debug of trgfifo_din : signal is "true"; +-- attribute mark_debug of trgfifo_wr_busy : signal is "true"; + begin - crutrg_delay_comp <= Control_register_I.crutrg_delay_comp; - --crutrg_delay_comp <= x"00f"; - max_data_packet_payload <= Control_register_I.max_data_payload; --- max_data_packet_payload <= x"01c2"; - Readout_Mode_ff00 <= FIT_GBT_status_I.Readout_Mode; - - SLCTFIFO_WE_O <= slck_fifo_we; - - CNTPTFIFO_data_word_O <= cntpckfifo_data_fromff; - CNTPFIFO_Is_Empty_O <= cntpckfifo_empty; - cntpckfifo_re <= CNTPFIFO_RE_I; - - CNTPFIFO_count_O <= cntpckfifo_dcount_rd; - TRGFIFO_count_O <= trgfifo_dcount_rd; - - - hits_rd_counter_selector_O.hits_send_porbit <= hits_send_porbit; - hits_rd_counter_selector_O.hits_skipped <= dropped_events; - hits_rd_counter_selector_O.first_orbit_hdrop <= first_dropped_orbit; - hits_rd_counter_selector_O.first_bc_hdrop <= first_dropped_bc; - hits_rd_counter_selector_O.last_orbit_hdrop <= last_dropped_orbit; - hits_rd_counter_selector_O.last_bc_hdrop <= last_dropped_bc; - - --- TRG FIFO ****************************************** - trgfifo_data_toff <= FIT_GBT_status_I.Trigger_from_CRU & FIT_GBT_status_I.ORBIT_from_CRU & FIT_GBT_status_I.BCID_from_CRU; - - trgfifo_out_trigger <= trgfifo_data_fromff(trgfifo_data_bitdepth-1 downto BC_id_bitdepth + Orbit_id_bitdepth); - trgfifo_out_orbit <= trgfifo_data_fromff(BC_id_bitdepth + Orbit_id_bitdepth -1 downto BC_id_bitdepth); - trgfifo_out_bc <= trgfifo_data_fromff(BC_id_bitdepth - 1 downto 0); - - - is_trg_eq_data <= '0' WHEN (trgfifo_empty = '1') ELSE - '0' WHEN (RAWFIFO_Is_Empty_I = '1') ELSE - '0' WHEN (trgfifo_out_orbit = ORBIT_const_void) ELSE - '0' WHEN (rawfifo_packet_orbit_ff = ORBIT_const_void) ELSE - -- '1' WHEN ( (trgfifo_out_orbit = rawfifo_packet_orbit_ff) and (trgfifo_out_bc = rawfifo_packet_bc_ff) and (trgfifo_out_trigger = Control_register_I.trg_data_select) ) ELSE - '1' WHEN ( (trgfifo_out_orbit = rawfifo_packet_orbit_ff) and (trgfifo_out_bc = rawfifo_packet_bc_ff) ) ELSE - '0'; - - is_trg_first_data_late <= '0' WHEN (trgfifo_empty = '1') ELSE - '0' WHEN (RAWFIFO_Is_Empty_I = '1') ELSE - '0' WHEN (trgfifo_out_orbit = ORBIT_const_void) ELSE - '0' WHEN (rawfifo_packet_orbit_ff = ORBIT_const_void) ELSE - '1' WHEN ( (trgfifo_out_orbit < rawfifo_packet_orbit_ff) ) ELSE - '1' WHEN ( (trgfifo_out_orbit = rawfifo_packet_orbit_ff) and (trgfifo_out_bc < rawfifo_packet_bc_ff) ) ELSE - '0'; - - -- trigger always late - is_trg_late_data_first <= '0' WHEN (trgfifo_empty = '1') ELSE - '0' WHEN (RAWFIFO_Is_Empty_I = '1') ELSE - '0' WHEN (trgfifo_out_orbit = ORBIT_const_void) ELSE - '0' WHEN (rawfifo_packet_orbit_ff = ORBIT_const_void) ELSE - '1' WHEN ( (trgfifo_out_orbit > rawfifo_packet_orbit_ff) ) ELSE - '1' WHEN ( (trgfifo_out_orbit = rawfifo_packet_orbit_ff) and (trgfifo_out_bc > rawfifo_packet_bc_ff) ) ELSE - '0'; - - trgfifo_empty_real <= '1' WHEN (FSM_Clocks_I.Reset = '1') ELSE - '0' WHEN (trgfifo_empty = '0') ELSE - '0' WHEN (trgfifo_we = '1') ELSE - '0' WHEN (trgfifo_we_ff01 = '1') ELSE - '0' WHEN (trgfifo_we_ff02 = '1') ELSE - '0' WHEN (trgfifo_we_ff03 = '1') ELSE - trgfifo_empty; - - is_hb_response <= '0' WHEN (FSM_Clocks_I.Reset = '1') ELSE - '0' WHEN (trgfifo_empty = '1') ELSE - '1' WHEN ((trgfifo_out_trigger and TRG_const_HB) > 0) ELSE - '0'; --- *************************************************** - - - --- RAW FIFO ****************************************** -is_fullpacket_in_rawfifo <= '0' WHEN (RAWFIFO_Is_Empty_I = '1') ELSE - '1' when (unsigned(RAWFIFO_data_count_I) > unsigned(rawfifo_packet_ndwords_ff)) else - '0'; - -rawfifo_packet_ndwords <= func_FITDATAHD_ndwords(RAWFIFO_data_word_I); -rawfifo_packet_orbit <= func_FITDATAHD_orbit(RAWFIFO_data_word_I); -rawfifo_packet_bc <= func_FITDATAHD_bc(RAWFIFO_data_word_I); - - -is_trg_forrawdata_must_present <= '0' WHEN (RAWFIFO_Is_Empty_I = '1') ELSE - '1' WHEN ( rawfifo_packet_orbit_ff < fromcru_dec_orbit_ff ) ELSE - '1' WHEN ( (rawfifo_packet_orbit_ff = fromcru_dec_orbit_ff) and (rawfifo_packet_bc_ff < fromcru_dec_bc_ff) ) ELSE - '0'; - - -fromcru_dec_bc_ff_next <= (fromcru_bc_ff - crutrg_delay_comp) WHEN (fromcru_bc_ff >= crutrg_delay_comp) ELSE - fromcru_bc_ff - crutrg_delay_comp + LHC_BCID_max + 1; - -fromcru_dec_orbit_ff_next <= fromcru_orbit_ff WHEN (fromcru_bc_ff >= crutrg_delay_comp) ELSE - fromcru_orbit_ff - 1; --- *************************************************** + -- inputs + data_ndwords <= func_FITDATAHD_ndwords(header_fifo_data_i); + data_orbit <= func_FITDATAHD_orbit(header_fifo_data_i); + data_bc <= func_FITDATAHD_bc(header_fifo_data_i); + -- outputs + header_fifo_rden_o <= header_fifo_rd; + data_fifo_rden_o <= data_fifo_rd; + slct_fifo_cnt_o <= '0'&slct_fifo_count_rd; + slct_fifo_cnt_max_o <= '0'&fifo_cnt_max; + slct_fifo_empty_o <= slct_fifo_empty; + cntpck_fifo_empty_o <= cntpck_fifo_empty; + trg_fifo_empty_o <= trgfifo_empty_dc; -- TRG FIFO ============================================= -trg_fifo_comp_c : entity work.trg_fifo_comp -port map( - wr_clk => FSM_Clocks_I.Data_Clk, - rd_clk => FSM_Clocks_I.System_Clk, - rst => trgfifo_reset, - DIN => trgfifo_data_toff, - WR_EN => trgfifo_we, - RD_EN => trgfifo_re, - - DOUT => trgfifo_data_fromff, - rd_data_count => trgfifo_dcount_rd, - EMPTY => trgfifo_empty - ); + trg_fifo_comp_c : entity work.trg_fifo_comp + port map( + wr_clk => FSM_Clocks_I.Data_Clk, + rd_clk => FSM_Clocks_I.System_Clk, + rst => FSM_Clocks_I.Reset_dclk, + DIN => trgfifo_din, + WR_EN => trgfifo_we, + RD_EN => trgfifo_re, + + DOUT => trgfifo_dout, + EMPTY => trgfifo_empty, + FULL => trgfifo_full, + + wr_rst_busy => trgfifo_wr_busy, + rd_rst_busy => open + ); + + trgfifo_we <= '1' when (((Control_register_I.trg_data_select or TRG_const_HB) and Status_register_I.Trigger_from_CRU) /= TRG_const_void) + and Status_register_I.Readout_Mode /= mode_IDLE else '0'; + trgfifo_din <= Status_register_I.Trigger_from_CRU & Status_register_I.ORBIT_from_CRU & Status_register_I.BCID_from_CRU; + trgfifo_out_trigger <= trgfifo_dout(75 downto BC_id_bitdepth + Orbit_id_bitdepth); + trgfifo_out_orbit <= trgfifo_dout(BC_id_bitdepth + Orbit_id_bitdepth -1 downto BC_id_bitdepth); + trgfifo_out_bc <= trgfifo_dout(BC_id_bitdepth - 1 downto 0); -- =========================================================== - - - -- CNTPCK FIFO ============================================= -cntpck_fifo_comp_c : entity work.cntpck_fifo_comp -port map( - wr_clk => FSM_Clocks_I.System_Clk, - rd_clk => FSM_Clocks_I.Data_Clk, - rst => cntpckfifo_reset, - DIN => cntpckfifo_data_toff, - WR_EN => cntpckfifo_we, - RD_EN => cntpckfifo_re, - - DOUT => cntpckfifo_data_fromff, - rd_data_count => cntpckfifo_dcount_rd, - EMPTY => cntpckfifo_empty - ); + cntpck_fifo_comp_c : entity work.cntpck_fifo_comp + port map( + wr_clk => FSM_Clocks_I.System_Clk, + rd_clk => FSM_Clocks_I.Data_Clk, + rst => FSM_Clocks_I.Reset_sclk, + DIN => cntpck_fifo_din_ff, + WR_EN => cntpck_fifo_wren_ff, + RD_EN => cntpck_fifo_rden_i, + + DOUT => cntpck_fifo_dout_o, + EMPTY => cntpck_fifo_empty, + full => cntpck_fifo_full + ); -- =========================================================== +-- Slc_data_fifo ============================================= + slct_fifo_comp : entity work.slct_data_fifo + port map( + wr_clk => FSM_Clocks_I.System_Clk, + rd_clk => FSM_Clocks_I.Data_Clk, + rd_data_count => slct_fifo_count_rd, + wr_data_count => slct_fifo_count_wr, + rst => FSM_Clocks_I.Reset_sclk, + WR_EN => slct_fifo_wren_ff, + RD_EN => slct_fifo_rden_i, + DIN => slct_fifo_din_ff, + DOUT => slct_fifo_dout_o, + prog_full => slct_fifo_full, + EMPTY => slct_fifo_empty, + wr_rst_busy => slct_fifo_busy, + rd_rst_busy => open + ); +-- =========================================================== - - - -- Data ff data clk *********************************** - PROCESS (FSM_Clocks_I.Data_Clk) - BEGIN - IF(FSM_Clocks_I.Data_Clk'EVENT and FSM_Clocks_I.Data_Clk = '1') THEN - - is_hb_response_s<=Control_register_I.is_hb_response; - - IF(FSM_Clocks_I.Reset40 = '1') THEN - Readout_Mode_ff01 <= mode_IDLE; - - trgfifo_we_ff01 <= '0'; - trgfifo_we_ff02 <= '0'; - trgfifo_we_ff03 <= '0'; - - --Readout_Mode_manage_DtClk <= mode_IDLE; - - fromcru_orbit_ff <= (others => '0'); - fromcru_bc_ff <= (others => '0'); - fromcru_dec_orbit_ff <= (others => '0'); - fromcru_dec_bc_ff <= (others => '0'); - - ELSE - Readout_Mode_ff01 <= Readout_Mode_ff00; - - trgfifo_we_ff01 <= trgfifo_we; - trgfifo_we_ff02 <= trgfifo_we_ff01; - trgfifo_we_ff03 <= trgfifo_we_ff02; - - --Readout_Mode_manage_DtClk <= Readout_Mode_manage; - - fromcru_orbit_ff <= FIT_GBT_status_I.ORBIT_from_CRU; - fromcru_bc_ff <= FIT_GBT_status_I.BCID_from_CRU; - fromcru_dec_orbit_ff <= fromcru_dec_orbit_ff_next; - fromcru_dec_bc_ff <= fromcru_dec_bc_ff_next; - - - END IF; - END IF; - END PROCESS; + process (FSM_Clocks_I.Data_Clk) + begin + if(rising_edge(FSM_Clocks_I.Data_Clk))then + + packets_dropped_o <= drop_counter; + errors_o <= trgfifo_full_latch & fifo_notempty_while_start; + event_counter_o <= event_counter; + no_data_o <= (trgfifo_empty_dc = '1') and (cntpck_fifo_empty = '1') and (slct_fifo_empty = '1') and not send_gear_rdh_dc and not send_last_rdh_dc; + + is_readout_ff1 <= Status_register_I.Readout_Mode /= mode_IDLE; + is_readout_ff2 <= is_readout_ff1; + is_readout_ff3 <= is_readout_ff2; + + trgfifo_empty_dc <= trgfifo_empty; + send_gear_rdh_dc <= send_gear_rdh; + send_last_rdh_dc <= send_last_rdh; + + if Status_register_I.BCID_from_CRU >= bcid_delay then + curr_orbit <= Status_register_I.ORBIT_from_CRU; + curr_orbit_p1 <= Status_register_I.ORBIT_from_CRU+1; + curr_bc <= (Status_register_I.BCID_from_CRU - bcid_delay); + else + curr_orbit <= Status_register_I.ORBIT_from_CRU - 1; + curr_orbit_p1 <= Status_register_I.ORBIT_from_CRU; + curr_bc <= Status_register_I.BCID_from_CRU - bcid_delay + LHC_BCID_max + 1; + end if; + + if(FSM_Clocks_I.Reset_dclk = '1') then + + fifo_cnt_max <= (others => '0'); + trgfifo_full_latch <= '0'; + + else + + -- select data fifo max count + if Control_register_I.reset_data_counters = '1' then + fifo_cnt_max <= (others => '0'); + else + if fifo_cnt_max < slct_fifo_count_rd then fifo_cnt_max <= slct_fifo_count_rd; end if; + end if; + + -- trigger fifo full latching + if (trgfifo_full = '1') and (Status_register_I.Readout_Mode /= mode_IDLE) then trgfifo_full_latch <= '1'; end if; + + end if; + + end if; + end process; -- **************************************************** -- Data ff sys clk ************************************ - PROCESS (FSM_Clocks_I.System_Clk) - BEGIN - IF(FSM_Clocks_I.System_Clk'EVENT and FSM_Clocks_I.System_Clk = '1') THEN - IF(FSM_Clocks_I.Reset = '1') THEN - - Readout_Mode_ff00_syscl <= mode_IDLE; - cntpckws_state <= s0_simpl_pcw; - rdata_state <= s0_start; - FSM_STATE <= s0_DT_comp; - Readout_Mode_manage <= mode_IDLE; - - current_hb_orbit <= (others => '0'); - current_hb_bc <= (others => '0'); - data_header_orbit_ff <= (others => '0'); - data_header_bc_ff <= (others => '0'); - data_header_nwrd_ff <= (others => '0'); - wcnt_inpck <= (others => '0'); - wcnt_fullpck <= (others => '0'); - wcnt_fullpck_ff <= (others => '0'); - is_sending_packet_ff <= '0'; - is_frame_open <= '0'; - pages_counter <= (others => '0'); - - data_rate_counter <= (others => '0'); - hits_send_porbit <= (others => '0'); - - dropped_events <= (others => '0'); - first_dropped_orbit <= (others => '0'); - first_dropped_bc <= (others => '0'); - last_dropped_orbit <= (others => '0'); - last_dropped_bc <= (others => '0'); - - ELSE - - Readout_Mode_ff00_syscl <= Readout_Mode_ff00; - cntpckws_state <= cntpckws_state_next; - rdata_state <= rdata_state_next; - FSM_STATE <= FSM_STATE_NEXT; - - if(Readout_Mode_ff00_syscl /= mode_IDLE) then - Readout_Mode_manage <= Readout_Mode_ff00_syscl; - else - Readout_Mode_manage <= Readout_Mode_manage_next; - end if; - - current_hb_orbit <= current_hb_orbit_next; - current_hb_bc <= current_hb_bc_next; - data_header_orbit_ff <= data_header_orbit_ff_next; - data_header_bc_ff <= data_header_bc_ff_next; - data_header_nwrd_ff <= data_header_nwrd_ff_next; - wcnt_inpck <= wcnt_inpck_next; - wcnt_fullpck <= wcnt_fullpck_next; - wcnt_fullpck_ff <= wcnt_fullpck; - is_sending_packet_ff <= is_sending_packet_ff_next; - is_frame_open <= is_frame_open_next; - pages_counter <= pages_counter_next; - - data_rate_counter <= data_rate_counter_next; - hits_send_porbit <= hits_send_porbit_next; - - dropped_events <= dropped_events_next; - first_dropped_orbit <= first_dropped_orbit_next; - first_dropped_bc <= first_dropped_bc_next; - last_dropped_orbit <= last_dropped_orbit_next; - last_dropped_bc <= last_dropped_bc_next; - END IF; - END IF; - END PROCESS; --- **************************************************** + process (FSM_Clocks_I.System_Clk) + begin + if(rising_edge(FSM_Clocks_I.System_Clk))then + + curr_orbit_sc <= curr_orbit; + curr_orbit_p1_sc <= curr_orbit_p1; + curr_bc_sc <= curr_bc; + data_enabled_sc <= Status_register_I.data_enable = '1'; + is_readout_sc <= Status_register_I.Readout_Mode /= mode_IDLE; + is_readout_ff3_sc <= is_readout_ff3; + start_of_run <= Status_register_I.Start_run = '1'; + trigger_select_val_sc <= Control_register_I.trg_data_select; + reset_dt_counters_sc <= Control_register_I.reset_data_counters = '1'; + hb_rdh_response <= Control_register_I.is_hb_response = '1'; + readout_bypass <= Control_register_I.readout_bypass = '1'; + hb_reject <= Control_register_I.is_hb_reject = '1'; + -- event_counter_ff <= event_counter; + -- cntpck_fifo_empty_sc <= cntpck_fifo_empty; + -- slct_fifo_empty_sc <= slct_fifo_empty; + + -- put raw data in select fifo for readout bypass mode + if readout_bypass then + slct_fifo_din_ff <= raw_data_i; + slct_fifo_wren_ff <= raw_isdata_i; + else + slct_fifo_din_ff <= slct_fifo_din; + slct_fifo_wren_ff <= slct_fifo_wren; + end if; + + cntpck_fifo_din_ff <= cntpck_fifo_din; + cntpck_fifo_wren_ff <= cntpck_fifo_wren; + start_select <= read_data or read_trigger; + + -- readout mode is latched at the start of run, to select last data + if start_of_run then send_trg_mode_sc <= Status_register_I.Readout_Mode = mode_TRG; end if; + + if(FSM_Clocks_I.Reset_sclk = '1') then + FSM_STATE <= s0_idle; + word_counter <= (others => '0'); + drop_counter <= (others => '0'); + fifo_notempty_while_start <= (others => '0'); + select_timeout <= 7; + + + else + + FSM_STATE <= FSM_STATE_NEXT; + + -- latching readout commands + if FSM_STATE_NEXT = s1_select then + + select_timeout <= 0; - rawfifo_packet_ndwords_ff <= rawfifo_packet_ndwords; - rawfifo_packet_orbit_ff <= rawfifo_packet_orbit; - rawfifo_packet_bc_ff <= rawfifo_packet_bc; - - -- FSM *********************************************** - Readout_Mode_manage_next <= mode_IDLE WHEN (FSM_Clocks_I.Reset = '1') ELSE - Readout_Mode_ff00_syscl WHEN (Readout_Mode_ff00_syscl /= mode_IDLE) ELSE - Readout_Mode_ff01 WHEN (Readout_Mode_ff01 /= mode_IDLE) ELSE - Readout_Mode_manage WHEN (trgfifo_empty_real = '0') ELSE - Readout_Mode_ff01; - - - - FSM_STATE_NEXT <= s0_DT_comp WHEN (FSM_Clocks_I.Reset = '1') ELSE - - -- ------------------- IDL ------------------- - s0_DT_comp WHEN (Readout_Mode_manage = mode_IDLE) ELSE - s0_DT_comp WHEN (FIT_GBT_status_I.BCIDsync_Mode = mode_STR) ELSE - s0_DT_comp WHEN (FIT_GBT_status_I.BCIDsync_Mode = mode_LOST) ELSE - - s1_dread WHEN (FSM_STATE = s1_dread) and (rdata_state /= s3_lastw) ELSE -- reading data - s0_DT_comp WHEN (FSM_STATE = s1_dread) and (rdata_state = s3_lastw) ELSE -- return to s0 - - - s0_DT_comp WHEN (FSM_STATE = s0_DT_comp) and (trgfifo_empty = '1') and (RAWFIFO_Is_Empty_I = '1') ELSE -- wait - s2_send_wpacket WHEN (FSM_STATE = s0_DT_comp) and (trgfifo_empty = '0') and (RAWFIFO_Is_Empty_I = '1') ELSE -- no data send response - - s1_dread WHEN (FSM_STATE = s0_DT_comp) and (is_trg_eq_data = '1') and (is_hb_response = '0') ELSE -- read data for trigger - s2_send_wpacket WHEN (FSM_STATE = s0_DT_comp) and (is_trg_eq_data = '1') and (cntpckws_state = s0_simpl_pcw) and (is_hb_response = '1') ELSE -- no read HB data; send SF first - s1_dread WHEN (FSM_STATE = s0_DT_comp) and (is_trg_eq_data = '1') and (cntpckws_state = s1_closefr_pcw) and (is_hb_response = '1') ELSE -- read HB data after SF - s2_send_wpacket WHEN (FSM_STATE = s0_DT_comp) and (is_trg_eq_data = '1') ELSE -- send trg+data - - s2_send_wpacket WHEN (FSM_STATE = s0_DT_comp) and (is_trg_first_data_late = '1') ELSE -- send trg - - s2_send_wpacket WHEN (FSM_STATE = s0_DT_comp) and (wcnt_fullpck_ff >= max_data_packet_payload) ELSE -- send by payload - - - s1_dread WHEN (FSM_STATE = s0_DT_comp) and (is_trg_late_data_first = '1') ELSE -- send data - s1_dread WHEN (FSM_STATE = s0_DT_comp) and (trgfifo_empty = '1') and (RAWFIFO_Is_Empty_I = '0') and (is_trg_forrawdata_must_present = '1') ELSE -- no trg, send data - s0_DT_comp; - - - - - - is_sending_packet_ff_next <= '0' WHEN (FSM_Clocks_I.Reset = '1') ELSE - -- ------------------- IDL ------------------- - '0' WHEN (Readout_Mode_manage = mode_IDLE) ELSE - -- ------------------- SLCT FIFO FULL ------------------- - '0' WHEN (FSM_STATE = s1_dread) and (rdata_state = s0_start) and (SLCTFIFO_Is_spacefpacket_I = '0') ELSE --- '0' WHEN (FSM_STATE = s1_dread) and (rdata_state = s0_start) and (data_header_orbit_ff /= current_hb_orbit) ELSE - -- ------------------- TRG ------------------- - '1' WHEN (is_trg_eq_data = '1') and ((trgfifo_out_trigger and Control_register_I.trg_data_select) > 1) and (FSM_STATE = s1_dread) and (rdata_state = s0_start) and (Readout_Mode_manage = mode_TRG) ELSE - '0' WHEN (is_trg_first_data_late = '1') and (FSM_STATE = s1_dread) and (rdata_state = s0_start) and (Readout_Mode_manage = mode_TRG) ELSE - '0' WHEN (is_trg_late_data_first = '1') and (FSM_STATE = s1_dread) and (rdata_state = s0_start) and (Readout_Mode_manage = mode_TRG) ELSE - '0' WHEN (is_trg_forrawdata_must_present = '1') and (FSM_STATE = s1_dread) and (rdata_state = s0_start) and (Readout_Mode_manage = mode_TRG) ELSE - -- ------------------- CNT ------------------- - '1' WHEN (FSM_STATE = s1_dread) and (rdata_state = s0_start) and (Readout_Mode_manage = mode_CNT) ELSE - -- ------------------- --- ------------------- - is_sending_packet_ff; - - - - rdata_state_next <= s0_start WHEN (FSM_Clocks_I.Reset = '1') ELSE --- s0_start WHEN (Readout_Mode_manage = mode_IDLE) ELSE - s0_start WHEN (FSM_STATE = s1_dread) and (rdata_state = s0_start) and (is_fullpacket_in_rawfifo = '0') ELSE - s1_header WHEN (FSM_STATE = s1_dread) and (rdata_state = s0_start) ELSE - s3_lastw WHEN (FSM_STATE = s1_dread) and (rdata_state = s1_header) and (data_header_nwrd_ff=1) ELSE - s2_data WHEN (FSM_STATE = s1_dread) and (rdata_state = s1_header) ELSE - s2_data WHEN (FSM_STATE = s1_dread) and (rdata_state = s2_data) and (wcnt_inpck < data_header_nwrd_ff-1) ELSE - s3_lastw WHEN (FSM_STATE = s1_dread) and (rdata_state = s2_data) and (wcnt_inpck = data_header_nwrd_ff-1) ELSE - s0_start; - - - cntpckws_state_next <= s0_simpl_pcw WHEN (FSM_Clocks_I.Reset = '1') ELSE - s0_simpl_pcw WHEN (FSM_STATE_NEXT = s2_send_wpacket) and (cntpckws_state = s1_closefr_pcw) ELSE - s1_closefr_pcw WHEN (FSM_STATE_NEXT = s2_send_wpacket) and (is_hb_response = '1') and (is_frame_open = '1') ELSE - s0_simpl_pcw WHEN (FSM_STATE_NEXT = s2_send_wpacket) and (wcnt_fullpck_ff >= max_data_packet_payload) ELSE - cntpckws_state; - - --- is_frame_open_next <= '0' WHEN (FSM_Clocks_I.Reset = '1') ELSE --- '0' WHEN (Readout_Mode_manage = mode_IDLE) ELSE --- --'0' WHEN (FSM_STATE_NEXT = s2_send_wpacket) and (cntpckws_state = s1_closefr_pcw) ELSE --- --'0' WHEN (cntpckws_state_next = s0_simpl_pcw) and (cntpckws_state = s1_closefr_pcw) ELSE --- '0' WHEN (cntpckfifo_we = '1') and (cntpckws_state = s1_closefr_pcw) ELSE --- --- --'1' WHEN (FSM_STATE_NEXT = s2_send_wpacket) and (is_hb_response = '1') ELSE --- '1' WHEN (cntpckfifo_we = '1') and (is_hb_response = '1') ELSE --- --- --'0' WHEN (FSM_STATE_NEXT = s2_send_wpacket) and (cntpckws_state = s1_closefr_pcw) ELSE --- is_frame_open; - - - is_frame_open_next <= '0' WHEN (FSM_Clocks_I.Reset = '1') ELSE - '0' WHEN (Readout_Mode_manage = mode_IDLE) ELSE - '1' WHEN (FSM_STATE_NEXT = s2_send_wpacket) and (is_hb_response = '1') ELSE - '0' WHEN (FSM_STATE_NEXT = s2_send_wpacket) and (cntpckws_state = s1_closefr_pcw) ELSE - is_frame_open; - - - -- pages_counter_next <= (others => '0') WHEN (FSM_Clocks_I.Reset = '1') ELSE - -- (others => '0') WHEN (Readout_Mode_ff00 = mode_IDLE) ELSE - -- (others => '0') WHEN (FSM_STATE_NEXT = s2_send_wpacket) and (is_hb_response = '1') and (cntpckws_state_next /= s1_closefr_pcw) ELSE - -- pages_counter + 1 WHEN (FSM_STATE_NEXT = s2_send_wpacket) ELSE - -- pages_counter; - - pages_counter_next <= (others => '0') WHEN (FSM_Clocks_I.Reset = '1') ELSE - (others => '0') WHEN (Readout_Mode_manage = mode_IDLE) ELSE - (others => '0') WHEN (cntpckfifo_we = '1') and (cntpckws_state = s1_closefr_pcw) ELSE - pages_counter + 1 WHEN (cntpckfifo_we = '1') ELSE - pages_counter; - - - - - - - current_hb_orbit_next <= (others => '0') WHEN (FSM_Clocks_I.Reset = '1') ELSE - FIT_GBT_status_I.ORBIT_from_CRU WHEN (Readout_Mode_manage = mode_IDLE) and ((FIT_GBT_status_I.Trigger_from_CRU and TRG_const_HB) > 0) ELSE - trgfifo_out_orbit WHEN (is_hb_response = '1') and (cntpckws_state = s1_closefr_pcw) ELSE - current_hb_orbit; - - current_hb_bc_next <= (others => '0') WHEN (FSM_Clocks_I.Reset = '1') ELSE - FIT_GBT_status_I.BCID_from_CRU WHEN (Readout_Mode_manage = mode_IDLE) and ((FIT_GBT_status_I.Trigger_from_CRU and TRG_const_HB) > 0) ELSE - trgfifo_out_bc WHEN (is_hb_response = '1') and (cntpckws_state = s1_closefr_pcw) ELSE - current_hb_bc; - - - wcnt_inpck_next <= (others => '0') WHEN (FSM_Clocks_I.Reset = '1') ELSE - (others => '0') WHEN (rdata_state = s0_start) ELSE - wcnt_inpck + 1 WHEN (FSM_STATE = s1_dread) ELSE - (others => '0'); - --- wcnt_fullpck_next <= (others => '0') WHEN (FSM_Clocks_I.Reset = '1') ELSE --- (others => '0') WHEN (FSM_STATE = s2_send_wpacket) and (Readout_Mode_manage = mode_CNT) ELSE --- wcnt_fullpck WHEN (FSM_STATE = s2_send_wpacket) and (cntpckws_state = s1_closefr_pcw) and (Readout_Mode_manage = mode_TRG) ELSE --- (others => '0') WHEN (FSM_STATE = s2_send_wpacket) and (cntpckws_state = s0_simpl_pcw) and (Readout_Mode_manage = mode_TRG) ELSE --- wcnt_fullpck + 1 WHEN (slck_fifo_we = '1') ELSE --- wcnt_fullpck; - - wcnt_fullpck_next <= (others => '0') WHEN (FSM_Clocks_I.Reset = '1') ELSE - (others => '0') WHEN (FSM_STATE = s2_send_wpacket) and (cntpckfifo_we = '1') ELSE - wcnt_fullpck + 1 WHEN (slck_fifo_we = '1') ELSE - wcnt_fullpck; - - data_header_nwrd_ff_next <= (others => '0') WHEN (FSM_Clocks_I.Reset = '1') ELSE - rawfifo_packet_ndwords_ff WHEN (FSM_STATE = s1_dread) and (rdata_state = s0_start) ELSE - data_header_nwrd_ff; - - data_header_orbit_ff_next <= (others => '0') WHEN (FSM_Clocks_I.Reset = '1') ELSE - rawfifo_packet_orbit_ff WHEN (FSM_STATE = s1_dread) and (rdata_state = s0_start) ELSE - data_header_orbit_ff; - - data_header_bc_ff_next <= (others => '0') WHEN (FSM_Clocks_I.Reset = '1') ELSE - rawfifo_packet_bc_ff WHEN (FSM_STATE = s1_dread) and (rdata_state = s0_start) ELSE - data_header_bc_ff; - - - - - - - trgfifo_reset <= FSM_Clocks_I.Reset40; - RAWFIFO_RESET_O <= FSM_Clocks_I.Reset; - SLCTFIFO_RESET_O <= FSM_Clocks_I.Reset; - cntpckfifo_reset <= FSM_Clocks_I.Reset; - - - trgfifo_we <= '0' WHEN (FSM_Clocks_I.Reset = '1') ELSE - '1' WHEN ((x"ffffffff" and FIT_GBT_status_I.Trigger_from_CRU) > 0) and (Readout_Mode_ff00_syscl /= mode_IDLE) ELSE - '0'; - - trgfifo_re <= '0' WHEN (FSM_Clocks_I.Reset = '1') ELSE - '1' WHEN (FSM_STATE = s2_send_wpacket) and (cntpckws_state = s0_simpl_pcw) ELSE - '0' WHEN (FSM_STATE = s2_send_wpacket) and (cntpckws_state = s0_simpl_pcw) and (wcnt_fullpck_ff >= max_data_packet_payload) ELSE - '0'; - - - - - RAWFIFO_RE_O <= '0' WHEN (FSM_Clocks_I.Reset = '1') ELSE - '1' WHEN (FSM_STATE = s1_dread) and (rdata_state /= s0_start) ELSE - '0'; - - - - - slck_fifo_we <= '0' WHEN (FSM_Clocks_I.Reset = '1') ELSE - '1' WHEN (FSM_STATE = s1_dread) and (rdata_state /= s0_start) and (is_sending_packet_ff = '1') ELSE - '0'; - - SLCTFIFO_data_word_O <= RAWFIFO_data_word_I; - - - cntpckfifo_we <= '0' WHEN (FSM_Clocks_I.Reset = '1') ELSE - '0' WHEN (Readout_Mode_manage = mode_IDLE) ELSE - '1' WHEN (FSM_STATE = s2_send_wpacket) and (is_hb_response = '1') and (is_hb_response_s = '1') ELSE - '1' WHEN (FSM_STATE = s2_send_wpacket) and (wcnt_fullpck_ff >= max_data_packet_payload) ELSE - '0'; - - - - cntpckfifo_data_toff <= (others => '0') WHEN (FSM_Clocks_I.Reset = '1') ELSE - - func_CNTPCKword_get_word('1', pages_counter, wcnt_fullpck, TRG_const_void, ORBIT_const_void, BC_const_void, current_hb_orbit, current_hb_bc) -- close frame - WHEN (FSM_STATE = s2_send_wpacket) and (cntpckws_state = s1_closefr_pcw) ELSE - - func_CNTPCKword_get_word('0', pages_counter, wcnt_fullpck, TRG_const_void, ORBIT_const_void, BC_const_void, current_hb_orbit, current_hb_bc) -- data overload - WHEN (FSM_STATE = s2_send_wpacket) and (wcnt_fullpck_ff >= max_data_packet_payload) ELSE - - func_CNTPCKword_get_word('0', pages_counter, wcnt_fullpck, trgfifo_out_trigger, trgfifo_out_orbit, trgfifo_out_bc, current_hb_orbit, current_hb_bc) -- trigger response - WHEN (FSM_STATE = s2_send_wpacket) ELSE - - - (others => '0'); - - - - - - --- Event counter ------------------------------------ -reset_drop_counters <= Control_register_I.reset_drophit_counter; --- reset_drop_counters <= '1' WHEN (FSM_Clocks_I.Reset = '1') ELSE - -- '1' WHEN (FIT_GBT_status_I.Start_run = '1') ELSE - -- '0'; - -data_rate_counter_next <= (others => '0') WHEN (FSM_Clocks_I.Reset = '1') ELSE - (others => '0') WHEN (FIT_GBT_status_I.BCID_from_CRU = x"001") ELSE - data_rate_counter + 1 WHEN (FSM_STATE = s1_dread) and (rdata_state = s1_header) and (is_sending_packet_ff = '1') ELSE - data_rate_counter; - -hits_send_porbit_next <= (others => '0') WHEN (FSM_Clocks_I.Reset = '1') ELSE - data_rate_counter WHEN (FIT_GBT_status_I.BCID_from_CRU = x"000") ELSE - hits_send_porbit; - - - -is_dropping_event <= '0' WHEN (FSM_Clocks_I.Reset = '1') ELSE - '0' WHEN (Readout_Mode_manage = mode_IDLE) ELSE - '1' WHEN (FSM_STATE = s1_dread) and (rdata_state = s1_header) and (SLCTFIFO_Is_spacefpacket_I = '0') ELSE --- '1' WHEN (FSM_STATE = s1_dread) and (rdata_state = s1_header) and (data_header_orbit_ff /= current_hb_orbit) ELSE - '0'; - -dropped_events_next <= (others => '0') WHEN (FSM_Clocks_I.Reset = '1') ELSE - (others => '0') WHEN (reset_drop_counters = '1') ELSE - dropped_events + 1 WHEN (is_dropping_event = '1') ELSE - dropped_events; - -last_dropped_orbit_next <= (others => '0') WHEN (FSM_Clocks_I.Reset = '1') ELSE - (others => '0') WHEN (reset_drop_counters = '1') ELSE - data_header_orbit_ff WHEN (is_dropping_event = '1') ELSE - last_dropped_orbit; - -last_dropped_bc_next <= (others => '0') WHEN (FSM_Clocks_I.Reset = '1') ELSE - (others => '0') WHEN (reset_drop_counters = '1') ELSE - data_header_bc_ff WHEN (is_dropping_event = '1') ELSE - last_dropped_bc; - -first_dropped_orbit_next <= (others => '0') WHEN (FSM_Clocks_I.Reset = '1') ELSE - (others => '0') WHEN (reset_drop_counters = '1') ELSE - data_header_orbit_ff WHEN (is_dropping_event = '1') and (last_dropped_orbit = ORBIT_const_void) ELSE - first_dropped_orbit; - -first_dropped_bc_next <= (others => '0') WHEN (FSM_Clocks_I.Reset = '1') ELSE - (others => '0') WHEN (reset_drop_counters = '1') ELSE - data_header_bc_ff WHEN (is_dropping_event = '1') and (last_dropped_orbit = ORBIT_const_void) ELSE - first_dropped_bc; - - - -- **************************************************** + read_data_cmd <= read_data; + read_trigger_cmd <= read_trigger; + is_hbtrg_cmd <= is_hbtrg and read_trigger; + rdh_close_cmd <= (is_hbtrg and read_trigger and hb_rdh_response) or (rdh_size_counter >= max_rdh_size) or send_last_rdh; + -- rejecting by trigger in TRG mode + data_reject_cmd <= (send_trg_mode_sc and not (trg_eq_data and is_sel_trg)) or (not data_enabled_sc); + data_ndwords_cmd <= data_ndwords; + dropping_data_cmd <= (slct_fifo_full = '1') or (cntpck_fifo_full = '1'); + if is_hb_r_trg and read_trigger then hb_reject_cmd <= true; + elsif is_hbtrg and read_trigger then hb_reject_cmd <= false; end if; + + else + + -- counting select timeout + if select_timeout < 7 then select_timeout <= select_timeout + 1; end if; + + end if; + + + if FSM_STATE = s1_select then + + word_counter <= (others => '0'); + + if is_hbtrg_cmd then + rdh_trigger <= trgfifo_out_trigger; + rdh_orbit <= trgfifo_out_orbit; + rdh_bc <= trgfifo_out_bc; + end if; + + if rdh_close_cmd then + if is_hbtrg_cmd then rdh_packet_counter <= 0; else rdh_packet_counter <= rdh_packet_counter + 1; end if; + rdh_size_counter <= 0; + end if; + + -- send_gear_rdh is true after first trigger read + send_last_rdh <= false; + if is_readout_sc and read_trigger_cmd then send_gear_rdh <= true; end if; + + if FSM_STATE_NEXT = s2_dread then reading_header <= true; end if; + + elsif FSM_STATE = s2_dread then + + reading_header <= false; + + -- iterating words while reading data + word_counter <= word_counter + 1; + + elsif FSM_STATE = s0_idle then + + -- readout is idle (delayed to wait fifo empty), trg_fifo is empty, and send_gear_rdh is true, send last rdh response + if not is_readout_ff3_sc and send_gear_rdh and (trgfifo_empty = '1') then send_gear_rdh <= false; send_last_rdh <= true; end if; + + + end if; + + -- counting rdh payload + if slct_fifo_wren = '1' then rdh_size_counter <= rdh_size_counter + 1; end if; + -- dropping packets counter + if reading_header and dropping_data_cmd and drop_counter < x"ffff" then drop_counter <= drop_counter + 1; end if; + if slct_fifo_wren = '1' and header_fifo_rd = '1' then event_counter <= event_counter + 1; end if; + if reset_dt_counters_sc then drop_counter <= (others => '0'); event_counter <= (others => '0'); end if; + -- errors if fifos are not empty while run starts + if start_of_run then fifo_notempty_while_start <= (not trgfifo_empty) & (not cntpck_fifo_empty) & (not slct_fifo_empty); end if; + + + -- zero event rate counter for ila triggering + -- if reset_dt_counters_sc then event_counter_zero_counter <= (others => '0'); + -- elsif event_counter = event_counter_ff then event_counter_zero_counter <= event_counter_zero_counter+1; + -- elsif event_counter /= event_counter_ff then event_counter_zero_counter <= (others => '0'); end if; + + + end if; + end if; + end process; +-- **************************************************** +-- SELECTOR decision +-- | TRG = 0 | DATA < CURR | read data | no trigger for data +-- | TRG > DATA | | read data | no trigger for data +-- | TRG < DATA | | read trigger | no data for trigger +-- | DATA = 0 | TRG /= 0 | read trigger | no data for trigger +-- | TRG = DATA | | read trigger and data | data match trigger + + is_hbtrg <= (trgfifo_empty = '0') and (trgfifo_out_trigger and TRG_const_HB) /= TRG_const_void; + is_hb_r_trg <= (trgfifo_empty = '0') and (trgfifo_out_trigger and TRG_const_HBr) /= TRG_const_void; + is_sox <= (trgfifo_empty = '0') and (trgfifo_out_trigger and (TRG_const_SOT or TRG_const_SOC)) /= TRG_const_void; + is_eox <= (trgfifo_empty = '0') and (trgfifo_out_trigger and (TRG_const_EOT or TRG_const_EOC)) /= TRG_const_void; + is_sel_trg <= (trgfifo_empty = '0') and (trgfifo_out_trigger and trigger_select_val_sc) /= TRG_const_void; + trg_eq_data <= (trgfifo_empty = '0') and (header_fifo_empty_i = '0') and (data_orbit = trgfifo_out_orbit) and (data_bc = trgfifo_out_bc) and (trgfifo_empty = '0') and (header_fifo_empty_i = '0'); + data_not_actual <= (header_fifo_empty_i = '0') and ((data_orbit > curr_orbit_p1_sc) or(data_orbit < curr_orbit_sc) or ((data_orbit = curr_orbit_sc) and (data_bc < curr_bc_sc))); + trg_not_actual <= (trgfifo_empty = '0') and ((trgfifo_out_orbit > curr_orbit_p1_sc) or (trgfifo_out_orbit < curr_orbit_sc) or ((trgfifo_out_orbit = curr_orbit_sc) and (trgfifo_out_bc < curr_bc_sc))); + trg_later_data <= (trgfifo_empty = '0') and (header_fifo_empty_i = '0') and ((data_orbit < trgfifo_out_orbit) or ((data_orbit = trgfifo_out_orbit) and (data_bc < trgfifo_out_bc))); + data_later_trg <= (trgfifo_empty = '0') and (header_fifo_empty_i = '0') and ((data_orbit > trgfifo_out_orbit) or ((data_orbit = trgfifo_out_orbit) and (data_bc > trgfifo_out_bc))); + +-- no data in fifo + read_data <= false when header_fifo_empty_i = '1' else + -- no trigger for data + true when (trgfifo_empty = '1') and data_not_actual else + -- trigger equal data + true when trg_eq_data else + -- no trigger for data + true when (trgfifo_empty = '0') and trg_later_data else + false; + +-- no trigger in fifo + read_trigger <= false when trgfifo_empty = '1' else + -- no data for trigger + true when header_fifo_empty_i = '1' and trg_not_actual else + true when data_later_trg else + -- trigger equal data + true when trg_eq_data else + false; + + FSM_STATE_NEXT <= + -- IDLE in BYPASS mode + s0_idle when readout_bypass else + -- START READING + s2_dread when (FSM_STATE = s1_select) and read_data_cmd else + -- IDLE after SELECT (trg read) + s0_idle when (FSM_STATE = s1_select) and not read_data_cmd else + + -- SELECT from IDLE + s1_select when (FSM_STATE = s0_idle) and start_select and (select_timeout > 2) else + -- SELECT from DREAD + s1_select when (FSM_STATE = s2_dread) and reading_last_word and start_select and (select_timeout > 2) else + + -- IDLE from DREAD + s0_idle when (FSM_STATE = s2_dread) and reading_last_word else + + -- SELECT last rdh + s1_select when (FSM_STATE = s0_idle) and send_last_rdh and (select_timeout > 2) else + + -- FSM state the same + FSM_STATE; + + + + + +-- reading data FSM + --reading_header <= word_counter = 0 and FSM_STATE = s2_dread; + reading_last_word <= FSM_STATE = s2_dread and word_counter = data_ndwords_cmd; + +-- stop bit for HB and last packet + stop_bit <= '1' when is_hbtrg_cmd else + '1' when send_last_rdh else + '0'; + +-- not reading trigger + trgfifo_re <= '1' when (FSM_STATE = s1_select) and read_trigger_cmd else '0'; + +-- pushing RDH info while closing RDH packet + cntpck_fifo_din <= std_logic_vector(to_unsigned(0, 128-97)) & stop_bit & std_logic_vector(to_unsigned(rdh_packet_counter, 8)) & std_logic_vector(to_unsigned(rdh_size_counter, 12)) & rdh_orbit & rdh_bc & rdh_trigger; + cntpck_fifo_wren <= '1' when (FSM_STATE = s1_select) and rdh_close_cmd and (send_gear_rdh or send_last_rdh) else '0'; + +-- reading header when counter 0 and fsm state is reading data + header_fifo_rd <= '1' when reading_header else '0'; +-- reading data when counter /= 0 and fsm state is reading data + data_fifo_rd <= '1' when not reading_header and FSM_STATE = s2_dread else '0'; + +-- pushing data from raw to slct fifo + slct_fifo_din <= header_fifo_data_i when reading_header else data_fifo_data_i; + slct_fifo_wren <= (header_fifo_rd or data_fifo_rd) when not data_reject_cmd and not (hb_reject_cmd and hb_reject) and not dropping_data_cmd else '0'; end Behavioral; diff --git a/firmware/common/gbt-readout/hdl/FIT_GBT_IPBUS_control.vhd b/firmware/common/gbt-readout/hdl/FIT_GBT_IPBUS_control.vhd deleted file mode 100644 index f1bac31..0000000 --- a/firmware/common/gbt-readout/hdl/FIT_GBT_IPBUS_control.vhd +++ /dev/null @@ -1,201 +0,0 @@ ----------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 11.10.2018 15:55:10 --- Design Name: --- Module Name: FIT_GBT_IPBUS_control - Behavioral --- Project Name: --- Target Devices: --- Tool Versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- - - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; -use IEEE.NUMERIC_STD.ALL; - -library unisim; -use unisim.vcomponents.all; - -library UNISIM; -use UNISIM.VComponents.all; - -library work; -use work.fit_gbt_common_package.all; - -entity FIT_GBT_IPBUS_control is - Port ( - reset_i : in std_logic; - DataClk_I : in STD_LOGIC; -- 40MHz data clock - RegClk_I : in std_logic; - - Reg_status_O : out STD_LOGIC_VECTOR (31 downto 0); - Rer_control_I : in STD_LOGIC_VECTOR (31 downto 0); - - FIT_Readout_status_I : in FIT_GBT_status_type; - FIT_Readout_control_O : out CONTROL_REGISTER_type - ); -end FIT_GBT_IPBUS_control; - -architecture Behavioral of FIT_GBT_IPBUS_control is - - - - signal ipbus_di, ipbus_do, ipbus_do_next : STD_LOGIC_VECTOR (31 downto 0); - signal ipbus_ack, ipbus_err :std_logic; - - -- | DataClk_I | IPBUS clock | - -- -|> FIT_GBT_status_I -#-> ipbus_status_reg_map -> ipbus_status_reg_map_dc -|-> ipbus_status_reg_ipbclk -> IBBUS | - - -- <|- Control_register_reg_dc <-|- Control_register_reg_map_ipbclk <-#- ipbus_control_reg <- IBBUS | - -- -|> Control_register_reg_dc -#-> Control_register_rdmap_dc -|-> Control_register_rdmap_ipbclk -> IBBUS | - - signal Control_register_reg_map_ipbclk, Control_register_reg_dc : CONTROL_REGISTER_type; - signal ipbus_control_reg, Control_register_rdmap_dc, Control_register_rdmap_ipbclk : cntr_reg_addrreg_type; - signal ipbus_status_reg_map, ipbus_status_reg_map_dc, ipbus_status_reg_ipbclk : status_reg_addrreg_type; - signal ipbus_arrd_int : integer := 0; - signal ipbus_base_arrd_int : integer := 0; - - -- test debug signals - signal debug_ipb_clk :std_logic; - signal debug_ipb_rst :std_logic; - signal debug_ipb_iswr :std_logic; - signal debug_ipb_isrd :std_logic; - signal debug_ipb_ack :std_logic; - signal debug_ipb_err :std_logic; - signal debug_ipb_data_O : std_logic_vector (31 downto 0); - signal debug_ipb_data_I :std_logic_vector (31 downto 0); - signal debug_ipb_addr :std_logic_vector (11 downto 0); - - attribute keep : string; - attribute keep of debug_ipb_clk : signal is "true"; - attribute keep of debug_ipb_rst : signal is "true"; - attribute keep of debug_ipb_iswr : signal is "true"; - attribute keep of debug_ipb_isrd : signal is "true"; - attribute keep of debug_ipb_ack : signal is "true"; - attribute keep of debug_ipb_err : signal is "true"; - attribute keep of debug_ipb_data_O : signal is "true"; - attribute keep of debug_ipb_data_I : signal is "true"; - attribute keep of debug_ipb_addr : signal is "true"; - - attribute keep of ipbus_control_reg : signal is "true"; - attribute keep of ipbus_status_reg_map_dc : signal is "true"; - - attribute keep of Control_register_rdmap_ipbclk : signal is "true"; - attribute keep of Control_register_reg_map_ipbclk : signal is "true"; - attribute keep of ipbus_status_reg_ipbclk : signal is "true"; - attribute keep of ipbus_status_reg_map : signal is "true"; - attribute keep of Control_register_reg_dc : signal is "true"; - -begin - --- debug signal assignement - debug_ipb_clk <= DataClk_I; - debug_ipb_rst <= IPBUS_rst_I; - debug_ipb_iswr <= IPBUS_iswr_I; - debug_ipb_isrd <= IPBUS_isrd_I; - debug_ipb_ack <= ipbus_ack; - debug_ipb_err <= ipbus_err; - debug_ipb_data_O <= ipbus_do; - debug_ipb_data_I <= IPBUS_data_in_I; - debug_ipb_addr <= IPBUS_addr_I; - - -ipbus_di <= IPBUS_data_in_I; -IPBUS_data_out_O <= ipbus_do; -IPBUS_ack_O <= ipbus_ack; -IPBUS_err_O <= ipbus_err; -Control_register_O <= Control_register_reg_dc; - - --- Control_register_reg_map_ipbclk <= test_CONTROL_REG WHEN (IPBUS_rst_I = '1') ELSE func_CNTRREG_getcntrreg(ipbus_control_reg); -Control_register_reg_map_ipbclk <= func_CNTRREG_getcntrreg(ipbus_control_reg); - -Control_register_rdmap_dc <= func_CNTRREG_getaddrreg(Control_register_reg_dc); -ipbus_status_reg_map <= func_STATREG_getaddrreg(FIT_GBT_status_I); - -ipbus_arrd_int <= to_integer(unsigned(IPBUS_addr_I)); -ipbus_base_arrd_int <= to_integer(unsigned(IPBUS_base_addr_I)); - - --- IP-BUS register *********************************** - PROCESS (DataClk_I) - BEGIN - IF(DataClk_I'EVENT and DataClk_I = '1') THEN - - IF(IPBUS_rst_I = '1') THEN - Control_register_reg_dc <= test_CONTROL_REG; - ELSE - Control_register_reg_dc <= Control_register_reg_map_ipbclk; - ipbus_status_reg_map_dc <= ipbus_status_reg_map; - END IF; - - END IF; - END PROCESS; - - - --- IP-BUS register *********************************** - PROCESS (IPBUS_clk_I) - BEGIN - IF(IPBUS_clk_I'EVENT and IPBUS_clk_I = '1') THEN - - ipbus_status_reg_ipbclk <= ipbus_status_reg_map_dc; - Control_register_rdmap_ipbclk <= Control_register_rdmap_dc; - - IF(IPBUS_rst_I = '1') THEN - ipbus_control_reg <= func_CNTRREG_getaddrreg(test_CONTROL_REG); - - ELSIF(IPBUS_isrd_I = '1') THEN - - -- if(ipbus_ack = '1') then - -- if(ipbus_arrd_int < cntr_reg_n_32word) then - -- ipbus_do <= Control_register_rdmap_ipbclk(ipbus_arrd_int); - -- else - -- ipbus_do <= ipbus_status_reg_ipbclk(ipbus_arrd_int - cntr_reg_n_32word); - -- end if; - - -- end if; - - ELSIF(IPBUS_iswr_I = '1') THEN - - if(ipbus_ack = '1') then - ipbus_control_reg(ipbus_arrd_int) <= ipbus_di; - end if; - - ELSE - - END IF; - - END IF; - END PROCESS; --- *************************************************** - - --- FSM *********************************************** -ipbus_err <= '0'; -ipbus_ack <='0' WHEN (IPBUS_rst_I = '1') ELSE - '1' WHEN (IPBUS_isrd_I = '1') and (ipbus_arrd_int < (cntr_reg_n_32word + status_reg_n_32word) ) ELSE - '1' WHEN (IPBUS_iswr_I = '1') and (ipbus_arrd_int < (cntr_reg_n_32word) ) ELSE - '0'; - -ipbus_do <= (others => '0') WHEN (IPBUS_rst_I = '1') ELSE - (others => '0') WHEN ( ipbus_ack = '0') ELSE - Control_register_rdmap_ipbclk(ipbus_arrd_int) WHEN (ipbus_arrd_int < cntr_reg_n_32word) ELSE - ipbus_status_reg_ipbclk(ipbus_arrd_int - cntr_reg_n_32word); - - -end Behavioral; - - - diff --git a/firmware/common/gbt-readout/hdl/FIT_GBT_project.vhd b/firmware/common/gbt-readout/hdl/FIT_GBT_project.vhd index 61f85d1..a065f8f 100644 --- a/firmware/common/gbt-readout/hdl/FIT_GBT_project.vhd +++ b/firmware/common/gbt-readout/hdl/FIT_GBT_project.vhd @@ -1,384 +1,484 @@ ---------------------------------------------------------------------------------- -- Company: INR RAS --- Engineer: Finogeev D.A. dmitry-finogeev@yandex.ru +-- Engineer: Finogeev D. A. dmitry-finogeev@yandex.ru -- --- Create Date: 10:29:21 01/09/2017 --- Design Name: FIT GBT --- Module Name: FIT_GBT_project - Behavioral --- Project Name: --- Target Devices: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: +-- Create Date: 2017 +-- Description: TOP FIT GBT readout module -- +-- Revision: 07/2021 ---------------------------------------------------------------------------------- library IEEE; -use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_1164.all; use work.all; use work.fit_gbt_common_package.all; use work.fit_gbt_board_package.all; entity FIT_GBT_project is - generic ( - GENERATE_GBT_BANK : integer := 1 - ); - - Port ( - RESET_I : in STD_LOGIC; - SysClk_I : in STD_LOGIC; -- 320MHz system clock - DataClk_I : in STD_LOGIC; -- 40MHz data clock - MgtRefClk_I : in STD_LOGIC; -- 200MHz ref clock - RxDataClk_I : in STD_LOGIC; -- 40MHz data clock in RX domain --- FabricClk_I : in STD_LOGIC; -- GBT fabric clk - GBT_RxFrameClk_O : out STD_LOGIC; --Rx GBT frame clk 40MHz - - Board_data_I : in board_data_type; --PM or TCM data - Control_register_I : in CONTROL_REGISTER_type; - - MGT_RX_P_I : in STD_LOGIC; - MGT_RX_N_I : in STD_LOGIC; - MGT_TX_P_O : out STD_LOGIC; - MGT_TX_N_O : out STD_LOGIC; - MGT_TX_dsbl_O : out STD_LOGIC; - - -- GBT data to/from FIT readout - RxData_rxclk_to_FITrd_I : in std_logic_vector(GBT_data_word_bitdepth-1 downto 0); - IsRxData_rxclk_to_FITrd_I : in STD_LOGIC; - Data_from_FITrd_O : out std_logic_vector(GBT_data_word_bitdepth-1 downto 0); - IsData_from_FITrd_O : out STD_LOGIC; - - -- GBT data to/from GBT project - Data_to_GBT_I : in std_logic_vector(GBT_data_word_bitdepth-1 downto 0); - IsData_to_GBT_I : in STD_LOGIC; - RxData_rxclk_from_GBT_O : out std_logic_vector(GBT_data_word_bitdepth-1 downto 0); - IsRxData_rxclk_from_GBT_O : out STD_LOGIC; - - -- FIT readour status, including BCOR_ID to PM/TCM - FIT_GBT_status_O : out FIT_GBT_status_type; - rx_ph320 : out std_logic_vector(2 downto 0); - ph_error320 : out std_logic - - - --GPIO_O : out std_logic_vector(15 downto 0) - ); + generic ( + IS_SIMULATION : integer := 0 + ); + + port ( + RESET_I : in std_logic; + SysClk_I : in std_logic; -- 320MHz system clock + DataClk_I : in std_logic; -- 40MHz data clock + MgtRefClk_I : in std_logic; -- 200MHz ref clock + RxDataClk_I : in std_logic; -- 40MHz data clock in RX domain + GBT_RxFrameClk_O : out std_logic; --Rx GBT frame clk 40MHz + FSM_Clocks_O : out rdclocks_t; + + IPbusClk_I : in std_logic; -- IPbus clock for error fifo read + err_report_fifo_rden_i : in std_logic; -- IPbus error report fifo read enable + + Board_data_I : in board_data_type; --PM or TCM data @320MHz + Control_register_I : in readout_control_t; -- control registers @DataClk + errors_rden_I : in std_logic; -- status register EA (errors) was read + + MGT_RX_P_I : in std_logic; + MGT_RX_N_I : in std_logic; + MGT_TX_P_O : out std_logic; + MGT_TX_N_O : out std_logic; + MGT_TX_dsbl_O : out std_logic; + + -- GBT data to/from FIT readout + RxData_rxclk_to_FITrd_I : in std_logic_vector(GBT_data_word_bitdepth-1 downto 0); + IsRxData_rxclk_to_FITrd_I : in std_logic; + Data_from_FITrd_O : out std_logic_vector(GBT_data_word_bitdepth-1 downto 0); + IsData_from_FITrd_O : out std_logic; + + -- GBT data to/from GBT project + Data_to_GBT_I : in std_logic_vector(GBT_data_word_bitdepth-1 downto 0); + IsData_to_GBT_I : in std_logic; + RxData_rxclk_from_GBT_O : out std_logic_vector(GBT_data_word_bitdepth-1 downto 0); + IsRxData_rxclk_from_GBT_O : out std_logic; + + -- FIT readour status, including BCOR_ID to PM/TCM + readout_status_o : out readout_status_t + ); end FIT_GBT_project; architecture Behavioral of FIT_GBT_project is -- reset signals -signal FSM_Clocks : FSM_Clocks_type; -signal reset_to_syscount, reset_to_syscount40 : std_logic; -signal gbt_reset, reset_l : std_logic; -signal Is_SysClkCounter_ready : std_logic; + signal FSM_Clocks : rdclocks_t; + signal gbt_reset : std_logic; + +-- GBT data + signal RX_IsData_DataClk : std_logic; + signal RX_exData_from_RXsync : std_logic_vector(GBT_data_word_bitdepth+GBT_slowcntr_bitdepth-1 downto 0); + signal RX_Data_DataClk : std_logic_vector(GBT_data_word_bitdepth-1 downto 0); + signal RX_IsData_from_orbcgen : std_logic; + signal RX_Data_from_orbcgen : std_logic_vector(GBT_data_word_bitdepth-1 downto 0); + signal TX_IsData_from_txgen : std_logic; + signal TX_Data_from_txgen : std_logic_vector(GBT_data_word_bitdepth-1 downto 0); + signal RX_IsData_rxclk_from_GBT : std_logic; + signal RX_Data_rxclk_from_GBT : std_logic_vector(GBT_data_word_bitdepth-1 downto 0); + signal data_from_cru_constructor : std_logic_vector(GBT_data_word_bitdepth-1 downto 0); + signal is_data_from_cru_constructor : std_logic; + signal RxData_rxclk_to_FITrd_ext : std_logic_vector(GBT_data_word_bitdepth+4-1 downto 0); --- from rx sync -signal RX_IsData_DataClk : std_logic; -signal RX_exData_from_RXsync : std_logic_vector(GBT_data_word_bitdepth+GBT_slowcntr_bitdepth-1 downto 0); +-- status + signal from_gbt_bank_prj_GBT_status : gbt_status_t; + signal FIT_GBT_STATUS : readout_status_t; + signal ORBC_ID_from_RXdecoder : std_logic_vector(Orbit_id_bitdepth + BC_id_bitdepth-1 downto 0); -- EVENT ID from CRUS + signal ORBC_ID_corrected_from_RXdecoder : std_logic_vector(Orbit_id_bitdepth + BC_id_bitdepth-1 downto 0); -- EVENT ID to PM/TCM + signal errors_scl : std_logic_vector(15 downto 0); + signal readout_status_scl : readout_status_t; + signal readout_control_db : readout_control_t; -signal RX_Data_DataClk : std_logic_vector(GBT_data_word_bitdepth-1 downto 0); -signal RX_Phase_Counter : std_logic_vector(rx_phase_bitdepth-1 downto 0); --- status -signal from_gbt_bank_prj_GBT_status : Type_GBT_status; -signal FIT_GBT_STATUS : FIT_GBT_status_type; --- from data generator -signal Board_data_from_main_gen : board_data_type; -signal RX_IsData_from_orbcgen : std_logic; -signal RX_Data_from_orbcgen : std_logic_vector(GBT_data_word_bitdepth-1 downto 0); --- from rx data decoder -signal ORBC_ID_from_RXdecoder : std_logic_vector(Orbit_id_bitdepth + BC_id_bitdepth-1 downto 0); -- EVENT ID from CRUS -signal ORBC_ID_corrected_from_RXdecoder : std_logic_vector(Orbit_id_bitdepth + BC_id_bitdepth-1 downto 0); -- EVENT ID to PM/TCM -signal Trigger_from_RXdecoder : std_logic_vector(Trigger_bitdepth-1 downto 0); -signal Readout_Mode_from_RXdecoder : Type_Readout_Mode; -signal CRU_Readout_Mode_from_RXdecoder : Type_Readout_Mode; -signal Start_run_from_RXdecoder : std_logic; -signal Stop_run_from_RXdecoder : std_logic; -signal BCIDsync_Mode_from_RXdecoder : Type_BCIDsync_Mode; +-- data packager + signal raw_header_dout, raw_data_dout : std_logic_vector(GBT_data_word_bitdepth-1 downto 0); + signal raw_heaer_rden, raw_data_rden, raw_header_empty, raw_data_empty : std_logic; + signal no_raw_data, no_sel_data : boolean; + + signal raw_data : std_logic_vector(GBT_data_word_bitdepth-1 downto 0); + signal raw_isdata : std_logic; + signal data_bcid : std_logic_vector(BC_id_bitdepth-1 downto 0); + signal data_bcen : std_logic; + --- from data packajer -signal TX_IsData_from_packager : std_logic; -signal TX_Data_from_packager : std_logic_vector(GBT_data_word_bitdepth-1 downto 0); + signal slct_fifo_dout : std_logic_vector(GBT_data_word_bitdepth-1 downto 0); + signal slct_fifo_empty : std_logic; + signal slct_fifo_rden : std_logic; --- from GBT Rx -signal RX_IsData_rxclk_from_GBT : std_logic; -signal RX_Data_rxclk_from_GBT : std_logic_vector(GBT_data_word_bitdepth-1 downto 0); -signal RX_ErrDet_latch, RX_ErrDet_latch_next : std_logic; + signal cntpck_fifo_dout : std_logic_vector(127 downto 0); + signal cntpck_fifo_empty : std_logic; + signal cntpck_fifo_rden : std_logic; + + signal error_report_fifo_empty : std_logic; + +-- from data generator + signal Board_data_from_main_gen : board_data_type; -attribute mark_debug : string; -attribute mark_debug of Board_data_from_main_gen : signal is "true"; -attribute mark_debug of RX_IsData_DataClk : signal is "true"; -attribute mark_debug of RX_Data_DataClk : signal is "true"; -attribute mark_debug of TX_IsData_from_packager : signal is "true"; -attribute mark_debug of TX_Data_from_packager : signal is "true"; -attribute mark_debug of RX_IsData_from_orbcgen : signal is "true"; -attribute mark_debug of RX_Data_from_orbcgen : signal is "true"; + -- attribute mark_debug : string; + -- attribute mark_debug of Board_data_from_main_gen : signal is "true"; + -- attribute mark_debug of RX_Data_DataClk : signal is "true"; + -- attribute mark_debug of RX_IsData_DataClk : signal is "true"; + -- attribute mark_debug of errors_scl : signal is "true"; + -- attribute mark_debug of FIT_GBT_STATUS : signal is "true"; + -- attribute mark_debug of readout_status_scl : signal is "true"; + -- attribute mark_debug of readout_control_db : signal is "true"; begin -- WIRING ====================================================== - FSM_Clocks.System_Clk <= SysClk_I; - FSM_Clocks.Data_Clk <= DataClk_I; - - -- SFP turned ON - MGT_TX_dsbl_O <= '0'; - - -- Status - FIT_GBT_status_O <= FIT_GBT_STATUS; - - FIT_GBT_STATUS.GBT_status <= from_gbt_bank_prj_GBT_status; - FIT_GBT_STATUS.Readout_Mode <= Readout_Mode_from_RXdecoder; - FIT_GBT_STATUS.CRU_Readout_Mode <= CRU_Readout_Mode_from_RXdecoder; - FIT_GBT_STATUS.BCIDsync_Mode <= BCIDsync_Mode_from_RXdecoder; - FIT_GBT_STATUS.Start_run <= Start_run_from_RXdecoder; - FIT_GBT_STATUS.Stop_run <= Stop_run_from_RXdecoder; - - FIT_GBT_STATUS.Trigger_from_CRU <= Trigger_from_RXdecoder; - FIT_GBT_STATUS.BCID_from_CRU <= ORBC_ID_from_RXdecoder(BC_id_bitdepth-1 downto 0); - FIT_GBT_STATUS.ORBIT_from_CRU <= ORBC_ID_from_RXdecoder(Orbit_id_bitdepth + BC_id_bitdepth-1 downto BC_id_bitdepth); - FIT_GBT_STATUS.BCID_from_CRU_corrected <= ORBC_ID_corrected_from_RXdecoder(BC_id_bitdepth-1 downto 0); - FIT_GBT_STATUS.ORBIT_from_CRU_corrected <= ORBC_ID_corrected_from_RXdecoder(Orbit_id_bitdepth + BC_id_bitdepth-1 downto BC_id_bitdepth); - - FIT_GBT_STATUS.rx_phase <= RX_Phase_Counter; - - - - - - RX_Data_DataClk <= RX_exData_from_RXsync(GBT_data_word_bitdepth-1 downto 0); - - Data_from_FITrd_O <= TX_Data_from_packager WHEN (Control_register_I.Trigger_Gen.usage_generator /= use_TX_generator) ELSE RX_Data_from_orbcgen; - IsData_from_FITrd_O <= TX_IsData_from_packager WHEN (Control_register_I.Trigger_Gen.usage_generator /= use_TX_generator) ELSE RX_IsData_from_orbcgen; - - - RxData_rxclk_from_GBT_O <= RX_Data_rxclk_from_GBT; - IsRxData_rxclk_from_GBT_O <= RX_IsData_rxclk_from_GBT; + FSM_Clocks_O <= FSM_Clocks; + FSM_Clocks.System_Clk <= SysClk_I; + FSM_Clocks.Data_Clk <= DataClk_I; + FSM_Clocks.Data_Clk <= DataClk_I; + FSM_Clocks.ipbus_clk <= IPbusClk_I; + + -- SFP turned ON + MGT_TX_dsbl_O <= '0'; + + -- Status + readout_status_o <= FIT_GBT_STATUS; + FIT_GBT_STATUS.GBT_status <= from_gbt_bank_prj_GBT_status; + FIT_GBT_STATUS.BCID_from_CRU <= ORBC_ID_from_RXdecoder(BC_id_bitdepth-1 downto 0); + FIT_GBT_STATUS.ORBIT_from_CRU <= ORBC_ID_from_RXdecoder(Orbit_id_bitdepth + BC_id_bitdepth-1 downto BC_id_bitdepth); + FIT_GBT_STATUS.BCID_from_CRU_corrected <= ORBC_ID_corrected_from_RXdecoder(BC_id_bitdepth-1 downto 0); + FIT_GBT_STATUS.ORBIT_from_CRU_corrected <= ORBC_ID_corrected_from_RXdecoder(Orbit_id_bitdepth + BC_id_bitdepth-1 downto BC_id_bitdepth); + FIT_GBT_STATUS.fsm_errors(14 downto 12) <= (others => '0'); + FIT_GBT_STATUS.fsm_errors(15) <= '0' when no_raw_data and no_sel_data else '1'; + FIT_GBT_STATUS.fifos_empty(7 downto 6) <= (others => '0'); + FIT_GBT_STATUS.ipbusrd_fifo_cnt <= (others => '0'); + FIT_GBT_STATUS.ipbusrd_fifo_out <= (others => '0'); + + + RX_Data_DataClk <= RX_exData_from_RXsync(GBT_data_word_bitdepth-1 downto 0); + Data_from_FITrd_O <= TX_Data_from_txgen when (Control_register_I.Trigger_Gen.usage_generator /= gen_tx_out) else RX_Data_from_orbcgen; + IsData_from_FITrd_O <= TX_IsData_from_txgen when (Control_register_I.Trigger_Gen.usage_generator /= gen_tx_out) else RX_IsData_from_orbcgen; + RxData_rxclk_from_GBT_O <= RX_Data_rxclk_from_GBT; + IsRxData_rxclk_from_GBT_O <= RX_IsData_rxclk_from_GBT; + + -- errors by sys clock for ila + process (SysClk_I) + begin + if(rising_edge(SysClk_I))then + -- errors_scl <= FIT_GBT_STATUS.fsm_errors; + -- readout_status_scl <= FIT_GBT_STATUS; + end if; + end process; + + -- fifos empty bits 320 -> 40 for status + process (DataClk_I) + begin + if(rising_edge(DataClk_I))then + -- readout_control_db <= Control_register_I; + + FIT_GBT_STATUS.fifos_empty(0) <= raw_header_empty; + FIT_GBT_STATUS.fifos_empty(1) <= raw_data_empty; + FIT_GBT_STATUS.fifos_empty(3) <= slct_fifo_empty; + FIT_GBT_STATUS.fifos_empty(4) <= cntpck_fifo_empty; + FIT_GBT_STATUS.fifos_empty(5) <= error_report_fifo_empty; + end if; + end process; -- ============================================================= -- Reset FSM ================================================= -Reset_Generator_comp: entity work.Reset_Generator -port map( - RESET_I => RESET_I, - SysClk_I => SysClk_I, - DataClk_I => DataClk_I, - Sys_Cntr_ready_I => Is_SysClkCounter_ready, - Reset_DClk_O => reset_to_syscount, - General_reset_O => FSM_Clocks.Reset, - Reset_DClk40_O => reset_to_syscount40, - General_reset40_O => FSM_Clocks.Reset40 - ); --- =========================================================== + Reset_Generator_comp : entity work.Reset_Generator + port map( + RESET40_I => RESET_I, + SysClk_I => SysClk_I, + DataClk_I => DataClk_I, + + Control_register_I => Control_register_I, + gbt_not_ready_I => from_gbt_bank_prj_GBT_status.gbt_not_ready, + + SysClk_count_O => FSM_Clocks.System_Counter, + + Reset_DClk_O => FSM_Clocks.Reset_dclk, + Reset_SClk_O => FSM_Clocks.Reset_sclk, + ResetGBT_O => gbt_reset + ); +-- ============================================================= --- Data Clk strobe =========================================== -DataClk_I_strobe_comp: entity work.DataClk_strobe -port map( - RESET_I => reset_to_syscount, - RESET40_I => reset_to_syscount40, - SysClk_I => SysClk_I, - DataClk_I => DataClk_I, - SysClk_count_O => FSM_Clocks.System_Counter, - Counter_ready_O => Is_SysClkCounter_ready - ); --- =========================================================== -- RX Data Clk Sync ============================================ -RxData_ClkSync_comp : entity work.RXDATA_CLKSync -port map ( - FSM_Clocks_I => FSM_Clocks, - Control_register_I => Control_register_I, - - RX_CLK_I => RxDataClk_I, - - RX_IS_DATA_RXCLK_I => IsRxData_rxclk_to_FITrd_I, - RX_DATA_RXCLK_I => x"0" & RxData_rxclk_to_FITrd_I, - RX_IS_DATA_DATACLK_O => RX_IsData_DataClk, - RX_DATA_DataClk_O => RX_exData_from_RXsync, - CLK_PH_CNT_O => RX_Phase_Counter, - CLK_PH_ERROR_O => FIT_GBT_STATUS.GBT_status.Rx_Phase_error, - rx_ph320 => rx_ph320, - ph_error320 => ph_error320 -); + RxData_ClkSync_comp : entity work.RXDATA_CLKSync + port map ( + FSM_Clocks_I => FSM_Clocks, + Control_register_I => Control_register_I, + + RX_CLK_I => RxDataClk_I, + + RX_IS_DATA_RXCLK_I => IsRxData_rxclk_to_FITrd_I, + RX_DATA_RXCLK_I => RxData_rxclk_to_FITrd_ext, + RX_IS_DATA_DATACLK_O => RX_IsData_DataClk, + RX_DATA_DataClk_O => RX_exData_from_RXsync, + CLK_PH_CNT_O => FIT_GBT_STATUS.rx_phase, + CLK_PH_ERROR_O => FIT_GBT_STATUS.Rx_Phase_error + ); + RxData_rxclk_to_FITrd_ext <= x"0" & RxData_rxclk_to_FITrd_I; -- ============================================================= -- RX Data Decoder ============================================ -RX_Data_Decoder_comp : entity work.RX_Data_Decoder -Port map ( - FSM_Clocks_I => FSM_Clocks, - - FIT_GBT_status_I => FIT_GBT_STATUS, - Control_register_I => Control_register_I, - - RX_IsData_I => RX_IsData_from_orbcgen, - RX_Data_I => RX_Data_from_orbcgen, - - ORBC_ID_from_CRU_O => ORBC_ID_from_RXdecoder, - ORBC_ID_from_CRU_corrected_O => ORBC_ID_corrected_from_RXdecoder, - Trigger_O => Trigger_from_RXdecoder, - - Readout_Mode_O => Readout_Mode_from_RXdecoder, - CRU_Readout_Mode_O => CRU_Readout_Mode_from_RXdecoder, - Start_run_O => Start_run_from_RXdecoder, - Stop_run_O => Stop_run_from_RXdecoder, - BCIDsync_Mode_O => BCIDsync_Mode_from_RXdecoder - ); + ltu_rx_decoder_comp : entity work.ltu_rx_decoder + port map ( + FSM_Clocks_I => FSM_Clocks, + Status_register_I => FIT_GBT_STATUS, + Control_register_I => Control_register_I, + + RX_IsData_I => RX_IsData_from_orbcgen, + RX_Data_I => RX_Data_from_orbcgen, + + ORBC_ID_from_CRU_O => ORBC_ID_from_RXdecoder, + ORBC_ID_from_CRU_corrected_O => ORBC_ID_corrected_from_RXdecoder, + ORBC_ID_from_CRU_sync_O => FIT_GBT_STATUS.ORBC_from_CRU_sync, + + Trigger_O => FIT_GBT_STATUS.Trigger_from_CRU, + trg_match_resp_mask_o => FIT_GBT_STATUS.trg_match_resp_mask, + laser_start_o => FIT_GBT_STATUS.laser_start, + + Readout_Mode_O => FIT_GBT_STATUS.Readout_Mode, + CRU_Readout_Mode_O => FIT_GBT_STATUS.CRU_Readout_Mode, + Start_run_O => FIT_GBT_STATUS.Start_run, + Stop_run_O => FIT_GBT_STATUS.Stop_run, + BCIDsync_Mode_O => FIT_GBT_STATUS.BCIDsync_Mode, + Data_enable_o => FIT_GBT_STATUS.data_enable, + apply_bc_delay_o => FIT_GBT_STATUS.bc_delay_apply, + + bcsync_lost_inrun_o => FIT_GBT_STATUS.fsm_errors(10), + bcsync_lost_flag_o => FIT_GBT_STATUS.bcsync_lost_flag, + bcsync_lost_cnt_o => FIT_GBT_STATUS.bcsync_lost_cnt, + + bcsyncl_outrun_reset_i => errors_rden_I, + bcsync_lost_outrun_o => FIT_GBT_STATUS.fsm_errors(11) + ); -- ============================================================= +-- DATA BC INDICATOR ===================================== + bc_indicator_data_comp : entity work.bc_indicator + generic map(USE_SYSCLK => true) + port map( + FSM_Clocks_I => FSM_Clocks, + Control_register_I => Control_register_I, + bcid_i => data_bcid, + bcen_i => data_bcen, + indicator_o => FIT_GBT_STATUS.bcind_evt + ); +-- ===================================================== + +-- TRI BC INDICATOR ===================================== + bc_indicator_trg_comp : entity work.bc_indicator + generic map(USE_SYSCLK => false) + port map( + FSM_Clocks_I => FSM_Clocks, + Control_register_I => Control_register_I, + bcid_i => FIT_GBT_STATUS.BCID_from_CRU, + bcen_i => FIT_GBT_STATUS.trg_match_resp_mask, + indicator_o => FIT_GBT_STATUS.bcind_trg + ); +-- ===================================================== + -- DATA GENERATOR ===================================== -Module_Data_Gen_comp : entity work.Module_Data_Gen - - Port map( - FSM_Clocks_I => FSM_Clocks, - - FIT_GBT_status_I => FIT_GBT_STATUS, - Control_register_I => Control_register_I, - - Board_data_I => Board_data_I, - Board_data_O => Board_data_from_main_gen, - - data_gen_report_O => FIT_GBT_STATUS.Data_gen_report - ); + Module_Data_Gen_comp : entity work.Module_Data_Gen + generic map(IS_SIMULATION => IS_SIMULATION) + port map( + FSM_Clocks_I => FSM_Clocks, + + Status_register_I => FIT_GBT_STATUS, + Control_register_I => Control_register_I, + + Board_data_I => Board_data_I, + Board_data_O => Board_data_from_main_gen, + + datagen_report_o => FIT_GBT_STATUS.datagen_report + ); -- ===================================================== -- CRU ORBC GENERATOR ================================== -CRU_ORBC_Gen_comp : entity work.CRU_ORBC_Gen - - Port map( - FSM_Clocks_I => FSM_Clocks, - - FIT_GBT_status_I => FIT_GBT_STATUS, - Control_register_I => Control_register_I, - - RX_IsData_I => RX_IsData_DataClk, - RX_Data_I => RX_Data_DataClk, - - RX_IsData_O => RX_IsData_from_orbcgen, - RX_Data_O => RX_Data_from_orbcgen, - - Current_BCID_from_O => open, - Current_ORBIT_from_O=> open, - Current_Trigger_from_O => open - - ); + cru_ltu_emu_comp : entity work.cru_ltu_emu + + port map( + FSM_Clocks_I => FSM_Clocks, + + Status_register_I => FIT_GBT_STATUS, + Control_register_I => Control_register_I, + + RX_IsData_I => RX_IsData_DataClk, + RX_Data_I => RX_Data_DataClk, + + RX_IsData_O => RX_IsData_from_orbcgen, + RX_Data_O => RX_Data_from_orbcgen + ); -- ===================================================== +-- Data Converter =============================================== + DataConverter_comp : entity work.DataConverter + port map( + FSM_Clocks_I => FSM_Clocks, + + Status_register_I => FIT_GBT_STATUS, + Control_register_I => Control_register_I, + + Board_data_I => Board_data_from_main_gen, + + header_fifo_data_o => raw_header_dout, + data_fifo_data_o => raw_data_dout, + header_fifo_rden_i => raw_heaer_rden, + data_fifo_rden_i => raw_data_rden, + header_fifo_empty_o => raw_header_empty, + data_fifo_empty_o => raw_data_empty, + no_data_o => no_raw_data, + + drop_ounter_o => FIT_GBT_STATUS.cnv_drop_cnt, + fifo_cnt_max_o => FIT_GBT_STATUS.cnv_fifo_max, + + raw_data_o => raw_data, + raw_isdata_o => raw_isdata, + data_bcid_o => data_bcid, + data_bcen_o => data_bcen, + + pm_data_shreg_o => FIT_GBT_STATUS.pm_data_buff, + rawdatfifo_rd_rate_o => FIT_GBT_STATUS.rawdatfifo_rd_rate, + rawdatfifo_wr_rate_o => FIT_GBT_STATUS.rawdatfifo_wr_rate, + + errors_o => FIT_GBT_STATUS.fsm_errors(9 downto 5) + ); +-- =========================================================== --- Data Packager =============================================== -Data_Packager_comp : entity work.Data_Packager -port map ( - FSM_Clocks_I => FSM_Clocks, - - FIT_GBT_status_I => FIT_GBT_STATUS, - Control_register_I => Control_register_I, - - Board_data_I => Board_data_from_main_gen, - - fifo_status_O => FIT_GBT_STATUS.fifo_status, - hits_rd_counter_converter_O => FIT_GBT_STATUS.hits_rd_counter_converter, - hits_rd_counter_selector_O => FIT_GBT_STATUS.hits_rd_counter_selector, - - TX_Data_O => TX_Data_from_packager, - TX_IsData_O => TX_IsData_from_packager --- GPIO_O => GPIO_O -); --- ============================================================= +-- Event Selector ====================================== + Event_Selector_comp : entity work.Event_Selector + port map ( + FSM_Clocks_I => FSM_Clocks, + Status_register_I => FIT_GBT_STATUS, + Control_register_I => Control_register_I, + header_fifo_data_i => raw_header_dout, + data_fifo_data_i => raw_data_dout, + header_fifo_rden_o => raw_heaer_rden, + data_fifo_rden_o => raw_data_rden, + header_fifo_empty_i => raw_header_empty, + raw_data_i => raw_data, + raw_isdata_i => raw_isdata, --- Data ff data clk ********************************** - process (FSM_Clocks.Data_Clk) - begin - - - IF(rising_edge(FSM_Clocks.Data_Clk) )THEN - reset_l<=Control_register_I.reset_gbt; - - IF (FSM_Clocks.Reset40 = '1') THEN - RX_ErrDet_latch <= '0'; - ELSE - RX_ErrDet_latch <= RX_ErrDet_latch_next; - END IF; - END IF; - - end process; - - FIT_GBT_STATUS.GBT_status.gbtRx_ErrorLatch <= RX_ErrDet_latch; - - RX_ErrDet_latch_next <= '0' WHEN FSM_Clocks.Reset = '1' ELSE - '0' WHEN (Control_register_I.reset_gbt_rxerror = '1') ELSE - '1' WHEN (FIT_GBT_STATUS.GBT_status.gbtRx_ErrorDet = '1') ELSE - '1' WHEN (RX_ErrDet_latch = '1') ELSE - '0' WHEN (Control_register_I.strt_rdmode_lock = '1') ELSE - '0'; --- *************************************************** - -gbt_reset <= RESET_I or reset_l; - - - -gbt_bank_gen: if GENERATE_GBT_BANK = 1 generate - gbtBankDsgn : entity work.GBT_TX_RX - port map ( - RESET => gbt_reset, - MgtRefClk => MgtRefClk_I, - MGT_RX_P => MGT_RX_P_I, - MGT_RX_N => MGT_RX_N_I, - MGT_TX_P => MGT_TX_P_O, - MGT_TX_N => MGT_TX_N_O, - TXDataClk => DataClk_I, - TXData => Data_to_GBT_I, - TXData_SC => x"0", - IsTXData => IsData_to_GBT_I, - RXDataClk => GBT_RxFrameClk_O, - RXData => RX_Data_rxclk_from_GBT, - RXData_SC => open, - IsRXData => RX_IsData_rxclk_from_GBT, - GBT_Status_O => from_gbt_bank_prj_GBT_status - ); -end generate gbt_bank_gen; - -gbt_bank_gen_sim: if GENERATE_GBT_BANK = 0 generate - MGT_TX_P_O <= '0'; - MGT_TX_N_O <= '0'; - GBT_RxFrameClk_O <= DataClk_I; - RX_Data_rxclk_from_GBT <= (others => '0'); - RX_IsData_rxclk_from_GBT <= '0'; - - from_gbt_bank_prj_GBT_status.txWordClk <= '0'; - from_gbt_bank_prj_GBT_status.rxFrameClk <= '0'; - from_gbt_bank_prj_GBT_status.rxWordClk <= '0'; - from_gbt_bank_prj_GBT_status.txOutClkFabric <= '0'; - - from_gbt_bank_prj_GBT_status.mgt_phalin_cplllock <= '0'; - - from_gbt_bank_prj_GBT_status.rxWordClkReady <= '0'; - from_gbt_bank_prj_GBT_status.rxFrameClkReady <= '0'; - - from_gbt_bank_prj_GBT_status.mgtLinkReady <= '0'; - from_gbt_bank_prj_GBT_status.tx_resetDone <= '0'; - from_gbt_bank_prj_GBT_status.tx_fsmResetDone <= '0'; - - from_gbt_bank_prj_GBT_status.gbtRx_Ready <= '0'; - from_gbt_bank_prj_GBT_status.gbtRx_ErrorDet <= '0'; - from_gbt_bank_prj_GBT_status.gbtRx_ErrorLatch <= '0'; - from_gbt_bank_prj_GBT_status.Rx_Phase_error <= '0'; -end generate gbt_bank_gen_sim; - - - -- ============================================================= + slct_fifo_dout_o => slct_fifo_dout, + slct_fifo_empty_o => slct_fifo_empty, + slct_fifo_rden_i => slct_fifo_rden, + + cntpck_fifo_dout_o => cntpck_fifo_dout, + cntpck_fifo_empty_o => cntpck_fifo_empty, + cntpck_fifo_rden_i => cntpck_fifo_rden, + + trg_fifo_empty_o => FIT_GBT_STATUS.fifos_empty(2), + + slct_fifo_cnt_o => open, + slct_fifo_cnt_max_o => FIT_GBT_STATUS.sel_fifo_max, + packets_dropped_o => FIT_GBT_STATUS.sel_drop_cnt, + event_counter_o => FIT_GBT_STATUS.event_counter, + errors_o => FIT_GBT_STATUS.fsm_errors(4 downto 1), + no_data_o => no_sel_data + ); +-- =========================================================== + +-- CRU Packet Constructer ====================================== + CRU_packet_Builder_comp : entity work.CRU_packet_Builder + port map ( + FSM_Clocks_I => FSM_Clocks, + + Status_register_I => FIT_GBT_STATUS, + Control_register_I => Control_register_I, + + SLCTFIFO_data_word_I => slct_fifo_dout, + SLCTFIFO_Is_Empty_I => slct_fifo_empty, + SLCTFIFO_RE_O => slct_fifo_rden, + + CNTPTFIFO_data_word_I => cntpck_fifo_dout, + CNTPFIFO_Is_Empty_I => cntpck_fifo_empty, + CNTPFIFO_RE_O => cntpck_fifo_rden, + + Is_Data_O => is_data_from_cru_constructor, + Data_O => data_from_cru_constructor, + + errors_o => FIT_GBT_STATUS.fsm_errors(0 downto 0) + ); +-- =========================================================== + + + +-- TX Data Gen =============================================== + TX_Data_Gen_comp : entity work.TX_Data_Gen + port map( + FSM_Clocks_I => FSM_Clocks, + + Control_register_I => Control_register_I, + Status_register_I => FIT_GBT_STATUS, + + TX_IsData_I => is_data_from_cru_constructor, + TX_Data_I => data_from_cru_constructor, + + TX_IsData_O => TX_IsData_from_txgen, + TX_Data_O => TX_Data_from_txgen, + + gbt_data_counter_o => FIT_GBT_STATUS.gbt_data_cnt + ); +-- =========================================================== + +-- ERRORs REPORT ======================================== + error_report_comp : entity work.error_report + port map( + RESET_I => RESET_I, + FSM_Clocks_I => FSM_Clocks, + + Control_register_I => Control_register_I, + Status_register_I => FIT_GBT_STATUS, + + RX_IsData_I => RX_IsData_from_orbcgen, + RX_Data_I => RX_Data_from_orbcgen, + + err_report_fifo_rden_i => err_report_fifo_rden_i, + report_fifo_o => FIT_GBT_STATUS.ipbusrd_err_report, + report_fifo_empty_o => error_report_fifo_empty + ); +-- ===================================================== + + +-- ============================================================= + gbt_bank_gen : if IS_SIMULATION = 0 generate + gbtBankDsgn : entity work.GBT_TX_RX + port map ( + RESET => gbt_reset, + MgtRefClk => MgtRefClk_I, + MGT_RX_P => MGT_RX_P_I, + MGT_RX_N => MGT_RX_N_I, + MGT_TX_P => MGT_TX_P_O, + MGT_TX_N => MGT_TX_N_O, + TXDataClk => DataClk_I, + TXData => Data_to_GBT_I, + TXData_SC => x"0", + IsTXData => IsData_to_GBT_I, + RXDataClk => GBT_RxFrameClk_O, + RXData => RX_Data_rxclk_from_GBT, + RXData_SC => open, + IsRXData => RX_IsData_rxclk_from_GBT, + reset_rx_errors => Control_register_I.reset_gbt_rxerror, + reset_fsm => FSM_Clocks.Reset_dclk, + GBT_Status_O => from_gbt_bank_prj_GBT_status + ); + end generate gbt_bank_gen; + + gbt_bank_gen_sim : if IS_SIMULATION = 1 generate + MGT_TX_P_O <= '0'; + MGT_TX_N_O <= '0'; + GBT_RxFrameClk_O <= DataClk_I; + RX_Data_rxclk_from_GBT <= (others => '0'); + RX_IsData_rxclk_from_GBT <= '0'; + from_gbt_bank_prj_GBT_status <= test_gbt_status_void; + end generate gbt_bank_gen_sim; + -- ============================================================= end Behavioral; diff --git a/firmware/common/gbt-readout/hdl/GBT_TXRX5.vhd b/firmware/common/gbt-readout/hdl/GBT_TXRX5.vhd index d8d5fb8..bf349eb 100644 --- a/firmware/common/gbt-readout/hdl/GBT_TXRX5.vhd +++ b/firmware/common/gbt-readout/hdl/GBT_TXRX5.vhd @@ -1,58 +1,20 @@ ---=================================================================================================-- ---################################## Module Information #######################################-- ---=================================================================================================-- --- --- Company: CERN (PH-ESE-BE) --- Engineer: Manoel Barros Marin (manoel.barros.marin@cern.ch) (m.barros.marin@ieee.org) --- --- Project Name: GBT-FPGA --- Module Name: Xilinx Kintex 7 & Virtex 7 - GBT Bank example design --- --- Language: VHDL'93 --- --- Target Device: Xilinx Kintex 7 & Virtex 7 --- Tool version: ISE 14.5 --- --- Version: 3.2 --- --- Description: --- --- Versions history: DATE VERSION AUTHOR DESCRIPTION --- --- 28/10/2013 3.0 M. Barros Marin First .vhd module definition --- --- 14/08/2014 3.2 M. Barros Marin Minor modifications --- --- Additional Comments: Note!! Only ONE GBT Bank with ONE link can be used in this example design. +---------------------------------------------------------------------------------- +-- Company: INR RAS +-- Engineer: Finogeev D. A. dmitry-finogeev@yandex.ru +-- +-- Create Date: 2017 +-- Description: GBT v5 TOP unit -- --- !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! --- !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! IMPORTANT !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! --- !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! --- !! !! --- !! * The different parameters of the GBT Bank are set through: !! --- !! (Note!! These parameters are vendor specific) !! --- !! !! --- !! - The MGT control ports of the GBT Bank module (these ports are listed in the records !! --- !! of the file "__gbt_bank_package.vhd"). !! --- !! (e.g. xlx_v6_gbt_bank_package.vhd) !! --- !! !! --- !! - By modifying the content of the file "__gbt_bank_user_setup.vhd". !! --- !! (e.g. xlx_v6_gbt_bank_user_setup.vhd) !! --- !! !! --- !! * The "__gbt_bank_user_setup.vhd" is the only file of the GBT Bank that !! --- !! may be modified by the user. The rest of the files MUST be used as is. !! --- !! !! --- !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! --- !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! --- ---=================================================================================================-- ---#################################################################################################-- ---=================================================================================================-- +-- Revision: 06/2021 +---------------------------------------------------------------------------------- + -- IEEE VHDL standard library: library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; +use ieee.std_logic_unsigned.all; + -- Xilinx devices library: library unisim; @@ -68,24 +30,24 @@ use work.fit_gbt_common_package.all; --####################################### Entity ##############################################-- --=================================================================================================-- entity GBT_TX_RX is - Port ( RESET : in STD_LOGIC; - MgtRefClk : in STD_LOGIC; - MGT_RX_P : in STD_LOGIC; - MGT_RX_N : in STD_LOGIC; - MGT_TX_P : out STD_LOGIC; - MGT_TX_N : out STD_LOGIC; - TXDataClk : in STD_LOGIC; - TXData : in STD_LOGIC_VECTOR (79 downto 0); - TXData_SC : in STD_LOGIC_VECTOR (3 downto 0); - IsTXData : in STD_LOGIC; - RXDataClk : out STD_LOGIC; - RXData : out STD_LOGIC_VECTOR (79 downto 0); - RXData_SC : out STD_LOGIC_VECTOR (3 downto 0); - IsRXData : out STD_LOGIC; - RX_ready : out STD_LOGIC; - RX_errors: out STD_LOGIC; - GBT_Status_O : out Type_GBT_status - ); + port (RESET : in std_logic; + MgtRefClk : in std_logic; + MGT_RX_P : in std_logic; + MGT_RX_N : in std_logic; + MGT_TX_P : out std_logic; + MGT_TX_N : out std_logic; + TXDataClk : in std_logic; + TXData : in std_logic_vector (79 downto 0); + TXData_SC : in std_logic_vector (3 downto 0); + IsTXData : in std_logic; + RXDataClk : out std_logic; + RXData : out std_logic_vector (79 downto 0); + RXData_SC : out std_logic_vector (3 downto 0); + IsRXData : out std_logic; + reset_rx_errors : in std_logic; + reset_fsm : in std_logic; + GBT_Status_O : out gbt_status_t + ); end GBT_TX_RX; @@ -95,287 +57,302 @@ end GBT_TX_RX; --#################################### Architecture ###########################################-- --=================================================================================================-- -architecture structural of GBT_TX_RX is - - attribute keep : string; - - - --================================ Signal Declarations ================================-- - -- GBT Bank 1: - -------------- - - - signal to_gbtBank_clks : gbtBankClks_i_R; - signal from_gbtBank_clks : gbtBankClks_o_R; - -------------------------------------------------------- - signal to_gbtBank_gbtTx : gbtTx_i_R_A(1 to GBT_BANKS_USER_SETUP(1).NUM_LINKS); - signal from_gbtBank_gbtTx : gbtTx_o_R_A(1 to GBT_BANKS_USER_SETUP(1).NUM_LINKS); - -------------------------------------------------------- - signal to_gbtBank_mgt : mgt_i_R; - signal from_gbtBank_mgt : mgt_o_R; - attribute keep of from_gbtBank_mgt : signal is "true"; - - -------------------------------------------------------- - signal to_gbtBank_gbtRx : gbtRx_i_R_A(1 to GBT_BANKS_USER_SETUP(1).NUM_LINKS); - signal from_gbtBank_gbtRx : gbtRx_o_R_A(1 to GBT_BANKS_USER_SETUP(1).NUM_LINKS); - attribute keep of from_gbtBank_gbtRx : signal is "true"; - - - -- Resets: - ----------- - signal mgtTxReset_from_gbtBank_gbtBankRst : std_logic_vector(1 to GBT_BANKS_USER_SETUP(1).NUM_LINKS); - signal mgtRxReset_from_gbtBank_gbtBankRst : std_logic_vector(1 to GBT_BANKS_USER_SETUP(1).NUM_LINKS); - signal gbtTxReset_from_gbtBank_gbtBankRst : std_logic_vector(1 to GBT_BANKS_USER_SETUP(1).NUM_LINKS); - signal gbtRxReset_from_gbtBank_gbtBankRst : std_logic_vector(1 to GBT_BANKS_USER_SETUP(1).NUM_LINKS); - signal reset_from_genRst : std_logic; - +architecture structural of GBT_TX_RX is + + attribute keep : string; + + + --================================ Signal Declarations ================================-- + -- GBT Bank 1: + -------------- + + signal to_gbtBank_clks : gbtBankClks_i_R; + signal from_gbtBank_clks : gbtBankClks_o_R; + -------------------------------------------------------- + signal to_gbtBank_gbtTx : gbtTx_i_R_A(1 to GBT_BANKS_USER_SETUP(1).NUM_LINKS); + signal from_gbtBank_gbtTx : gbtTx_o_R_A(1 to GBT_BANKS_USER_SETUP(1).NUM_LINKS); + -------------------------------------------------------- + signal to_gbtBank_mgt : mgt_i_R; + signal from_gbtBank_mgt : mgt_o_R; + attribute keep of from_gbtBank_mgt : signal is "true"; + + -------------------------------------------------------- + signal to_gbtBank_gbtRx : gbtRx_i_R_A(1 to GBT_BANKS_USER_SETUP(1).NUM_LINKS); + signal from_gbtBank_gbtRx : gbtRx_o_R_A(1 to GBT_BANKS_USER_SETUP(1).NUM_LINKS); + attribute keep of from_gbtBank_gbtRx : signal is "true"; + + + -- Resets: + ----------- + signal mgtTxReset_from_gbtBank_gbtBankRst : std_logic_vector(1 to GBT_BANKS_USER_SETUP(1).NUM_LINKS); + signal mgtRxReset_from_gbtBank_gbtBankRst : std_logic_vector(1 to GBT_BANKS_USER_SETUP(1).NUM_LINKS); + signal gbtTxReset_from_gbtBank_gbtBankRst : std_logic_vector(1 to GBT_BANKS_USER_SETUP(1).NUM_LINKS); + signal gbtRxReset_from_gbtBank_gbtBankRst : std_logic_vector(1 to GBT_BANKS_USER_SETUP(1).NUM_LINKS); + signal reset_from_genRst : std_logic; + -- RX frameclk aligner: - ----------------------- - signal phaseAlignDone_from_gbtBank_rxFrmClkPhAlgnr : std_logic_vector(1 to GBT_BANKS_USER_SETUP(1).NUM_LINKS); - signal pllLocked_from_gbtBank_rxFrmClkPhAlgnr : std_logic_vector(1 to GBT_BANKS_USER_SETUP(1).NUM_LINKS); - signal gbtBank_rxFrameClkReady_staticMux : std_logic_vector(1 to GBT_BANKS_USER_SETUP(1).NUM_LINKS); - signal rxFrameClk_from_gbtBank_rxFrmClkPhAlgnr : std_logic_vector(1 to GBT_BANKS_USER_SETUP(1).NUM_LINKS); - - signal latOptGbtBank_rx : std_logic_vector(1 to GBT_BANKS_USER_SETUP(1).NUM_LINKS); - signal rxWordClkReady : std_logic_vector(1 to GBT_BANKS_USER_SETUP(1).NUM_LINKS); - signal mgt_cpllLock : std_logic_vector(1 to GBT_BANKS_USER_SETUP(1).NUM_LINKS); - signal mgt_outclkfabric : std_logic_vector(1 to GBT_BANKS_USER_SETUP(1).NUM_LINKS); - signal header_flag : std_logic_vector(1 to GBT_BANKS_USER_SETUP(1).NUM_LINKS); - ---=================================================================================================-- -begin --========#### Architecture Body ####========-- ---=================================================================================================-- - - --==================================== User Logic =====================================-- - - --##############################################################################-- - --##################################################################################-- - --################################## #####################################-- - --################################## GBT Bank #####################################-- - --################################## #####################################-- - --##################################################################################-- - --##############################################################################-- - - --============-- - -- Clocks -- - --============-- - - gbtBank_rxFrmClkPhAlgnr: entity work.gbt_rx_frameclk_phalgnr - generic map( - TX_OPTIMIZATION => GBT_BANKS_USER_SETUP(1).TX_OPTIMIZATION, - RX_OPTIMIZATION => GBT_BANKS_USER_SETUP(1).RX_OPTIMIZATION, - - WORDCLK_FREQ => 120, - - SHIFT_CNTER => 280, -- ((8*VCO_FREQ)/wordclk_freq) for Altera - REF_MATCHING => (4 ,6) - ) - port map ( - - RESET_I => gbtRxReset_from_gbtBank_gbtBankRst(1), - - RX_WORDCLK_I => from_gbtBank_clks.mgt_clks.rx_wordClk(1), - FRAMECLK_I => TXDataClk, - RX_FRAMECLK_O => rxFrameClk_from_gbtBank_rxFrmClkPhAlgnr(1), - - SYNC_I => header_flag(1), - - PLL_LOCKED_O => pllLocked_from_gbtBank_rxFrmClkPhAlgnr(1), - DONE_O => phaseAlignDone_from_gbtBank_rxFrmClkPhAlgnr(1) - ); - - latOptGbtBank_rx(1) <= from_gbtBank_gbtRx(1).latOptGbtBank_rx; - rxWordClkReady(1) <= from_gbtBank_mgt.mgtLink(1).rxWordClkReady; - header_flag(1) <= from_gbtBank_gbtRx(1).header_flag; - mgt_cpllLock(1) <= from_gbtBank_mgt.mgtLink(1).cpllLock; - - RXDataClk <= rxFrameClk_from_gbtBank_rxFrmClkPhAlgnr(1); - mgt_outclkfabric(1) <= from_gbtBank_clks.mgt_clks.tx_outclkfabric(1); - - to_gbtBank_clks.tx_frameClk(1) <= TXDataClk; - to_gbtBank_clks.rx_frameClk(1) <= rxFrameClk_from_gbtBank_rxFrmClkPhAlgnr(1); - - - gbtBank_rxFrameClkReady_staticMux(1) <= phaseAlignDone_from_gbtBank_rxFrmClkPhAlgnr(1) when GBT_BANKS_USER_SETUP(1).RX_OPTIMIZATION = LATENCY_OPTIMIZED else - pllLocked_from_gbtBank_rxFrmClkPhAlgnr(1); - - - - - - to_gbtBank_clks.mgt_clks.mgtRefClk <= MgtRefClk; -- 200MHz - to_gbtBank_clks.mgt_clks.mgtRstCtrlRefClk <= TXDataClk; - to_gbtBank_clks.mgt_clks.cpllLockDetClk <= TXDataClk; - to_gbtBank_clks.mgt_clks.drpClk <= TXDataClk; - - --============-- - -- Resets -- - --============-- - -- General reset: - ----------------- - - - gbtBank_gbtBankRst: entity work.gbt_bank_reset - generic map ( - RX_INIT_FIRST => false, - INITIAL_DELAY => 1 * 40e6, -- Comment: * 1s - TIME_N => 1 * 40e5, -- * 1s - GAP_DELAY => 1 * 40e6) -- * 1s - port map ( - CLK_I => TXDataClk, - -------------------------------------------------- - GENERAL_RESET_I => RESET, - MANUAL_RESET_TX_I => '0', - MANUAL_RESET_RX_I => '0', - -------------------------------------------------- - MGT_TX_RESET_O => mgtTxReset_from_gbtBank_gbtBankRst(1), - MGT_RX_RESET_O => mgtRxReset_from_gbtBank_gbtBankRst(1), - GBT_TX_RESET_O => gbtTxReset_from_gbtBank_gbtBankRst(1), - GBT_RX_RESET_O => gbtRxReset_from_gbtBank_gbtBankRst(1), - -------------------------------------------------- - BUSY_O => open, - DONE_O => open - ); - - - --============-- - -- GBT Tx -- - --============-- - to_gbtBank_gbtTx(1).reset <= gbtTxReset_from_gbtBank_gbtBankRst(1); - to_gbtBank_gbtTx(1).isDataSel <= IsTXData; - to_gbtBank_gbtTx(1).data <= TXData_SC & TXData; - to_gbtBank_gbtTx(1).extraData_wideBus <= x"00000000"; - - - - --============-- - -- GBT Rx -- - --============-- - - to_gbtBank_gbtRx(1).reset <= gbtRxReset_from_gbtBank_gbtBankRst(1); - to_gbtBank_gbtRx(1).rxFrameClkReady <= gbtBank_rxFrameClkReady_staticMux(1); - RX_ready <= from_gbtBank_gbtRx(1).ready; - - RXData <= from_gbtBank_gbtRx(1).data(79 downto 0); - RXData_SC <= from_gbtBank_gbtRx(1).data(83 downto 80); - - IsRXData <= from_gbtBank_gbtRx(1).isDataFlag; - RX_errors <= from_gbtBank_gbtRx(1).rxErrorDetected; - - - - --=============-- - -- Transceiver -- - --=============-- - - - - to_gbtBank_mgt.mgtLink(1).drp_addr <= "000000000"; - to_gbtBank_mgt.mgtLink(1).drp_en <= '0'; - to_gbtBank_mgt.mgtLink(1).drp_di <= x"0000"; - to_gbtBank_mgt.mgtLink(1).drp_we <= '0'; - - to_gbtBank_mgt.mgtLink(1).prbs_txSel <= "000"; - to_gbtBank_mgt.mgtLink(1).prbs_rxSel <= "000"; - to_gbtBank_mgt.mgtLink(1).prbs_txForceErr <= '0'; - to_gbtBank_mgt.mgtLink(1).prbs_rxCntReset <= '0'; - - to_gbtBank_mgt.mgtLink(1).conf_diffCtrl <= "1000"; -- Comment: 807 mVppd - to_gbtBank_mgt.mgtLink(1).conf_postCursor <= "00000"; -- Comment: 0.00 dB (default) - to_gbtBank_mgt.mgtLink(1).conf_preCursor <= "00000"; -- Comment: 0.00 dB (default) - to_gbtBank_mgt.mgtLink(1).conf_txPol <= '0'; -- Comment: Not inverted - to_gbtBank_mgt.mgtLink(1).conf_rxPol <= '0'; -- Comment: Not inverted - - to_gbtBank_mgt.mgtLink(1).rxBitSlip_enable <= '1'; - to_gbtBank_mgt.mgtLink(1).rxBitSlip_ctrl <= '0'; - to_gbtBank_mgt.mgtLink(1).rxBitSlip_nbr <= "000000"; - to_gbtBank_mgt.mgtLink(1).rxBitSlip_run <= '0'; - to_gbtBank_mgt.mgtLink(1).rxBitSlip_oddRstEn <= '0'; -- Comment: If '1' resets the MGT RX when the the number of bitslips - -- is odd (GTX only performs a number of bitslips multiple of 2). - - to_gbtBank_mgt.mgtLink(1).loopBack <= "000"; - - to_gbtBank_mgt.mgtLink(1).rx_p <= MGT_RX_P; - to_gbtBank_mgt.mgtLink(1).rx_n <= MGT_RX_N; - - MGT_TX_P <= from_gbtBank_mgt.mgtLink(1).tx_p; - MGT_TX_N <= from_gbtBank_mgt.mgtLink(1).tx_n; - - to_gbtBank_mgt.mgtLink(1).tx_reset <= mgtTxReset_from_gbtBank_gbtBankRst(1); - to_gbtBank_mgt.mgtLink(1).rx_reset <= mgtRxReset_from_gbtBank_gbtBankRst(1); - to_gbtBank_mgt.mgtCommon.dummy_i <='0'; - - - --============-- - -- GBT Bank 1 -- - --============-- - - -- Comment: Note!! This example design instantiates two GBT Banks: - -- - -- - GBT Bank 1: One GBT Link (Standard GBT TX and Latency-Optimized GBT RX). - -- - -- - GBT Bank 2: Three GBT Links (Latency-Optimized GBT TX and Standard GBT RX). - - gbtBank: entity work.gbt_bank - generic map ( - GBT_BANK_ID => 1, - NUM_LINKS => GBT_BANKS_USER_SETUP(1).NUM_LINKS, - TX_OPTIMIZATION => GBT_BANKS_USER_SETUP(1).TX_OPTIMIZATION, - RX_OPTIMIZATION => GBT_BANKS_USER_SETUP(1).RX_OPTIMIZATION, - TX_ENCODING => GBT_BANKS_USER_SETUP(1).TX_ENCODING, - RX_ENCODING => GBT_BANKS_USER_SETUP(1).RX_ENCODING) - port map ( - CLKS_I => to_gbtBank_clks, - CLKS_O => from_gbtBank_clks, - -------------------------------------------------- - GBT_TX_I => to_gbtBank_gbtTx, - GBT_TX_O => from_gbtBank_gbtTx, - -------------------------------------------------- - MGT_I => to_gbtBank_mgt, - MGT_O => from_gbtBank_mgt, - -------------------------------------------------- - GBT_RX_I => to_gbtBank_gbtRx, - GBT_RX_O => from_gbtBank_gbtRx - ); - - - --============-- - -- Status -- - --============-- - - process(TXDataClk) - begin - - if TXDataClk'event and (TXDataClk='1') then - GBT_Status_O.gbtRx_Ready <= from_gbtBank_gbtRx(1).ready; - GBT_Status_O.gbtRx_ErrorDet <= from_gbtBank_gbtRx(1).rxErrorDetected; -end if; -end process; - - - - GBT_Status_O.txWordClk <= from_gbtBank_clks.mgt_clks.tx_wordClk(1); - GBT_Status_O.rxFrameClk <= rxFrameClk_from_gbtBank_rxFrmClkPhAlgnr(1); - GBT_Status_O.rxWordClk <= from_gbtBank_clks.mgt_clks.rx_wordClk(1); - GBT_Status_O.txOutClkFabric <= from_gbtBank_clks.mgt_clks.tx_outclkfabric(1); - - GBT_Status_O.mgt_phalin_cplllock <= pllLocked_from_gbtBank_rxFrmClkPhAlgnr(1); - - GBT_Status_O.rxWordClkReady <= from_gbtBank_mgt.mgtLink(1).rxWordClkReady; - GBT_Status_O.rxFrameClkReady <= phaseAlignDone_from_gbtBank_rxFrmClkPhAlgnr(1); - - GBT_Status_O.mgtLinkReady <= from_gbtBank_mgt.mgtLink(1).ready; - GBT_Status_O.tx_resetDone <= from_gbtBank_mgt.mgtLink(1).tx_resetDone; - GBT_Status_O.tx_fsmResetDone <= from_gbtBank_mgt.mgtLink(1).tx_fsmResetDone; - - - - - - + ----------------------- + signal phaseAlignDone_from_gbtBank_rxFrmClkPhAlgnr : std_logic_vector(1 to GBT_BANKS_USER_SETUP(1).NUM_LINKS); + signal pllLocked_from_gbtBank_rxFrmClkPhAlgnr : std_logic_vector(1 to GBT_BANKS_USER_SETUP(1).NUM_LINKS); + signal gbtBank_rxFrameClkReady_staticMux : std_logic_vector(1 to GBT_BANKS_USER_SETUP(1).NUM_LINKS); + signal rxFrameClk_from_gbtBank_rxFrmClkPhAlgnr : std_logic_vector(1 to GBT_BANKS_USER_SETUP(1).NUM_LINKS); + + signal latOptGbtBank_rx : std_logic_vector(1 to GBT_BANKS_USER_SETUP(1).NUM_LINKS); + signal rxWordClkReady : std_logic_vector(1 to GBT_BANKS_USER_SETUP(1).NUM_LINKS); + signal mgt_cpllLock : std_logic_vector(1 to GBT_BANKS_USER_SETUP(1).NUM_LINKS); + signal mgt_outclkfabric : std_logic_vector(1 to GBT_BANKS_USER_SETUP(1).NUM_LINKS); + signal header_flag : std_logic_vector(1 to GBT_BANKS_USER_SETUP(1).NUM_LINKS); + signal gbtRx_ErrorDet_ff, Rx_Ready_ff : std_logic; + signal gbt_not_ready : std_logic; + signal gbt_ready_cnt : std_logic_vector(27 downto 0); -end structural; + -- attribute mark_debug : string; + -- attribute mark_debug of gbt_not_ready : signal is "true"; + -- attribute mark_debug of gbt_ready_cnt : signal is "true"; + -- attribute mark_debug of gbtRx_ErrorDet_ff : signal is "true"; + -- attribute mark_debug of Rx_Ready_ff : signal is "true"; + + --=================================================================================================-- ---#################################################################################################-- ---=================================================================================================-- \ No newline at end of file +begin --========#### Architecture Body ####========-- +--=================================================================================================-- + + --==================================== User Logic =====================================-- + + --============-- + -- Clocks -- + --============-- + + gbtBank_rxFrmClkPhAlgnr : entity work.gbt_rx_frameclk_phalgnr + generic map( + TX_OPTIMIZATION => GBT_BANKS_USER_SETUP(1).TX_OPTIMIZATION, + RX_OPTIMIZATION => GBT_BANKS_USER_SETUP(1).RX_OPTIMIZATION, + + WORDCLK_FREQ => 120, + + SHIFT_CNTER => 280, -- ((8*VCO_FREQ)/wordclk_freq) for Altera + REF_MATCHING => (4, 6) + ) + port map ( + + RESET_I => gbtRxReset_from_gbtBank_gbtBankRst(1), + + RX_WORDCLK_I => from_gbtBank_clks.mgt_clks.rx_wordClk(1), + FRAMECLK_I => TXDataClk, + RX_FRAMECLK_O => rxFrameClk_from_gbtBank_rxFrmClkPhAlgnr(1), + + SYNC_I => header_flag(1), + + PLL_LOCKED_O => pllLocked_from_gbtBank_rxFrmClkPhAlgnr(1), + DONE_O => phaseAlignDone_from_gbtBank_rxFrmClkPhAlgnr(1) + ); + + latOptGbtBank_rx(1) <= from_gbtBank_gbtRx(1).latOptGbtBank_rx; + rxWordClkReady(1) <= from_gbtBank_mgt.mgtLink(1).rxWordClkReady; + header_flag(1) <= from_gbtBank_gbtRx(1).header_flag; + mgt_cpllLock(1) <= from_gbtBank_mgt.mgtLink(1).cpllLock; + + RXDataClk <= rxFrameClk_from_gbtBank_rxFrmClkPhAlgnr(1); + mgt_outclkfabric(1) <= from_gbtBank_clks.mgt_clks.tx_outclkfabric(1); + + to_gbtBank_clks.tx_frameClk(1) <= TXDataClk; + to_gbtBank_clks.rx_frameClk(1) <= rxFrameClk_from_gbtBank_rxFrmClkPhAlgnr(1); + + + gbtBank_rxFrameClkReady_staticMux(1) <= phaseAlignDone_from_gbtBank_rxFrmClkPhAlgnr(1) when GBT_BANKS_USER_SETUP(1).RX_OPTIMIZATION = LATENCY_OPTIMIZED else + pllLocked_from_gbtBank_rxFrmClkPhAlgnr(1); + + + + + + to_gbtBank_clks.mgt_clks.mgtRefClk <= MgtRefClk; -- 200MHz + to_gbtBank_clks.mgt_clks.mgtRstCtrlRefClk <= TXDataClk; + to_gbtBank_clks.mgt_clks.cpllLockDetClk <= TXDataClk; + to_gbtBank_clks.mgt_clks.drpClk <= TXDataClk; + + --============-- + -- Resets -- + --============-- + -- General reset: + ----------------- + + + gbtBank_gbtBankRst : entity work.gbt_bank_reset + generic map ( + RX_INIT_FIRST => false, + INITIAL_DELAY => 1 * 40e6, -- Comment: * 1s + TIME_N => 1 * 40e5, -- * 1s + GAP_DELAY => 1 * 40e6) -- * 1s + port map ( + CLK_I => TXDataClk, + -------------------------------------------------- + GENERAL_RESET_I => RESET, + MANUAL_RESET_TX_I => '0', + MANUAL_RESET_RX_I => '0', + -------------------------------------------------- + MGT_TX_RESET_O => mgtTxReset_from_gbtBank_gbtBankRst(1), + MGT_RX_RESET_O => mgtRxReset_from_gbtBank_gbtBankRst(1), + GBT_TX_RESET_O => gbtTxReset_from_gbtBank_gbtBankRst(1), + GBT_RX_RESET_O => gbtRxReset_from_gbtBank_gbtBankRst(1), + -------------------------------------------------- + BUSY_O => open, + DONE_O => open + ); + + + --============-- + -- GBT Tx -- + --============-- + to_gbtBank_gbtTx(1).reset <= gbtTxReset_from_gbtBank_gbtBankRst(1); + to_gbtBank_gbtTx(1).isDataSel <= IsTXData; + to_gbtBank_gbtTx(1).data <= TXData_SC & TXData; + to_gbtBank_gbtTx(1).extraData_wideBus <= x"00000000"; + + + + --============-- + -- GBT Rx -- + --============-- + + to_gbtBank_gbtRx(1).reset <= gbtRxReset_from_gbtBank_gbtBankRst(1); + to_gbtBank_gbtRx(1).rxFrameClkReady <= gbtBank_rxFrameClkReady_staticMux(1); + + RXData <= from_gbtBank_gbtRx(1).data(79 downto 0); + RXData_SC <= from_gbtBank_gbtRx(1).data(83 downto 80); + + IsRXData <= from_gbtBank_gbtRx(1).isDataFlag; + + + + --=============-- + -- Transceiver -- + --=============-- + + + + to_gbtBank_mgt.mgtLink(1).drp_addr <= "000000000"; + to_gbtBank_mgt.mgtLink(1).drp_en <= '0'; + to_gbtBank_mgt.mgtLink(1).drp_di <= x"0000"; + to_gbtBank_mgt.mgtLink(1).drp_we <= '0'; + + to_gbtBank_mgt.mgtLink(1).prbs_txSel <= "000"; + to_gbtBank_mgt.mgtLink(1).prbs_rxSel <= "000"; + to_gbtBank_mgt.mgtLink(1).prbs_txForceErr <= '0'; + to_gbtBank_mgt.mgtLink(1).prbs_rxCntReset <= '0'; + + to_gbtBank_mgt.mgtLink(1).conf_diffCtrl <= "1000"; -- Comment: 807 mVppd + to_gbtBank_mgt.mgtLink(1).conf_postCursor <= "00000"; -- Comment: 0.00 dB (default) + to_gbtBank_mgt.mgtLink(1).conf_preCursor <= "00000"; -- Comment: 0.00 dB (default) + to_gbtBank_mgt.mgtLink(1).conf_txPol <= '0'; -- Comment: Not inverted + to_gbtBank_mgt.mgtLink(1).conf_rxPol <= '0'; -- Comment: Not inverted + + to_gbtBank_mgt.mgtLink(1).rxBitSlip_enable <= '1'; + to_gbtBank_mgt.mgtLink(1).rxBitSlip_ctrl <= '0'; + to_gbtBank_mgt.mgtLink(1).rxBitSlip_nbr <= "000000"; + to_gbtBank_mgt.mgtLink(1).rxBitSlip_run <= '0'; + to_gbtBank_mgt.mgtLink(1).rxBitSlip_oddRstEn <= '0'; -- Comment: If '1' resets the MGT RX when the the number of bitslips + -- is odd (GTX only performs a number of bitslips multiple of 2). + + to_gbtBank_mgt.mgtLink(1).loopBack <= "000"; + + to_gbtBank_mgt.mgtLink(1).rx_p <= MGT_RX_P; + to_gbtBank_mgt.mgtLink(1).rx_n <= MGT_RX_N; + + MGT_TX_P <= from_gbtBank_mgt.mgtLink(1).tx_p; + MGT_TX_N <= from_gbtBank_mgt.mgtLink(1).tx_n; + + to_gbtBank_mgt.mgtLink(1).tx_reset <= mgtTxReset_from_gbtBank_gbtBankRst(1); + to_gbtBank_mgt.mgtLink(1).rx_reset <= mgtRxReset_from_gbtBank_gbtBankRst(1); + to_gbtBank_mgt.mgtCommon.dummy_i <= '0'; + + + --============-- + -- GBT Bank 1 -- + --============-- + + -- Comment: Note!! This example design instantiates two GBT Banks: + -- + -- - GBT Bank 1: One GBT Link (Standard GBT TX and Latency-Optimized GBT RX). + -- + -- - GBT Bank 2: Three GBT Links (Latency-Optimized GBT TX and Standard GBT RX). + + gbtBank : entity work.gbt_bank + generic map ( + GBT_BANK_ID => 1, + NUM_LINKS => GBT_BANKS_USER_SETUP(1).NUM_LINKS, + TX_OPTIMIZATION => GBT_BANKS_USER_SETUP(1).TX_OPTIMIZATION, + RX_OPTIMIZATION => GBT_BANKS_USER_SETUP(1).RX_OPTIMIZATION, + TX_ENCODING => GBT_BANKS_USER_SETUP(1).TX_ENCODING, + RX_ENCODING => GBT_BANKS_USER_SETUP(1).RX_ENCODING) + port map ( + CLKS_I => to_gbtBank_clks, + CLKS_O => from_gbtBank_clks, + -------------------------------------------------- + GBT_TX_I => to_gbtBank_gbtTx, + GBT_TX_O => from_gbtBank_gbtTx, + -------------------------------------------------- + MGT_I => to_gbtBank_mgt, + MGT_O => from_gbtBank_mgt, + -------------------------------------------------- + GBT_RX_I => to_gbtBank_gbtRx, + GBT_RX_O => from_gbtBank_gbtRx + ); + + + --============-- + -- Status -- + --============-- + + process(TXDataClk) + begin + + if TXDataClk'event and (TXDataClk = '1') then + gbtRx_ErrorDet_ff <= from_gbtBank_gbtRx(1).rxErrorDetected; + Rx_Ready_ff <= from_gbtBank_gbtRx(1).ready; + + GBT_Status_O.gbtRx_ErrorDet <= gbtRx_ErrorDet_ff; + + GBT_Status_O.mgt_phalin_cplllock <= pllLocked_from_gbtBank_rxFrmClkPhAlgnr(1); + + GBT_Status_O.rxWordClkReady <= from_gbtBank_mgt.mgtLink(1).rxWordClkReady; + GBT_Status_O.rxFrameClkReady <= phaseAlignDone_from_gbtBank_rxFrmClkPhAlgnr(1); + + GBT_Status_O.mgtLinkReady <= from_gbtBank_mgt.mgtLink(1).ready; + GBT_Status_O.tx_resetDone <= from_gbtBank_mgt.mgtLink(1).tx_resetDone; + GBT_Status_O.tx_fsmResetDone <= from_gbtBank_mgt.mgtLink(1).tx_fsmResetDone; + GBT_Status_O.gbt_not_ready <= gbt_not_ready; + GBT_Status_O.gbtRx_Ready <= Rx_Ready_ff; + + + -- rx_err_det reset done by command, gbt_reset, after each gbt sync procedure + if reset_rx_errors = '1' or RESET = '1' or gbt_not_ready = '1' then GBT_Status_O.gbtRx_ErrorLatch <= '0'; + elsif gbtRx_ErrorDet_ff = '1' then GBT_Status_O.gbtRx_ErrorLatch <= '1'; end if; + + -- rx_ready cleared by command or gbt_reset only + if reset_rx_errors = '1' or RESET = '1' then GBT_Status_O.gbt_was_ready <= '1'; end if; + + if RESET = '1' then gbt_not_ready <= '1'; gbt_ready_cnt <= (others => '0'); + -- if gbt failed then wait sinc and set rx_ready_err flag + elsif gbt_not_ready = '0' and Rx_Ready_ff = '0' then gbt_not_ready <= '1'; gbt_ready_cnt <= (others => '0'); GBT_Status_O.gbt_was_ready <= '0'; + -- go to ready after 500ms + elsif gbt_ready_cnt = x"121_2d00" then gbt_not_ready <= '0'; + elsif Rx_Ready_ff = '0' or gbtRx_ErrorDet_ff = '1' then gbt_ready_cnt <= (others => '0'); + else gbt_ready_cnt <= gbt_ready_cnt + 1; end if; + + end if; + end process; + + + + + + + + + + + + +end structural; diff --git a/firmware/common/gbt-readout/hdl/Module_Data_Gen_PM.vhd b/firmware/common/gbt-readout/hdl/Module_Data_Gen_PM.vhd index c50972f..25169c1 100644 --- a/firmware/common/gbt-readout/hdl/Module_Data_Gen_PM.vhd +++ b/firmware/common/gbt-readout/hdl/Module_Data_Gen_PM.vhd @@ -2,276 +2,225 @@ -- Company: INR RAS -- Engineer: Finogeev D. A. dmitry-finogeev@yandex.ru -- --- Create Date: 07/11/2017 --- Design Name: --- Module Name: RXDATA_CLKSync - Behavioral --- Project Name: --- Target Devices: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision --- Additional Comments: +-- Create Date: 2017 +-- Description: generate data test pattern for standalone tests -- +-- Revision: 07/2021 ---------------------------------------------------------------------------------- library IEEE; -use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_1164.all; use ieee.numeric_std.all; -use ieee.std_logic_unsigned.all ; +use ieee.std_logic_unsigned.all; use work.fit_gbt_common_package.all; use work.fit_gbt_board_package.all; entity Module_Data_Gen is - Port ( - FSM_Clocks_I : in FSM_Clocks_type; - - FIT_GBT_status_I : in FIT_GBT_status_type; - Control_register_I : in CONTROL_REGISTER_type; - - Board_data_I : in board_data_type; - Board_data_O : out board_data_type; - data_gen_report_O : out std_logic_vector(31 downto 0) - ); + generic ( + IS_SIMULATION : integer := 0 + ); + + port ( + FSM_Clocks_I : in rdclocks_t; + + Status_register_I : in readout_status_t; + Control_register_I : in readout_control_t; + + Board_data_I : in board_data_type; + Board_data_O : out board_data_type; + datagen_report_o : out datagen_report_t + ); end Module_Data_Gen; architecture Behavioral of Module_Data_Gen is - signal Board_data_gen_ff, Board_data_gen_ff_next, Board_data_in_ff : board_data_type; - signal Board_data_header, Board_data_data, Board_data_void : board_data_type; - - - signal Trigger_from_CRU_40ff, Trigger_from_CRU_320ff : std_logic_vector(Trigger_bitdepth-1 downto 0); -- Trigger ID from CRUS - - - signal trigger_resp_mask : std_logic_vector(Trigger_bitdepth-1 downto 0); - signal bunch_pattern : std_logic_vector(31 downto 0); - signal bunch_freq : std_logic_vector(15 downto 0); - signal bunch_freq_hboffset : std_logic_vector(BC_id_bitdepth-1 downto 0); - signal reset_offset : std_logic; - - type n_words_in_packet_arr_type is array (0 to 8) of std_logic_vector(3 downto 0); - signal n_words_in_packet_mask : n_words_in_packet_arr_type; - signal n_words_in_packet_send, n_words_in_packet_send_next : std_logic_vector(3 downto 0); - - type FSM_STATE_T is (s0_wait, s1_header, s2_data); - signal FSM_STATE, FSM_STATE_NEXT : FSM_STATE_T; - - signal is_packet_send_for_cntr, is_packet_send_for_cntr_ff, is_packet_send_for_cntr_next : std_logic; - signal bfreq_counter, bfreq_counter_next : std_logic_vector(15 downto 0); - signal is_boffset_sync, is_boffset_sync_next : std_logic; - signal bpattern_counter, bpattern_counter_next : integer := 0; - signal cnt_packet_counter, cnt_packet_counter_next : std_logic_vector(data_word_bitdepth-tdwords_bitdepth-1 downto 0); -- continious packet counter - signal pword_counter, pword_counter_next : std_logic_vector(3 downto 0); - signal wchannel_counter, wchannel_counter_w2, wchannel_counter_next : std_logic_vector(tdwords_bitdepth-1 downto 0); - - - - - attribute keep : string; - attribute keep of Board_data_gen_ff : signal is "true"; - - -begin - trigger_resp_mask <= Control_register_I.Data_Gen.trigger_resp_mask; - bunch_pattern <=Control_register_I.Data_Gen.bunch_pattern; - bunch_freq <= Control_register_I.Data_Gen.bunch_freq; - bunch_freq_hboffset <= Control_register_I.Data_Gen.bunch_freq_hboffset; + -- data generator bunch pattern + signal gen_sync_reset, gen_sync_reset_sc : boolean; + signal bc_start : std_logic_vector(BC_id_bitdepth-1 downto 0); + signal bunch_freq : natural range 0 to 65535; + signal using_generator_sc : boolean; + type packet_size_mask_t is array (0 to 7) of std_logic_vector(3 downto 0); + signal packet_size_mask : packet_size_mask_t; + signal packet_size_select, packet_size_select_sc : natural range 0 to 15; - data_gen_report_O <= (others => '0'); -- todo for PM + -- fsm signals + signal bunch_counter : natural range 0 to 65535; + signal bunch_in_sync : boolean; + signal event_orbit, event_orbit_sc : std_logic_vector(Orbit_id_bitdepth-1 downto 0); + signal event_bc, event_bc_sc : std_logic_vector(BC_id_bitdepth-1 downto 0); + signal event_rx_ph : std_logic_vector(rx_phase_bitdepth-1 downto 0); + signal event_rx_ph_err : std_logic; + signal event_size : natural range 0 to 15; + signal word_counter : natural range 0 to 16; + signal cnt_packet_counter : std_logic_vector(data_word_bitdepth-tdwords_bitdepth-1 downto 0); -- continious packet counter + signal Board_data_header, Board_data_data, Board_data_void, data_gen_result : board_data_type; + signal datagen_report : datagen_report_t; + -- simulating data delay in PM/TCM FEE logic to check start data rejection in selector + type board_data_type_arr16 is array (0 to 15) of board_data_type; + signal Board_data_gen_pipe : board_data_type_arr16; --- *************************************************** - Board_data_O <= Board_data_gen_ff WHEN (Control_register_I.Data_Gen.usage_generator = use_MAIN_generator) ELSE Board_data_in_ff; - - Board_data_header.data_word <= func_FITDATAHD_get_header(x"0" & n_words_in_packet_send, FIT_GBT_status_I.ORBIT_from_CRU_corrected, - FIT_GBT_status_I.BCID_from_CRU_corrected, FIT_GBT_status_I.rx_phase, FIT_GBT_status_I.GBT_status.Rx_Phase_error, '0'); - Board_data_header.is_header <= '1'; - Board_data_header.is_data <= '1'; - Board_data_header.is_packet <= '1'; - - Board_data_data.data_word <= wchannel_counter & cnt_packet_counter & wchannel_counter_w2 & cnt_packet_counter; - Board_data_data.is_header <= '0'; - Board_data_data.is_data <= '1'; - Board_data_data.is_packet <= '1'; - - Board_data_void.data_word <= (others => '0'); - Board_data_void.is_header <= '0'; - Board_data_void.is_data <= '0'; - Board_data_void.is_packet <= '0'; - - - wchannel_counter_w2 <= wchannel_counter + 1; - - n_words_in_packet_mask(0) <= bunch_pattern(3 downto 0); - n_words_in_packet_mask(1) <= bunch_pattern(7 downto 4); - n_words_in_packet_mask(2) <= bunch_pattern(11 downto 8); - n_words_in_packet_mask(3) <= bunch_pattern(15 downto 12); - n_words_in_packet_mask(4) <= bunch_pattern(19 downto 16); - n_words_in_packet_mask(5) <= bunch_pattern(23 downto 20); - n_words_in_packet_mask(6) <= bunch_pattern(27 downto 24); - n_words_in_packet_mask(7) <= bunch_pattern(31 downto 28); - n_words_in_packet_mask(8) <= (others => '0'); --- *************************************************** +begin + Board_data_O <= Board_data_gen_pipe(15) when using_generator_sc else Board_data_I; + + gen_sync_reset <= Control_register_I.reset_gensync = '1'; + bunch_freq <= to_integer(unsigned(Control_register_I.Data_Gen.bunch_freq)); + bc_start <= x"deb" when Control_register_I.Data_Gen.bc_start = 0 else + Control_register_I.Data_Gen.bc_start - 1; + +-- *************************************************** + Board_data_header.is_header <= '1'; + Board_data_header.is_data <= '1'; + Board_data_data.is_header <= '0'; + Board_data_data.is_data <= '1'; + Board_data_void.data_word <= (others => '0'); + Board_data_void.is_header <= '0'; + Board_data_void.is_data <= '0'; + + packet_size_mask(0) <= Control_register_I.Data_Gen.bunch_pattern(3 downto 0); + packet_size_mask(1) <= Control_register_I.Data_Gen.bunch_pattern(7 downto 4); + packet_size_mask(2) <= Control_register_I.Data_Gen.bunch_pattern(11 downto 8); + packet_size_mask(3) <= Control_register_I.Data_Gen.bunch_pattern(15 downto 12); + packet_size_mask(4) <= Control_register_I.Data_Gen.bunch_pattern(19 downto 16); + packet_size_mask(5) <= Control_register_I.Data_Gen.bunch_pattern(23 downto 20); + packet_size_mask(6) <= Control_register_I.Data_Gen.bunch_pattern(27 downto 24); + packet_size_mask(7) <= Control_register_I.Data_Gen.bunch_pattern(31 downto 28); +-- *************************************************** -- Data ff data clk ********************************** - process (FSM_Clocks_I.Data_Clk) - begin - - - IF(rising_edge(FSM_Clocks_I.Data_Clk) )THEN - IF (FSM_Clocks_I.Reset = '1') THEN - - bfreq_counter <= (others => '0'); - bpattern_counter <= 0; - is_boffset_sync <= '0'; - Trigger_from_CRU_40ff <= (others => '0'); - ELSE - - bfreq_counter <= bfreq_counter_next; - bpattern_counter <= bpattern_counter_next; - is_boffset_sync <= is_boffset_sync_next; - --- bunch_freq_ff01 <= bunch_freq; - - Trigger_from_CRU_40ff <= FIT_GBT_status_I.Trigger_from_CRU; - END IF; - END IF; - - end process; --- *************************************************** + process (FSM_Clocks_I.Data_Clk) + begin + if(rising_edge(FSM_Clocks_I.Data_Clk))then + if (FSM_Clocks_I.Reset_dclk = '1') then --- Data ff system clk ********************************** - process (FSM_Clocks_I.System_Clk) - begin - - IF(rising_edge(FSM_Clocks_I.System_Clk) )THEN - IF (FSM_Clocks_I.Reset = '1') THEN - Board_data_in_ff <= Board_data_void; - Board_data_gen_ff <= Board_data_void; - - FSM_STATE <= s0_wait; - pword_counter <= (others => '0'); - wchannel_counter <= (others => '0'); - n_words_in_packet_send <= (others => '0'); - - is_packet_send_for_cntr <= '0'; - is_packet_send_for_cntr_ff <= '0'; - cnt_packet_counter <= (others => '0'); - - Trigger_from_CRU_320ff <= (others => '0'); - ELSE - Board_data_in_ff <= Board_data_I; - Board_data_gen_ff <= Board_data_gen_ff_next; - - FSM_STATE <= FSM_STATE_NEXT; - pword_counter <= pword_counter_next; - wchannel_counter <= wchannel_counter_next; - n_words_in_packet_send <= n_words_in_packet_send_next; - - is_packet_send_for_cntr <= is_packet_send_for_cntr_next; - is_packet_send_for_cntr_ff <= is_packet_send_for_cntr; - cnt_packet_counter <= cnt_packet_counter_next; - - Trigger_from_CRU_320ff <= Trigger_from_CRU_40ff; - END IF; - END IF; - - end process; --- *************************************************** + bunch_counter <= 0; + bunch_in_sync <= false; + else + if (bunch_counter > 0) and (bunch_counter <= 8) then + packet_size_select <= to_integer(unsigned(packet_size_mask(bunch_counter-1))); + elsif ((Status_register_I.Trigger_from_CRU and Control_register_I.Data_Gen.trigger_resp_mask) /= TRG_const_void) then + packet_size_select <= to_integer(unsigned(packet_size_mask(0))); + else packet_size_select <= 0; end if; + -- bunch counter fsm + -- reset by gensync + if gen_sync_reset then bunch_counter <= 0; + -- start since bc_start and not in sync + elsif (not bunch_in_sync) and (Status_register_I.BCID_from_CRU = bc_start) then bunch_counter <= 1; + -- bunch_in_sync rised next cycle after sync, reset if not + elsif (not bunch_in_sync) then bunch_counter <= 0; + -- generator is off, counter max + elsif (bunch_freq = 0) or (bunch_counter = 65535) then bunch_counter <= 0; + -- counter cycle + elsif bunch_counter = bunch_freq-1 then bunch_counter <= 0; + -- counter iteration + else bunch_counter <= bunch_counter + 1; end if; + -- reset sync + if gen_sync_reset then bunch_in_sync <= false; + -- start sync when bc_start + elsif (not bunch_in_sync) and (Status_register_I.BCID_from_CRU = bc_start) and (Status_register_I.BCIDsync_Mode = mode_SYNC) then bunch_in_sync <= true; end if; --- *************************************************** + -- Event id latched to match fired bc + event_orbit <= Status_register_I.ORBIT_from_CRU_corrected; + event_bc <= Status_register_I.BCID_from_CRU_corrected; + + datagen_report_o <= datagen_report; + end if; + end if; ----------- Counters --------------------------------- -reset_offset <= Control_register_I.reset_gen_offset; --- reset_offset <= '1' WHEN (FSM_Clocks_I.Reset = '1') ELSE - -- '1' WHEN (bunch_freq /= bunch_freq_ff01) ELSE - -- '0'; - - -cnt_packet_counter_next <= (others => '0') WHEN (FSM_Clocks_I.Reset = '1') ELSE - cnt_packet_counter + 1 WHEN (is_packet_send_for_cntr = '1') and (is_packet_send_for_cntr_ff = '0') ELSE - cnt_packet_counter; - -bfreq_counter_next <= (others => '0') WHEN (FSM_Clocks_I.Reset = '1') ELSE - (others => '0') WHEN (bfreq_counter = bunch_freq-1) ELSE - (others => '0') WHEN (bunch_freq = 0) ELSE - (others => '0') WHEN (is_boffset_sync = '0') ELSE - x"0001" WHEN (FIT_GBT_status_I.BCID_from_CRU_corrected = bunch_freq_hboffset) and (FIT_GBT_status_I.BCIDsync_Mode = mode_SYNC) and (is_boffset_sync = '0') ELSE - bfreq_counter + 1; - -is_boffset_sync_next <= '0' WHEN (FSM_Clocks_I.Reset = '1') ELSE - '0' WHEN (reset_offset = '1') ELSE - '1' WHEN (is_boffset_sync = '0') and (FIT_GBT_status_I.BCID_from_CRU_corrected = bunch_freq_hboffset) and (FIT_GBT_status_I.BCIDsync_Mode = mode_SYNC) ELSE - is_boffset_sync; - -bpattern_counter_next <= 0 WHEN (FSM_Clocks_I.Reset = '1') ELSE - 0 WHEN (bfreq_counter = bunch_freq-1) ELSE - 8 WHEN (is_boffset_sync = '0') ELSE - 8 WHEN (bpattern_counter = 8) ELSE - bpattern_counter + 1; - - - -pword_counter_next <= (others => '0') WHEN (FSM_Clocks_I.Reset = '1') ELSE - (others => '0') WHEN (FSM_STATE = s0_wait) ELSE - (others => '0') WHEN (FSM_STATE = s1_header) ELSE - pword_counter + 1; - - -wchannel_counter_next <= x"1" WHEN (FSM_Clocks_I.Reset = '1') ELSE - x"1" WHEN (FSM_STATE = s0_wait) ELSE - x"1" WHEN (FSM_STATE = s1_header) ELSE - wchannel_counter + x"2"; ---wchannel_counter_next <= (others => '0') WHEN (FSM_Clocks_I.Reset = '1') ELSE --- (others => '0') WHEN (FSM_STATE = s0_wait) ELSE --- (others => '0') WHEN (FSM_STATE = s1_header) ELSE --- wchannel_counter + x"2"; - - -FSM_STATE_NEXT <= s0_wait WHEN (FSM_Clocks_I.Reset = '1') ELSE - s1_header WHEN (FSM_STATE = s0_wait) and (FSM_Clocks_I.System_Counter = x"0") and (n_words_in_packet_mask(bpattern_counter) > 0) ELSE - s1_header WHEN (FSM_STATE = s0_wait) and (FSM_Clocks_I.System_Counter = x"0") and ((Trigger_from_CRU_320ff and trigger_resp_mask) > 0) ELSE - s2_data WHEN (FSM_STATE = s1_header) ELSE - s2_data WHEN (FSM_STATE = s2_data) and (n_words_in_packet_send > pword_counter_next) ELSE - s0_wait WHEN (FSM_STATE = s2_data) and (n_words_in_packet_send = pword_counter_next) ELSE - s0_wait; - -is_packet_send_for_cntr_next <= '0' WHEN (FSM_Clocks_I.Reset = '1') ELSE - '1' WHEN (FSM_STATE = s2_data) and (FSM_STATE_NEXT = s0_wait) ELSE - '0' WHEN (FSM_Clocks_I.System_Counter = x"0") ELSE - is_packet_send_for_cntr; - -n_words_in_packet_send_next <= (others => '0') WHEN (FSM_Clocks_I.Reset = '1') ELSE - n_words_in_packet_mask(0) WHEN (FSM_STATE = s0_wait) and (FSM_STATE_NEXT = s1_header) and ((Trigger_from_CRU_320ff and trigger_resp_mask) > 0) ELSE - n_words_in_packet_mask(bpattern_counter) WHEN (FSM_STATE = s0_wait) and (FSM_STATE_NEXT = s1_header) ELSE - n_words_in_packet_send; - - ----------- Board data gen --------------------------- -Board_data_gen_ff_next <= Board_data_void WHEN (FSM_Clocks_I.Reset = '1') ELSE - Board_data_void WHEN (FSM_STATE = s0_wait) ELSE - Board_data_header WHEN (FSM_STATE = s1_header) ELSE - Board_data_data WHEN (FSM_STATE = s2_data) ELSE - Board_data_void; + end process; -- *************************************************** +-- Data ff system clk ********************************** + process (FSM_Clocks_I.System_Clk) + begin + + if(rising_edge(FSM_Clocks_I.System_Clk))then + + + if (FSM_Clocks_I.Reset_sclk = '1') then + + word_counter <= 16; + Board_data_gen_pipe <= (others => Board_data_void); + using_generator_sc <= false; + gen_sync_reset_sc <= gen_sync_reset; + cnt_packet_counter <= (others => '0'); + + datagen_report.orbit <= (others => '0'); + datagen_report.bc <= (others => '0'); + datagen_report.size <= (others => '0'); + datagen_report.packet_num <= (others => '0'); + + + else + + packet_size_select_sc <= packet_size_select; + using_generator_sc <= Control_register_I.Data_Gen.usage_generator = data_gen_on; + + Board_data_gen_pipe(0) <= data_gen_result; + Board_data_gen_pipe(1 to 15) <= Board_data_gen_pipe(0 to 14); + + -- start event + if (FSM_Clocks_I.System_Counter = x"1") and (word_counter = 16 or word_counter = event_size) and (packet_size_select_sc > 0) then + event_size <= packet_size_select_sc; + event_orbit_sc <= event_orbit; + event_bc_sc <= event_bc; + event_rx_ph <= Status_register_I.rx_phase; + event_rx_ph_err <= Status_register_I.Rx_Phase_error; + word_counter <= 0; + cnt_packet_counter <= cnt_packet_counter + 1; + + -- not sending + elsif word_counter = 16 then word_counter <= 16; + -- stop event (event size -1 to send zero packets) + elsif word_counter = event_size-1 then word_counter <= 16; + -- sending event + else word_counter <= word_counter +1; end if; + + -- reset packet counter + if gen_sync_reset_sc then cnt_packet_counter <= (others => '0'); end if; + + + if IS_SIMULATION = 1 then + -- datagenreport sync to output data. pipe(6) is the last 320 cycle before 40 cycle + if Board_data_gen_pipe(3).is_header = '1' then + datagen_report.orbit <= func_FITDATAHD_orbit(Board_data_gen_pipe(3).data_word); + datagen_report.bc <= func_FITDATAHD_bc(Board_data_gen_pipe(3).data_word); + datagen_report.size <= func_FITDATAHD_ndwords(Board_data_gen_pipe(3).data_word)+1; -- +1 for marking zero packets + datagen_report.packet_num <= Board_data_gen_pipe(2).data_word(35 downto 0); + else + datagen_report.orbit <= (others => '0'); + datagen_report.bc <= (others => '0'); + datagen_report.size <= (others => '0'); + datagen_report.packet_num <= (others => '0'); + end if; + end if; + + end if; + end if; + + end process; +-- *************************************************** + Board_data_data.data_word <= std_logic_vector(to_unsigned((word_counter+1), tdwords_bitdepth)) & cnt_packet_counter & std_logic_vector(to_unsigned((word_counter+1), tdwords_bitdepth)) & cnt_packet_counter; + Board_data_header.data_word <= func_FITDATAHD_get_header(std_logic_vector(to_unsigned(event_size-1, n_pckt_wrds_bitdepth)), event_orbit_sc, event_bc_sc, event_rx_ph, event_rx_ph_err, '0'); + + data_gen_result <= Board_data_void when (word_counter = 16) else + Board_data_header when (word_counter = 0) else + Board_data_data; + + end Behavioral; diff --git a/firmware/common/gbt-readout/hdl/Module_Data_Gen_TCM.vhd b/firmware/common/gbt-readout/hdl/Module_Data_Gen_TCM.vhd index 0a83d6b..4622b25 100644 --- a/firmware/common/gbt-readout/hdl/Module_Data_Gen_TCM.vhd +++ b/firmware/common/gbt-readout/hdl/Module_Data_Gen_TCM.vhd @@ -2,267 +2,233 @@ -- Company: INR RAS -- Engineer: Finogeev D. A. dmitry-finogeev@yandex.ru -- --- Create Date: 07/11/2017 --- Design Name: --- Module Name: RXDATA_CLKSync - Behavioral --- Project Name: --- Target Devices: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision --- Additional Comments: +-- Create Date: 2017 +-- Description: generate data test pattern for standalone tests +-- Compare to PM data, TCM generate two gbt words per sysclk cycle +-- The emulator generates 160 bit words instead 80 bit words +-- First word always header and first data word +-- Bunch pattern define numger of 160 bit word +-- Actual number of tcm packet payload is n*2+1 or nword<<1 + 1 +-- There is no channels enumerating in gbt payload. each gbt word is counter -- +-- Revision: 07/2021 ---------------------------------------------------------------------------------- library IEEE; -use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_1164.all; use ieee.numeric_std.all; -use ieee.std_logic_unsigned.all ; +use ieee.std_logic_unsigned.all; use work.fit_gbt_common_package.all; use work.fit_gbt_board_package.all; entity Module_Data_Gen is - Port ( - FSM_Clocks_I : in FSM_Clocks_type; - - FIT_GBT_status_I : in FIT_GBT_status_type; - Control_register_I : in CONTROL_REGISTER_type; - - Board_data_I : in board_data_type; - Board_data_O : out board_data_type; - data_gen_report_O : out std_logic_vector(31 downto 0) - ); + generic ( + IS_SIMULATION : integer := 0 + ); + port ( + FSM_Clocks_I : in rdclocks_t; + + Status_register_I : in readout_status_t; + Control_register_I : in readout_control_t; + + Board_data_I : in board_data_type; + Board_data_O : out board_data_type; + datagen_report_o : out datagen_report_t + ); end Module_Data_Gen; architecture Behavioral of Module_Data_Gen is - signal Board_data_gen_ff, Board_data_gen_ff_next, Board_data_in_ff : board_data_type; - signal Board_data_header, Board_data_data, Board_data_void : board_data_type; - - - signal Trigger_from_CRU_40ff, Trigger_from_CRU_320ff : std_logic_vector(Trigger_bitdepth-1 downto 0); -- Trigger ID from CRUS - - - signal trigger_resp_mask : std_logic_vector(Trigger_bitdepth-1 downto 0); - signal bunch_pattern : std_logic_vector(31 downto 0); - signal bunch_freq, bunch_freq_ff01 : std_logic_vector(15 downto 0); - signal bunch_freq_hboffset : std_logic_vector(BC_id_bitdepth-1 downto 0); - signal reset_offset : std_logic; - - type n_words_in_packet_arr_type is array (0 to 8) of std_logic_vector(3 downto 0); - signal n_words_in_packet_mask : n_words_in_packet_arr_type; - signal n_words_in_packet_send, n_words_in_packet_send_next : std_logic_vector(3 downto 0); - signal n_words_in_packet_send_tcm : std_logic_vector(n_pckt_wrds_bitdepth-1 downto 0); - - type FSM_STATE_T is (s0_wait, s1_header, s2_data); - signal FSM_STATE, FSM_STATE_NEXT : FSM_STATE_T; - - signal is_packet_send_for_cntr, is_packet_send_for_cntr_ff, is_packet_send_for_cntr_next : std_logic; - signal bfreq_counter, bfreq_counter_next : std_logic_vector(15 downto 0); - signal is_boffset_sync, is_boffset_sync_next : std_logic; - signal bpattern_counter, bpattern_counter_next : integer := 0; - signal cnt_packet_counter, cnt_packet_counter_next : std_logic_vector(data_word_bitdepth/2-1 downto 0); -- continious packet counter - signal pword_counter, pword_counter_next : std_logic_vector(3 downto 0); - - signal data_gen_report : std_logic_vector(31 downto 0); -- used only in simulation - - - - - attribute keep : string; - attribute keep of Board_data_gen_ff : signal is "true"; - - -begin - trigger_resp_mask <= Control_register_I.Data_Gen.trigger_resp_mask; - bunch_pattern <=Control_register_I.Data_Gen.bunch_pattern; - bunch_freq <= Control_register_I.Data_Gen.bunch_freq; - bunch_freq_hboffset <= Control_register_I.Data_Gen.bunch_freq_hboffset; - - n_words_in_packet_send_tcm <= x"0" & n_words_in_packet_send(2 downto 0) & "1"; + -- data generator bunch pattern + signal gen_sync_reset, gen_sync_reset_sc : boolean; + signal bc_start : std_logic_vector(BC_id_bitdepth-1 downto 0); + signal bunch_freq : natural range 0 to 65535; + signal using_generator_sc : boolean; + type packet_size_mask_t is array (0 to 7) of std_logic_vector(3 downto 0); + signal packet_size_mask : packet_size_mask_t; + signal packet_size_select, packet_size_select_sc : natural range 0 to 15; - data_gen_report_O <= data_gen_report; - data_gen_report <= x"0000_000" & n_words_in_packet_mask(bpattern_counter); + -- fsm signals + signal bunch_counter : natural range 0 to 65535; + signal bunch_in_sync : boolean; + signal event_orbit, event_orbit_sc : std_logic_vector(Orbit_id_bitdepth-1 downto 0); + signal event_bc, event_bc_sc : std_logic_vector(BC_id_bitdepth-1 downto 0); + signal event_rx_ph : std_logic_vector(rx_phase_bitdepth-1 downto 0); + signal event_rx_ph_err : std_logic; + signal event_size : natural range 0 to 15; + signal word_counter : natural range 0 to 16; + signal cnt_packet_counter : std_logic_vector(data_word_bitdepth/2-1 downto 0); -- continious packet counter + signal Board_data_header, Board_data_data, Board_data_void, data_gen_result : board_data_type; + signal datagen_report, datagen_report_ff : datagen_report_t; --- *************************************************** - Board_data_O <= Board_data_gen_ff WHEN (Control_register_I.Data_Gen.usage_generator = use_MAIN_generator) ELSE Board_data_in_ff; - - Board_data_header.data_word <= func_FITDATAHD_get_header(n_words_in_packet_send_tcm, FIT_GBT_status_I.ORBIT_from_CRU_corrected, - FIT_GBT_status_I.BCID_from_CRU_corrected, FIT_GBT_status_I.rx_phase, FIT_GBT_status_I.GBT_status.Rx_Phase_error, '1') & cnt_packet_counter; --- Board_data_header.data_word <= (others => '0'); - Board_data_header.is_header <= '1'; - Board_data_header.is_data <= '1'; --- Board_data_header.is_packet <= '1'; - - Board_data_data.data_word <= cnt_packet_counter & cnt_packet_counter; - Board_data_data.is_header <= '0'; - Board_data_data.is_data <= '1'; --- Board_data_data.is_packet <= '1'; - - Board_data_void.data_word <= (others => '0'); - Board_data_void.is_header <= '0'; - Board_data_void.is_data <= '0'; --- Board_data_void.is_packet <= '0'; - - - n_words_in_packet_mask(0) <= bunch_pattern(3 downto 0); - n_words_in_packet_mask(1) <= bunch_pattern(7 downto 4); - n_words_in_packet_mask(2) <= bunch_pattern(11 downto 8); - n_words_in_packet_mask(3) <= bunch_pattern(15 downto 12); - n_words_in_packet_mask(4) <= bunch_pattern(19 downto 16); - n_words_in_packet_mask(5) <= bunch_pattern(23 downto 20); - n_words_in_packet_mask(6) <= bunch_pattern(27 downto 24); - n_words_in_packet_mask(7) <= bunch_pattern(31 downto 28); - n_words_in_packet_mask(8) <= (others => '0'); --- *************************************************** + -- simulating data delay in PM/TCM FEE logic to check start data rejection in selector + type board_data_type_arr16 is array (0 to 15) of board_data_type; + signal Board_data_gen_pipe : board_data_type_arr16; --- Data ff data clk ********************************** - process (FSM_Clocks_I.Data_Clk) - begin - - - IF(rising_edge(FSM_Clocks_I.Data_Clk) )THEN - IF (FSM_Clocks_I.Reset40 = '1') THEN - - bfreq_counter <= (others => '0'); - bpattern_counter <= 0; - is_boffset_sync <= '0'; - Trigger_from_CRU_40ff <= (others => '0'); - ELSE - - bfreq_counter <= bfreq_counter_next; - bpattern_counter <= bpattern_counter_next; - is_boffset_sync <= is_boffset_sync_next; - - bunch_freq_ff01 <= bunch_freq; - - Trigger_from_CRU_40ff <= FIT_GBT_status_I.Trigger_from_CRU; - END IF; - END IF; - - end process; +begin + + Board_data_O <= Board_data_gen_pipe(15) when using_generator_sc else Board_data_I; + + gen_sync_reset <= Control_register_I.reset_gensync = '1'; + bunch_freq <= to_integer(unsigned(Control_register_I.Data_Gen.bunch_freq)); + bc_start <= x"deb" when Control_register_I.Data_Gen.bc_start = 0 else + Control_register_I.Data_Gen.bc_start - 1; + +-- *************************************************** + Board_data_header.is_header <= '1'; + Board_data_header.is_data <= '1'; + Board_data_data.is_header <= '0'; + Board_data_data.is_data <= '1'; + Board_data_void.data_word <= (others => '0'); + Board_data_void.is_header <= '0'; + Board_data_void.is_data <= '0'; + + packet_size_mask(0) <= Control_register_I.Data_Gen.bunch_pattern(3 downto 0); + packet_size_mask(1) <= Control_register_I.Data_Gen.bunch_pattern(7 downto 4); + packet_size_mask(2) <= Control_register_I.Data_Gen.bunch_pattern(11 downto 8); + packet_size_mask(3) <= Control_register_I.Data_Gen.bunch_pattern(15 downto 12); + packet_size_mask(4) <= Control_register_I.Data_Gen.bunch_pattern(19 downto 16); + packet_size_mask(5) <= Control_register_I.Data_Gen.bunch_pattern(23 downto 20); + packet_size_mask(6) <= Control_register_I.Data_Gen.bunch_pattern(27 downto 24); + packet_size_mask(7) <= Control_register_I.Data_Gen.bunch_pattern(31 downto 28); -- *************************************************** +-- Data ff data clk ********************************** + process (FSM_Clocks_I.Data_Clk) + begin + if(rising_edge(FSM_Clocks_I.Data_Clk))then + + if (FSM_Clocks_I.Reset_dclk = '1') then + + bunch_counter <= 0; + bunch_in_sync <= false; + + else + + if (bunch_counter > 0) and (bunch_counter <= 8) then + packet_size_select <= to_integer(unsigned(packet_size_mask(bunch_counter-1))); + elsif ((Status_register_I.Trigger_from_CRU and Control_register_I.Data_Gen.trigger_resp_mask) /= TRG_const_void) then + packet_size_select <= to_integer(unsigned(packet_size_mask(0))); + else packet_size_select <= 0; end if; + + -- bunch counter fsm + -- reset by gensync + if gen_sync_reset then bunch_counter <= 0; + -- start since bc_start and not in sync + elsif (not bunch_in_sync) and (Status_register_I.BCID_from_CRU = bc_start) then bunch_counter <= 1; + -- bunch_in_sync rised next cycle after sync, reset if not + elsif (not bunch_in_sync) then bunch_counter <= 0; + -- generator is off, counter max + elsif (bunch_freq = 0) or (bunch_counter = 65535) then bunch_counter <= 0; + -- counter cycle + elsif bunch_counter = bunch_freq-1 then bunch_counter <= 0; + -- counter iteration + else bunch_counter <= bunch_counter + 1; end if; + + -- reset sync + if gen_sync_reset then bunch_in_sync <= false; + -- start sync when bc_start + elsif (not bunch_in_sync) and (Status_register_I.BCID_from_CRU = bc_start) and (Status_register_I.BCIDsync_Mode = mode_SYNC) then bunch_in_sync <= true; end if; + + -- Event id latched to match fired bc + event_orbit <= Status_register_I.ORBIT_from_CRU_corrected; + event_bc <= Status_register_I.BCID_from_CRU_corrected; + + datagen_report_o <= datagen_report_ff; + datagen_report_ff <= datagen_report; + + end if; + + end if; + + end process; +-- *************************************************** -- Data ff system clk ********************************** - process (FSM_Clocks_I.System_Clk) - begin - - IF(rising_edge(FSM_Clocks_I.System_Clk) )THEN - IF (FSM_Clocks_I.Reset = '1') THEN - Board_data_in_ff <= Board_data_void; - Board_data_gen_ff <= Board_data_void; - - FSM_STATE <= s0_wait; - pword_counter <= (others => '0'); - n_words_in_packet_send <= (others => '0'); - - is_packet_send_for_cntr <= '0'; - is_packet_send_for_cntr_ff <= '0'; - cnt_packet_counter <= (others => '0'); - Trigger_from_CRU_320ff <= (others => '0'); - ELSE - Board_data_in_ff <= Board_data_I; - Board_data_gen_ff <= Board_data_gen_ff_next; - - FSM_STATE <= FSM_STATE_NEXT; - pword_counter <= pword_counter_next; - n_words_in_packet_send <= n_words_in_packet_send_next; - - is_packet_send_for_cntr <= is_packet_send_for_cntr_next; - is_packet_send_for_cntr_ff <= is_packet_send_for_cntr; - cnt_packet_counter <= cnt_packet_counter_next; - - Trigger_from_CRU_320ff <= Trigger_from_CRU_40ff; - END IF; - END IF; - - end process; --- *************************************************** + process (FSM_Clocks_I.System_Clk) + begin + if(rising_edge(FSM_Clocks_I.System_Clk))then + if (FSM_Clocks_I.Reset_sclk = '1') then + word_counter <= 16; + Board_data_gen_pipe <= (others => Board_data_void); + using_generator_sc <= false; + gen_sync_reset_sc <= gen_sync_reset; + cnt_packet_counter <= (others => '0'); --- *************************************************** + datagen_report.orbit <= (others => '0'); + datagen_report.bc <= (others => '0'); + datagen_report.size <= (others => '0'); + datagen_report.packet_num <= (others => '0'); + else ----------- Counters --------------------------------- -reset_offset <= Control_register_I.reset_gen_offset; --- reset_offset <= '1' WHEN (FSM_Clocks_I.Reset = '1') ELSE - -- '1' WHEN (bunch_freq /= bunch_freq_ff01) ELSE - -- '0'; - - -cnt_packet_counter_next <= (others => '0') WHEN (FSM_Clocks_I.Reset = '1') ELSE - cnt_packet_counter + 1 WHEN (is_packet_send_for_cntr = '1') and (is_packet_send_for_cntr_ff = '0') ELSE - cnt_packet_counter; - -bfreq_counter_next <= (others => '0') WHEN (FSM_Clocks_I.Reset = '1') ELSE - (others => '0') WHEN (bfreq_counter = bunch_freq-1) ELSE - (others => '0') WHEN (bunch_freq = 0) ELSE - (others => '0') WHEN (is_boffset_sync = '0') ELSE - x"0001" WHEN (FIT_GBT_status_I.BCID_from_CRU_corrected = bunch_freq_hboffset) and (FIT_GBT_status_I.BCIDsync_Mode = mode_SYNC) and (is_boffset_sync = '0') ELSE - bfreq_counter + 1; - -is_boffset_sync_next <= '0' WHEN (FSM_Clocks_I.Reset = '1') ELSE - '0' WHEN (reset_offset = '1') ELSE - '1' WHEN (is_boffset_sync = '0') and (FIT_GBT_status_I.BCID_from_CRU_corrected = bunch_freq_hboffset) and (FIT_GBT_status_I.BCIDsync_Mode = mode_SYNC) ELSE - is_boffset_sync; - -bpattern_counter_next <= 0 WHEN (FSM_Clocks_I.Reset = '1') ELSE - 0 WHEN (bfreq_counter = bunch_freq-1) ELSE - 8 WHEN (is_boffset_sync = '0') ELSE - 8 WHEN (bpattern_counter = 8) ELSE - bpattern_counter + 1; - - - -pword_counter_next <= (others => '0') WHEN (FSM_Clocks_I.Reset = '1') ELSE - (others => '0') WHEN (FSM_STATE = s0_wait) ELSE - (others => '0') WHEN (FSM_STATE = s1_header) ELSE - pword_counter + 1; - - - -FSM_STATE_NEXT <= s0_wait WHEN (FSM_Clocks_I.Reset = '1') ELSE - s1_header WHEN (FSM_STATE = s0_wait) and (FSM_Clocks_I.System_Counter = x"0") and (n_words_in_packet_mask(bpattern_counter) > 0) ELSE - s1_header WHEN (FSM_STATE = s0_wait) and (FSM_Clocks_I.System_Counter = x"0") and ((Trigger_from_CRU_320ff and trigger_resp_mask) > 0) ELSE - s2_data WHEN (FSM_STATE = s1_header) ELSE - s2_data WHEN (FSM_STATE = s2_data) and (n_words_in_packet_send > pword_counter_next) ELSE - s0_wait WHEN (FSM_STATE = s2_data) and (n_words_in_packet_send = pword_counter_next) ELSE - s0_wait; - -is_packet_send_for_cntr_next <= '0' WHEN (FSM_Clocks_I.Reset = '1') ELSE - '1' WHEN (FSM_STATE = s2_data) and (FSM_STATE_NEXT = s0_wait) ELSE - '0' WHEN (FSM_Clocks_I.System_Counter = x"0") ELSE - is_packet_send_for_cntr; - -n_words_in_packet_send_next <= (others => '0') WHEN (FSM_Clocks_I.Reset = '1') ELSE - n_words_in_packet_mask(0) WHEN (FSM_STATE = s0_wait) and (FSM_STATE_NEXT = s1_header) and ((Trigger_from_CRU_320ff and trigger_resp_mask) > 0) ELSE - n_words_in_packet_mask(bpattern_counter) WHEN (FSM_STATE = s0_wait) and (FSM_STATE_NEXT = s1_header) ELSE - n_words_in_packet_send; - - - ----------- Board data gen --------------------------- -Board_data_gen_ff_next <= Board_data_void WHEN (FSM_Clocks_I.Reset = '1') ELSE - Board_data_void WHEN (FSM_STATE = s0_wait) ELSE - Board_data_header WHEN (FSM_STATE = s1_header) ELSE - Board_data_data WHEN (FSM_STATE = s2_data) ELSE - Board_data_void; + -- for TCM n gbt words is 2n+1, max pattern size is 7 + if packet_size_select < 7 then packet_size_select_sc <= packet_size_select; else packet_size_select_sc <= 7; end if; + using_generator_sc <= Control_register_I.Data_Gen.usage_generator = data_gen_on; + + Board_data_gen_pipe(0) <= data_gen_result; + Board_data_gen_pipe(1 to 15) <= Board_data_gen_pipe(0 to 14); + + -- start event + if (FSM_Clocks_I.System_Counter = x"1") and (word_counter = 16 or word_counter = event_size) and (packet_size_select_sc > 0) then + event_size <= packet_size_select_sc; + event_orbit_sc <= event_orbit; + event_bc_sc <= event_bc; + event_rx_ph <= Status_register_I.rx_phase; + event_rx_ph_err <= Status_register_I.Rx_Phase_error; + word_counter <= 0; + cnt_packet_counter <= cnt_packet_counter + 1; + + + -- not sending + elsif word_counter = 16 then word_counter <= 16; + -- stop event + elsif word_counter = event_size then word_counter <= 16; + -- sending event + else word_counter <= word_counter +1; end if; + + -- reset packet counter + if gen_sync_reset_sc then cnt_packet_counter <= (others => '0'); end if; + + -- datagenreport sync to output data. pipe(6) is the last 320 cycle before 40 cycle + if IS_SIMULATION = 1 then + if Board_data_gen_pipe(11).is_header = '1' then + datagen_report.orbit <= func_FITDATAHD_orbit(Board_data_gen_pipe(11).data_word(159 downto 80)); + datagen_report.bc <= func_FITDATAHD_bc(Board_data_gen_pipe(11).data_word(159 downto 80)); + datagen_report.size <= func_FITDATAHD_ndwords(Board_data_gen_pipe(11).data_word(159 downto 80)); + datagen_report.packet_num <= Board_data_gen_pipe(11).data_word(35 downto 0); + else + datagen_report.orbit <= (others => '0'); + datagen_report.bc <= (others => '0'); + datagen_report.size <= (others => '0'); + datagen_report.packet_num <= (others => '0'); + end if; + end if; + + + end if; + end if; + + end process; -- *************************************************** + Board_data_data.data_word <= cnt_packet_counter & cnt_packet_counter; + Board_data_header.data_word <= func_FITDATAHD_get_header(std_logic_vector(to_unsigned(event_size*2+1, n_pckt_wrds_bitdepth)), event_orbit_sc, event_bc_sc, event_rx_ph, event_rx_ph_err, '1') & cnt_packet_counter; + + data_gen_result <= Board_data_void when (word_counter = 16) else + Board_data_header when (word_counter = 0) else + Board_data_data; + end Behavioral; diff --git a/firmware/common/gbt-readout/hdl/Module_FIFO_Data_Converter.vhd b/firmware/common/gbt-readout/hdl/Module_FIFO_Data_Converter.vhd deleted file mode 100644 index 4e02f3e..0000000 --- a/firmware/common/gbt-readout/hdl/Module_FIFO_Data_Converter.vhd +++ /dev/null @@ -1,253 +0,0 @@ ----------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 15:42:21 04/12/2017 --- Design Name: --- Module Name: Test_Generator - Behavioral --- Project Name: --- Target Devices: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use work.fit_gbt_common_package.all; -use work.fit_gbt_board_package.all; - - -entity Module_FIFO_Data_Converter is - Port ( - FSM_Clocks_I : in FSM_Clocks_type; - - FIT_GBT_status_I : in FIT_GBT_status_type; - Control_register_I : in CONTROL_REGISTER_type; - - MODULE_data_I : in module_data_type; - FIFO_is_space_for_packet_I : in boolean; - - FIFO_WE_O : out STD_LOGIC; - FIFO_data_word_O : out std_logic_vector(fifo_data_bitdepth-1 downto 0) - ); -end Module_FIFO_Data_Converter; - -architecture Behavioral of Module_FIFO_Data_Converter is - - type FSM_STATE_T is (s1_head, s2_word); - signal FSM_STATE, FSM_STATE_NEXT : FSM_STATE_T; - signal Is_First_word, Is_First_word_next : boolean; - - signal N_Words_In_packet : std_logic_vector(tdwords_bitdepth-1 downto 0); - signal FIFO_data_word : std_logic_vector(fifo_word_bitdeph-1 downto 0); - signal FIFO_header_word : std_logic_vector(fifo_header_bitdepth-1 downto 0); - - signal FIFO_data_word_ff, FIFO_data_word_ff_next : std_logic_vector(fifo_data_bitdepth-1 downto 0); - signal FIFO_WE_ff, FIFO_WE_ff_next : STD_LOGIC; - signal MODULE_data_I_ff, MODULE_data_I_ff_next : module_data_type; - - - signal Data_Strobe_zero : std_logic_vector(0 to total_data_words-1); - signal Data_Strobe_input : std_logic_vector(0 to total_data_words-1); - signal Data_Strobe_to_sel : std_logic_vector(0 to total_data_words-1); - signal Data_Strobe_next_from_sel : std_logic_vector(0 to total_data_words-1); - - signal Data_Strobe : std_logic_vector(0 to total_data_words-1); - - signal Is_input_data_void : boolean; - signal Is_strobe_data_void : boolean; - signal Is_strobe_data_void_from_sel : boolean; - - signal First_n_words_from_strobe : words_to_write_type; - signal First_n_words : words_to_write_type; - -begin - - FIFO_data_word_O <= FIFO_data_word_ff; - FIFO_WE_O <= FIFO_WE_ff; - - Data_Strobe_zero <= (others => '0'); - - FIFO_header_word(event_id_bitdepth-1 downto 0) <= MODULE_data_I_ff.EVENT_ID; - FIFO_header_word(event_id_bitdepth+rx_phase_bitdepth-1 downto event_id_bitdepth) <= MODULE_data_I_ff.rx_phase; - FIFO_header_word(fifo_header_bitdepth-1 downto event_id_bitdepth+rx_phase_bitdepth) <= N_Words_In_packet; - - MODULE_data_I_ff_next <= MODULE_data_I; - --- Module Data Strobe ====================================== - Module_Data_Strobe_comp: entity work.Module_Data_Strobe - port map ( - MODULE_data_I => MODULE_data_I_ff, - - Module_Data_Strobe_O => Data_Strobe_input, - N_Words_In_packet_O => N_Words_In_packet, - Is_Module_data_void_O => Is_input_data_void - ); --- =========================================================== - --- Module Data Selector ====================================== - Module_Data_Selector_comp: entity work.Module_Data_Selector - port map ( - Data_Strobe_I => Data_Strobe_to_sel, - - Data_Strobe_next_O => Data_Strobe_next_from_sel, - First_n_words_O => First_n_words_from_strobe, - Is_strobe_data_void_O => Is_strobe_data_void_from_sel - ); --- =========================================================== - --- -- Module Data first n words by strobe ======================= - -- Module_Data_strobe_first_n_words_comp: entity work.Module_Data_strobe_first_n_words - -- port map ( - -- Data_Strobe_I => Data_Strobe_to_sel, - - -- first_n_words_O => First_n_words_from_strobe - -- ); --- -- =========================================================== - --- Module form FIFO Data ==================================== - Module_Data_Form_FIFO_Word_comp: entity work.Module_Data_Form_FIFO_Word - port map ( - MODULE_data_I => MODULE_data_I_ff, - Words_to_write_I => First_n_words, - - FIFO_data_word_O => FIFO_data_word - ); --- =========================================================== - - PROCESS (SysClk_I) - BEGIN - - IF(SysClk_I'EVENT and SysClk_I = '1') THEN - - IF(RESET_I = '1') THEN - FSM_STATE <= s2_word; - Is_First_word <= false; - Data_Strobe <= Data_Strobe_zero; - Is_strobe_data_void <= true; - - ELSE - FSM_STATE <= FSM_STATE_NEXT; - Is_First_word <= Is_First_word_next; - First_n_words <= First_n_words_from_strobe; - Data_Strobe <= Data_Strobe_next_from_sel; - Is_strobe_data_void <= Is_strobe_data_void_from_sel; - - FIFO_data_word_ff <= FIFO_data_word_ff_next; - FIFO_WE_ff <= FIFO_WE_ff_next; - - MODULE_data_I_ff <= MODULE_data_I_ff_next; - END IF; - - END IF; - - - FIFO_WE_ff_next <= '0'; - - case FSM_STATE is - - when s1_head => - FSM_STATE_NEXT <= s2_word; - Is_First_word_next <= true; - Data_Strobe_to_sel <= Data_Strobe_input; - - FIFO_data_word_ff_next <= (others => '0'); - FIFO_data_word_ff_next(fifo_header_bitdepth-1 downto 0) <= FIFO_header_word; - - -- if( not Is_input_data_void) then - if( - (not Is_input_data_void) or - ((MODULE_data_I_ff.EVENT_ID(event_id_bitdepth-1 downto event_id_bitdepth - Trigger_bitdepth) - and x"ffffffff") /= TRG_const_void) - ) then - FIFO_WE_ff_next <= '1'; - else - -- change to 1 for whaiting header of void data - FIFO_WE_ff_next <= '0'; - end if; - - when s2_word => - Is_First_word_next <= false; - Data_Strobe_to_sel <= Data_Strobe; - - FIFO_data_word_ff_next <= (others => '0'); - FIFO_data_word_ff_next(fifo_word_bitdeph-1 downto 0) <= FIFO_data_word; - - if( not Is_strobe_data_void ) then - FIFO_WE_ff_next <= '1'; - else - FIFO_WE_ff_next <= '0'; - end if; - --- if(Is_strobe_data_void and (Data_Clk_strobe_I = '1')) then - if(Is_strobe_data_void and (SysClk_count_I = x"0")) then - FSM_STATE_NEXT <= s1_head; - else - FSM_STATE_NEXT <= s2_word; - end if; - end case; - - - END PROCESS; - - - -- process (FSM_STATE, Data_Strobe_input, Data_Strobe, Is_input_data_void, Is_strobe_data_void, FIFO_is_space_for_packet_I, SysClk_count_I, FIFO_header_word, FIFO_data_word) - -- begin - -- FIFO_WE_ff_next <= '0'; - - -- case FSM_STATE is - - -- when s1_head => - -- FSM_STATE_NEXT <= s2_word; - -- Is_First_word_next <= true; - -- Data_Strobe_to_sel <= Data_Strobe_input; - - -- FIFO_data_word_ff_next <= (others => '0'); - -- FIFO_data_word_ff_next(fifo_header_bitdepth-1 downto 0) <= FIFO_header_word; - - -- -- if( not Is_input_data_void) then - -- if( - -- (not Is_input_data_void) or - -- ((MODULE_data_I_ff.EVENT_ID(event_id_bitdepth-1 downto event_id_bitdepth - Trigger_bitdepth) - -- and TRG_const_response) /= TRG_const_void) - -- ) then - -- FIFO_WE_ff_next <= '1'; - -- else - -- -- change to 1 for whaiting header of void data - -- FIFO_WE_ff_next <= '0'; - -- end if; - - -- when s2_word => - -- Is_First_word_next <= false; - -- Data_Strobe_to_sel <= Data_Strobe; - - -- FIFO_data_word_ff_next <= (others => '0'); - -- FIFO_data_word_ff_next(fifo_word_bitdeph-1 downto 0) <= FIFO_data_word; - - -- if( not Is_strobe_data_void ) then - -- FIFO_WE_ff_next <= '1'; - -- else - -- FIFO_WE_ff_next <= '0'; - -- end if; - --- -- if(Is_strobe_data_void and (Data_Clk_strobe_I = '1')) then - -- if(Is_strobe_data_void and (SysClk_count_I = 0)) then - -- FSM_STATE_NEXT <= s1_head; - -- else - -- FSM_STATE_NEXT <= s2_word; - -- end if; - -- end case; - - - -- end process; - - - -end Behavioral; - diff --git a/firmware/common/gbt-readout/hdl/RXDataClkSync.vhd b/firmware/common/gbt-readout/hdl/RXDataClkSync.vhd index 662354d..16413ff 100644 --- a/firmware/common/gbt-readout/hdl/RXDataClkSync.vhd +++ b/firmware/common/gbt-readout/hdl/RXDataClkSync.vhd @@ -2,145 +2,149 @@ -- Company: INR RAS -- Engineer: Finogeev D. A. dmitry-finogeev@yandex.ru -- --- Create Date: 06/11/2017 --- Design Name: --- Module Name: RXDATA_CLKSync - Behavioral --- Project Name: --- Target Devices: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision --- Additional Comments: +-- Create Date: 2017 +-- Description: GBT RX data clock domain crossing RX -> Data clocks; RX->Data_Clk phase counter @320MHz -- +-- Revision: 06/2021 ---------------------------------------------------------------------------------- library IEEE; -use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_1164.all; use ieee.numeric_std.all; use ieee.std_logic_unsigned.all; use work.fit_gbt_common_package.all; entity RXDATA_CLKSync is -Port ( - FSM_Clocks_I : in FSM_Clocks_type; - Control_register_I : in CONTROL_REGISTER_type; - - RX_CLK_I : in STD_LOGIC; -- 40MHz RX word clock - - RX_IS_DATA_RXCLK_I : in STD_LOGIC; -- data@RX_CLK - RX_DATA_RXCLK_I : in STD_LOGIC_VECTOR (GBT_data_word_bitdepth+GBT_slowcntr_bitdepth-1 downto 0); -- data@RX_CLK - - RX_IS_DATA_DATACLK_O : out STD_LOGIC; -- data@SYS_CLK - RX_DATA_DATACLK_O : out STD_LOGIC_VECTOR (GBT_data_word_bitdepth+GBT_slowcntr_bitdepth-1 downto 0); -- data@SYS_CLK - - CLK_PH_CNT_O : out std_logic_vector(rx_phase_bitdepth-1 downto 0); - CLK_PH_ERROR_O : out std_logic; - - rx_ph320 : out std_logic_vector(2 downto 0); - ph_error320 : out std_logic - ); + port ( + FSM_Clocks_I : in rdclocks_t; + Control_register_I : in readout_control_t; + + RX_CLK_I : in std_logic; -- 40MHz RX word clock + + RX_IS_DATA_RXCLK_I : in std_logic; -- data@RX_CLK + RX_DATA_RXCLK_I : in std_logic_vector (GBT_data_word_bitdepth+GBT_slowcntr_bitdepth-1 downto 0); -- data@RX_CLK + + RX_IS_DATA_DATACLK_O : out std_logic; -- data@SYS_CLK + RX_DATA_DATACLK_O : out std_logic_vector (GBT_data_word_bitdepth+GBT_slowcntr_bitdepth-1 downto 0); -- data@SYS_CLK + + CLK_PH_CNT_O : out std_logic_vector(rx_phase_bitdepth-1 downto 0); + CLK_PH_ERROR_O : out std_logic + ); end RXDATA_CLKSync; architecture Behavioral of RXDATA_CLKSync is -- rx clk ff by sysclk - signal RX_CLK_from00, RX_CLK_from01, RX_CLK_from02 : STD_LOGIC; - + signal RX_CLK_from00, RX_CLK_from01, RX_CLK_from02 : std_logic; + -- -- I data ff by rx clk -- -- data ff by sysclk - signal RX_IS_DATA_DATACLK : STD_LOGIC; - signal RX_DATA_DATACLK : STD_LOGIC_VECTOR (GBT_data_word_bitdepth+GBT_slowcntr_bitdepth-1 downto 0); + signal RX_IS_DATA_sysclk, RX_IS_DATA_to_dclk : std_logic; + signal RX_DATA_sysclk, RX_DATA_to_dclk : std_logic_vector (GBT_data_word_bitdepth+GBT_slowcntr_bitdepth-1 downto 0); -- -- data ff by data clk - signal CLK_PH_counter_stop : STD_LOGIC_VECTOR (2 downto 0) := "000"; - signal CLK_PH_counter_dc, CLK_PH_counter_dcp, CLK_PH_counter_dcm : STD_LOGIC_VECTOR(2 downto 0); + signal CLK_PH_counter_stop : std_logic_vector (2 downto 0) := "000"; + signal CLK_PH_counter_dc, CLK_PH_counter_dcp, CLK_PH_counter_dcm : std_logic_vector(2 downto 0) := "000"; - - signal is_phase_changed : STD_LOGIC; - signal reset_ph_chng, rx_clk_tg, c_locked : STD_LOGIC; + signal is_phase_changed : std_logic; + signal rxclk_sync_shift : std_logic; + signal reset_ph_chng, rx_clk_tg, c_locked : std_logic := '0'; + signal rx_error_reset : std_logic; + signal rx_error_reset_sclk, rx_error_reset_sclk_ff : boolean; --- attribute keep : string; --- attribute keep of CLK_PH_counter_ff_sc : signal is "true"; --- attribute keep of CLK_PH_counter_stop_ff_sc : signal is "true"; --- attribute keep of RX_CLK_from_ff01 : signal is "true"; --- attribute keep of RX_CLK_from_ff02 : signal is "true"; --- attribute keep of RX_DATA_RXCLK_ffrxc : signal is "true"; --- attribute keep of RX_DATA_DATACLK_ffsc : signal is "true"; + attribute keep : string; + attribute keep of RX_IS_DATA_sysclk : signal is "true"; + attribute keep of RX_DATA_sysclk : signal is "true"; + attribute keep of RX_CLK_from00 : signal is "true"; + attribute keep of RX_CLK_from01 : signal is "true"; begin - - --- *************************************************** - rx_ph320 <= CLK_PH_counter_stop; ph_error320 <= is_phase_changed; - -- Data ff RX clk ************************************ - PROCESS (RX_CLK_I) - BEGIN - IF(RX_CLK_I'EVENT and RX_CLK_I = '1') THEN - rx_clk_tg <=not rx_clk_tg; - - END IF; - END PROCESS; + process (RX_CLK_I) + begin + if(RX_CLK_I'event and RX_CLK_I = '1') then + rx_clk_tg <= not rx_clk_tg; + + end if; + end process; -- *************************************************** - - + + -- Data ff data clk ********************************** - PROCESS (FSM_Clocks_I.Data_Clk) - BEGIN - IF(FSM_Clocks_I.Data_Clk'EVENT and FSM_Clocks_I.Data_Clk = '1') THEN - CLK_PH_ERROR_O <= is_phase_changed; - RX_DATA_DATACLK_O <=RX_DATA_DATACLK; - RX_IS_DATA_DATACLK_O <= RX_IS_DATA_DATACLK; - CLK_PH_CNT_O<= CLK_PH_counter_stop; - END IF; - END PROCESS; --- *************************************************** - --- Async Registers, count ph ************************* - PROCESS (FSM_Clocks_I.System_Clk) - BEGIN -IF(FSM_Clocks_I.System_Clk'EVENT and FSM_Clocks_I.System_Clk = '1') THEN - RX_CLK_from00 <= rx_clk_tg; RX_CLK_from01 <= RX_CLK_from00; RX_CLK_from02 <= RX_CLK_from01; - - if ((Control_register_I.strt_rdmode_lock or Control_register_I.reset_rxph_error or FSM_Clocks_I.Reset)= '1') then is_phase_changed<='0'; c_locked<='0'; - else - if (RX_CLK_from01 /= RX_CLK_from02) then - CLK_PH_counter_stop<= FSM_Clocks_I.System_Counter(2 downto 0); - if (c_locked='0') then CLK_PH_counter_dc <=FSM_Clocks_I.System_Counter(2 downto 0); c_locked<='1'; - else - if (CLK_PH_counter_stop/=CLK_PH_counter_dc) and (CLK_PH_counter_stop/=CLK_PH_counter_dcm) and (CLK_PH_counter_stop/=CLK_PH_counter_dcp) then is_phase_changed<='1'; end if; - end if; + process (FSM_Clocks_I.Data_Clk) + begin + if(FSM_Clocks_I.Data_Clk'event and FSM_Clocks_I.Data_Clk = '1') then + CLK_PH_ERROR_O <= is_phase_changed; + RX_DATA_DATACLK_O <= RX_DATA_to_dclk; + RX_IS_DATA_DATACLK_O <= RX_IS_DATA_to_dclk; + CLK_PH_CNT_O <= CLK_PH_counter_stop; + + rx_error_reset <= Control_register_I.force_idle or Control_register_I.reset_rxph_error; end if; - - if (FSM_Clocks_I.System_Counter(2 downto 0)=CLK_PH_counter_dcp) then - RX_IS_DATA_DATACLK<= RX_IS_DATA_RXCLK_I; - RX_DATA_DATACLK<= RX_DATA_RXCLK_I; - end if; - - end if; -END IF; -END PROCESS; + end process; -- *************************************************** -CLK_PH_counter_dcp <= CLK_PH_counter_dc+"001"; -CLK_PH_counter_dcm <= CLK_PH_counter_dc-"001"; - +-- Async Registers, count ph ************************* + process (FSM_Clocks_I.System_Clk) + begin + if(FSM_Clocks_I.System_Clk'event and FSM_Clocks_I.System_Clk = '1') then + RX_CLK_from00 <= rx_clk_tg; RX_CLK_from01 <= RX_CLK_from00; RX_CLK_from02 <= RX_CLK_from01; + rx_error_reset_sclk <= rx_error_reset = '1'; + rx_error_reset_sclk_ff <= rx_error_reset_sclk; + rxclk_sync_shift <= Control_register_I.rxclk_sync_shift; + + if (FSM_Clocks_I.Reset_sclk = '1') or (not rx_error_reset_sclk and rx_error_reset_sclk_ff) then + + is_phase_changed <= '0'; + c_locked <= '0'; + CLK_PH_counter_stop <= (others => '0'); + CLK_PH_counter_dc <= (others => '0'); + + else + + if (RX_CLK_from01 /= RX_CLK_from02) then + CLK_PH_counter_stop <= FSM_Clocks_I.System_Counter(2 downto 0); + + if (c_locked = '0') then + CLK_PH_counter_dc <= FSM_Clocks_I.System_Counter(2 downto 0); + c_locked <= '1'; + else + + if rx_error_reset_sclk_ff then + is_phase_changed <= '0'; + elsif (CLK_PH_counter_stop /= CLK_PH_counter_dc) and (CLK_PH_counter_stop /= CLK_PH_counter_dcm) and (CLK_PH_counter_stop /= CLK_PH_counter_dcp) then + is_phase_changed <= '1'; + end if; + + end if; + + end if; + + if (FSM_Clocks_I.System_Counter(2 downto 0) = CLK_PH_counter_dcp) then + RX_IS_DATA_sysclk <= RX_IS_DATA_RXCLK_I; + RX_DATA_sysclk <= RX_DATA_RXCLK_I; + end if; + + if rxclk_sync_shift = '0' then + if FSM_Clocks_I.System_Counter = x"6" then RX_IS_DATA_to_dclk <= RX_IS_DATA_sysclk; RX_DATA_to_dclk <= RX_DATA_sysclk; end if; + else + if FSM_Clocks_I.System_Counter = x"2" then RX_IS_DATA_to_dclk <= RX_IS_DATA_sysclk; RX_DATA_to_dclk <= RX_DATA_sysclk; end if; + end if; + --- FSM *********************************************** + end if; + end if; + end process; -- *************************************************** - - + CLK_PH_counter_dcp <= CLK_PH_counter_dc+"001"; + CLK_PH_counter_dcm <= CLK_PH_counter_dc-"001"; end Behavioral; diff --git a/firmware/common/gbt-readout/hdl/RX_Data_Decoder.vhd b/firmware/common/gbt-readout/hdl/RX_Data_Decoder.vhd deleted file mode 100644 index b9b2f2e..0000000 --- a/firmware/common/gbt-readout/hdl/RX_Data_Decoder.vhd +++ /dev/null @@ -1,337 +0,0 @@ ----------------------------------------------------------------------------------- --- Company: INR RAS --- Engineer: Finogeev D. A. dmitry-finogeev@yandex.ru --- --- Create Date: 07/11/2017 --- Design Name: --- Module Name: RXDATA_CLKSync - Behavioral --- Project Name: --- Target Devices: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision --- Additional Comments: --- - ----------------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use ieee.numeric_std.all; -use ieee.std_logic_unsigned.all ; - -use work.fit_gbt_common_package.all; - - -entity RX_Data_Decoder is - Port ( - FSM_Clocks_I : in FSM_Clocks_type; - - FIT_GBT_status_I : in FIT_GBT_status_type; - Control_register_I : in CONTROL_REGISTER_type; - - -- RX data @ DataClk, ff in RX sync - RX_Data_I : in std_logic_vector(GBT_data_word_bitdepth-1 downto 0); - RX_IsData_I : in STD_LOGIC; -- unused in tests - - ORBC_ID_from_CRU_O : out std_logic_vector(Orbit_id_bitdepth + BC_id_bitdepth-1 downto 0); -- EVENT ID from CRU - ORBC_ID_from_CRU_corrected_O : out std_logic_vector(Orbit_id_bitdepth + BC_id_bitdepth-1 downto 0); -- EVENT ID to PM/TCM - Trigger_O : out std_logic_vector(Trigger_bitdepth-1 downto 0); - - BCIDsync_Mode_O : out Type_BCIDsync_Mode; - Readout_Mode_O : out Type_Readout_Mode; - CRU_Readout_Mode_O : out Type_Readout_Mode; - Start_run_O : out std_logic; - Stop_run_O : out std_logic - ); -end RX_Data_Decoder; - -architecture Behavioral of RX_Data_Decoder is - - attribute keep : string; - - signal STATE_SYNC, STATE_SYNC_NEXT : Type_BCIDsync_Mode; - signal STATE_RDMODE, STATE_RDMODE_NEXT : Type_Readout_Mode; - signal Start_run_ff, Start_run_ff_next : std_logic; - signal Stop_run_ff, Stop_run_ff_next : std_logic; - - signal TRGTYPE_received_ff, TRGTYPE_received_ff_next : std_logic_vector(Trigger_bitdepth-1 downto 0); - signal ORBC_ID_received_ff, ORBC_ID_received_ff_next : std_logic_vector(Orbit_id_bitdepth + BC_id_bitdepth-1 downto 0); - - -- transform received rx data to trigger and evid, in FIT_Readout used: ORBC_ID = OrID(32) & BCID(12) - signal ORBC_ID_received : std_logic_vector(Orbit_id_bitdepth + BC_id_bitdepth-1 downto 0); - signal TRGTYPE_received : std_logic_vector(Trigger_bitdepth-1 downto 0); - signal TRGTYPE_ORBCrsv_ff, TRGTYPE_ORBCrsv_ff_next : boolean; - - signal EV_ID_counter : std_logic_vector(Orbit_id_bitdepth + BC_id_bitdepth-1 downto 0); - signal EV_ID_counter_BC : std_logic_vector(BC_id_bitdepth-1 downto 0); - signal EV_ID_counter_ORBIT : std_logic_vector(Orbit_id_bitdepth-1 downto 0); - - signal ORBC_counter_init : std_logic; - - - signal ORBC_ID_from_CRU_ff, ORBC_ID_from_CRU_ff_next : std_logic_vector(Orbit_id_bitdepth + BC_id_bitdepth-1 downto 0); -- EVENT ID from CRU - signal ORBC_ID_from_CRU_corrected_ff, ORBC_ID_from_CRU_corrected_ff_next : std_logic_vector(Orbit_id_bitdepth + BC_id_bitdepth-1 downto 0); -- EVENT ID to PM/TCM - signal Trigger_ff, Trigger_ff_next : std_logic_vector(Trigger_bitdepth-1 downto 0); - signal Trigger_valid_bit : std_logic; - signal CRU_readout_mode, CRU_readout_mode_next : Type_Readout_Mode; - - - - signal EV_ID_counter_corrected : std_logic_vector(Orbit_id_bitdepth + BC_id_bitdepth-1 downto 0); - signal EV_ID_delay : std_logic_vector(BC_id_bitdepth-1 downto 0); - signal EV_ID_counter_BC_corrected : std_logic_vector(BC_id_bitdepth-1 downto 0); - signal EV_ID_counter_ORBIT_corrected : std_logic_vector(Orbit_id_bitdepth-1 downto 0); - - - attribute keep of STATE_SYNC : signal is "true"; - attribute keep of TRGTYPE_received_ff : signal is "true"; - attribute keep of ORBC_ID_received_ff : signal is "true"; - attribute keep of EV_ID_counter : signal is "true"; - - -begin - --- *************************************************** - -- equetion define by CRU, must be also defined in RX data generator - -- Orbit_ID(32) & x"0" & BC_IC(12) & TRGTYPE(32) - - TRGTYPE_received <= RX_Data_I(Trigger_bitdepth-1 downto 0) WHEN (Trigger_valid_bit = '1') ELSE - (others => '0'); --- ORBC_ID_received <= RX_Data_I(Trigger_bitdepth + Orbit_id_bitdepth + BC_id_bitdepth-1 downto Trigger_bitdepth) WHEN (RX_IsData_I = '1') ELSE --- (others => '0'); --- Trigger_valid_bit <= '1' when RX_Data_I(Trigger_bitdepth + Orbit_id_bitdepth + BC_id_bitdepth+1 downto Trigger_bitdepth + Orbit_id_bitdepth + BC_id_bitdepth) = "1" and (RX_IsData_I = '1') else '0'; - --- new versions of LTU GBT word, corrected on 18/11/2020 - ORBC_ID_received <= RX_Data_I(79 downto 48) & RX_Data_I(43 downto 32) - WHEN (RX_IsData_I = '1') ELSE (others => '0'); - - Trigger_valid_bit <= '1' WHEN (x"FFFF9FFF" and RX_Data_I(31 downto 0)) > 0 ELSE '0'; - - - - -- if recieved rx data contain Event counter - TRGTYPE_ORBCrsv_ff_next <= (TRGTYPE_received and x"0000000f") /= TRG_const_void; - ORBC_ID_received_ff_next <= ORBC_ID_received; -- delayed signal for comparison with counter - - BCIDsync_Mode_O <= STATE_SYNC; - Readout_Mode_O <= STATE_RDMODE; - CRU_Readout_Mode_O <= CRU_readout_mode; - Start_run_O <= Start_run_ff; - Stop_run_O <= Stop_run_ff; - - ORBC_ID_from_CRU_O <= ORBC_ID_from_CRU_ff; - ORBC_ID_from_CRU_corrected_O <= ORBC_ID_from_CRU_corrected_ff; - Trigger_O <= Trigger_ff; - --- *************************************************** - - - - --- BC Counter ================================================== - BC_counter_rxdecoder_comp : entity work.BC_counter - port map ( - RESET_I => FSM_Clocks_I.Reset40, - DATA_CLK_I => FSM_Clocks_I.Data_Clk, - - IS_INIT_I => ORBC_counter_init, - ORBC_ID_INIT_I => ORBC_ID_received, - - ORBC_ID_COUNT_O => EV_ID_counter, - IS_Orbit_trg_O => open - ); --- ============================================================= - --- type Type_Readout_Mode is (mode_CNT, mode_TRG, mode_IDLE); --- type Type_BCIDsync_Mode is (mode_STR, mode_SYNC, mode_LOST); - --- Data ff data clk ********************************** - process (FSM_Clocks_I.Data_Clk) - begin - - IF(rising_edge(FSM_Clocks_I.Data_Clk) )THEN - IF (FSM_Clocks_I.Reset40 = '1') THEN - STATE_SYNC <= mode_STR; - STATE_RDMODE <= mode_IDLE; - CRU_readout_mode <= mode_IDLE; - - Start_run_ff <= '0'; - Stop_run_ff <= '0'; - - TRGTYPE_ORBCrsv_ff <= false; - - TRGTYPE_received_ff <= (others => '0'); - ORBC_ID_received_ff <= (others => '0'); - - - - ELSE - STATE_SYNC <= STATE_SYNC_NEXT; - STATE_RDMODE <= STATE_RDMODE_NEXT; - CRU_readout_mode <= CRU_readout_mode_next; - - Start_run_ff <= Start_run_ff_next; - Stop_run_ff <= Stop_run_ff_next; - - TRGTYPE_ORBCrsv_ff <= TRGTYPE_ORBCrsv_ff_next; - - TRGTYPE_received_ff <= TRGTYPE_received_ff_next; - ORBC_ID_received_ff <= ORBC_ID_received_ff_next; - - ORBC_ID_from_CRU_ff <= ORBC_ID_from_CRU_ff_next; - ORBC_ID_from_CRU_corrected_ff <= ORBC_ID_from_CRU_corrected_ff_next; - Trigger_ff <= Trigger_ff_next; - - END IF; - END IF; - - end process; --- *************************************************** - - - --- FSM *********************************************** -STATE_RDMODE_NEXT <= mode_IDLE WHEN (FSM_Clocks_I.Reset = '1') ELSE - mode_IDLE WHEN (Control_register_I.strt_rdmode_lock = '1') ELSE - mode_IDLE WHEN (STATE_SYNC = mode_LOST) ELSE - - mode_TRG WHEN (STATE_RDMODE = mode_IDLE) and ((TRGTYPE_received_ff and TRG_const_SOT) /= TRG_const_void) ELSE - mode_TRG WHEN (STATE_RDMODE = mode_IDLE) and ((Trigger_ff and TRG_const_SOT) /= TRG_const_void) ELSE - - mode_CNT WHEN (STATE_RDMODE = mode_IDLE) and ((TRGTYPE_received_ff and TRG_const_SOC) /= TRG_const_void) ELSE - mode_CNT WHEN (STATE_RDMODE = mode_IDLE) and ((Trigger_ff and TRG_const_SOC) /= TRG_const_void) ELSE - - mode_IDLE WHEN (STATE_RDMODE = mode_TRG) and ((Trigger_ff and TRG_const_EOT) /= TRG_const_void) ELSE - mode_IDLE WHEN (STATE_RDMODE = mode_CNT) and ((Trigger_ff and TRG_const_EOC) /= TRG_const_void) ELSE - - -- auto run restore - mode_CNT WHEN (STATE_RDMODE = mode_IDLE) and ((Trigger_ff and TRG_const_RS) /= TRG_const_void) and ((Trigger_ff and TRG_const_RT) /= TRG_const_void) ELSE - mode_TRG WHEN (STATE_RDMODE = mode_IDLE) and ((Trigger_ff and TRG_const_RS) /= TRG_const_void) and ((Trigger_ff and TRG_const_RT) = TRG_const_void) ELSE - - STATE_RDMODE; - -Start_run_ff_next <= '0' WHEN (FSM_Clocks_I.Reset = '1') ELSE - '1' WHEN ((Trigger_ff and TRG_const_SOC) /= TRG_const_void) ELSE - '1' WHEN ((Trigger_ff and TRG_const_SOT) /= TRG_const_void) ELSE - '0'; - -Stop_run_ff_next <= '0' WHEN (FSM_Clocks_I.Reset = '1') ELSE - '1' WHEN ((Trigger_ff and TRG_const_EOC) /= TRG_const_void) ELSE - '1' WHEN ((Trigger_ff and TRG_const_EOT) /= TRG_const_void) ELSE - '0'; - --- SYNC FSM -STATE_SYNC_NEXT <= mode_STR WHEN (FSM_Clocks_I.Reset = '1') ELSE --- mode_STR WHEN (STATE_SYNC = mode_LOST) ELSE - mode_STR WHEN (Control_register_I.strt_rdmode_lock = '1') ELSE - mode_STR WHEN (Control_register_I.reset_orbc_synd = '1') ELSE - mode_SYNC WHEN TRGTYPE_ORBCrsv_ff_next and (STATE_SYNC = mode_STR) ELSE - mode_LOST WHEN (EV_ID_counter /= ORBC_ID_received_ff) and (STATE_SYNC = mode_SYNC) and TRGTYPE_ORBCrsv_ff ELSE - STATE_SYNC; - -ORBC_counter_init <= '0' WHEN (FSM_Clocks_I.Reset = '1') ELSE - '1' WHEN TRGTYPE_ORBCrsv_ff_next and (STATE_SYNC = mode_STR) ELSE - '0'; - -TRGTYPE_received_ff_next <= (others => '0') WHEN (FSM_Clocks_I.Reset = '1') ELSE - TRGTYPE_received WHEN (STATE_SYNC = mode_SYNC) ELSE - (others => '0'); - -ORBC_ID_from_CRU_ff_next <= (others => '0') WHEN (FSM_Clocks_I.Reset = '1') ELSE - EV_ID_counter WHEN STATE_SYNC = mode_SYNC ELSE - (others => '0'); - -ORBC_ID_from_CRU_corrected_ff_next <= (others => '0') WHEN (FSM_Clocks_I.Reset = '1') ELSE - EV_ID_counter_corrected WHEN STATE_SYNC = mode_SYNC ELSE - (others => '0'); - - - --- Event ID delayed (corrected) -EV_ID_delay <= Control_register_I.n_BCID_delay; - -EV_ID_counter_BC <= EV_ID_counter(BC_id_bitdepth-1 downto 0); -EV_ID_counter_ORBIT <= EV_ID_counter(Orbit_id_bitdepth + BC_id_bitdepth-1 downto BC_id_bitdepth); - -EV_ID_counter_BC_corrected <= (EV_ID_counter_BC + EV_ID_delay) WHEN (EV_ID_counter_BC + EV_ID_delay) <= LHC_BCID_max ELSE - EV_ID_counter_BC + EV_ID_delay - LHC_BCID_max - 1; - -EV_ID_counter_ORBIT_corrected <= EV_ID_counter_ORBIT WHEN EV_ID_counter_BC + EV_ID_delay <= LHC_BCID_max ELSE - EV_ID_counter_ORBIT + 1; - -EV_ID_counter_corrected <= EV_ID_counter_ORBIT_corrected & EV_ID_counter_BC_corrected; --- *************************************************** - - -Trigger_ff_next <= TRGTYPE_received_ff; - - -CRU_readout_mode_next <= mode_IDLE WHEN (FSM_Clocks_I.Reset = '1') ELSE - CRU_readout_mode WHEN (Trigger_valid_bit = '0') ELSE - mode_IDLE WHEN (TRGTYPE_received and TRG_const_RS) = TRG_const_void ELSE - mode_TRG WHEN (TRGTYPE_received and TRG_const_RT) = TRG_const_void ELSE - mode_CNT WHEN (TRGTYPE_received and TRG_const_RT) /= TRG_const_void ELSE - CRU_readout_mode; - -end Behavioral; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/firmware/common/gbt-readout/hdl/Reset_Generator.vhd b/firmware/common/gbt-readout/hdl/Reset_Generator.vhd index 7e5129e..c1bf95c 100644 --- a/firmware/common/gbt-readout/hdl/Reset_Generator.vhd +++ b/firmware/common/gbt-readout/hdl/Reset_Generator.vhd @@ -2,95 +2,132 @@ -- Company: INR RAS -- Engineer: Finogeev D. A. dmitry-finogeev@yandex.ru -- --- Create Date: 09/11/2017 --- Design Name: --- Module Name: RXDATA_CLKSync - Behavioral --- Project Name: --- Target Devices: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision --- Additional Comments: +-- Create Date: 2017 +-- Description: generate reset signals and sysclk counter -- +-- Revision: 06/2021 ---------------------------------------------------------------------------------- library IEEE; -use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_1164.all; use work.fit_gbt_common_package.all; -use ieee.std_logic_unsigned.all ; +use ieee.std_logic_unsigned.all; entity Reset_Generator is - Port ( - RESET_I : in STD_LOGIC; - SysClk_I : in STD_LOGIC; - DataClk_I : in STD_LOGIC; - Sys_Cntr_ready_I: in STD_LOGIC; - - Reset_DClk_O : out std_logic; - General_reset_O : out std_logic; - Reset_DClk40_O : out std_logic; - General_reset40_O : out std_logic - - ); + port ( + RESET40_I : in std_logic; + SysClk_I : in std_logic; + DataClk_I : in std_logic; + + Control_register_I : in readout_control_t; + gbt_not_ready_I : in std_logic; + + SysClk_count_O : out std_logic_vector(3 downto 0); + + Reset_DClk_O : out std_logic; + Reset_SClk_O : out std_logic; + ResetGBT_O : out std_logic + ); end Reset_Generator; architecture Behavioral of Reset_Generator is - signal GenRes_DataClk_ff, GenRes_DataClk_ff1, GenRes_DataClk_ff_next :std_logic; - signal General_reset_ff, General_reset_ff_next : std_logic; - signal Cntr_reset_ff, Cntr_reset_ff1, Cntr_reset_ff_next : std_logic; - attribute keep : string; - attribute keep of GenRes_DataClk_ff1 : signal is "true"; - + signal reset_in, reset_sclk, reset_fsm, reset_fsm_cmd, reset_gbt : std_logic; + signal DataClk_q_dataclk : std_logic := '0'; + signal DataClk_qff00_sysclk : std_logic; + signal DataClk_front_sysclk : std_logic; + + signal count_ready, count_ready_clk40 : std_logic; + signal sysclk_count_ff : std_logic_vector(2 downto 0); + signal rd_bypass, rd_bypass_ff : boolean; + signal reset_counter : std_logic_vector(7 downto 0) := x"FF"; + signal resetin_cnt_db : std_logic_vector(31 downto 0); -- counter after reset_i for ila triggering + signal reset_by_bypass : std_logic; + + + + -- attribute mark_debug : string; + -- attribute mark_debug of reset_in : signal is "true"; + -- attribute mark_debug of reset_gbt : signal is "true"; + -- attribute mark_debug of reset_fsm : signal is "true"; + -- attribute mark_debug of resetin_cnt_db : signal is "true"; + +-- attribute mark_debug of reset_fsm_cmd : signal is "true"; +-- attribute mark_debug of reset_sclk : signal is "true"; +-- attribute mark_debug of reset_counter : signal is "true"; +-- attribute mark_debug of sysclk_count_ff : signal is "true"; +-- attribute mark_debug of count_ready : signal is "true"; + -- attribute mark_debug of : signal is "true"; + begin -Reset_DClk40_O<= Cntr_reset_ff1; General_reset40_O<= GenRes_DataClk_ff1; - -PROCESS (SysClk_I) -BEGIN - IF rising_edge(SysClk_I)THEN - - Reset_DClk_O <= Cntr_reset_ff1; - General_reset_O <= GenRes_DataClk_ff1; - - END IF; -END PROCESS; - --- Sys clk *********************************** - PROCESS (DataClk_I) - BEGIN - IF rising_edge(DataClk_I)THEN - IF(RESET_I = '1') THEN - GenRes_DataClk_ff <= '1'; - General_reset_ff <= '1'; - Cntr_reset_ff <= '1'; - ELSE - GenRes_DataClk_ff <= GenRes_DataClk_ff_next; - General_reset_ff <= General_reset_ff_next; - Cntr_reset_ff <= Cntr_reset_ff_next; - - Cntr_reset_ff1 <= Cntr_reset_ff; - GenRes_DataClk_ff1 <= GenRes_DataClk_ff; - END IF; - END IF; - END PROCESS; --- ******************************************** + ResetGBT_O <= reset_gbt; + Reset_DClk_O <= reset_fsm; + SysClk_count_O <= '0' & sysclk_count_ff; + +-- Data clk ********************************* + process(DataClk_I) + begin + if rising_edge(DataClk_I)then + reset_in <= RESET40_I; + + -- reset (15 cycles) after rd_bypass switched off + rd_bypass <= Control_register_I.readout_bypass = '1'; + rd_bypass_ff <= rd_bypass; + if (rd_bypass_ff and not rd_bypass) then reset_by_bypass <= '1'; else reset_by_bypass <= '0'; end if; + + count_ready_clk40 <= count_ready; + DataClk_q_dataclk <= not DataClk_q_dataclk; + reset_gbt <= reset_in or Control_register_I.reset_gbt; + reset_fsm_cmd <= reset_gbt or Control_register_I.reset_readout or gbt_not_ready_I or not count_ready_clk40 or reset_by_bypass; + + if reset_fsm_cmd = '1' then + reset_counter <= (others => '0'); + reset_fsm <= '1'; + elsif reset_counter < x"ff" then + reset_counter <= reset_counter + 1; + reset_fsm <= '1'; + else + reset_counter <= x"ff"; + reset_fsm <= '0'; + end if; + + -- counter after reset_i for ila triggering + if reset_in = '1' then resetin_cnt_db <= (others => '0'); else resetin_cnt_db <= resetin_cnt_db + 1; end if; + + + end if; + end process; +-- *************************************************** + + +-- Clock clk ********************************* + process(SysClk_I) + begin + if rising_edge(SysClk_I)then + + reset_sclk <= reset_in; + Reset_SClk_O <= reset_fsm; + + if(reset_sclk = '1')then + count_ready <= '0'; + + else + DataClk_qff00_sysclk <= DataClk_q_dataclk; + + if (DataClk_front_sysclk = '1') then sysclk_count_ff <= "001"; count_ready <= '1'; + else sysclk_count_ff <= sysclk_count_ff+1; + end if; + + end if; + + end if; + end process; +-- *************************************************** -- FSM *********************************************** -GenRes_DataClk_ff_next <= '1' WHEN (RESET_I = '1') ELSE - General_reset_ff; - -Cntr_reset_ff_next <= '1' WHEN (RESET_I = '1') ELSE - '0'; - -General_reset_ff_next <= '1' WHEN (RESET_I = '1') ELSE - '1' WHEN (General_reset_ff = '1') and (Sys_Cntr_ready_I = '0') ELSE - '0'; + DataClk_front_sysclk <= DataClk_q_dataclk xor DataClk_qff00_sysclk; end Behavioral; diff --git a/firmware/common/gbt-readout/hdl/TX_Data_Gen.vhd b/firmware/common/gbt-readout/hdl/TX_Data_Gen.vhd index 9cd8cdf..1e07387 100644 --- a/firmware/common/gbt-readout/hdl/TX_Data_Gen.vhd +++ b/firmware/common/gbt-readout/hdl/TX_Data_Gen.vhd @@ -1,170 +1,131 @@ ---------------------------------------------------------------------------------- --- Company: --- Engineer: +-- Company: INR RAS +-- Engineer: Finogeev D. A. dmitry-finogeev@yandex.ru -- --- Create Date: 14:40:15 01/30/2017 --- Design Name: --- Module Name: TX_Data_Gen - Behavioral --- Project Name: --- Target Devices: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: +-- Create Date: 2017 +-- Description: generate test pattern for GBT tests -- +-- Revision: 07/2021 ---------------------------------------------------------------------------------- library IEEE; -use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_1164.all; use ieee.numeric_std.all; -use ieee.std_logic_unsigned.all ; +use ieee.std_logic_unsigned.all; use work.fit_gbt_common_package.all; use work.fit_gbt_board_package.all; --- Uncomment the following library declaration if using --- arithmetic functions with Signed or Unsigned values ---use IEEE.NUMERIC_STD.ALL; - --- Uncomment the following library declaration if instantiating --- any Xilinx primitives in this code. ---library UNISIM; ---use UNISIM.VComponents.all; - entity TX_Data_Gen is - Port ( - FSM_Clocks_I : in FSM_Clocks_type; - - Control_register_I : in CONTROL_REGISTER_type; - - FIT_GBT_status_I : in FIT_GBT_status_type; - TX_IsData_I : in STD_LOGIC; - TX_Data_I : in std_logic_vector(GBT_data_word_bitdepth-1 downto 0); - - RAWFIFO_data_word_I : in std_logic_vector(fifo_data_bitdepth-1 downto 0); - RAWFIFO_Is_Empty_I : in STD_LOGIC; - RAWFIFO_RE_O : out STD_LOGIC; - - TX_IsData_O : out STD_LOGIC; - TX_Data_O : out std_logic_vector(GBT_data_word_bitdepth-1 downto 0) - ); + port ( + FSM_Clocks_I : in rdclocks_t; + + Control_register_I : in readout_control_t; + Status_register_I : in readout_status_t; + + TX_IsData_I : in std_logic; + TX_Data_I : in std_logic_vector(GBT_data_word_bitdepth-1 downto 0); + + TX_IsData_O : out std_logic; + TX_Data_O : out std_logic_vector(GBT_data_word_bitdepth-1 downto 0); + + gbt_data_counter_o : out std_logic_vector(31 downto 0) + ); end TX_Data_Gen; architecture Behavioral of TX_Data_Gen is -signal TX_generation : std_logic_vector(GBT_data_word_bitdepth-1 downto 0); -signal Data_bypass : std_logic_vector(GBT_data_word_bitdepth-1 downto 0); -signal TX_data_gen : std_logic_vector(GBT_data_word_bitdepth-1 downto 0); -signal TX_IsData_generation : STD_LOGIC; -signal IsData_bypass : STD_LOGIC; + signal TX_generation : std_logic_vector(GBT_data_word_bitdepth-1 downto 0); + signal Data_bypass : std_logic_vector(GBT_data_word_bitdepth-1 downto 0); + signal TX_data_gen : std_logic_vector(GBT_data_word_bitdepth-1 downto 0); + signal TX_IsData_generation : std_logic; -signal data320to40fifo_empty : std_logic; -signal data320to40fifo_WREN : std_logic; -signal data320to40fifo_RDEN : std_logic; + signal gen_counter_ff, gen_counter_ff_next : std_logic_vector(15 downto 0); + signal cont_counter_ff, cont_counter_ff_next : std_logic_vector(GBT_data_word_bitdepth-1 downto 0); + + signal is_rdmode, is_rdmode_ff : boolean; + signal tx_isdata : std_logic; + signal gbt_data_counter : std_logic_vector(31 downto 0); -signal gen_counter_ff, gen_counter_ff_next: std_logic_vector(GEN_count_bitdepth-1 downto 0); -signal cont_counter_ff, cont_counter_ff_next: std_logic_vector(GBT_data_word_bitdepth-1 downto 0); -signal count_val_void, count_val_data: std_logic_vector(GEN_count_bitdepth-1 downto 0); + constant count_val_void : std_logic_vector(15 downto 0) := x"0f00"; + constant count_val_data : std_logic_vector(15 downto 0) := x"0f0a"; --- signal rx_phase_latch : std_logic_vector(rx_phase_bitdepth-1 downto 0); -attribute keep : string; -attribute keep of gen_counter_ff : signal is "true"; -attribute keep of cont_counter_ff : signal is "true"; begin -TX_Data_O <= TX_generation WHEN (Control_register_I.Data_Gen.usage_generator = use_TX_generator) ELSE - Data_bypass WHEN (Control_register_I.readout_bypass = '1') ELSE - TX_Data_I; - -TX_IsData_O <= TX_IsData_generation WHEN (Control_register_I.Data_Gen.usage_generator = use_TX_generator) ELSE - IsData_bypass WHEN (Control_register_I.readout_bypass = '1') ELSE - TX_IsData_I; - --- TX_data_gen <= x"01231111" & Control_register_I.PAR & x"1111" & Control_register_I.FEE_ID; -TX_data_gen <= cont_counter_ff; -count_val_void <= x"0f00"; -count_val_data <= x"0f0a"; - - - --- Slc_data_fifo ============================================= -data320to40_fifo_comp : entity work.slct_data_fifo -port map( - wr_clk => FSM_Clocks_I.System_Clk, - rd_clk => FSM_Clocks_I.Data_Clk, - wr_data_count => open, - rst => FSM_Clocks_I.Reset, - WR_EN => data320to40fifo_WREN, - RD_EN => data320to40fifo_RDEN, - DIN => RAWFIFO_data_word_I, - DOUT => Data_bypass, - FULL => open, - EMPTY => data320to40fifo_empty - ); - -data320to40fifo_WREN <= not RAWFIFO_Is_Empty_I; -data320to40fifo_RDEN <= not data320to40fifo_empty; -RAWFIFO_RE_O <= not RAWFIFO_Is_Empty_I; -IsData_bypass <= not data320to40fifo_empty; --- =========================================================== + TX_Data_O <= TX_generation when (Control_register_I.Data_Gen.usage_generator = gen_tx_out) else + TX_Data_I; + TX_IsData_O <= tx_isdata; + tx_isdata <= TX_IsData_generation when (Control_register_I.Data_Gen.usage_generator = gen_tx_out) else + TX_IsData_I; + + gbt_data_counter_o <= gbt_data_counter; + TX_data_gen <= cont_counter_ff; -- Data ff data clk ********************************** - process (FSM_Clocks_I.Data_Clk) - begin - - IF(rising_edge(FSM_Clocks_I.Data_Clk) )THEN - IF (FSM_Clocks_I.Reset40 = '1') THEN - gen_counter_ff <= (others => '0'); - cont_counter_ff <= (others => '0'); - ELSE - gen_counter_ff <= gen_counter_ff_next; - cont_counter_ff <= cont_counter_ff_next; - END IF; - END IF; + process (FSM_Clocks_I.Data_Clk) + begin + + if(rising_edge(FSM_Clocks_I.Data_Clk))then + if (FSM_Clocks_I.Reset_dclk = '1') then + + gen_counter_ff <= (others => '0'); + cont_counter_ff <= (others => '0'); + gbt_data_counter <= (others => '0'); + + else + + -- counting gbt words, reset by start of run and reset_data_counters + is_rdmode <= Status_register_I.Readout_Mode /= mode_IDLE; + is_rdmode_ff <= is_rdmode; + if is_rdmode and not is_rdmode_ff then gbt_data_counter <= (others => '0'); + elsif Control_register_I.reset_data_counters = '1' then gbt_data_counter <= (others => '0'); + elsif tx_isdata = '1' then gbt_data_counter <= gbt_data_counter + 1; end if; - end process; + gen_counter_ff <= gen_counter_ff_next; + cont_counter_ff <= cont_counter_ff_next; + + end if; + end if; + + end process; -- *************************************************** -- *************************************************** -gen_counter_ff_next <= (others => '0') WHEN (FSM_Clocks_I.Reset = '1') ELSE - (others => '0') WHEN (gen_counter_ff = count_val_data+1) ELSE - gen_counter_ff + 1; - - - -cont_counter_ff_next <= (others => '0') WHEN (FSM_Clocks_I.Reset = '1') ELSE - (others => '0') WHEN (Control_register_I.Data_Gen.usage_generator /= use_TX_generator) ELSE - cont_counter_ff WHEN (gen_counter_ff < count_val_void) ELSE - cont_counter_ff WHEN (gen_counter_ff = count_val_void) ELSE - cont_counter_ff WHEN (gen_counter_ff = count_val_data+1) ELSE - cont_counter_ff + 1; - - - -TX_generation <= x"00000000000000000000" WHEN (FSM_Clocks_I.Reset = '1') ELSE - x"00000000000000000000" WHEN (gen_counter_ff < count_val_void) ELSE - data_word_cnst_SOP WHEN (gen_counter_ff = count_val_void) ELSE - data_word_cnst_EOP WHEN (gen_counter_ff = count_val_data+1) ELSE - TX_data_gen; - --x"123456789abcdef01234"; - -TX_IsData_generation <= '0' WHEN (FSM_Clocks_I.Reset = '1') ELSE - '0' WHEN (gen_counter_ff < count_val_void) ELSE - '0' WHEN (gen_counter_ff = count_val_void) ELSE - '0' WHEN (gen_counter_ff = count_val_data+1) ELSE - '1'; + gen_counter_ff_next <= (others => '0') when (FSM_Clocks_I.Reset_dclk = '1') else + (others => '0') when (gen_counter_ff = count_val_data+1) else + gen_counter_ff + 1; + + + + cont_counter_ff_next <= (others => '0') when (FSM_Clocks_I.Reset_dclk = '1') else + (others => '0') when (Control_register_I.Data_Gen.usage_generator /= gen_tx_out) else + cont_counter_ff when (gen_counter_ff < count_val_void) else + cont_counter_ff when (gen_counter_ff = count_val_void) else + cont_counter_ff when (gen_counter_ff = count_val_data+1) else + cont_counter_ff + 1; + + + + TX_generation <= x"00000000000000000000" when (FSM_Clocks_I.Reset_dclk = '1') else + x"00000000000000000000" when (gen_counter_ff < count_val_void) else + x"10000000000000000000" when (gen_counter_ff = count_val_void) else + x"20000000000000000000" when (gen_counter_ff = count_val_data+1) else + TX_data_gen; + --x"123456789abcdef01234"; + + TX_IsData_generation <= '0' when (FSM_Clocks_I.Reset_dclk = '1') else + '0' when (gen_counter_ff < count_val_void) else + '0' when (gen_counter_ff = count_val_void) else + '0' when (gen_counter_ff = count_val_data+1) else + '1'; -- *************************************************** diff --git a/firmware/common/gbt-readout/hdl/bc_indicator.vhd b/firmware/common/gbt-readout/hdl/bc_indicator.vhd new file mode 100644 index 0000000..202acd4 --- /dev/null +++ b/firmware/common/gbt-readout/hdl/bc_indicator.vhd @@ -0,0 +1,132 @@ +---------------------------------------------------------------------------------- +-- Company: INR RAS +-- Engineer: Finogeev D. A. dmitry-finogeev@yandex.ru +-- +-- Create Date: 2017 +-- Description: generate test pattern for GBT tests +-- +-- Revision: 07/2021 +---------------------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use ieee.numeric_std.all; +use ieee.std_logic_unsigned.all; + +use work.fit_gbt_common_package.all; +use work.fit_gbt_board_package.all; + +entity bc_indicator is + + generic ( + USE_SYSCLK : boolean := false + ); + + port ( + FSM_Clocks_I : in rdclocks_t; + Control_register_I : in readout_control_t; + + bcid_i : in std_logic_vector(BC_id_bitdepth-1 downto 0); + bcen_i : in std_logic; + + indicator_o : out bc_indicator_t + ); +end bc_indicator; + +architecture Behavioral of bc_indicator is + + signal clock, reset, bcid_en : std_logic; + signal bcid_in, bc_value, bc_out : std_logic_vector(BC_id_bitdepth-1 downto 0); + signal bc_count, bc_rate : std_logic_vector(3 downto 0); + signal count_tot, count_sel : std_logic_vector(5 downto 0); + +-- attribute mark_debug : string; +-- attribute mark_debug of reset : signal is "true"; +-- attribute mark_debug of bcid_en : signal is "true"; +-- attribute mark_debug of bcid_in : signal is "true"; +-- attribute mark_debug of bc_value : signal is "true"; +-- attribute mark_debug of bc_count : signal is "true"; +-- attribute mark_debug of count_tot : signal is "true"; +-- attribute mark_debug of count_sel : signal is "true"; +-- attribute mark_debug of bc_out : signal is "true"; +-- attribute mark_debug of bc_rate : signal is "true"; + + +begin + + datackl_switch1 : if USE_SYSCLK generate + clock <= FSM_Clocks_I.System_Clk; + end generate datackl_switch1; + + datackl_switch0 : if not USE_SYSCLK generate + clock <= FSM_Clocks_I.Data_Clk; + end generate datackl_switch0; + + + process (FSM_Clocks_I.Data_Clk) + begin + if(rising_edge(FSM_Clocks_I.Data_Clk))then + indicator_o.bc <= bc_out; + indicator_o.count <= bc_rate; + end if; + end process; + + + process (clock) + begin + + if(rising_edge(clock))then + + reset <= Control_register_I.reset_data_counters or FSM_Clocks_I.Reset_dclk; + bcid_en <= bcen_i; + bcid_in <= bcid_i; + + if (reset = '1') then + bc_value <= (others => '0'); + bc_count <= (others => '0'); + count_tot <= (others => '0'); + count_sel <= (others => '0'); + bc_rate <= (others => '0'); + bc_out <= (others => '0'); + else + + + if bcid_en = '1' then + + count_tot <= count_tot + 1; + + if bc_value = bcid_in then + if bc_count < x"F" then bc_count <= bc_count + 1; end if; + count_sel <= count_sel + 1; + elsif bc_count = x"0" then + bc_value <= bcid_in; + bc_rate <= (others => '0'); + count_tot <= (others => '0'); + count_sel <= (others => '0'); + bc_out <= (others => '0'); + elsif bc_value /= bcid_in then + bc_count <= bc_count - 1; + end if; + + if count_tot = x"3f" then + bc_rate <= count_sel(5 downto 2); + bc_out <= bc_value; + count_tot <= (others => '0'); + count_sel <= (others => '0'); + end if; + + end if; + + + end if; + end if; + + end process; +-- *************************************************** + + + + + +end Behavioral; + diff --git a/firmware/common/gbt-readout/hdl/cru_ltu_emu.vhd b/firmware/common/gbt-readout/hdl/cru_ltu_emu.vhd new file mode 100644 index 0000000..f067654 --- /dev/null +++ b/firmware/common/gbt-readout/hdl/cru_ltu_emu.vhd @@ -0,0 +1,222 @@ +---------------------------------------------------------------------------------- +-- Company: INR RAS +-- Engineer: Finogeev D. A. dmitry-finogeev@yandex.ru +-- +-- Create Date: 2017 +-- Description: generate RX data from CRU/LTU for standalone tests +-- +-- Revision: 06/2021 +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use ieee.numeric_std.all; +use ieee.std_logic_unsigned.all; + +use work.fit_gbt_common_package.all; +use work.fit_gbt_board_package.all; + + +entity cru_ltu_emu is + port ( + FSM_Clocks_I : in rdclocks_t; + + Status_register_I : in readout_status_t; + Control_register_I : in readout_control_t; + + RX_IsData_I : in std_logic; + RX_Data_I : in std_logic_vector(GBT_data_word_bitdepth-1 downto 0); + + RX_IsData_O : out std_logic; + RX_Data_O : out std_logic_vector(GBT_data_word_bitdepth-1 downto 0) + ); +end cru_ltu_emu; + +architecture Behavioral of cru_ltu_emu is + + signal bunch_freq : natural range 0 to 65535; + signal bc_start : std_logic_vector(BC_id_bitdepth-1 downto 0); + signal hbr_rate, hbr_count : std_logic_vector(3 downto 0); + + -- Event ID + signal orbit_gen, orbit_gen_mod : std_logic_vector(Orbit_id_bitdepth-1 downto 0); + signal bc_gen : std_logic_vector(BC_id_bitdepth-1 downto 0); + + -- fsm signals + signal run_state, run_state_ff, run_command : rdcmd_t := idle; + signal bunch_counter : natural range 0 to 65535; + signal bunch_in_sync : boolean; + signal send_trgcnt, send_soc, send_eoc, send_sot, send_eot : boolean; + signal orbit_jump, orbit_jump_ff, orbit_jump_active : boolean; + + signal trggen_cnt, trggen_sox, trggen_hb, trggen_rdstate : std_logic_vector(Trigger_bitdepth-1 downto 0); + + signal rx_data_gen : std_logic_vector(GBT_data_word_bitdepth-1 downto 0); + signal rx_isdata_gen : std_logic; + + +begin + + RX_Data_O <= RX_Data_I when (Control_register_I.Trigger_Gen.usage_generator = gen_off) else rx_data_gen; + RX_IsData_O <= RX_IsData_I when (Control_register_I.Trigger_Gen.usage_generator = gen_off) else rx_isdata_gen; + + + run_command <= Control_register_I.Trigger_Gen.Readout_command; + bunch_freq <= to_integer(unsigned(Control_register_I.Trigger_Gen.bunch_freq)); + bc_start <= x"deb" when Control_register_I.Trigger_Gen.bc_start = 0 else + Control_register_I.Trigger_Gen.bc_start - 1; + hbr_rate <= Control_register_I.Trigger_Gen.hbr_rate; + + orbit_jump <= Control_register_I.Data_Gen.orbit_jump = '1'; + orbit_gen_mod <= orbit_gen + 1 when orbit_jump_active else orbit_gen; + +-- Data ff data clk ********************************** + process (FSM_Clocks_I.Data_Clk) + begin + if(rising_edge(FSM_Clocks_I.Data_Clk))then + + orbit_jump_ff <= orbit_jump; + + if (FSM_Clocks_I.Reset_dclk = '1') then + + orbit_gen <= (others => '0'); + bc_gen <= (others => '0'); + hbr_count <= (others => '0'); + run_state <= idle; + bunch_counter <= 0; + bunch_in_sync <= false; + + else + -- orbit jump option for rx_sync_lost debugging in simulation + if orbit_jump and not orbit_jump_ff then orbit_jump_active <= true; end if; + if orbit_jump_active and bc_gen = x"000" then orbit_jump_active <= false; end if; + + -- last cycle with EOR trigger is also with RS/RT + run_state_ff <= run_state; + + -- Event ID generator + if bc_gen < LHC_BCID_max then bc_gen <= bc_gen + 1; + else bc_gen <= (others => '0'); orbit_gen <= orbit_gen + 1; end if; + + + -- Continious trigger + -- reset by gensync + if Control_register_I.reset_gensync = '1' then bunch_counter <= 0; + -- start since bc_start and not in sync + elsif (not bunch_in_sync) and (bc_gen = bc_start) then bunch_counter <= 1; + -- bunch_in_sync rised next cycle after sync, reset if not + elsif (not bunch_in_sync) then bunch_counter <= 0; + -- generator is off, counter max + elsif (bunch_freq = 0) or (bunch_counter = 65535) then bunch_counter <= 0; + -- counter cycle + elsif bunch_counter = bunch_freq-1 then bunch_counter <= 0; + -- counter iteration + else bunch_counter <= bunch_counter + 1; end if; + -- reset sync + if Control_register_I.reset_gensync = '1' then bunch_in_sync <= false; + -- start sync when bc_start + elsif (not bunch_in_sync) and (bc_gen = bc_start) then bunch_in_sync <= true; end if; + + + -- HBr generator + if bc_gen = x"000" then + if hbr_rate = x"0" then hbr_count <= x"F"; + elsif hbr_count = hbr_rate then hbr_count <= x"0"; + else hbr_count <= hbr_count + 1; end if; + end if; + + + -- SOX / EOX generator + if bc_gen = LHC_BCID_max then + + if run_state = idle and run_command = continious then send_soc <= true; run_state <= continious; end if; + if run_state = continious and run_command = idle then send_eoc <= true; run_state <= idle; end if; + if run_state = idle and run_command = trigger then send_sot <= true; run_state <= trigger; end if; + if run_state = trigger and run_command = idle then send_eot <= true; run_state <= idle; end if; + + else + send_soc <= false; + send_eoc <= false; + send_sot <= false; + send_eot <= false; + end if; + + + + end if; + + end if; + + end process; +-- *************************************************** + + send_trgcnt <= false when (bunch_counter = 0) or (bunch_counter > 64) else Control_register_I.Trigger_Gen.trigger_pattern(bunch_counter-1) = '1'; + trggen_cnt <= Control_register_I.Trigger_Gen.trigger_cont_value when send_trgcnt else (others => '0'); + + trggen_sox <= TRG_const_SOC when send_soc else + TRG_const_EOC when send_eoc else + TRG_const_SOT when send_sot else + TRG_const_EOT when send_eot else + (others => '0'); + + trggen_hb <= TRG_const_Orbit or TRG_const_HB or TRG_const_HBr or TRG_const_TF when bc_gen = x"000" and (hbr_count = hbr_rate) else + TRG_const_Orbit or TRG_const_HB or TRG_const_TF when bc_gen = x"000" and (hbr_count /= hbr_rate) else + (others => '0'); + + trggen_rdstate <= TRG_const_RS when (run_state = trigger) or (run_state_ff = trigger) else + TRG_const_RS or TRG_const_RT when (run_state = continious) or (run_state_ff = continious) else + (others => '0'); + + rx_data_gen <= orbit_gen_mod & x"0"&bc_gen & (trggen_hb or trggen_sox or trggen_rdstate or trggen_cnt); + rx_isdata_gen <= '1' when (trggen_hb or trggen_sox or trggen_cnt) /= TRG_const_void else '0'; + +end Behavioral; + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/common/gbt-readout/hdl/error_report.vhd b/firmware/common/gbt-readout/hdl/error_report.vhd new file mode 100644 index 0000000..800a927 --- /dev/null +++ b/firmware/common/gbt-readout/hdl/error_report.vhd @@ -0,0 +1,235 @@ +---------------------------------------------------------------------------------- +-- Company: INR RAS +-- Engineer: Finogeev D. A. dmitry-finogeev@yandex.ru +-- +-- Create Date: 07/2022 +-- Description: provides error reporting via check registers +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use ieee.numeric_std.all; +use ieee.std_logic_unsigned.all; + +use work.all; +use work.fit_gbt_common_package.all; + + +entity error_report is + port ( + RESET_I : in std_logic; + FSM_Clocks_I : in rdclocks_t; + + Status_register_I : in readout_status_t; + Control_register_I : in readout_control_t; + + RX_IsData_I : in std_logic; + RX_Data_I : in std_logic_vector(GBT_data_word_bitdepth-1 downto 0); + + err_report_fifo_rden_i : in std_logic; + report_fifo_o : out std_logic_vector(31 downto 0); + report_fifo_empty_o : out std_logic + ); +end error_report; + +architecture Behavioral of error_report is + + -- shift registers for data history report + signal gbt_data_shreg : std_logic_vector(errrep_crugbt_len*96-1 downto 0); + signal gbt_data_counter : std_logic_vector(15 downto 0); + + -- error report register + signal err_rep_pmdat, err_rep_rawfull, err_rep_gbtcru, err_rep_mux : std_logic_vector(errrep_fifo_len*32-1 downto 0); + + -- report fifo output + signal report_fifo_full, snshot_fifo_emtpy, snshot_fifo_rden, report_fifo_rden : std_logic; + signal snshot_fifo_do, report_fifo_do : std_logic_vector(31 downto 0); + + -- trigger for error + signal err_trg_bclost, err_trg_pmhd, err_sel_full : std_logic; + signal pm_data_early_header, pm_data_early_header_ff : std_logic; + signal cnv_fifo_max_ff01, cnv_fifo_max_ff02 : std_logic_vector(15 downto 0); + + + -- reset signal + signal reset : std_logic; + + -- attribute mark_debug : string; + -- attribute mark_debug of gbt_data_shreg : signal is "true"; + -- attribute mark_debug of err_rep_pmdat : signal is "true"; + -- attribute mark_debug of err_rep_gbtcru : signal is "true"; + -- attribute mark_debug of err_rep_mux : signal is "true"; + -- attribute mark_debug of report_fifo_do : signal is "true"; + -- attribute mark_debug of err_trg_bclost : signal is "true"; + -- attribute mark_debug of err_trg_pmhd : signal is "true"; + -- attribute mark_debug of snshot_fifo_do : signal is "true"; + -- attribute mark_debug of snshot_fifo_emtpy : signal is "true"; + -- attribute mark_debug of snshot_fifo_rden : signal is "true"; + -- attribute mark_debug of report_fifo_full : signal is "true"; + -- attribute mark_debug of report_fifo_rden : signal is "true"; + + +begin + +-- signal mapping ------------------------------------------ + report_fifo_o <= report_fifo_do; + report_fifo_rden <= err_report_fifo_rden_i; + pm_data_early_header <= Status_register_I.fsm_errors(9); + + -- errors report mapping + err_rep_gbtcru(31 downto 0) <= x"EEEE000A"; -- header + err_rep_gbtcru(errrep_crugbt_len*96+31 downto 32) <= gbt_data_shreg; + + err_rep_pmdat(31 downto 0) <= x"EEEE0009"; -- header + err_rep_pmdat(errrep_pmdat_len*80+31 downto 32) <= Status_register_I.pm_data_buff; + err_rep_pmdat(errrep_fifo_len*32-1 downto errrep_pmdat_len*80+32) <= (others => '0'); + + err_rep_rawfull(31 downto 0) <= x"EEEE0008"; -- header + err_rep_rawfull((errrep_pmdat_len-1)*80+31 downto 32) <= Status_register_I.pm_data_buff((errrep_pmdat_len-1)*80-1 downto 0); + err_rep_rawfull(errrep_fifo_len*32-1 downto (errrep_pmdat_len-1)*80+32) <= x"000000000"&Status_register_I.rawdatfifo_wr_rate & x"0"&Status_register_I.rawdatfifo_rd_rate & x"0000"; + + +-- triggering bcid sync lost error snapshot + err_trg_bclost <= '1' when Status_register_I.bcsync_lost_flag = '1' else '0'; + err_trg_pmhd <= '1' when pm_data_early_header = '1' and pm_data_early_header_ff = '0' else '0'; + err_sel_full <= '1' when cnv_fifo_max_ff02(11) = '0' and cnv_fifo_max_ff01(11) = '1' else '0'; + + err_rep_mux <= err_rep_gbtcru when err_trg_bclost='1' else + err_rep_pmdat when err_trg_pmhd = '1' else + err_rep_rawfull when err_sel_full = '1' else + (others => '0'); + + + + + +-- shapshot fifo ============================================= + error_rep_fifo_cmp : entity work.snapshot_fifo + generic map(n32_size => errrep_fifo_len) + port map( + wr_clk_i => FSM_Clocks_I.Data_Clk, + rd_clk_i => FSM_Clocks_I.ipbus_clk, + asreset_i => reset, + + di_i => err_rep_mux, + do_o => snshot_fifo_do, + empty_o => snshot_fifo_emtpy, + + wren_i => err_trg_bclost or err_trg_pmhd or err_sel_full, + rden_i => snshot_fifo_rden + ); + snshot_fifo_rden <= '1' when snshot_fifo_emtpy = '0' and report_fifo_full = '0' else '0'; +-- =========================================================== + +-- error report fifo ========================================= + err_report_fifo_comp : entity work.err_report_fifo + port map( + clk => FSM_Clocks_I.ipbus_clk, + srst => reset, + WR_EN => snshot_fifo_rden, + RD_EN => report_fifo_rden, + DIN => snshot_fifo_do, + DOUT => report_fifo_do, + FULL => report_fifo_full, + EMPTY => report_fifo_empty_o + ); +-- =========================================================== + + + + + +-- data clk ********************************** + process (FSM_Clocks_I.Data_Clk) + begin + if(rising_edge(FSM_Clocks_I.Data_Clk))then + + -- reset + reset <= Control_register_I.reset_err_report or RESET_I; + + -- errors signals + pm_data_early_header_ff <= pm_data_early_header; + cnv_fifo_max_ff01 <= Status_register_I.cnv_fifo_max; + cnv_fifo_max_ff02 <= cnv_fifo_max_ff01; + + -- errors report mapping (delayed) + err_rep_gbtcru((errrep_crugbt_len*96)+32*2-1 downto (errrep_crugbt_len*96)+32*1) <= x"0"&Status_register_I.BCID_from_CRU & x"0"&Status_register_I.ORBC_from_CRU_sync(11 downto 0); + err_rep_gbtcru((errrep_crugbt_len*96)+32*3-1 downto (errrep_crugbt_len*96)+32*2) <= Status_register_I.ORBIT_from_CRU; + err_rep_gbtcru((errrep_crugbt_len*96)+32*4-1 downto (errrep_crugbt_len*96)+32*3) <= Status_register_I.ORBC_from_CRU_sync(32+12-1 downto 12); + err_rep_gbtcru(errrep_fifo_len*32-1 downto (errrep_crugbt_len*96)+32*4) <= (others => '0'); + + + if (reset = '1') then + + gbt_data_counter <= (others => '0'); + gbt_data_shreg <= (others => '0'); + pm_data_early_header_ff <= '0'; + + else + + gbt_data_counter <= gbt_data_counter+1; + + -- shift registers for error reporting + if RX_IsData_I = '1' or Control_register_I.errrep_slost_allgbtw = '1' then + gbt_data_shreg <= gbt_data_shreg(errrep_crugbt_len*96-97 downto 0) & "000" & RX_IsData_I & gbt_data_counter(11 downto 0) & RX_Data_I; + end if; + + + end if; + + end if; + + end process; +-- *************************************************** + +end Behavioral; + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/common/gbt-readout/hdl/fit_gbt_boardPM_package.vhd b/firmware/common/gbt-readout/hdl/fit_gbt_boardPM_package.vhd index b0ea317..586c3fa 100644 --- a/firmware/common/gbt-readout/hdl/fit_gbt_boardPM_package.vhd +++ b/firmware/common/gbt-readout/hdl/fit_gbt_boardPM_package.vhd @@ -44,7 +44,6 @@ package fit_gbt_board_package is type board_data_type is record is_header : std_logic; is_data : std_logic; - is_packet : std_logic; data_word : std_logic_vector(GBT_data_word_bitdepth-1 downto 0); end record; @@ -52,7 +51,6 @@ package fit_gbt_board_package is ( is_header => '0', is_data => '0', - is_packet => '0', data_word => (others => '0') ); -- ============================================================= diff --git a/firmware/common/gbt-readout/hdl/fit_gbt_common_package.vhd b/firmware/common/gbt-readout/hdl/fit_gbt_common_package.vhd index 622c4fb..d8eb331 100644 --- a/firmware/common/gbt-readout/hdl/fit_gbt_common_package.vhd +++ b/firmware/common/gbt-readout/hdl/fit_gbt_common_package.vhd @@ -3,7 +3,7 @@ -- Engineer: Finogeev D.A. dmitry-finogeev@yandex.ru -- -- Create Date: 10:29:21 08/11/2017 --- Design Name: +-- Design Name: -- Module Name: -- Project Name: -- Target Devices: @@ -19,378 +19,332 @@ ---------------------------------------------------------------------------------- library IEEE; -use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_1164.all; use ieee.numeric_std.all; -use ieee.std_logic_unsigned.all ; +use ieee.std_logic_unsigned.all; package fit_gbt_common_package is --- ===== CONSTANTS ============================================= - - constant ENABLED : integer := 1; - constant DISABLED : integer := 0; - --- data size constants ----------------------------------------- - constant GBT_data_word_bitdepth : integer := 80; - constant GBT_slowcntr_bitdepth : integer := 4; - constant Orbit_id_bitdepth : integer := 32; - constant BC_id_bitdepth : integer := 12; - constant Trigger_bitdepth : integer := 32; - constant rx_phase_bitdepth : integer := 3; - constant RDH_pages_counter_bitdepth : integer := 16; - constant FEE_ID_bitdepth : integer := 16; - constant PAR_bitdepth : integer := 16; - constant DETFIELD_bitdepth : integer := 16; - - constant n_pckt_wrds_bitdepth : integer := 8; - constant GEN_count_bitdepth : integer := 16; --- ------------------------------------------------------------- - - constant GEN_const_void : std_logic_vector(GEN_count_bitdepth-1 downto 0) := x"0000"; - constant GEN_const_full : std_logic_vector(GEN_count_bitdepth-1 downto 0) := x"ffff"; - constant ORBIT_const_void : std_logic_vector(Orbit_id_bitdepth-1 downto 0) := (others => '0'); - constant BC_const_void : std_logic_vector(BC_id_bitdepth-1 downto 0) := (others => '0'); - - --- Trigger constants ------------------------------------------- - -- constant TRG_const_void : std_logic_vector(Trigger_bitdepth-1 downto 0) := x"00000000"; - -- constant TRG_const_Orbit : std_logic_vector(Trigger_bitdepth-1 downto 0) := x"00000001"; - -- constant TRG_const_HB : std_logic_vector(Trigger_bitdepth-1 downto 0) := x"00000002"; - -- constant TRG_const_HC : std_logic_vector(Trigger_bitdepth-1 downto 0) := x"00000003"; - -- constant TRG_const_Ph : std_logic_vector(Trigger_bitdepth-1 downto 0) := x"00000010"; - -- constant TRG_const_SOT : std_logic_vector(Trigger_bitdepth-1 downto 0) := x"00000080"; - -- constant TRG_const_EOT : std_logic_vector(Trigger_bitdepth-1 downto 0) := x"00000100"; - -- constant TRG_const_SOC : std_logic_vector(Trigger_bitdepth-1 downto 0) := x"00000200"; - -- constant TRG_const_EOC : std_logic_vector(Trigger_bitdepth-1 downto 0) := x"00000400"; - -- constant TRG_const_ORBCrsv : std_logic_vector(Trigger_bitdepth-1 downto 0) := x"0000000f"; - -- constant TRG_const_response : std_logic_vector(Trigger_bitdepth-1 downto 0) := x"ffffffff"; - - constant TRG_const_void : std_logic_vector(Trigger_bitdepth-1 downto 0) := x"00000000"; - constant TRG_const_Orbit : std_logic_vector(Trigger_bitdepth-1 downto 0) := x"00000001"; --0 - constant TRG_const_HB : std_logic_vector(Trigger_bitdepth-1 downto 0) := x"00000002"; --1 - constant TRG_const_HBr : std_logic_vector(Trigger_bitdepth-1 downto 0) := x"00000004"; --2 - constant TRG_const_HC : std_logic_vector(Trigger_bitdepth-1 downto 0) := x"00000008"; --3 - constant TRG_const_Ph : std_logic_vector(Trigger_bitdepth-1 downto 0) := x"00000010"; --4 - constant TRG_const_PP : std_logic_vector(Trigger_bitdepth-1 downto 0) := x"00000020"; --5 - constant TRG_const_Cal : std_logic_vector(Trigger_bitdepth-1 downto 0) := x"00000040"; --6 - constant TRG_const_SOT : std_logic_vector(Trigger_bitdepth-1 downto 0) := x"00000080"; --7 - constant TRG_const_EOT : std_logic_vector(Trigger_bitdepth-1 downto 0) := x"00000100"; --8 - constant TRG_const_SOC : std_logic_vector(Trigger_bitdepth-1 downto 0) := x"00000200"; --9 - constant TRG_const_EOC : std_logic_vector(Trigger_bitdepth-1 downto 0) := x"00000400"; --10 - constant TRG_const_TF : std_logic_vector(Trigger_bitdepth-1 downto 0) := x"00000800"; -- time frame delimiter - constant TRG_const_FErst : std_logic_vector(Trigger_bitdepth-1 downto 0) := x"00001000"; -- FEE reset - constant TRG_const_RT : std_logic_vector(Trigger_bitdepth-1 downto 0) := x"00002000"; -- Run Type; 1=Cont, 0=Trig - constant TRG_const_RS : std_logic_vector(Trigger_bitdepth-1 downto 0) := x"00004000"; --Running State; 1=Running --- ------------------------------------------------------------- - --- Experiment constants ---------------------------------------- - constant LHC_BCID_max : std_logic_vector(BC_id_bitdepth-1 downto 0) := x"deb"; +-- signal size constants --------------------------------------- + constant GBT_data_word_bitdepth : integer := 80; + constant GBT_slowcntr_bitdepth : integer := 4; + constant Orbit_id_bitdepth : integer := 32; + constant BC_id_bitdepth : integer := 12; + constant Trigger_bitdepth : integer := 32; + constant rx_phase_bitdepth : integer := 3; + constant n_pckt_wrds_bitdepth : integer := 8; -- ------------------------------------------------------------- - --- DAQ Constants ----------------------------------------------- ---constant data_word_cnst_SOP : std_logic_vector(GBT_data_word_bitdepth-1 downto 0) := x"10000000000000000000"; -- SOP CRU -constant data_word_cnst_SOP : std_logic_vector(GBT_data_word_bitdepth-1 downto 0) := x"00000000000000000001"; -- SOP G-RORC - ---constant data_word_cnst_EOP : std_logic_vector(GBT_data_word_bitdepth-1 downto 0) := x"20000000000000000000"; -- eop CRU -constant data_word_cnst_EOP : std_logic_vector(GBT_data_word_bitdepth-1 downto 0) := x"00000000000000000002"; -- eop G-RORC - --- ------------------------------------------------------------- - - --- FIFO constants ---------------------------------------------- - -- raw_data_fifo - constant fifo_data_bitdepth : integer := GBT_data_word_bitdepth; - constant rawfifo_depth : integer := 4096; - constant rawfifo_count_bitdepth : integer := 13; - constant slctfifo_depth : integer := 4096; - constant slctfifo_count_bitdepth : integer := 13; - -- trg_fifo_comt - constant trgfifo_data_bitdepth : integer := Orbit_id_bitdepth+BC_id_bitdepth+Trigger_bitdepth; --76 - constant trgfifo_depth : integer := 512; - constant trgfifo_count_bitdepth : integer := 10; - -- cntpck_fifo_comp - constant cntpckfifo_data_bitdepth : integer := GEN_count_bitdepth+RDH_pages_counter_bitdepth+Orbit_id_bitdepth+BC_id_bitdepth+Orbit_id_bitdepth+BC_id_bitdepth+Trigger_bitdepth + 8; -- 8+16+16+76 + 44 = 160 - constant cntpckfifo_depth : integer := 128; - constant cntpckfifo_count_bitdepth : integer := 8; - - - +-- Trigger constants ------------------------------------------- + constant TRG_const_void : std_logic_vector(Trigger_bitdepth-1 downto 0) := x"00000000"; + constant TRG_const_Orbit : std_logic_vector(Trigger_bitdepth-1 downto 0) := x"00000001"; --0 + constant TRG_const_HB : std_logic_vector(Trigger_bitdepth-1 downto 0) := x"00000002"; --1 + constant TRG_const_HBr : std_logic_vector(Trigger_bitdepth-1 downto 0) := x"00000004"; --2 + constant TRG_const_HC : std_logic_vector(Trigger_bitdepth-1 downto 0) := x"00000008"; --3 + constant TRG_const_Ph : std_logic_vector(Trigger_bitdepth-1 downto 0) := x"00000010"; --4 + constant TRG_const_PP : std_logic_vector(Trigger_bitdepth-1 downto 0) := x"00000020"; --5 + constant TRG_const_Cal : std_logic_vector(Trigger_bitdepth-1 downto 0) := x"00000040"; --6 + constant TRG_const_SOT : std_logic_vector(Trigger_bitdepth-1 downto 0) := x"00000080"; --7 + constant TRG_const_EOT : std_logic_vector(Trigger_bitdepth-1 downto 0) := x"00000100"; --8 + constant TRG_const_SOC : std_logic_vector(Trigger_bitdepth-1 downto 0) := x"00000200"; --9 + constant TRG_const_EOC : std_logic_vector(Trigger_bitdepth-1 downto 0) := x"00000400"; --10 + constant TRG_const_TF : std_logic_vector(Trigger_bitdepth-1 downto 0) := x"00000800"; -- time frame delimiter + constant TRG_const_FErst : std_logic_vector(Trigger_bitdepth-1 downto 0) := x"00001000"; -- FEE reset + constant TRG_const_RT : std_logic_vector(Trigger_bitdepth-1 downto 0) := x"00002000"; -- Run Type; 1=Cont, 0=Trig + constant TRG_const_RS : std_logic_vector(Trigger_bitdepth-1 downto 0) := x"00004000"; --Running State; 1=Running + + constant TRG_LASER_STR : std_logic_vector(Trigger_bitdepth-1 downto 0) := TRG_const_Cal; + + constant LHC_BCID_max : std_logic_vector(BC_id_bitdepth-1 downto 0) := x"deb"; -- ------------------------------------------------------------- --- ============================================================= - - - - - -- ===== FIT GBT Readout types ================================= - type FSM_Clocks_type is record - Reset : std_logic; - Reset40 : std_logic; - Data_Clk : std_logic; - System_Clk : std_logic; - System_Counter : std_logic_vector(3 downto 0); - GBT_RX_Clk : std_logic; --used in TESTB - IPBUS_Data_Clk : std_logic; --used in TESTB - end record; + type rdclocks_t is record + Reset_dclk : std_logic; -- reset by gbt TX clock + Reset_sclk : std_logic; -- reset system clock 320 MHz + Data_Clk : std_logic; + System_Clk : std_logic; + System_Counter : std_logic_vector(3 downto 0); + GBT_RX_Clk : std_logic; --used in TESTB + ipbus_clk : std_logic; + end record; -- ============================================================= - - +-- ===== ERRORS report types =================================== + constant errrep_crugbt_len : integer := 10; + constant errrep_pmdat_len : integer := 14; + constant errrep_fifo_len : integer := 36; + type gbt_data_arr_t is array (natural range <>) of std_logic_vector(95 downto 0); +-- ============================================================= -- ===== CONTROL REGISTER ====================================== - constant cntr_reg_n_32word : integer := 13; - type cntr_reg_addrreg_type is array (0 to cntr_reg_n_32word-1) of std_logic_vector(31 downto 0); - - type Type_Gen_use_type is (use_NO_generator, use_MAIN_generator, use_TX_generator); - type Data_Gen_CONTROL_type is record - usage_generator : Type_Gen_use_type; - trigger_resp_mask : std_logic_vector(Trigger_bitdepth-1 downto 0); -- data generated for this trigger - bunch_pattern : std_logic_vector(31 downto 0); -- pattern lenghts of packet - bunch_freq : std_logic_vector(15 downto 0); -- pattern frequency - bunch_freq_hboffset : std_logic_vector(BC_id_bitdepth-1 downto 0); -- offset of freq counter to first Orbit TRG - end record; - - - type Type_trgGen_use_type is (use_NO_generator, use_CONT_generator, use_TX_generator); - type Readout_command_type is (idle, continious, trigger); - - type Trigger_Gen_CONTROL_type is record - usage_generator : Type_trgGen_use_type; - Readout_command : Readout_command_type; - trigger_single_val : std_logic_vector(Trigger_bitdepth-1 downto 0); -- send this trigger (once then moved from 0->1) - trigger_pattern : std_logic_vector(63 downto 0); -- trigger pattern 32 BC lenght - trigger_cont_value : std_logic_vector(Trigger_bitdepth-1 downto 0); -- trigger that sendign continious - bunch_freq : std_logic_vector(15 downto 0); -- trigger frequency - bunch_freq_hboffset : std_logic_vector(BC_id_bitdepth-1 downto 0); -- offset of freq counter to first Orbit TRG - end record; - - type RDH_data_type is record - FEE_ID : std_logic_vector(FEE_ID_bitdepth-1 downto 0); - PAR : std_logic_vector(PAR_bitdepth-1 downto 0); - DET_Field : std_logic_vector(DETFIELD_bitdepth-1 downto 0); - end record; - - type CONTROL_REGISTER_type is record - Data_Gen : Data_Gen_CONTROL_type; - Trigger_Gen : Trigger_Gen_CONTROL_type; - RDH_data : RDH_data_type; - - readout_bypass : std_logic; - is_hb_response : std_logic; - trg_data_select : std_logic_vector(Trigger_bitdepth-1 downto 0); - - n_BCID_delay : std_logic_vector(BC_id_bitdepth-1 downto 0); -- delay between ID from TX and ID in module data - crutrg_delay_comp : std_logic_vector(BC_id_bitdepth-1 downto 0); -- how long data keeped in raw fifo waiting trigger - max_data_payload: std_logic_vector(GEN_count_bitdepth-1 downto 0); - reset_orbc_synd : std_logic; -- sync ORBIT, BC to CRU then moved from 0->1 - reset_drophit_counter : std_logic; -- reset FIFO statistic then moved from 0->1 - reset_gen_offset: std_logic; -- reset generators offset - reset_gbt_rxerror: std_logic; -- reset gbt rx error bit - reset_gbt :std_logic; -- reset gbt (not ready) - reset_rxph_error:std_logic; -- reset gbt (not ready) - strt_rdmode_lock : std_logic; - end record; - - constant test_CONTROL_REG : CONTROL_REGISTER_type := - ( - Data_Gen => ( - usage_generator => use_TX_generator, - --usage_generator => use_MAIN_generator, - - trigger_resp_mask => TRG_const_void, - bunch_pattern => x"10e0766f", - bunch_freq => x"0deb", - bunch_freq_hboffset => x"ddc" - ), - - Trigger_Gen => ( - usage_generator => use_CONT_generator, - --usage_generator => use_NO_generator - Readout_command => idle, - trigger_single_val => x"00000000", - trigger_pattern => x"0000000080000000", - trigger_cont_value => TRG_const_Ph, - bunch_freq => x"0deb", - bunch_freq_hboffset => x"ddc" - ), - - RDH_data => ( - FEE_ID => x"0001", - PAR => x"ffff", - DET_Field => x"1234" - ), - - readout_bypass => '0', - is_hb_response => '1', - trg_data_select => x"00000010", - - n_BCID_delay => x"01f", - crutrg_delay_comp => x"00f", - max_data_payload => x"00f0", - reset_orbc_synd => '0', - reset_drophit_counter => '0', - reset_gen_offset => '0', - reset_gbt_rxerror => '0', - reset_gbt => '0', - reset_rxph_error => '0', - strt_rdmode_lock => '0' - ); + constant ctrl_reg_size : integer := 13; + type ctrl_reg_t is array (0 to ctrl_reg_size-1) of std_logic_vector(31 downto 0); + + type gen_mode_t is (gen_off, data_gen_on, gen_tx_out); + type trggen_mode_t is (gen_off, ltu_emu_on, gen_tx_out); + type rdcmd_t is (idle, continious, trigger); + + type ctrl_gen_t is record + usage_generator : gen_mode_t; + trigger_resp_mask : std_logic_vector(Trigger_bitdepth-1 downto 0); -- data generated for this trigger + bunch_pattern : std_logic_vector(31 downto 0); -- pattern lenghts of packet + bunch_freq : std_logic_vector(15 downto 0); -- pattern frequency + bc_start : std_logic_vector(BC_id_bitdepth-1 downto 0); -- offset of freq counter to first Orbit TRG + orbit_jump : std_logic; -- orbit jump to generate bcid_sync_lost in simulation + end record; + + type ctrl_trggen_t is record + usage_generator : trggen_mode_t; + Readout_command : rdcmd_t; + trigger_pattern : std_logic_vector(63 downto 0); -- trigger pattern 32 BC lenght + trigger_cont_value : std_logic_vector(Trigger_bitdepth-1 downto 0); -- trigger that sendign continious + bunch_freq : std_logic_vector(15 downto 0); -- trigger frequency + bc_start : std_logic_vector(BC_id_bitdepth-1 downto 0); -- offset of freq counter to first Orbit TRG + hbr_rate : std_logic_vector(3 downto 0); -- HB reject rate, 0 - off + end record; + + type rdh_ctrl_t is record + FEE_ID : std_logic_vector(15 downto 0); + SYS_ID : std_logic_vector(7 downto 0); + PRT_BIT : std_logic_vector(7 downto 0); + end record; + + type readout_control_t is record + Data_Gen : ctrl_gen_t; + Trigger_Gen : ctrl_trggen_t; + RDH_data : rdh_ctrl_t; + + readout_bypass : std_logic; + is_hb_response : std_logic; + is_hb_reject : std_logic; + rxclk_sync_shift : std_logic; + force_idle : std_logic; -- reset phase error, sync move to start, lock CNT/TRG mode to IDLE + trg_data_select : std_logic_vector(Trigger_bitdepth-1 downto 0); + + errrep_slost_allgbtw : std_logic; + + reset_orbc_sync : std_logic; -- sync ORBIT, BC to CRU + reset_data_counters : std_logic; -- reset FIFO statistic + reset_gensync : std_logic; -- reset generators offset + reset_gbt_rxerror : std_logic; -- reset gbt rx error bit + reset_rxph_error : std_logic; -- reset gbt phase error + reset_readout : std_logic; -- reset readout fsm + reset_gbt : std_logic; -- reset gbt + reset_err_report : std_logic; -- reset error report fifo + + BCID_offset : std_logic_vector(BC_id_bitdepth-1 downto 0); -- delay between ID from TX and ID in module data + + end record; + + constant test_CONTROL_REG : readout_control_t := + ( + Data_Gen => ( + usage_generator => gen_off, + trigger_resp_mask => TRG_const_void, + bunch_pattern => x"00000000", + bunch_freq => x"0000", + bc_start => x"000", + orbit_jump => '0' + ), + + Trigger_Gen => ( + usage_generator => gen_off, + Readout_command => idle, + trigger_pattern => x"0000000000000000", + trigger_cont_value => TRG_const_void, + bunch_freq => x"0000", + bc_start => x"000", + hbr_rate => x"0" + ), + + RDH_data => ( + FEE_ID => x"0000", + SYS_ID => x"00", + PRT_BIT => x"00" + ), + + readout_bypass => '0', + is_hb_response => '1', + is_hb_reject => '1', + rxclk_sync_shift => '0', + trg_data_select => x"00000000", + + errrep_slost_allgbtw => '0', + + reset_orbc_sync => '0', + reset_data_counters => '0', + reset_gensync => '0', + reset_gbt_rxerror => '0', + reset_readout => '0', + reset_gbt => '0', + reset_rxph_error => '0', + force_idle => '0', + reset_err_report => '0', + + BCID_offset => x"000" + ); -- ============================================================= - - - - - - - -- ===== FIT GBT STATUS ======================================== - constant status_reg_n_32word : integer := 8; - constant status_reg_sim_n_32word : integer := status_reg_n_32word+4; - type status_reg_addrreg_type is array (0 to status_reg_n_32word-1) of std_logic_vector(31 downto 0); - type status_reg_addrreg_sim_type is array (0 to status_reg_sim_n_32word-1) of std_logic_vector(31 downto 0); -- extended status registers set for simulation (trigger added) - - type Type_Readout_Mode is (mode_IDLE, mode_CNT, mode_TRG); - type Type_BCIDsync_Mode is (mode_STR, mode_SYNC, mode_LOST); - - type Type_GBT_status is record - txWordClk : std_logic; - rxFrameClk : std_logic; - rxWordClk : std_logic; - txOutClkFabric : std_logic; - - mgt_phalin_cplllock : std_logic; --reg bit 0 - - rxWordClkReady : std_logic; --reg bit 1 - rxFrameClkReady : std_logic; --reg bit 2 - - mgtLinkReady :std_logic; --reg bit 3 - tx_resetDone :std_logic; --reg bit 4 - tx_fsmResetDone :std_logic; --reg bit 5 - - gbtRx_Ready :std_logic; --reg bit 6 - gbtRx_ErrorDet :std_logic; --reg bit 7 - gbtRx_ErrorLatch :std_logic; --reg bit 8 - - Rx_Phase_error :std_logic; --reg bit 9 - end record; - - - type FIFO_STATUS_type is record - raw_fifo_count : std_logic_vector(rawfifo_count_bitdepth-1 downto 0); - slct_fifo_count : std_logic_vector(slctfifo_count_bitdepth-1 downto 0); - ftmipbus_fifo_count : std_logic_vector(slctfifo_count_bitdepth-1 downto 0); - trg_fifo_count : std_logic_vector(trgfifo_count_bitdepth-1 downto 0); - cntr_fifo_count : std_logic_vector(cntpckfifo_count_bitdepth-1 downto 0); - end record; - - type hit_rd_counter_type is record - hits_send_porbit : std_logic_vector(15 downto 0); - hits_skipped : std_logic_vector(31 downto 0); - first_orbit_hdrop : std_logic_vector(Orbit_id_bitdepth-1 downto 0); - first_bc_hdrop : std_logic_vector(BC_id_bitdepth-1 downto 0); - last_orbit_hdrop : std_logic_vector(Orbit_id_bitdepth-1 downto 0); - last_bc_hdrop : std_logic_vector(BC_id_bitdepth-1 downto 0); - end record; - - - - type FIT_GBT_status_type is record - GBT_status : Type_GBT_status; - Readout_Mode : Type_Readout_Mode; - CRU_Readout_Mode : Type_Readout_Mode; - BCIDsync_Mode : Type_BCIDsync_Mode; - Start_run : std_logic; - Stop_run : std_logic; - - Trigger_from_CRU : std_logic_vector(Trigger_bitdepth-1 downto 0); -- Trigger ID from CRUS - BCID_from_CRU : std_logic_vector(BC_id_bitdepth-1 downto 0); -- BC ID from CRUS - ORBIT_from_CRU : std_logic_vector(Orbit_id_bitdepth-1 downto 0); -- ORBIT from CRUS - BCID_from_CRU_corrected : std_logic_vector(BC_id_bitdepth-1 downto 0); -- BC ID from CRUS - ORBIT_from_CRU_corrected : std_logic_vector(Orbit_id_bitdepth-1 downto 0); -- ORBIT from CRUS - - Data_gen_report : std_logic_vector(31 downto 0); -- info of generated data; used only in simulation - - fifo_status : FIFO_STATUS_type; - hits_rd_counter_converter : hit_rd_counter_type; - hits_rd_counter_selector : hit_rd_counter_type; - - - rx_phase : std_logic_vector(rx_phase_bitdepth-1 downto 0); - - end record; + constant stat_reg_size : integer := 11; + constant stat_reg_size_sim : integer := stat_reg_size+6; + constant ipbusrd_stat_addr_offset : integer := 16; + constant ipbusrd_fifo_out_addr : integer := 8; + type stat_reg_t is array (0 to stat_reg_size-1) of std_logic_vector(31 downto 0); + type stat_reg_sim_t is array (0 to stat_reg_size_sim-1) of std_logic_vector(31 downto 0); -- extended status registers set for simulation (trigger added) + + type rdmode_t is (mode_IDLE, mode_CNT, mode_TRG); + type bcid_sync_t is (mode_STR, mode_SYNC, mode_LOST); + + type gbt_status_t is record + mgt_phalin_cplllock : std_logic; --reg bit 0 + rxWordClkReady : std_logic; --reg bit 1 + rxFrameClkReady : std_logic; --reg bit 2 + mgtLinkReady : std_logic; --reg bit 3 + tx_resetDone : std_logic; --reg bit 4 + tx_fsmResetDone : std_logic; --reg bit 5 + gbtRx_Ready : std_logic; + gbtRx_ErrorDet : std_logic; --reg bit 7 + gbtRx_ErrorLatch : std_logic; --reg bit 8 + gbt_not_ready : std_logic; --reg bit 9 + gbt_was_ready : std_logic; --reg bit 6 + end record; + + type datagen_report_t is record + orbit : std_logic_vector(Orbit_id_bitdepth-1 downto 0); + bc : std_logic_vector(BC_id_bitdepth-1 downto 0); + size : std_logic_vector(n_pckt_wrds_bitdepth-1 downto 0); + packet_num : std_logic_vector(35 downto 0); + end record; + + type bc_indicator_t is record + bc : std_logic_vector(BC_id_bitdepth-1 downto 0); + count : std_logic_vector(3 downto 0); + end record; + + + type readout_status_t is record + GBT_status : gbt_status_t; + datagen_report : datagen_report_t; -- header of generated data; used only in simulation + + Readout_Mode : rdmode_t; + CRU_Readout_Mode : rdmode_t; -- !!! got value for one cycle in HB + BCIDsync_Mode : bcid_sync_t; + Start_run : std_logic; + Stop_run : std_logic; + data_enable : std_logic; + bc_delay_apply : std_logic; + trg_match_resp_mask : std_logic; + laser_start : std_logic; + + Trigger_from_CRU : std_logic_vector(Trigger_bitdepth-1 downto 0); -- Trigger ID from CRUS + BCID_from_CRU : std_logic_vector(BC_id_bitdepth-1 downto 0); -- BC ID from CRUS + ORBIT_from_CRU : std_logic_vector(Orbit_id_bitdepth-1 downto 0); -- ORBIT from CRUS + BCID_from_CRU_corrected : std_logic_vector(BC_id_bitdepth-1 downto 0); -- BC ID from CRUS + ORBIT_from_CRU_corrected : std_logic_vector(Orbit_id_bitdepth-1 downto 0); -- ORBIT from CRUS + ORBC_from_CRU_sync : std_logic_vector(Orbit_id_bitdepth + BC_id_bitdepth-1 downto 0); -- BC ID sync compared for errors report + + rx_phase : std_logic_vector(rx_phase_bitdepth-1 downto 0); + cnv_fifo_max : std_logic_vector(15 downto 0); + cnv_drop_cnt : std_logic_vector(15 downto 0); + sel_fifo_max : std_logic_vector(15 downto 0); + sel_drop_cnt : std_logic_vector(15 downto 0); + event_counter : std_logic_vector(31 downto 0); + gbt_data_cnt : std_logic_vector(31 downto 0); + + bcind_evt : bc_indicator_t; + bcind_trg : bc_indicator_t; + + -- readout via IPbus + ipbusrd_fifo_cnt : std_logic_vector(15 downto 0); + ipbusrd_fifo_out : std_logic_vector(31 downto 0); + ipbusrd_err_report : std_logic_vector(31 downto 0); + + -- bc sync lost + bcsync_lost_flag : std_logic; + bcsync_lost_cnt : std_logic_vector(7 downto 0); + + -- errors indicate unexpected FSM state, should be reset and debugged + -- 0 - [RDH builder] slct_fifo is empty while reading data + -- 1 - [Selector] slct_fifo is not empty when run starts + -- 2 - [Selector] cntpck_fifo is not empty when run starts + -- 3 - [Selector] trg_fifo is not empty when run starts + -- 4 - [Selector] trg_fifo was full + -- 5 - [Converter] data_fifo is not empty while start of run + -- 6 - [Converter] header_fifo is not empty while start of run + -- 7 - [Converter] tcm_data_fifo is full (TCM only) + ------ + -- 8 - [Converter] input packet corrupted: extra word (PM) + -- 9 - [Converter] input packet corrupted: header too early (PM) + -- 10- [ltu_rx_decoder] bc_sync lost during the run + -- 11- [ltu_rx_decoder] bc_sync lost out of the run + -- 15- [FRU] 0x1 = ready for run, all fifos are empty + fsm_errors : std_logic_vector(15 downto 0); + Rx_Phase_error : std_logic; --reg bit 9 + + -- fifos empty bits + -- 0 - [Converter] raw_header + -- 1 - [Converter] raw_data + -- 2 - [Selector] trg + -- 3 - [Selector] select + -- 4 - [Selector] cntpck + fifos_empty : std_logic_vector(7 downto 0); + + -- pm data circle buffer for error reporting + pm_data_buff : std_logic_vector(errrep_pmdat_len*80-1 downto 0); + rawdatfifo_wr_rate : std_logic_vector(11 downto 0); + rawdatfifo_rd_rate : std_logic_vector(11 downto 0); + + end record; + + constant test_gbt_status_void : gbt_status_t := + ( + mgt_phalin_cplllock => '0', + + rxWordClkReady => '0', + rxFrameClkReady => '0', + + mgtLinkReady => '0', + tx_resetDone => '0', + tx_fsmResetDone => '0', + + gbtRx_Ready => '0', + gbtRx_ErrorDet => '0', + gbtRx_ErrorLatch => '0', + gbt_not_ready => '0', + gbt_was_ready => '0' + ); -- ============================================================= - - - - - - -- ###################### CONVERSION FUNCTION ############################## -- FIT data header, formed in converter --------------------------- -function func_FITDATAHD_get_header -( - channel_n_words: std_logic_vector(n_pckt_wrds_bitdepth-1 downto 0); - ORBIT : std_logic_vector(Orbit_id_bitdepth-1 downto 0); - BCID : std_logic_vector(BC_id_bitdepth-1 downto 0); - rx_phase : std_logic_vector(rx_phase_bitdepth-1 downto 0); - rx_phase_error : std_logic; - is_tcm : std_logic -) -return std_logic_vector; - -function func_FITDATAHD_ndwords (header_w: std_logic_vector(fifo_data_bitdepth-1 downto 0) ) return std_logic_vector; -function func_FITDATAHD_orbit (header_w: std_logic_vector(fifo_data_bitdepth-1 downto 0) ) return std_logic_vector; -function func_FITDATAHD_bc (header_w: std_logic_vector(fifo_data_bitdepth-1 downto 0) ) return std_logic_vector; --- ---------------------------------------------------------------- - - - - --- Control word for FIT packet ------------------------------------ -function func_CNTPCKword_get_word -( - is_close_frame : std_logic; - pages_counter : std_logic_vector(RDH_pages_counter_bitdepth-1 downto 0); - n_words_in_packet : std_logic_vector(GEN_count_bitdepth-1 downto 0); - TRIGGER: std_logic_vector(Trigger_bitdepth-1 downto 0); - TRG_ORBIT : std_logic_vector(Orbit_id_bitdepth-1 downto 0); - TRG_BCID : std_logic_vector(BC_id_bitdepth-1 downto 0); - HB_ORBIT : std_logic_vector(Orbit_id_bitdepth-1 downto 0); - HB_BCID : std_logic_vector(BC_id_bitdepth-1 downto 0) -) -return std_logic_vector; - -function func_CNTPCKword_isclf (cntpck_w: std_logic_vector(cntpckfifo_data_bitdepth-1 downto 0) ) return std_logic; -function func_CNTPCKword_npwords (cntpck_w: std_logic_vector(cntpckfifo_data_bitdepth-1 downto 0) ) return std_logic_vector; -function func_CNTPCKword_pgcounter (cntpck_w: std_logic_vector(cntpckfifo_data_bitdepth-1 downto 0) ) return std_logic_vector; -function func_CNTPCKword_trigger (cntpck_w: std_logic_vector(cntpckfifo_data_bitdepth-1 downto 0) ) return std_logic_vector; -function func_CNTPCKword_trgorbit (cntpck_w: std_logic_vector(cntpckfifo_data_bitdepth-1 downto 0) ) return std_logic_vector; -function func_CNTPCKword_trgbc (cntpck_w: std_logic_vector(cntpckfifo_data_bitdepth-1 downto 0) ) return std_logic_vector; -function func_CNTPCKword_hborbit (cntpck_w: std_logic_vector(cntpckfifo_data_bitdepth-1 downto 0) ) return std_logic_vector; -function func_CNTPCKword_hbbc (cntpck_w: std_logic_vector(cntpckfifo_data_bitdepth-1 downto 0) ) return std_logic_vector; + function func_FITDATAHD_get_header + ( + channel_n_words : std_logic_vector(n_pckt_wrds_bitdepth-1 downto 0); + ORBIT : std_logic_vector(Orbit_id_bitdepth-1 downto 0); + BCID : std_logic_vector(BC_id_bitdepth-1 downto 0); + rx_phase : std_logic_vector(rx_phase_bitdepth-1 downto 0); + rx_phase_error : std_logic; + is_tcm : std_logic + ) + return std_logic_vector; + + function func_FITDATAHD_ndwords (header_w : std_logic_vector(GBT_data_word_bitdepth-1 downto 0)) return std_logic_vector; + function func_FITDATAHD_orbit (header_w : std_logic_vector(GBT_data_word_bitdepth-1 downto 0)) return std_logic_vector; + function func_FITDATAHD_bc (header_w : std_logic_vector(GBT_data_word_bitdepth-1 downto 0)) return std_logic_vector; -- ---------------------------------------------------------------- -- Control Register addres reg ------------------------------------ -function func_CNTRREG_getaddrreg (cntrl_reg: CONTROL_REGISTER_type ) return cntr_reg_addrreg_type; -function func_CNTRREG_getcntrreg (cntrl_reg_addrreg: cntr_reg_addrreg_type) return CONTROL_REGISTER_type; -function func_STATREG_getaddrreg (status_reg: FIT_GBT_status_type ) return status_reg_addrreg_type; -function func_STATREG_getaddrreg_sim (status_reg: FIT_GBT_status_type ) return status_reg_addrreg_sim_type; + function func_CNTRREG_getcntrreg (cntrl_reg_addrreg : ctrl_reg_t) return readout_control_t; + function func_STATREG_getaddrreg (status_reg : readout_status_t) return stat_reg_t; + function func_STATREG_getaddrreg_sim (status_reg : readout_status_t) return stat_reg_sim_t; -- ---------------------------------------------------------------- - - - - --- ######################################################################### - end fit_gbt_common_package; @@ -399,420 +353,212 @@ package body fit_gbt_common_package is -- ###################### CONVERSION FUNCTION ############################## - - -- FIT data header, formed in converter --------------------------- -function func_FITDATAHD_get_header -( - channel_n_words: std_logic_vector(n_pckt_wrds_bitdepth-1 downto 0); - ORBIT : std_logic_vector(Orbit_id_bitdepth-1 downto 0); - BCID : std_logic_vector(BC_id_bitdepth-1 downto 0); - rx_phase : std_logic_vector(rx_phase_bitdepth-1 downto 0); - rx_phase_error : std_logic; - is_tcm : std_logic -) -return std_logic_vector is - -begin - --return channel_n_words & x"000_0000" & ORBIT & BCID; - return x"F"&channel_n_words(3 downto 0) & x"000_00" & "000" & is_tcm & rx_phase_error & rx_phase & ORBIT & BCID; - -end function; - - - -function func_FITDATAHD_ndwords (header_w: std_logic_vector(fifo_data_bitdepth-1 downto 0) ) return std_logic_vector is -begin return x"0"&header_w(fifo_data_bitdepth-1-4 downto fifo_data_bitdepth-n_pckt_wrds_bitdepth); end function; - -function func_FITDATAHD_orbit (header_w: std_logic_vector(fifo_data_bitdepth-1 downto 0) ) return std_logic_vector is -begin return header_w(BC_id_bitdepth+Orbit_id_bitdepth-1 downto BC_id_bitdepth); end function; - -function func_FITDATAHD_bc (header_w: std_logic_vector(fifo_data_bitdepth-1 downto 0) ) return std_logic_vector is -begin return header_w(BC_id_bitdepth-1 downto 0); end function; + function func_FITDATAHD_get_header + ( + channel_n_words : std_logic_vector(n_pckt_wrds_bitdepth-1 downto 0); + ORBIT : std_logic_vector(Orbit_id_bitdepth-1 downto 0); + BCID : std_logic_vector(BC_id_bitdepth-1 downto 0); + rx_phase : std_logic_vector(rx_phase_bitdepth-1 downto 0); + rx_phase_error : std_logic; + is_tcm : std_logic + ) + return std_logic_vector is + + begin + return x"F"&channel_n_words(3 downto 0) & x"000_00" & "000" & is_tcm & rx_phase_error & rx_phase & ORBIT & BCID; + + end function; + + function func_FITDATAHD_ndwords (header_w : std_logic_vector(GBT_data_word_bitdepth-1 downto 0)) return std_logic_vector is + begin return x"0"&header_w(GBT_data_word_bitdepth-1-4 downto GBT_data_word_bitdepth-n_pckt_wrds_bitdepth); end function; + + function func_FITDATAHD_orbit (header_w : std_logic_vector(GBT_data_word_bitdepth-1 downto 0)) return std_logic_vector is + begin return header_w(BC_id_bitdepth+Orbit_id_bitdepth-1 downto BC_id_bitdepth); end function; + + function func_FITDATAHD_bc (header_w : std_logic_vector(GBT_data_word_bitdepth-1 downto 0)) return std_logic_vector is + begin return header_w(BC_id_bitdepth-1 downto 0); end function; -- ---------------------------------------------------------------- + function func_CNTRREG_getcntrreg (cntrl_reg_addrreg : ctrl_reg_t) return readout_control_t is + variable cntr_reg : readout_control_t; + begin + if(cntrl_reg_addrreg(0)(3 downto 0) = x"0") then + cntr_reg.Data_Gen.usage_generator := gen_off; + elsif(cntrl_reg_addrreg(0)(3 downto 0) = x"1") then + cntr_reg.Data_Gen.usage_generator := data_gen_on; + elsif(cntrl_reg_addrreg(0)(3 downto 0) = x"2") then + cntr_reg.Data_Gen.usage_generator := gen_tx_out; + else + cntr_reg.Data_Gen.usage_generator := gen_off; + end if; --- Control word for FIT packet ------------------------------------ -function func_CNTPCKword_get_word -( - is_close_frame : std_logic; - pages_counter : std_logic_vector(RDH_pages_counter_bitdepth-1 downto 0); - n_words_in_packet : std_logic_vector(GEN_count_bitdepth-1 downto 0); - TRIGGER: std_logic_vector(Trigger_bitdepth-1 downto 0); - TRG_ORBIT : std_logic_vector(Orbit_id_bitdepth-1 downto 0); - TRG_BCID : std_logic_vector(BC_id_bitdepth-1 downto 0); - HB_ORBIT : std_logic_vector(Orbit_id_bitdepth-1 downto 0); - HB_BCID : std_logic_vector(BC_id_bitdepth-1 downto 0) -) -return std_logic_vector is - -begin - return "0000000" & is_close_frame & pages_counter & n_words_in_packet & TRIGGER & TRG_ORBIT & TRG_BCID & HB_ORBIT & HB_BCID; -end function; - - - -function func_CNTPCKword_isclf (cntpck_w: std_logic_vector(cntpckfifo_data_bitdepth-1 downto 0) ) return std_logic is -begin return cntpck_w(cntpckfifo_data_bitdepth-8); end function; - -function func_CNTPCKword_npwords (cntpck_w: std_logic_vector(cntpckfifo_data_bitdepth-1 downto 0) ) return std_logic_vector is -begin return cntpck_w(BC_id_bitdepth+Orbit_id_bitdepth+Trigger_bitdepth+GEN_count_bitdepth+BC_id_bitdepth+Orbit_id_bitdepth-1 downto BC_id_bitdepth+Orbit_id_bitdepth+Trigger_bitdepth+BC_id_bitdepth+Orbit_id_bitdepth); end function; - -function func_CNTPCKword_pgcounter (cntpck_w: std_logic_vector(cntpckfifo_data_bitdepth-1 downto 0) ) return std_logic_vector is -begin return cntpck_w(cntpckfifo_data_bitdepth-8-1 downto cntpckfifo_data_bitdepth-8-RDH_pages_counter_bitdepth); end function; - -function func_CNTPCKword_trigger (cntpck_w: std_logic_vector(cntpckfifo_data_bitdepth-1 downto 0) ) return std_logic_vector is -begin return cntpck_w(BC_id_bitdepth+Orbit_id_bitdepth+Trigger_bitdepth+BC_id_bitdepth+Orbit_id_bitdepth-1 downto BC_id_bitdepth+Orbit_id_bitdepth+BC_id_bitdepth+Orbit_id_bitdepth); end function; - -function func_CNTPCKword_trgorbit (cntpck_w: std_logic_vector(cntpckfifo_data_bitdepth-1 downto 0) ) return std_logic_vector is -begin return cntpck_w(BC_id_bitdepth+Orbit_id_bitdepth+BC_id_bitdepth+Orbit_id_bitdepth-1 downto BC_id_bitdepth+BC_id_bitdepth+Orbit_id_bitdepth); end function; - -function func_CNTPCKword_trgbc (cntpck_w: std_logic_vector(cntpckfifo_data_bitdepth-1 downto 0) ) return std_logic_vector is -begin return cntpck_w(BC_id_bitdepth+BC_id_bitdepth+Orbit_id_bitdepth-1 downto BC_id_bitdepth+Orbit_id_bitdepth); end function; - -function func_CNTPCKword_hborbit (cntpck_w: std_logic_vector(cntpckfifo_data_bitdepth-1 downto 0) ) return std_logic_vector is -begin return cntpck_w(BC_id_bitdepth+Orbit_id_bitdepth-1 downto BC_id_bitdepth); end function; - -function func_CNTPCKword_hbbc (cntpck_w: std_logic_vector(cntpckfifo_data_bitdepth-1 downto 0) ) return std_logic_vector is -begin return cntpck_w(BC_id_bitdepth-1 downto 0); end function; - + if(cntrl_reg_addrreg(0)(7 downto 4) = x"0") then + cntr_reg.Trigger_Gen.usage_generator := gen_off; + elsif(cntrl_reg_addrreg(0)(7 downto 4) = x"1") then + cntr_reg.Trigger_Gen.usage_generator := ltu_emu_on; + elsif(cntrl_reg_addrreg(0)(7 downto 4) = x"2") then + cntr_reg.Trigger_Gen.usage_generator := gen_tx_out; + else + cntr_reg.Trigger_Gen.usage_generator := gen_off; + end if; + + + if(cntrl_reg_addrreg(0)(19 downto 16) = x"0") then + cntr_reg.Trigger_Gen.Readout_command := idle; + elsif(cntrl_reg_addrreg(0)(19 downto 16) = x"1") then + cntr_reg.Trigger_Gen.Readout_command := continious; + elsif(cntrl_reg_addrreg(0)(19 downto 16) = x"2") then + cntr_reg.Trigger_Gen.Readout_command := trigger; + else + cntr_reg.Trigger_Gen.Readout_command := idle; + end if; + + + cntr_reg.reset_orbc_sync := cntrl_reg_addrreg(0)(8); + cntr_reg.reset_data_counters := cntrl_reg_addrreg(0)(9); + cntr_reg.reset_gensync := cntrl_reg_addrreg(0)(10); + cntr_reg.reset_gbt_rxerror := cntrl_reg_addrreg(0)(11); + cntr_reg.reset_gbt := cntrl_reg_addrreg(0)(12); + cntr_reg.reset_rxph_error := cntrl_reg_addrreg(0)(13); + cntr_reg.reset_readout := cntrl_reg_addrreg(0)(14); + cntr_reg.reset_err_report := cntrl_reg_addrreg(0)(15); + + + + cntr_reg.is_hb_response := cntrl_reg_addrreg(0)(20); + cntr_reg.readout_bypass := cntrl_reg_addrreg(0)(21); + cntr_reg.force_idle := cntrl_reg_addrreg(0)(22); + cntr_reg.is_hb_reject := cntrl_reg_addrreg(0)(23); + cntr_reg.rxclk_sync_shift := cntrl_reg_addrreg(0)(24); + cntr_reg.Data_Gen.orbit_jump := cntrl_reg_addrreg(0)(25); + cntr_reg.errrep_slost_allgbtw := cntrl_reg_addrreg(0)(26); + -- reg [0](27 - 31) is empty + + cntr_reg.Data_Gen.trigger_resp_mask := cntrl_reg_addrreg(1); + cntr_reg.Data_Gen.bunch_pattern := cntrl_reg_addrreg(2); + -- reg3 is empty + cntr_reg.Trigger_Gen.trigger_pattern(31 downto 0) := cntrl_reg_addrreg(4); + cntr_reg.Trigger_Gen.trigger_pattern(63 downto 32) := cntrl_reg_addrreg(5); + cntr_reg.Trigger_Gen.trigger_cont_value := cntrl_reg_addrreg(6); + + cntr_reg.Data_Gen.bunch_freq := cntrl_reg_addrreg(7)(15 downto 0); + cntr_reg.Trigger_Gen.bunch_freq := cntrl_reg_addrreg(7)(31 downto 16); + + cntr_reg.Data_Gen.bc_start := cntrl_reg_addrreg(8)(11 downto 0); + cntr_reg.Trigger_Gen.bc_start := cntrl_reg_addrreg(8)(27 downto 16); + cntr_reg.Trigger_Gen.hbr_rate := cntrl_reg_addrreg(8)(31 downto 28); + + cntr_reg.RDH_data.FEE_ID := cntrl_reg_addrreg(9)(15 downto 0); + cntr_reg.RDH_data.SYS_ID := cntrl_reg_addrreg(9)(23 downto 16); + cntr_reg.RDH_data.PRT_BIT := cntrl_reg_addrreg(9)(31 downto 24); + -- reg 10 is empty + cntr_reg.BCID_offset := cntrl_reg_addrreg(11)(11 downto 0); + cntr_reg.trg_data_select := cntrl_reg_addrreg(12)(31 downto 0); + + return cntr_reg; + end function; + + + + + + function func_STATREG_getaddrreg (status_reg : readout_status_t) return stat_reg_t is + variable status_reg_addrreg : stat_reg_t; + variable gbt_status : std_logic_vector(15 downto 0); + variable bcid_sync_mode : std_logic_vector(3 downto 0); + variable rd_mode : std_logic_vector(3 downto 0); + variable cru_rd_mode : std_logic_vector(3 downto 0); + + begin + + + gbt_status := "000000" + & status_reg.GBT_status.gbt_not_ready -- 9 + & status_reg.Rx_Phase_error -- 8 + & status_reg.GBT_status.gbtRx_ErrorLatch -- 7 + & status_reg.GBT_status.gbt_was_ready -- 6 + & status_reg.GBT_status.tx_fsmResetDone -- 5 + & status_reg.GBT_status.tx_resetDone -- 4 + & status_reg.GBT_status.mgtLinkReady -- 3 + & status_reg.GBT_status.rxFrameClkReady -- 2 + & status_reg.GBT_status.rxWordClkReady -- 1 + & status_reg.GBT_status.mgt_phalin_cplllock; -- 0 + + + if status_reg.Readout_Mode = mode_IDLE then + rd_mode := x"0"; + elsif status_reg.Readout_Mode = mode_CNT then + rd_mode := x"1"; + elsif status_reg.Readout_Mode = mode_TRG then + rd_mode := x"2"; + else + rd_mode := x"f"; + end if; + + if status_reg.CRU_Readout_Mode = mode_IDLE then + cru_rd_mode := x"0"; + elsif status_reg.CRU_Readout_Mode = mode_CNT then + cru_rd_mode := x"1"; + elsif status_reg.CRU_Readout_Mode = mode_TRG then + cru_rd_mode := x"2"; + else + cru_rd_mode := x"f"; + end if; + + if status_reg.BCIDsync_Mode = mode_STR then + bcid_sync_mode := x"0"; + elsif status_reg.BCIDsync_Mode = mode_SYNC then + bcid_sync_mode := x"1"; + elsif status_reg.BCIDsync_Mode = mode_LOST then + bcid_sync_mode := x"2"; + else + bcid_sync_mode := x"f"; + end if; + + + + status_reg_addrreg(0) := cru_rd_mode & "0"&status_reg.rx_phase & bcid_sync_mode & rd_mode & gbt_status; + status_reg_addrreg(1) := status_reg.ORBIT_from_CRU; + status_reg_addrreg(2) := status_reg.fsm_errors & status_reg.bcsync_lost_cnt & status_reg.fifos_empty; + status_reg_addrreg(3) := status_reg.cnv_fifo_max & status_reg.cnv_drop_cnt; + status_reg_addrreg(4) := status_reg.sel_fifo_max & status_reg.sel_drop_cnt; + status_reg_addrreg(5) := status_reg.gbt_data_cnt; + status_reg_addrreg(6) := status_reg.bcind_trg.count & status_reg.bcind_trg.bc & status_reg.bcind_evt.count & status_reg.bcind_evt.bc; + status_reg_addrreg(7) := status_reg.ipbusrd_fifo_cnt & x"0000"; + status_reg_addrreg(ipbusrd_fifo_out_addr) := status_reg.ipbusrd_fifo_out; --8 + status_reg_addrreg(9) := status_reg.event_counter; + status_reg_addrreg(10) := status_reg.ipbusrd_err_report; + + return status_reg_addrreg; + end function; + + function func_STATREG_getaddrreg_sim (status_reg : readout_status_t) return stat_reg_sim_t is + variable status_reg_addrreg : stat_reg_t; + variable status_reg_addrreg_sim : stat_reg_sim_t; + + begin + status_reg_addrreg := func_STATREG_getaddrreg(status_reg); + for i in 0 to stat_reg_size-1 loop + status_reg_addrreg_sim(i) := status_reg_addrreg(i); + end loop; + + status_reg_addrreg_sim(stat_reg_size) := status_reg.ORBIT_from_CRU_corrected; + status_reg_addrreg_sim(stat_reg_size+1) := x"0" & status_reg.BCID_from_CRU & x"0" & status_reg.BCID_from_CRU_corrected; + status_reg_addrreg_sim(stat_reg_size+2) := status_reg.Trigger_from_CRU; + status_reg_addrreg_sim(stat_reg_size+3) := status_reg.datagen_report.orbit; + status_reg_addrreg_sim(stat_reg_size+4) := x"0" & "000"&status_reg.data_enable & status_reg.datagen_report.size & x"0" & status_reg.datagen_report.bc; + status_reg_addrreg_sim(stat_reg_size+5) := status_reg.datagen_report.packet_num(31 downto 0); + --packet_num + return status_reg_addrreg_sim; + end function; -- ---------------------------------------------------------------- - - - - - - - - - - --- Control Register addres reg ------------------------------------ -function func_CNTRREG_getaddrreg (cntrl_reg: CONTROL_REGISTER_type ) return cntr_reg_addrreg_type is - - variable cntr_reg_addrreg : cntr_reg_addrreg_type; - variable data_gen_cntr : std_logic_vector( 3 downto 0 ); - variable trg_gen_cntr : std_logic_vector( 3 downto 0 ); - variable start_rd_command : std_logic_vector( 3 downto 0 ); - variable reset_contr :std_logic_vector( 7 downto 0); - - -begin - - if cntrl_reg.Data_Gen.usage_generator = use_NO_generator then - data_gen_cntr := x"0"; - elsif cntrl_reg.Data_Gen.usage_generator = use_MAIN_generator then - data_gen_cntr := x"1"; - elsif cntrl_reg.Data_Gen.usage_generator = use_TX_generator then - data_gen_cntr := x"2"; - else - data_gen_cntr := x"f"; - end if; - - if cntrl_reg.Trigger_Gen.Readout_command = idle then - start_rd_command := x"0"; - elsif cntrl_reg.Trigger_Gen.Readout_command = continious then - start_rd_command := x"1"; - elsif cntrl_reg.Trigger_Gen.Readout_command = trigger then - start_rd_command := x"2"; - else - start_rd_command := x"f"; - end if; - - if cntrl_reg.Trigger_Gen.usage_generator = use_NO_generator then - trg_gen_cntr := x"0"; - elsif cntrl_reg.Trigger_Gen.usage_generator = use_CONT_generator then - trg_gen_cntr := x"1"; - elsif cntrl_reg.Trigger_Gen.usage_generator = use_TX_generator then - trg_gen_cntr := x"2"; - else - trg_gen_cntr := x"f"; - end if; - - - reset_contr := "00" & cntrl_reg.reset_rxph_error & cntrl_reg.reset_gbt & cntrl_reg.reset_gbt_rxerror & cntrl_reg.reset_gen_offset & cntrl_reg.reset_drophit_counter & cntrl_reg.reset_orbc_synd; - - - -cntr_reg_addrreg(0) := x"00" & "0"&cntrl_reg.strt_rdmode_lock&cntrl_reg.readout_bypass&cntrl_reg.is_hb_response & start_rd_command & reset_contr & trg_gen_cntr & data_gen_cntr; - -cntr_reg_addrreg(1) := cntrl_reg.Data_Gen.trigger_resp_mask; -cntr_reg_addrreg(2) := cntrl_reg.Data_Gen.bunch_pattern; -cntr_reg_addrreg(3) := cntrl_reg.Trigger_Gen.trigger_single_val; -cntr_reg_addrreg(4) := cntrl_reg.Trigger_Gen.trigger_pattern(63 downto 32); -cntr_reg_addrreg(5) := cntrl_reg.Trigger_Gen.trigger_pattern(31 downto 0); -cntr_reg_addrreg(6) := cntrl_reg.Trigger_Gen.trigger_cont_value; -cntr_reg_addrreg(7) := cntrl_reg.Trigger_Gen.bunch_freq & cntrl_reg.Data_Gen.bunch_freq; -cntr_reg_addrreg(8) := x"0"&cntrl_reg.Trigger_Gen.bunch_freq_hboffset & x"0"&cntrl_reg.Data_Gen.bunch_freq_hboffset; - -cntr_reg_addrreg(9) := cntrl_reg.RDH_data.FEE_ID & cntrl_reg.RDH_data.PAR; -cntr_reg_addrreg(10) := cntrl_reg.max_data_payload & cntrl_reg.RDH_data.DET_Field; - -cntr_reg_addrreg(11) := x"0"&cntrl_reg.crutrg_delay_comp & x"0"&cntrl_reg.n_BCID_delay; -cntr_reg_addrreg(12) := cntrl_reg.trg_data_select; - -return cntr_reg_addrreg; - -end function; - - - - - -function func_CNTRREG_getcntrreg (cntrl_reg_addrreg: cntr_reg_addrreg_type) return CONTROL_REGISTER_type is - -variable cntr_reg : CONTROL_REGISTER_type; - -begin - - if( cntrl_reg_addrreg(0)(3 downto 0) = x"0" ) then - cntr_reg.Data_Gen.usage_generator := use_NO_generator; - elsif( cntrl_reg_addrreg(0)(3 downto 0) = x"1" ) then - cntr_reg.Data_Gen.usage_generator := use_MAIN_generator; - elsif( cntrl_reg_addrreg(0)(3 downto 0) = x"2" ) then - cntr_reg.Data_Gen.usage_generator := use_TX_generator; - else - cntr_reg.Data_Gen.usage_generator := use_NO_generator; - end if; - - - - if( cntrl_reg_addrreg(0)(19 downto 16) = x"0" ) then - cntr_reg.Trigger_Gen.Readout_command := idle; - elsif( cntrl_reg_addrreg(0)(19 downto 16) = x"1" ) then - cntr_reg.Trigger_Gen.Readout_command := continious; - elsif( cntrl_reg_addrreg(0)(19 downto 16) = x"2" ) then - cntr_reg.Trigger_Gen.Readout_command := trigger; - else - cntr_reg.Trigger_Gen.Readout_command := idle; - end if; - - - - if( cntrl_reg_addrreg(0)(7 downto 4) = x"0" ) then - cntr_reg.Trigger_Gen.usage_generator := use_NO_generator; - elsif( cntrl_reg_addrreg(0)(7 downto 4) = x"1" ) then - cntr_reg.Trigger_Gen.usage_generator := use_CONT_generator; - elsif( cntrl_reg_addrreg(0)(7 downto 4) = x"2" ) then - cntr_reg.Trigger_Gen.usage_generator := use_TX_generator; - else - cntr_reg.Trigger_Gen.usage_generator := use_NO_generator; - end if; - - cntr_reg.is_hb_response := cntrl_reg_addrreg(0)(20); - cntr_reg.readout_bypass := cntrl_reg_addrreg(0)(21); - cntr_reg.strt_rdmode_lock := cntrl_reg_addrreg(0)(22); - - cntr_reg.reset_orbc_synd := cntrl_reg_addrreg(0)(8); - cntr_reg.reset_drophit_counter := cntrl_reg_addrreg(0)(9); - cntr_reg.reset_gen_offset := cntrl_reg_addrreg(0)(10); - cntr_reg.reset_gbt_rxerror := cntrl_reg_addrreg(0)(11); - cntr_reg.reset_gbt := cntrl_reg_addrreg(0)(12); - cntr_reg.reset_rxph_error := cntrl_reg_addrreg(0)(13); - - - cntr_reg.Data_Gen.trigger_resp_mask := cntrl_reg_addrreg(1); - cntr_reg.Data_Gen.bunch_pattern := cntrl_reg_addrreg(2); - cntr_reg.Trigger_Gen.trigger_single_val := cntrl_reg_addrreg(3); - cntr_reg.Trigger_Gen.trigger_pattern(63 downto 32) := cntrl_reg_addrreg(4); - cntr_reg.Trigger_Gen.trigger_pattern(31 downto 0) := cntrl_reg_addrreg(5); - cntr_reg.Trigger_Gen.trigger_cont_value := cntrl_reg_addrreg(6); - - - cntr_reg.Trigger_Gen.bunch_freq := cntrl_reg_addrreg(7)(31 downto 16); - cntr_reg.Data_Gen.bunch_freq := cntrl_reg_addrreg(7)(15 downto 0); - - cntr_reg.Trigger_Gen.bunch_freq_hboffset := cntrl_reg_addrreg(8)(27 downto 16); - cntr_reg.Data_Gen.bunch_freq_hboffset := cntrl_reg_addrreg(8)(11 downto 0); - - cntr_reg.RDH_data.FEE_ID := cntrl_reg_addrreg(9)(31 downto 16); - cntr_reg.RDH_data.PAR := cntrl_reg_addrreg(9)(15 downto 0); - - cntr_reg.max_data_payload := cntrl_reg_addrreg(10)(31 downto 16); - cntr_reg.RDH_data.DET_Field := cntrl_reg_addrreg(10)(15 downto 0); - - cntr_reg.crutrg_delay_comp := cntrl_reg_addrreg(11)(27 downto 16); - cntr_reg.n_BCID_delay := cntrl_reg_addrreg(11)(11 downto 0); - - cntr_reg.trg_data_select := cntrl_reg_addrreg(12)(31 downto 0); - - return cntr_reg; -end function; - - - - - -function func_STATREG_getaddrreg (status_reg: FIT_GBT_status_type ) return status_reg_addrreg_type is - variable status_reg_addrreg : status_reg_addrreg_type; - variable gbt_status : std_logic_vector(15 downto 0); - variable bcid_sync_mode : std_logic_vector( 3 downto 0 ); - variable rd_mode : std_logic_vector( 3 downto 0 ); - variable cru_rd_mode : std_logic_vector( 3 downto 0 ); - variable slct_fifo_count_reg : std_logic_vector(15 downto 0); - variable raw_fifo_count_reg : std_logic_vector(15 downto 0); - -begin - - - gbt_status := "000000" - & status_reg.GBT_status.Rx_Phase_error - & status_reg.GBT_status.gbtRx_ErrorLatch - & status_reg.GBT_status.gbtRx_ErrorDet - & status_reg.GBT_status.gbtRx_Ready - & status_reg.GBT_status.tx_fsmResetDone - & status_reg.GBT_status.tx_resetDone - & status_reg.GBT_status.mgtLinkReady - & status_reg.GBT_status.rxFrameClkReady - & status_reg.GBT_status.rxWordClkReady - & status_reg.GBT_status.mgt_phalin_cplllock; - - - if status_reg.Readout_Mode = mode_IDLE then - rd_mode := x"0"; - elsif status_reg.Readout_Mode = mode_CNT then - rd_mode := x"1"; - elsif status_reg.Readout_Mode = mode_TRG then - rd_mode := x"2"; - else - rd_mode := x"f"; - end if; - - if status_reg.CRU_Readout_Mode = mode_IDLE then - cru_rd_mode := x"0"; - elsif status_reg.CRU_Readout_Mode = mode_CNT then - cru_rd_mode := x"1"; - elsif status_reg.CRU_Readout_Mode = mode_TRG then - cru_rd_mode := x"2"; - else - cru_rd_mode := x"f"; - end if; - - if status_reg.BCIDsync_Mode = mode_STR then - bcid_sync_mode := x"0"; - elsif status_reg.BCIDsync_Mode = mode_SYNC then - bcid_sync_mode := x"1"; - elsif status_reg.BCIDsync_Mode = mode_LOST then - bcid_sync_mode := x"2"; - else - bcid_sync_mode := x"f"; - end if; - - slct_fifo_count_reg := "000" & status_reg.fifo_status.slct_fifo_count; - raw_fifo_count_reg := "000" & status_reg.fifo_status.raw_fifo_count; - - - status_reg_addrreg(0) := cru_rd_mode & "0"&status_reg.rx_phase & bcid_sync_mode & rd_mode & gbt_status; - status_reg_addrreg(1) := status_reg.ORBIT_from_CRU; - status_reg_addrreg(2) := x"00000" & status_reg.BCID_from_CRU; - status_reg_addrreg(3) := slct_fifo_count_reg & raw_fifo_count_reg; - status_reg_addrreg(4) := status_reg.hits_rd_counter_selector.first_orbit_hdrop; - status_reg_addrreg(5) := status_reg.hits_rd_counter_selector.last_orbit_hdrop; - status_reg_addrreg(6) := status_reg.hits_rd_counter_selector.hits_skipped; - status_reg_addrreg(7) := "000" & status_reg.fifo_status.ftmipbus_fifo_count & status_reg.hits_rd_counter_selector.hits_send_porbit; - - -return status_reg_addrreg; -end function; - - - - - - - - - -function func_STATREG_getaddrreg_sim (status_reg: FIT_GBT_status_type ) return status_reg_addrreg_sim_type is - variable status_reg_addrreg : status_reg_addrreg_sim_type; - variable gbt_status : std_logic_vector(15 downto 0); - variable bcid_sync_mode : std_logic_vector( 3 downto 0 ); - variable rd_mode : std_logic_vector( 3 downto 0 ); - variable cru_rd_mode : std_logic_vector( 3 downto 0 ); - variable slct_fifo_count_reg : std_logic_vector(15 downto 0); - variable raw_fifo_count_reg : std_logic_vector(15 downto 0); - -begin - - - gbt_status := "000000" - & status_reg.GBT_status.Rx_Phase_error - & status_reg.GBT_status.gbtRx_ErrorLatch - & status_reg.GBT_status.gbtRx_ErrorDet - & status_reg.GBT_status.gbtRx_Ready - & status_reg.GBT_status.tx_fsmResetDone - & status_reg.GBT_status.tx_resetDone - & status_reg.GBT_status.mgtLinkReady - & status_reg.GBT_status.rxFrameClkReady - & status_reg.GBT_status.rxWordClkReady - & status_reg.GBT_status.mgt_phalin_cplllock; - - - if status_reg.Readout_Mode = mode_IDLE then - rd_mode := x"0"; - elsif status_reg.Readout_Mode = mode_CNT then - rd_mode := x"1"; - elsif status_reg.Readout_Mode = mode_TRG then - rd_mode := x"2"; - else - rd_mode := x"f"; - end if; - - if status_reg.CRU_Readout_Mode = mode_IDLE then - cru_rd_mode := x"0"; - elsif status_reg.CRU_Readout_Mode = mode_CNT then - cru_rd_mode := x"1"; - elsif status_reg.CRU_Readout_Mode = mode_TRG then - cru_rd_mode := x"2"; - else - cru_rd_mode := x"f"; - end if; - - if status_reg.BCIDsync_Mode = mode_STR then - bcid_sync_mode := x"0"; - elsif status_reg.BCIDsync_Mode = mode_SYNC then - bcid_sync_mode := x"1"; - elsif status_reg.BCIDsync_Mode = mode_LOST then - bcid_sync_mode := x"2"; - else - bcid_sync_mode := x"f"; - end if; - - slct_fifo_count_reg := "000" & status_reg.fifo_status.slct_fifo_count; - raw_fifo_count_reg := "000" & status_reg.fifo_status.raw_fifo_count; - - - status_reg_addrreg(0) := cru_rd_mode & "0"&status_reg.rx_phase & bcid_sync_mode & rd_mode & gbt_status; - status_reg_addrreg(1) := status_reg.ORBIT_from_CRU; - status_reg_addrreg(2) := x"00000" & status_reg.BCID_from_CRU; - status_reg_addrreg(3) := slct_fifo_count_reg & raw_fifo_count_reg; - status_reg_addrreg(4) := status_reg.hits_rd_counter_selector.first_orbit_hdrop; - status_reg_addrreg(5) := status_reg.hits_rd_counter_selector.last_orbit_hdrop; - status_reg_addrreg(6) := status_reg.hits_rd_counter_selector.hits_skipped; - status_reg_addrreg(7) := "000" & status_reg.fifo_status.ftmipbus_fifo_count & status_reg.hits_rd_counter_selector.hits_send_porbit; - - status_reg_addrreg(8) := status_reg.ORBIT_from_CRU_corrected; - status_reg_addrreg(9) := x"00000" & status_reg.BCID_from_CRU_corrected; - status_reg_addrreg(10) := status_reg.Trigger_from_CRU; - status_reg_addrreg(11) := status_reg.Data_gen_report; - - -return status_reg_addrreg; -end function; - - --- ---------------------------------------------------------------- - - - - - -- ######################################################################### end fit_gbt_common_package; diff --git a/firmware/common/gbt-readout/hdl/ltu_rx_decoder.vhd b/firmware/common/gbt-readout/hdl/ltu_rx_decoder.vhd new file mode 100644 index 0000000..5ae046c --- /dev/null +++ b/firmware/common/gbt-readout/hdl/ltu_rx_decoder.vhd @@ -0,0 +1,409 @@ +---------------------------------------------------------------------------------- +-- Company: INR RAS +-- Engineer: Finogeev D. A. dmitry-finogeev@yandex.ru +-- +-- Create Date: 2017 +-- Description: read RX data; read triggers, SOX/EOX command, ORBIT/BCID sync +-- +-- Revision: 06/2021 +---------------------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use ieee.numeric_std.all; +use ieee.std_logic_unsigned.all; + +use work.fit_gbt_common_package.all; + + +entity ltu_rx_decoder is + port ( + FSM_Clocks_I : in rdclocks_t; + + Status_register_I : in readout_status_t; + Control_register_I : in readout_control_t; + + -- RX data @ DataClk, ff in RX sync + RX_Data_I : in std_logic_vector(GBT_data_word_bitdepth-1 downto 0); + RX_IsData_I : in std_logic; -- unused in tests + + ORBC_ID_from_CRU_O : out std_logic_vector(Orbit_id_bitdepth + BC_id_bitdepth-1 downto 0); -- EVENT ID from CRU + ORBC_ID_from_CRU_corrected_O : out std_logic_vector(Orbit_id_bitdepth + BC_id_bitdepth-1 downto 0); -- EVENT ID to PM/TCM + ORBC_ID_from_CRU_sync_O : out std_logic_vector(Orbit_id_bitdepth + BC_id_bitdepth-1 downto 0); -- EVENT ID sync compared for err report + Trigger_O : out std_logic_vector(Trigger_bitdepth-1 downto 0); + trg_match_resp_mask_o : out std_logic; + laser_start_o : out std_logic; + + BCIDsync_Mode_O : out bcid_sync_t; + Readout_Mode_O : out rdmode_t; + CRU_Readout_Mode_O : out rdmode_t; + Start_run_O : out std_logic; + Stop_run_O : out std_logic; + Data_enable_o : out std_logic; + apply_bc_delay_o : out std_logic; + + bcsync_lost_inrun_o : out std_logic; + bcsync_lost_flag_o : out std_logic; + bcsync_lost_cnt_o : out std_logic_vector(7 downto 0); + + bcsyncl_outrun_reset_i : in std_logic; + bcsync_lost_outrun_o : out std_logic + ); +end ltu_rx_decoder; + +architecture Behavioral of ltu_rx_decoder is + + signal post_reset_cnt : integer range 0 to 255 := 0; + + signal cru_orbit, cru_orbit_ff, sync_orbit, sync_orbit_corr : std_logic_vector(Orbit_id_bitdepth - 1 downto 0); + signal cru_bc, cru_bc_ff, sync_bc, sync_bc_corr : std_logic_vector(BC_id_bitdepth-1 downto 0); + signal cru_trigger, cru_trigger_ff : std_logic_vector(Trigger_bitdepth-1 downto 0); + signal cru_is_trg, cru_is_trg_ff, sync_is_trg : boolean; + signal cru_is_trg_bcidsync, cru_is_trg_bcidsync_ff : boolean; + signal cru_is_trg_crurmode, cru_is_trg_crurmode_ff : boolean; + + signal sync_bc_int, bc_delay_int, bc_max_int : natural; + signal bcsync_lost_inrun, bcsync_lost_outrun : std_logic; + signal bcsync_lost_flag : std_logic; + + signal gbt_ready : boolean; + signal run_not_permit, bc_apply_permit : boolean; + signal run_restore_permit : boolean; + signal orbc_sync_mode, orbc_sync_mode_ff : bcid_sync_t; + signal readout_mode, readout_mode_ff : rdmode_t; + signal cru_readout_mode, cru_readout_mode_prev, cru_rd_restore_cmd : rdmode_t; + + signal is_ORB, is_SOC, is_SOT, is_EOC, is_EOT, is_cru_run, is_cru_cnt : boolean; + + -- bc_delay should be changed out of run + signal bc_delay, bc_delay_in, bc_delay_in_ff : std_logic_vector(BC_id_bitdepth-1 downto 0); + type bc_apply_fsm_t is (s0_changed, s1_applied); + signal bc_apply_fsm : bc_apply_fsm_t; + signal apply_bc_delay, apply_bc_delay_ff : std_logic; + signal orbits_stb_counter : std_logic_vector(3 downto 0); -- bc_apply switched after 16 stable (HB in cync) orbits + + signal bc_slost_cnt : std_logic_vector(3 downto 0); -- counts bc sync lost in seque + constant bc_slost_cnt_max : std_logic_vector(3 downto 0) := x"1"; -- max num of wrong event id + signal bc_slost_err_cnt : std_logic_vector(7 downto 0); + + constant data_en_orbit_offset_cnt_max : natural := 1; + signal data_en_orbit_offset_cnt : natural range 0 to 15; + + + + -- attribute mark_debug : string; + -- attribute MARK_DEBUG of orbc_sync_mode : signal is "true"; + -- attribute MARK_DEBUG of orbc_sync_mode_ff : signal is "true"; + -- attribute MARK_DEBUG of bcsync_lost_inrun : signal is "true"; + -- attribute MARK_DEBUG of bcsync_lost_flag : signal is "true"; + -- attribute MARK_DEBUG of bc_slost_err_cnt : signal is "true"; + -- attribute MARK_DEBUG of bcsync_lost_outrun : signal is "true"; + -- attribute MARK_DEBUG of cru_rd_restore_cmd : signal is "true"; + + -- attribute MARK_DEBUG of readout_mode : signal is "true"; + -- attribute MARK_DEBUG of readout_mode_ff : signal is "true"; + -- attribute MARK_DEBUG of cru_readout_mode : signal is "true"; + -- attribute MARK_DEBUG of cru_readout_mode_prev : signal is "true"; + -- attribute MARK_DEBUG of run_not_permit : signal is "true"; + -- attribute MARK_DEBUG of run_restore_permit : signal is "true"; + + -- attribute MARK_DEBUG of is_cru_run : signal is "true"; + -- attribute MARK_DEBUG of is_cru_cnt : signal is "true"; + -- attribute MARK_DEBUG of is_SOC : signal is "true"; + -- attribute MARK_DEBUG of is_SOT : signal is "true"; + -- attribute MARK_DEBUG of is_EOC : signal is "true"; + -- attribute MARK_DEBUG of is_EOT : signal is "true"; + + -- attribute MARK_DEBUG of bc_apply_permit : signal is "true"; + -- attribute MARK_DEBUG of bc_apply_fsm : signal is "true"; + -- attribute MARK_DEBUG of apply_bc_delay : signal is "true"; + -- attribute MARK_DEBUG of bc_delay_in : signal is "true"; + -- attribute MARK_DEBUG of bc_delay : signal is "true"; + + -- attribute MARK_DEBUG of cru_orbit : signal is "true"; + -- attribute MARK_DEBUG of cru_bc : signal is "true"; + -- attribute MARK_DEBUG of cru_trigger : signal is "true"; + -- attribute MARK_DEBUG of cru_is_trg : signal is "true"; + -- attribute MARK_DEBUG of cru_is_trg_bcidsync : signal is "true"; + -- attribute MARK_DEBUG of cru_is_trg_crurmode : signal is "true"; + + -- attribute MARK_DEBUG of sync_orbit : signal is "true"; + -- attribute MARK_DEBUG of sync_bc : signal is "true"; + -- attribute MARK_DEBUG of cru_orbit_ff : signal is "true"; + -- attribute MARK_DEBUG of cru_bc_ff : signal is "true"; + -- attribute MARK_DEBUG of cru_is_trg_bcidsync_ff : signal is "true"; + + +begin + + ORBC_ID_from_CRU_corrected_O <= sync_orbit_corr & sync_bc_corr; + run_not_permit <= (Control_register_I.force_idle = '1') or (orbc_sync_mode /= mode_SYNC) or (bc_apply_fsm /= s1_applied) or((x"04FF" and Status_register_I.fsm_errors) /= x"0000"); + bc_apply_permit <= Status_register_I.fsm_errors(15) = '0' and readout_mode = mode_IDLE; + run_restore_permit <= Status_register_I.fifos_empty(4 downto 0) = "11111"; + + sync_bc_int <= to_integer(unsigned(sync_bc)); + bc_delay_int <= to_integer(unsigned(bc_delay)); + bc_max_int <= to_integer(unsigned(LHC_BCID_max)); + + + +-- Data ff data clk ********************************** + process (FSM_Clocks_I.Data_Clk) + begin + + if(rising_edge(FSM_Clocks_I.Data_Clk))then + + gbt_ready <= Status_register_I.GBT_status.gbtRx_Ready = '1'; + + bc_delay_in <= Control_register_I.BCID_offset; + bc_delay_in_ff <= bc_delay_in; + apply_bc_delay_ff <= apply_bc_delay; + + ORBC_ID_from_CRU_O <= sync_orbit & sync_bc; + ORBC_ID_from_CRU_sync_O <= cru_orbit_ff & cru_bc_ff; + BCIDsync_Mode_O <= orbc_sync_mode; + Readout_Mode_O <= readout_mode; + apply_bc_delay_o <= apply_bc_delay_ff; + bcsync_lost_inrun_o <= bcsync_lost_inrun; + bcsync_lost_flag_o <= bcsync_lost_flag; + bcsync_lost_cnt_o <= bc_slost_err_cnt; + bcsync_lost_outrun_o <= bcsync_lost_outrun; + + cru_orbit <= RX_Data_I(79 downto 48); + cru_bc <= RX_Data_I(43 downto 32); + cru_trigger <= RX_Data_I(31 downto 0); + cru_is_trg <= ((x"FFFF9FFF" and RX_Data_I(31 downto 0)) /= TRG_const_void) and (RX_IsData_I = '1'); + cru_is_trg_bcidsync <= ((x"00000017" and RX_Data_I(31 downto 0)) /= TRG_const_void) and (RX_IsData_I = '1'); -- 0x17 = 0b10111 (Ph, HBr, HB, Orbit) + cru_is_trg_crurmode <= ((x"00000003" and RX_Data_I(31 downto 0)) /= TRG_const_void) and (RX_IsData_I = '1'); -- cru readout mode (HB, Orbit) + + cru_orbit_ff <= cru_orbit; + cru_bc_ff <= cru_bc; + cru_trigger_ff <= cru_trigger; + cru_is_trg_ff <= cru_is_trg; + cru_is_trg_bcidsync_ff <= cru_is_trg_bcidsync; + cru_is_trg_crurmode_ff <= cru_is_trg_crurmode; + + readout_mode_ff <= readout_mode; + orbc_sync_mode_ff <= orbc_sync_mode; -- ila triggering + + if (FSM_Clocks_I.Reset_dclk = '1') then + + post_reset_cnt <= 0; + bc_slost_cnt <= (others => '0'); + + orbc_sync_mode <= mode_STR; + orbc_sync_mode_ff <= mode_STR; + readout_mode <= mode_IDLE; + readout_mode_ff <= mode_IDLE; + cru_readout_mode <= mode_IDLE; + + sync_orbit_corr <= (others => '0'); + sync_bc_corr <= (others => '0'); + bc_delay <= (others => '0') ; + bc_apply_fsm <= s0_changed; + orbits_stb_counter <= (others => '0'); + + bcsync_lost_inrun <= '0'; + bcsync_lost_flag <= '0'; + bc_slost_err_cnt <= (others => '0'); + bcsync_lost_outrun <= '0'; + + else + + if post_reset_cnt < 255 then post_reset_cnt <= post_reset_cnt + 1; end if; + + if readout_mode /= mode_IDLE and readout_mode_ff = mode_IDLE then Start_run_O <= '1'; else Start_run_O <= '0'; end if; + if readout_mode = mode_IDLE and readout_mode_ff /= mode_IDLE then Stop_run_O <= '1'; else Stop_run_O <= '0'; end if; + + if cru_is_trg_ff and (orbc_sync_mode = mode_SYNC) then Trigger_O <= cru_trigger_ff; else Trigger_O <= (others => '0'); end if; + if ((cru_trigger_ff and Control_register_I.Data_Gen.trigger_resp_mask) /= TRG_const_void) and (orbc_sync_mode = mode_SYNC) and cru_is_trg_ff then + trg_match_resp_mask_o <= '1'; else trg_match_resp_mask_o <= '0'; end if; + + if ((cru_trigger_ff and TRG_LASER_STR) /= TRG_const_void) and (orbc_sync_mode = mode_SYNC) and cru_is_trg_ff and gbt_ready then + laser_start_o <= '1'; else laser_start_o <= '0'; end if; + + -- wait time after fsm reset to skip trash + if post_reset_cnt /= 255 then orbc_sync_mode <= mode_STR; + -- syncronize orbc from cru to detector with first trigger + elsif orbc_sync_mode = mode_STR and cru_is_trg_bcidsync then + sync_orbit <= cru_orbit; + sync_bc <= cru_bc; + orbc_sync_mode <= mode_SYNC; + bc_slost_cnt <= (others => '1'); -- next evid after sync must be correct + -- evid from CRU is correct + elsif orbc_sync_mode = mode_SYNC and cru_is_trg_bcidsync_ff and (sync_orbit = cru_orbit_ff) and (sync_bc = cru_bc_ff) then + bc_slost_cnt <= (others => '0'); + -- check syncronisation each trigger (n times before error) + elsif orbc_sync_mode = mode_SYNC and cru_is_trg_bcidsync_ff and ((sync_orbit /= cru_orbit_ff) or (sync_bc /= cru_bc_ff)) and bc_slost_cnt < bc_slost_cnt_max then + bc_slost_cnt <= bc_slost_cnt + 1; + -- sync lost after max counter + elsif orbc_sync_mode = mode_SYNC and cru_is_trg_bcidsync_ff and ((sync_orbit /= cru_orbit_ff) or (sync_bc /= cru_bc_ff)) and bc_slost_cnt = bc_slost_cnt_max then + orbc_sync_mode <= mode_LOST; + if readout_mode /= mode_IDLE then bcsync_lost_inrun <= '1'; else bcsync_lost_outrun <= '1'; end if; + end if; + + -- flag for error report + if orbc_sync_mode = mode_SYNC and cru_is_trg_bcidsync_ff and ((sync_orbit /= cru_orbit_ff) or (sync_bc /= cru_bc_ff)) then + if readout_mode /= mode_IDLE then bcsync_lost_flag <= '1'; end if; + bc_slost_err_cnt <= bc_slost_err_cnt + 1; + else + bcsync_lost_flag <= '0'; + end if; + + -- incrementing sync counter then sync + if orbc_sync_mode = mode_SYNC then + if sync_bc < LHC_BCID_max then sync_bc <= sync_bc + 1; + else sync_bc <= (others => '0'); sync_orbit <= sync_orbit + 1; end if; + if bcsyncl_outrun_reset_i = '1' then bcsync_lost_outrun <= '0'; end if; + end if; + + -- orbc resync out of run + if (orbc_sync_mode = mode_LOST) and (readout_mode = mode_IDLE) then orbc_sync_mode <= mode_STR; + -- orbc resync by command + elsif (Control_register_I.reset_orbc_sync = '1') then orbc_sync_mode <= mode_STR; bc_slost_err_cnt <= (others => '0'); end if; + + -- CRU readout mode (get value for 1 cycle next to BC trigger) + if (not is_cru_run) then cru_readout_mode <= mode_IDLE; + elsif is_cru_cnt then cru_readout_mode <= mode_CNT; + else cru_readout_mode <= mode_TRG; end if; + + -- CRU readout mode prev, latch previous value while BC trigger, reset by EOx + if cru_is_trg_crurmode_ff then + if is_EOC or is_EOT then + cru_readout_mode_prev <= mode_IDLE; + CRU_Readout_Mode_O <= mode_IDLE; + else + cru_readout_mode_prev <= cru_readout_mode; + CRU_Readout_Mode_O <= cru_readout_mode; + end if; + end if; + + -- XOR FSM + if run_not_permit then readout_mode <= mode_IDLE; + elsif (readout_mode = mode_IDLE) and is_SOC then readout_mode <= mode_CNT; + elsif (readout_mode = mode_CNT) and is_EOC then readout_mode <= mode_IDLE; + elsif (readout_mode = mode_IDLE) and is_SOT then readout_mode <= mode_TRG; + elsif (readout_mode = mode_TRG) and is_EOT then readout_mode <= mode_IDLE; + elsif (readout_mode = mode_IDLE) and cru_rd_restore_cmd /= mode_IDLE then readout_mode <= cru_rd_restore_cmd; + end if; + + + -- evid corrected + if (sync_bc_int + bc_delay_int) <= bc_max_int then + sync_bc_corr <= (sync_bc + bc_delay); + sync_orbit_corr <= sync_orbit; + else + sync_bc_corr <= sync_bc + bc_delay - LHC_BCID_max - 1; + sync_orbit_corr <= sync_orbit + 1; + end if; + + -- data enabled since n orbit + if (readout_mode = mode_IDLE) then + data_en_orbit_offset_cnt <= 0; + Data_enable_o <= '0'; + elsif is_ORB and (readout_mode /= mode_IDLE) then + + if data_en_orbit_offset_cnt < data_en_orbit_offset_cnt_max then + data_en_orbit_offset_cnt <= data_en_orbit_offset_cnt + 1; + else + data_en_orbit_offset_cnt <= data_en_orbit_offset_cnt_max; + Data_enable_o <= '1'; + end if; + + end if; + + -- BC delay is applied only when out of run and with sync + if bc_apply_fsm = s1_applied and bc_apply_permit and ((bc_delay_in /= bc_delay) or (orbc_sync_mode = mode_STR)) then + bc_apply_fsm <= s0_changed; + orbits_stb_counter <= (others => '0'); + apply_bc_delay <= '0'; + elsif bc_apply_fsm = s0_changed and (orbits_stb_counter = x"F") then + bc_apply_fsm <= s1_applied; + bc_delay <= bc_delay_in; + apply_bc_delay <= '1'; + else + apply_bc_delay <= '0'; + end if; + + -- counting orbits while stable sync + if is_ORB and (orbc_sync_mode = mode_SYNC) and (bc_apply_fsm = s0_changed) and orbits_stb_counter /= x"F" then + orbits_stb_counter <= orbits_stb_counter+1; + elsif (orbc_sync_mode /= mode_SYNC) then + orbits_stb_counter <= (others => '0'); + end if; + + + end if; + end if; + + end process; +-- *************************************************** + + is_ORB <= ((cru_trigger and TRG_const_Orbit) /= TRG_const_void) and cru_is_trg; + is_SOC <= ((cru_trigger and TRG_const_SOC) /= TRG_const_void) and cru_is_trg; + is_SOT <= ((cru_trigger and TRG_const_SOT) /= TRG_const_void) and cru_is_trg; + is_EOC <= ((cru_trigger_ff and TRG_const_EOC) /= TRG_const_void) and cru_is_trg_ff; + is_EOT <= ((cru_trigger_ff and TRG_const_EOT) /= TRG_const_void) and cru_is_trg_ff; + is_cru_run <= ((cru_trigger and TRG_const_RS) /= TRG_const_void) and cru_is_trg_crurmode; + is_cru_cnt <= ((cru_trigger and TRG_const_RT) /= TRG_const_void) and cru_is_trg_crurmode; + + -- restoring run by CRU RUN status. If CRU currently run and prev BC was run -> restore readout if fifos are empty + cru_rd_restore_cmd <= cru_readout_mode when cru_readout_mode = cru_readout_mode_prev and run_restore_permit else mode_IDLE; + + end Behavioral; + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/firmware/common/gbt-readout/hdl/snapshot_fifo.vhd b/firmware/common/gbt-readout/hdl/snapshot_fifo.vhd new file mode 100644 index 0000000..78445d7 --- /dev/null +++ b/firmware/common/gbt-readout/hdl/snapshot_fifo.vhd @@ -0,0 +1,146 @@ +---------------------------------------------------------------------------------- +-- Company: INR RAS +-- Engineer: Finogeev D. A. dmitry-finogeev@yandex.ru +-- +-- Create Date: 07/2022 +-- Description: writes register n*32 to clk1. registers are read by clk2 with bus width 32 bits +-- +-- Revision: 07/2021 +---------------------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use ieee.numeric_std.all; +use ieee.std_logic_unsigned.all; + +entity snapshot_fifo is + + generic ( + n32_size : integer := 5 + ); + + port ( + wr_clk_i : in std_logic; + rd_clk_i : in std_logic; + asreset_i : in std_logic; + + di_i : in std_logic_vector(n32_size*32-1 downto 0); + do_o : out std_logic_vector(31 downto 0); + empty_o : out std_logic; + + wren_i : in std_logic; + rden_i : in std_logic + ); +end snapshot_fifo; + +architecture Behavioral of snapshot_fifo is + + signal reset_wclk, reset_rclk : std_logic; + + signal ireg_wrclk, ireg_rdclk : std_logic_vector(n32_size*32-1 downto 0); + + signal is_empty_wrclk, is_empty_rdclk : boolean; + signal end_reached_rdclk, end_reached_wrclk : boolean; + signal rd_cnt : integer range 0 to n32_size-1 := 0; + + -- attribute mark_debug : string; + -- attribute mark_debug of ireg_wrclk : signal is "true"; + -- attribute mark_debug of ireg_rdclk : signal is "true"; + -- attribute mark_debug of is_empty_wrclk : signal is "true"; + -- attribute mark_debug of is_empty_rdclk : signal is "true"; + -- attribute mark_debug of end_reached_rdclk : signal is "true"; + -- attribute mark_debug of end_reached_wrclk : signal is "true"; + -- attribute mark_debug of rd_cnt : signal is "true"; + + +begin + +-- reset write clock + process (wr_clk_i, asreset_i) + begin + if(asreset_i = '1') then reset_wclk <= '1'; end if; + if(rising_edge(wr_clk_i))then + if (reset_wclk = '1' and asreset_i = '0') then reset_wclk <= '0'; end if; + end if; + end process; + +-- reset read clock + process (rd_clk_i, asreset_i) + begin + if(asreset_i = '1') then reset_rclk <= '1'; end if; + if(rising_edge(rd_clk_i))then + if (reset_rclk = '1' and asreset_i = '0') then reset_rclk <= '0'; end if; + end if; + end process; + + + +-- writing to reg -------------------------------- + process (wr_clk_i) + begin + + if(rising_edge(wr_clk_i))then + + end_reached_wrclk <= end_reached_rdclk; + + if (reset_wclk = '1') then + + ireg_wrclk <= (others => '0'); + is_empty_wrclk <= true; + + else + + if wren_i = '1' and is_empty_wrclk then + ireg_wrclk <= di_i; + is_empty_wrclk <= false; + elsif end_reached_wrclk then + is_empty_wrclk <= true; + end if; + + + end if; + + end if; + + end process; + +-- not is_empty_wrclk -> rd_cnt=n32_size-1 -> end_reached -> is_empty<=true + +-- reading from reg ------------------------------ + process (rd_clk_i) + begin + + if(rising_edge(rd_clk_i))then + + is_empty_rdclk <= is_empty_wrclk; + ireg_rdclk <= ireg_wrclk; + + if (reset_rclk = '1') then + + rd_cnt <= 0; + end_reached_rdclk <= false; + + else + + if rden_i = '1' and not is_empty_rdclk then + if rd_cnt /= n32_size-1 then rd_cnt <= rd_cnt+1; + else end_reached_rdclk <= true; end if; + elsif is_empty_rdclk then + end_reached_rdclk <= false; + rd_cnt <= 0; + end if; + + end if; + + end if; + + end process; + + + do_o <= (others => '0') when end_reached_rdclk or is_empty_rdclk else ireg_rdclk(rd_cnt*32 + 31 downto rd_cnt*32); + empty_o <= '1' when end_reached_rdclk or is_empty_rdclk else '0'; + + + +end Behavioral; + diff --git a/firmware/common/gbt-readout/sim/main_signals.wcfg b/firmware/common/gbt-readout/sim/main_signals.wcfg index c3ad624..02f996f 100644 --- a/firmware/common/gbt-readout/sim/main_signals.wcfg +++ b/firmware/common/gbt-readout/sim/main_signals.wcfg @@ -13,492 +13,1495 @@ - - - + + + - - + + - - - INPUTS + + + + + + + TESTBENCH label - - FSM_Clocks_signal - FSM_Clocks_signal + + sim_iter_num[63:0] + sim_iter_num[63:0] + UNSIGNEDDECRADIX + + + RESET + RESET + + + DATA_CLK + DATA_CLK + + + SYS_CLK + SYS_CLK - - SysClk_count_O[3:0] - SysClk_count_O[3:0] + + RX_CLK + RX_CLK - + + IsRxData_rxclk_from_GBT_sim + IsRxData_rxclk_from_GBT_sim + + + .System_Counter[3:0] + .System_Counter[3:0] + + Control_register_from_file[0:12][31:0] Control_register_from_file[0:12][31:0] - + testbench_CONTROL_REG_dynamic testbench_CONTROL_REG_dynamic - + + .Data_Gen .Data_Gen - - + .Trigger_Gen .Trigger_Gen + - + .RDH_data .RDH_data - + .readout_bypass .readout_bypass - + .is_hb_response .is_hb_response - - .trg_data_select[31:0] - .trg_data_select[31:0] + + .is_hb_reject + .is_hb_reject + + + .rxclk_sync_shift + .rxclk_sync_shift - - .n_BCID_delay[11:0] - .n_BCID_delay[11:0] + + .force_idle + .force_idle - - .crutrg_delay_comp[11:0] - .crutrg_delay_comp[11:0] + + .trg_data_select[31:0] + .trg_data_select[31:0] - - .max_data_payload[15:0] - .max_data_payload[15:0] + + .BCID_offset[11:0] + .BCID_offset[11:0] - - .reset_orbc_synd - .reset_orbc_synd + + .reset_orbc_sync + .reset_orbc_sync - - .reset_drophit_counter - .reset_drophit_counter + + .reset_data_counters + .reset_data_counters - - .reset_gen_offset - .reset_gen_offset + + .reset_gensync + .reset_gensync - + .reset_gbt_rxerror .reset_gbt_rxerror - - .reset_gbt - .reset_gbt - - + .reset_rxph_error .reset_rxph_error - - .strt_rdmode_lock - .strt_rdmode_lock + + .reset_readout + .reset_readout + + + .reset_gbt + .reset_gbt + + + .reset_err_report + .reset_err_report - - Readout_unit - label + + GBT_status + GBT_status + + + + FSM_Clocks + FSM_Clocks + + + ClkSync + label + + .System_Counter[3:0] + .System_Counter[3:0] + + + RX_CLK_I + RX_CLK_I + + + .Data_Clk + .Data_Clk + + + .System_Clk + .System_Clk + + + rx_clk_tg + rx_clk_tg + + + RX_CLK_from00 + RX_CLK_from00 + + + RX_CLK_from01 + RX_CLK_from01 + + + RX_CLK_from02 + RX_CLK_from02 + + + CLK_PH_counter_stop[2:0] + CLK_PH_counter_stop[2:0] + + + c_locked + c_locked + + + CLK_PH_counter_dc[2:0] + CLK_PH_counter_dc[2:0] + + + CLK_PH_counter_dcp[2:0] + CLK_PH_counter_dcp[2:0] + + + CLK_PH_counter_dcm[2:0] + CLK_PH_counter_dcm[2:0] + + + RX_IS_DATA_RXCLK_I + RX_IS_DATA_RXCLK_I + + + RX_IS_DATA_sysclk + RX_IS_DATA_sysclk + + + RX_IS_DATA_to_dclk + RX_IS_DATA_to_dclk + + + RX_IS_DATA_DATACLK_O + RX_IS_DATA_DATACLK_O + + + + RXGENERATOR + label + + .trigger_pattern[63:0] + .trigger_pattern[63:0] + + + .trigger_cont_value[31:0] + .trigger_cont_value[31:0] + #FF00FF + true + + + .bunch_freq[15:0] + .bunch_freq[15:0] + #FF00FF + true + UNSIGNEDDECRADIX + + + .bc_start[11:0] + .bc_start[11:0] + #FF00FF + true + + + hbr_rate[3:0] + hbr_rate[3:0] + + + .reset_gensync + .reset_gensync + #FF00FF + true + + + orbit_jump + orbit_jump + + + orbit_jump_ff + orbit_jump_ff + + + orbit_jump_active + orbit_jump_active + + + orbit_gen[31:0] + orbit_gen[31:0] + #FFD700 + true + + + bc_gen[11:0] + bc_gen[11:0] + #FFD700 + true + HEXRADIX + + + orbit_gen_mod[31:0] + orbit_gen_mod[31:0] + + + run_command + run_command + #00FFFF + true + + + run_state + run_state + #00FFFF + true + + + send_trgcnt + send_trgcnt + #00FFFF + true + + + send_soc + send_soc + #00FFFF + true + + + send_eoc + send_eoc + #00FFFF + true + + + send_sot + send_sot + #00FFFF + true + + + send_eot + send_eot + #00FFFF + true + + + bunch_in_sync + bunch_in_sync + #FFFF00 + true + + + bunch_counter + bunch_counter + #FFFF00 + true + + + hbr_count[3:0] + hbr_count[3:0] + #FFFF00 + true + + + trggen_cnt[31:0] + trggen_cnt[31:0] + + + trggen_sox[31:0] + trggen_sox[31:0] + + + trggen_hb[31:0] + trggen_hb[31:0] + + + trggen_rdstate[31:0] + trggen_rdstate[31:0] + + + rx_data_gen[79:0] + rx_data_gen[79:0] + + + rx_isdata_gen + rx_isdata_gen + + + + RXDECODER + label + + + RX_Data_I[79:0] + RX_Data_I[79:0] + #FAAFBE + true + + + RX_IsData_I + RX_IsData_I + #FAAFBE + true + + + .BCID_offset[11:0] + .BCID_offset[11:0] + HEXRADIX + + + .reset_orbc_sync + .reset_orbc_sync + + + cru_orbit[31:0] + cru_orbit[31:0] + #FFFF00 + true + + + cru_bc[11:0] + cru_bc[11:0] + #FFFF00 + true + + + cru_trigger[31:0] + cru_trigger[31:0] + #FFFF00 + true + + + cru_is_trg + cru_is_trg + #FFFF00 + true + + + cru_orbit_ff[31:0] + cru_orbit_ff[31:0] + #00FF00 + true + + + cru_bc_ff[11:0] + cru_bc_ff[11:0] + #00FF00 + true + + + cru_trigger_ff[31:0] + cru_trigger_ff[31:0] + #00FF00 + true + + + cru_is_trg_ff + cru_is_trg_ff + #00FF00 + true + + + cru_is_trg_ff + cru_is_trg_ff + #00FF00 + true + + + cru_is_trg_crurmode + cru_is_trg_crurmode + + + run_not_permit + run_not_permit + #FF0000 + true + + + run_restore_permit + run_restore_permit + #FF0000 + true + + + readout_mode + readout_mode + #FFA500 + true + + + cru_readout_mode + cru_readout_mode + #FFA500 + true + + + cru_readout_mode_prev + cru_readout_mode_prev + #FFA500 + true + + + cru_rd_restore_cmd + cru_rd_restore_cmd + #FFA500 + true + + + orbc_sync_mode + orbc_sync_mode + #FFA500 + true + + + is_EOC + is_EOC + #FF00FF + true + + + is_EOT + is_EOT + #FF00FF + true + + + is_cru_run + is_cru_run + #FF00FF + true + + + is_cru_cnt + is_cru_cnt + #FF00FF + true + + + sync_orbit[31:0] + sync_orbit[31:0] + #FFD700 + true + + + sync_bc[11:0] + sync_bc[11:0] + #FFD700 + true + + + sync_orbit_corr[31:0] + sync_orbit_corr[31:0] + #FFD700 + true + + + sync_bc_corr[11:0] + sync_bc_corr[11:0] + #FFD700 + true + HEXRADIX + + + ORBC_ID_from_CRU_O[43:0] + ORBC_ID_from_CRU_O[43:0] + #00FFFF + true + + + ORBC_ID_from_CRU_corrected_O[43:0] + ORBC_ID_from_CRU_corrected_O[43:0] + #00FFFF + true + + + Trigger_O[31:0] + Trigger_O[31:0] + #00FFFF + true + + + trg_match_resp_mask_o + trg_match_resp_mask_o + + + BCIDsync_Mode_O + BCIDsync_Mode_O + #00FFFF + true + + + Readout_Mode_O + Readout_Mode_O + #00FFFF + true + + + CRU_Readout_Mode_O + CRU_Readout_Mode_O + #00FFFF + true + + + Start_run_O + Start_run_O + #00FFFF + true + + + Stop_run_O + Stop_run_O + #00FFFF + true + + + Data_enable_o + Data_enable_o + + + bc_apply_fsm + bc_apply_fsm + #FAAFBE + true + + + bc_delay_in[11:0] + bc_delay_in[11:0] + #FAAFBE + true + + + bc_delay[11:0] + bc_delay[11:0] + #FAAFBE + true + + + orbits_stb_counter[3:0] + orbits_stb_counter[3:0] + #FAAFBE + true + + + apply_bc_delay + apply_bc_delay + #FAAFBE + true + + + + DGENERATOR + label + + .BCIDsync_Mode + .BCIDsync_Mode + + + .Trigger_from_CRU[31:0] + .Trigger_from_CRU[31:0] + #FF00FF + true + + + .trigger_resp_mask[31:0] + .trigger_resp_mask[31:0] + #FF00FF + true + + + .BCID_from_CRU[11:0] + .BCID_from_CRU[11:0] + #FF00FF + true + + + .ORBIT_from_CRU[31:0] + .ORBIT_from_CRU[31:0] + #FF00FF + true + + + .bc_start[11:0] + .bc_start[11:0] + #FF00FF + true + + + .BCID_offset[11:0] + .BCID_offset[11:0] + + + .bunch_freq[15:0] + .bunch_freq[15:0] + #FF00FF + true + UNSIGNEDDECRADIX + + + .bunch_pattern[31:0] + .bunch_pattern[31:0] + + + bunch_in_sync + bunch_in_sync + #0000FF + true + + + bunch_counter + bunch_counter + #0000FF + true + + + packet_size_select + packet_size_select + #0000FF + true + + + .System_Counter[3:0] + .System_Counter[3:0] + + + packet_size_select_sc + packet_size_select_sc + #FFD700 + true + + + word_counter + word_counter + #FFD700 + true + + + event_size + event_size + #FFD700 + true + + + event_orbit[31:0] + event_orbit[31:0] + + + event_bc[11:0] + event_bc[11:0] + + + using_generator_sc + using_generator_sc + + + .Readout_Mode + .Readout_Mode + #800000 + true + + + event_orbit_sc[31:0] + event_orbit_sc[31:0] + #800000 + true + + + event_bc_sc[11:0] + event_bc_sc[11:0] + #800000 + true + + + Board_data_header + Board_data_header + #800000 + true + + + data_gen_result + data_gen_result + #800000 + true + + + datagen_report + datagen_report + + + datagen_report_o + datagen_report_o + #800000 + true + + + + Board_data_gen_pipe[0:15] + Board_data_gen_pipe[0:15] + + + Board_data_O + Board_data_O - - Reset_gen - label - - General_reset40_O - General_reset40_O - - - General_reset_O - General_reset_O - - - Reset_DClk_O - Reset_DClk_O - - - Reset_DClk40_O - Reset_DClk40_O - - - GenRes_DataClk_ff - GenRes_DataClk_ff - - - - ClkStrobe - label - - RESET_I - RESET_I - - - RESET40_I - RESET40_I - - - DataClk_I - DataClk_I - - - DataClk_q_dataclk - DataClk_q_dataclk - - - DataClk_qff00_sysclk - DataClk_qff00_sysclk - - - DataClk_front_sysclk - DataClk_front_sysclk - - - Counter_ready_O - Counter_ready_O - - - - TRG_gen - label - - .Readout_command - .Readout_command - - - readout_command_ff - readout_command_ff - - - readout_command_ff1 - readout_command_ff1 - - - rd_trg_send_mode - rd_trg_send_mode - - - is_rd_trg_send - is_rd_trg_send - - - runType_mode[31:0] - runType_mode[31:0] - - - running_mode[31:0] - running_mode[31:0] - - - TRG_readout_command[31:0] - TRG_readout_command[31:0] - - - TRG_result[31:0] - TRG_result[31:0] - - - RX_Data_gen_ff[79:0] - RX_Data_gen_ff[79:0] - - - Current_BCID_from_O[11:0] - Current_BCID_from_O[11:0] - - - Current_ORBIT_from_O[31:0] - Current_ORBIT_from_O[31:0] - - - Current_Trigger_from_O[31:0] - Current_Trigger_from_O[31:0] - - - - RX_decoder - label - - - Trigger_valid_bit - Trigger_valid_bit - - - TRGTYPE_received[31:0] - TRGTYPE_received[31:0] - - - CRU_readout_mode - CRU_readout_mode - - - - data_gen - label - - bunch_pattern[31:0] - bunch_pattern[31:0] - - - bunch_freq[15:0] - bunch_freq[15:0] - - - bunch_freq_hboffset[11:0] - bunch_freq_hboffset[11:0] - - - reset_offset - reset_offset - - - FSM_STATE - FSM_STATE - - - bfreq_counter[15:0] - bfreq_counter[15:0] - - - bpattern_counter - bpattern_counter - - - cnt_packet_counter[79:0] - cnt_packet_counter[79:0] - - - pword_counter[3:0] - pword_counter[3:0] - - - is_boffset_sync - is_boffset_sync - - - is_packet_send_for_cntr_ff - is_packet_send_for_cntr_ff - - - n_words_in_packet_send[3:0] - n_words_in_packet_send[3:0] - - - data_gen_report[31:0] - data_gen_report[31:0] - - - Board_data_gen_ff - Board_data_gen_ff - - - Board_data_O - Board_data_O - - - - converter - label - - Board_data_I - Board_data_I - - - raw_data_fifo_isempty - raw_data_fifo_isempty - - - data_fromfifo[79:0] - data_fromfifo[79:0] - - - is_header_from_fifo - is_header_from_fifo - - - is_data_from_fifo - is_data_from_fifo - - - FIFO_is_space_for_packet_ff - FIFO_is_space_for_packet_ff - - - sending_event - sending_event - - - FIFO_WE_O - FIFO_WE_O - - - FIFO_data_word_O[79:0] - FIFO_data_word_O[79:0] - - - raw_data_fifo_data_fromfifo[79:0] - raw_data_fifo_data_fromfifo[79:0] - - - raw_data_fifo_rden - raw_data_fifo_rden - - - - selector_fifos - label - - RAWFIFO_RE_O - RAWFIFO_RE_O - - - RAWFIFO_data_word_I[79:0] - RAWFIFO_data_word_I[79:0] - - - trgfifo_re - trgfifo_re - - - trgfifo_out_trigger[31:0] - trgfifo_out_trigger[31:0] - - - trgfifo_out_orbit[31:0] - trgfifo_out_orbit[31:0] - - - trgfifo_out_bc[11:0] - trgfifo_out_bc[11:0] - - - is_trg_first_data_late - is_trg_first_data_late - - - is_trg_eq_data - is_trg_eq_data - - - is_trg_late_data_first - is_trg_late_data_first - - - SLCTFIFO_WE_O - SLCTFIFO_WE_O - - - SLCTFIFO_data_word_O[79:0] - SLCTFIFO_data_word_O[79:0] - - - cntpckfifo_we - cntpckfifo_we - - - cntpckfifo_data_toff[159:0] - cntpckfifo_data_toff[159:0] - - - - readout_mode - label - - Readout_Mode_ff00 - Readout_Mode_ff00 - - - Readout_Mode_ff00_syscl - Readout_Mode_ff00_syscl - - - Readout_Mode_ff01 - Readout_Mode_ff01 - - - Readout_Mode_manage - Readout_Mode_manage - - - Readout_Mode_manage_DtClk - Readout_Mode_manage_DtClk - - - Readout_Mode_manage_next - Readout_Mode_manage_next - - - - selector_logic - label - - - FSM_STATE - FSM_STATE - - - rdata_state - rdata_state - - - cntpckws_state - cntpckws_state - - - is_hb_response - is_hb_response - - - is_frame_open - is_frame_open - - - is_sending_packet_ff - is_sending_packet_ff - - - max_data_packet_payload[15:0] - max_data_packet_payload[15:0] - - - wcnt_fullpck_ff[15:0] - wcnt_fullpck_ff[15:0] - - - + + CONVERTER + label + + Board_data_I + Board_data_I + #00FFFF + true + + + data_enabled_sclk + data_enabled_sclk + + + sending_event + sending_event + + + is_header + is_header + #FF00FF + true + + + is_data + is_data + #FF00FF + true + + + header_pcklen_latch[7:0] + header_pcklen_latch[7:0] + #FF0080 + true + + + word_counter[7:0] + word_counter[7:0] + #FF0080 + true + + + header_fifo_din[79:0] + header_fifo_din[79:0] + #00FF00 + true + + + header_fifo_we + header_fifo_we + #00FF00 + true + + + data_fifo_din[79:0] + data_fifo_din[79:0] + #00FF00 + true + + + data_fifo_we + data_fifo_we + #00FF00 + true + + + header_fifo_empty + header_fifo_empty + #00FFFF + true + + + data_fifo_empty + data_fifo_empty + #00FFFF + true + + + data_count[12:0] + data_count[12:0] + #00FFFF + true + + + data_count[12:0] + data_count[12:0] + #00FFFF + true + + + + FIFOs + label + + label + data_count[12:0] + data_count[12:0] + raw_header + STYLE_ANALOG + 100 + UNSIGNEDDECRADIX + + + label + data_count[12:0] + data_count[12:0] + raw_data + STYLE_ANALOG + 100 + UNSIGNEDDECRADIX + + + label + rd_data_count[11:0] + rd_data_count[11:0] + STYLE_ANALOG + 100 + trg_fifo + UNSIGNEDDECRADIX + + + label + rd_data_count[7:0] + rd_data_count[7:0] + cntpck + STYLE_ANALOG + 100 + UNSIGNEDDECRADIX + + + label + wr_data_count[14:0] + wr_data_count[14:0] + slct_data + STYLE_ANALOG + 100 + UNSIGNEDDECRADIX + + + + SELECTOR + label + + send_trg_mode_sc + send_trg_mode_sc + #FFD700 + true + + + header_fifo_data_i[79:0] + header_fifo_data_i[79:0] + #00FFFF + true + + + header_fifo_rden_o + header_fifo_rden_o + #00FFFF + true + + + data_fifo_data_i[79:0] + data_fifo_data_i[79:0] + #00FFFF + true + + + data_fifo_rden_o + data_fifo_rden_o + #00FFFF + true + + + header_fifo_empty_i + header_fifo_empty_i + #00FFFF + true + + + data_ndwords[7:0] + data_ndwords[7:0] + #FFD700 + true + + + data_orbit[31:0] + data_orbit[31:0] + #FFD700 + true + + + data_bc[11:0] + data_bc[11:0] + #FFD700 + true + + + trgfifo_we + trgfifo_we + #FFA500 + true + + + trgfifo_din[75:0] + trgfifo_din[75:0] + #FFA500 + true + + + trgfifo_empty + trgfifo_empty + #FFA500 + true + + + trgfifo_out_trigger[31:0] + trgfifo_out_trigger[31:0] + #FFD700 + true + + + trgfifo_out_orbit[31:0] + trgfifo_out_orbit[31:0] + #FFD700 + true + HEXRADIX + + + trgfifo_out_bc[11:0] + trgfifo_out_bc[11:0] + #FFD700 + true + + + trgfifo_re + trgfifo_re + #FFD700 + true + + + curr_orbit_sc[31:0] + curr_orbit_sc[31:0] + #FFD700 + true + + + curr_bc_sc[11:0] + curr_bc_sc[11:0] + #FFD700 + true + + + is_sox + is_sox + #00FF7F + true + + + is_eox + is_eox + #00FF7F + true + + + is_hbtrg + is_hbtrg + #00FF7F + true + + + is_hb_r_trg + is_hb_r_trg + #00FF7F + true + + + is_sel_trg + is_sel_trg + #00FF7F + true + + + read_data + read_data + #008000 + true + + + read_trigger + read_trigger + #008000 + true + + + rdh_close_cmd + rdh_close_cmd + #00FF7F + true + + + trg_eq_data + trg_eq_data + #00FF7F + true + + + trg_later_data + trg_later_data + #00FF7F + true + + + data_later_trg + data_later_trg + #00FF7F + true + + + send_gear_rdh + send_gear_rdh + + + send_last_rdh + send_last_rdh + + + start_select + start_select + #FF0000 + true + + + select_timeout + select_timeout + + + FSM_STATE + FSM_STATE + #FF0000 + true + + + data_ndwords_cmd[7:0] + data_ndwords_cmd[7:0] + #FF0000 + true + + + is_hbtrg_cmd + is_hbtrg_cmd + #FF0000 + true + + + read_data_cmd + read_data_cmd + #FF0000 + true + + + read_trigger_cmd + read_trigger_cmd + #FF0000 + true + + + rdh_close_cmd + rdh_close_cmd + #FF0000 + true + + + data_reject_cmd + data_reject_cmd + #FF0080 + true + + + dropping_data_cmd + dropping_data_cmd + #FF0000 + true + + + hb_reject_cmd + hb_reject_cmd + #FF0000 + true + + + drop_counter[15:0] + drop_counter[15:0] + #FF0000 + true + + + event_counter[31:0] + event_counter[31:0] + #FF0000 + true + + + rdh_trigger[31:0] + rdh_trigger[31:0] + #00FF7F + true + + + rdh_orbit[31:0] + rdh_orbit[31:0] + #00FF7F + true + + + rdh_bc[11:0] + rdh_bc[11:0] + #00FF7F + true + + + rdh_size_counter + rdh_size_counter + #00FF7F + true + + + rdh_packet_counter + rdh_packet_counter + #00FF7F + true + + + word_counter[7:0] + word_counter[7:0] + #0000FF + true + + + reading_header + reading_header + #0000FF + true + + + reading_last_word + reading_last_word + #0000FF + true + + + slct_fifo_din[79:0] + slct_fifo_din[79:0] + #FFD700 + true + + + slct_fifo_wren + slct_fifo_wren + #FFD700 + true + + + cntpck_fifo_din[127:0] + cntpck_fifo_din[127:0] + #FFD700 + true + + + cntpck_fifo_wren + cntpck_fifo_wren + #FFD700 + true + + + + .fsm_errors[15:0] + .fsm_errors[15:0] + #FF0000 + true + + + RDHGEN + label + + rdh_orbit[31:0] + rdh_orbit[31:0] + #00FFFF + true + + + rdh_bc[11:0] + rdh_bc[11:0] + #00FFFF + true + + + rdh_trg[31:0] + rdh_trg[31:0] + #00FFFF + true + + + rdh_stop[7:0] + rdh_stop[7:0] + #00FFFF + true + + + rdh_pages_counter[15:0] + rdh_pages_counter[15:0] + #00FFFF + true + + + rdh_offset_new_packet[15:0] + rdh_offset_new_packet[15:0] + #00FFFF + true + + + rdh_nwords + rdh_nwords + #00FFFF + true + + + Is_Data_O + Is_Data_O + + + Data_O[79:0] + Data_O[79:0] + + + + ERROR_REPORT + label + + RX_Data_I[79:0] + RX_Data_I[79:0] + + + RX_IsData_I + RX_IsData_I + + + gbt_data_shreg[959:0] + gbt_data_shreg[959:0] + + + .ORBIT_from_CRU[31:0] + .ORBIT_from_CRU[31:0] + + + .BCID_from_CRU[11:0] + .BCID_from_CRU[11:0] + + + .ORBC_from_CRU_sync[43:0] + .ORBC_from_CRU_sync[43:0] + + + report_fifo_o[31:0] + report_fifo_o[31:0] + #FFD700 + true + + + err_report_fifo_rden_i + err_report_fifo_rden_i + #FFD700 + true + + + ireg_wrclk[1151:0] + ireg_wrclk[1151:0] + + + ireg_rdclk[1151:0] + ireg_rdclk[1151:0] + + + is_empty_wrclk + is_empty_wrclk + + + is_empty_rdclk + is_empty_rdclk + + + rd_cnt + rd_cnt + + + end_reached_rdclk + end_reached_rdclk + + + end_reached_wrclk + end_reached_wrclk + + + OUTPUTS label - - sim_iter_num[63:0] - sim_iter_num[63:0] + + GBT_status_reg[0:16][31:0] + GBT_status_reg[0:16][31:0] - - Data_from_FITrd[79:0] - Data_from_FITrd[79:0] + + GBT_status + GBT_status + - - IsData_from_FITrd - IsData_from_FITrd + + Data_from_FITrd_O[79:0] + Data_from_FITrd_O[79:0] - - data_gen_report[31:0] - data_gen_report[31:0] + + IsData_from_FITrd_O + IsData_from_FITrd_O - - FIT_GBT_status_O - FIT_GBT_status_O - + + BCIND_DATA + label + + reset + reset + + + bcid_en + bcid_en + + + bcid_in[11:0] + bcid_in[11:0] + + + bc_value[11:0] + bc_value[11:0] + + + bc_count[3:0] + bc_count[3:0] + + + count_tot[5:0] + count_tot[5:0] + #00FFFF + true + + + count_sel[5:0] + count_sel[5:0] + #00FFFF + true + + + indicator_o + indicator_o + #00FFFF + true + + + + BCIND_TRG + label + + reset + reset + + + bcen_i + bcen_i + + + bcid_i[11:0] + bcid_i[11:0] + + + bcid_en + bcid_en + + + bcid_in[11:0] + bcid_in[11:0] + + + bc_value[11:0] + bc_value[11:0] + + + bc_count[3:0] + bc_count[3:0] + + + count_tot[5:0] + count_tot[5:0] + #00FFFF + true + + + count_sel[5:0] + count_sel[5:0] + #00FFFF + true + + + indicator_o + indicator_o + #00FFFF + true + diff --git a/firmware/common/gbt-readout/sim/readout_simulation.vhd b/firmware/common/gbt-readout/sim/readout_simulation.vhd index 125f704..78176c1 100644 --- a/firmware/common/gbt-readout/sim/readout_simulation.vhd +++ b/firmware/common/gbt-readout/sim/readout_simulation.vhd @@ -26,331 +26,264 @@ -- simulation model. -------------------------------------------------------------------------------- library IEEE; -use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_1164.all; use ieee.numeric_std.all; -use ieee.std_logic_unsigned.all ; +use ieee.std_logic_unsigned.all; use std.textio.all; -USE ieee.std_logic_textio.all; +use ieee.std_logic_textio.all; use std.env.stop; use work.all; use work.fit_gbt_common_package.all; use work.fit_gbt_board_package.all; - -ENTITY testbench_readout IS -END testbench_readout; - -ARCHITECTURE behavior OF testbench_readout IS - - -- inputs file -------------------------------------- - file input_reg_file : text open read_mode is "..\..\..\..\..\..\..\..\software\readout-sim\simulation_inputs\simple_sig_inputs.txt"; - file output_rd_file : text open write_mode is "..\..\..\..\..\..\..\..\software\readout-sim\simulation_outputs\readout_gbt_output.txt"; - file output_rd_info_file : text open write_mode is "..\..\..\..\..\..\..\..\software\readout-sim\simulation_outputs\readout_gbt_info_output.txt"; - file output_st_reg_file : text open write_mode is "..\..\..\..\..\..\..\..\software\readout-sim\simulation_outputs\readout_status_reg_output.txt"; - signal Control_register_from_file : cntr_reg_addrreg_type; - -- --------------------------------------------------- - - - --clocks - constant Sys_period : time := 3.125 ns; - constant ipbus_clock_period : time := 33.333 ns; - signal RESET : std_logic := '0'; - signal SYS_CLK : std_logic := '0'; - signal DATA_CLK, DATA_CLK_ff : std_logic := '0'; - signal IPBUS_CLK : std_logic := '0'; - signal GBT_RxFrameClk : std_logic := '0'; - - signal FSM_Clocks_signal : FSM_Clocks_type; - - - --ip-bus read - signal IPBUS_gen_rst : std_logic; - signal IPBUS_gen_isrd : std_logic; - signal IPBUS_gen_addr : std_logic_vector (11 downto 0); - signal IPBUS_data_out : std_logic_vector (31 downto 0); - signal IPBUS_ackn : std_logic; - - --Outputs - signal GBT_status : FIT_GBT_status_type; - signal GBT_status_reg : status_reg_addrreg_sim_type; - - signal Data_from_FITrd : std_logic_vector(GBT_data_word_bitdepth-1 downto 0); - signal IsData_from_FITrd : STD_LOGIC; - - signal RxData_rxclk_from_GBT : std_logic_vector(GBT_data_word_bitdepth-1 downto 0); - signal IsRxData_rxclk_from_GBT : STD_LOGIC; - - -- debub - signal sim_iter_num : std_logic_vector(63 downto 0); - - - constant testbench_CONTROL_REG_default : CONTROL_REGISTER_type := - ( - Data_Gen => ( - --usage_generator => use_TX_generator, - usage_generator => use_MAIN_generator, - - trigger_resp_mask => TRG_const_void, - bunch_pattern => x"10e0766f", - bunch_freq => x"0dff", - bunch_freq_hboffset => x"001" - ), - - Trigger_Gen => ( - usage_generator => use_CONT_generator, - --usage_generator => use_NO_generator - Readout_command => idle, - trigger_single_val => x"00000000", - trigger_pattern => x"0000000080000000", - trigger_cont_value => TRG_const_Ph, - bunch_freq => x"0deb", - bunch_freq_hboffset => x"ddc" - ), - - RDH_data => ( - FEE_ID => x"0001", - PAR => x"ffff", - DET_Field => x"1234" - ), - - readout_bypass => '0', - is_hb_response => '1', - trg_data_select => x"00000010", - - n_BCID_delay => x"01f", - crutrg_delay_comp => x"00f", - max_data_payload => x"00f0", - reset_orbc_synd => '0', - reset_drophit_counter => '0', - reset_gen_offset => '0', - reset_gbt_rxerror => '0', - reset_gbt => '0', - reset_rxph_error => '0', - strt_rdmode_lock => '0' - ); - signal testbench_CONTROL_REG_dynamic : CONTROL_REGISTER_type := testbench_CONTROL_REG_default; - - - -BEGIN - -FSM_Clocks_signal.Reset <= RESET; -FSM_Clocks_signal.Data_Clk <= DATA_CLK; -FSM_Clocks_signal.System_Clk <= SYS_CLK; -FSM_Clocks_signal.System_Counter <= x"0"; -FSM_Clocks_signal.IPBUS_Data_Clk <= IPBUS_CLK; - -GBT_status_reg <= func_STATREG_getaddrreg_sim(GBT_status); - - - + +entity testbench_readout is +end testbench_readout; + +architecture behavior of testbench_readout is + + -- inputs file -------------------------------------- +-- file input_reg_file : text open read_mode is "..\..\..\..\..\..\..\..\software\readout-sim\sim_data\sim_in_ctrlreg.txt"; +-- file output_dat_file : text open write_mode is "..\..\..\..\..\..\..\..\software\readout-sim\sim_data\sim_out_data.txt"; + file input_reg_file : text open read_mode is "../../../../../../../../software/readout-sim/sim_data/sim_in_ctrlreg.txt"; + file output_dat_file : text open write_mode is "../../../../../../../../software/readout-sim/sim_data/sim_out_data.txt"; + signal Control_register_from_file : ctrl_reg_t; + -- --------------------------------------------------- + + --clocks + constant rxclk_shift : time := 4 ns; + constant Sys_period : time := 3.125 ns; + constant ipbus_clock_period : time := 33.333 ns; + signal RESET : std_logic := '0'; + signal SYS_CLK : std_logic := '0'; + signal DATA_CLK : std_logic := '0'; + signal RX_CLK : std_logic := '0'; + signal IPBUS_CLK : std_logic := '0'; + signal GBT_RxFrameClk : std_logic := '0'; + signal FSM_Clocks_signal : rdclocks_t; + + -- Inputs + signal testbench_CONTROL_REG_dynamic : readout_control_t := test_CONTROL_REG; + + --Outputs + signal GBT_status : readout_status_t; + signal GBT_status_reg : stat_reg_sim_t; + signal Data_from_FITrd : std_logic_vector(GBT_data_word_bitdepth-1 downto 0); + signal IsData_from_FITrd : std_logic; + signal RxData_rxclk_from_GBT : std_logic_vector(GBT_data_word_bitdepth-1 downto 0); + signal IsRxData_rxclk_from_GBT : std_logic; + signal IsRxData_rxclk_from_GBT_sim : std_logic := '0'; + + -- debub + signal sim_iter_num : std_logic_vector(63 downto 0); + +begin + + FSM_Clocks_signal.Reset_dclk <= RESET; + FSM_Clocks_signal.Data_Clk <= DATA_CLK; + FSM_Clocks_signal.System_Clk <= SYS_CLK; + FSM_Clocks_signal.System_Counter <= x"0"; + + -- FIT GBT project ===================================== -FitGbtPrg: entity work.FIT_GBT_project - generic map( - GENERATE_GBT_BANK => 0 - ) - - Port map( - RESET_I => FSM_Clocks_signal.Reset, - SysClk_I => FSM_Clocks_signal.System_Clk, - DataClk_I => FSM_Clocks_signal.Data_Clk, - MgtRefClk_I => FSM_Clocks_signal.Data_Clk, - RxDataClk_I => GBT_RxFrameClk, -- 40MHz data clock in RX domain (loop back) - GBT_RxFrameClk_O => GBT_RxFrameClk, - - Board_data_I => board_data_test_const, - Control_register_I => testbench_CONTROL_REG_dynamic, - - MGT_RX_P_I => '0', - MGT_RX_N_I => '0', - MGT_TX_P_O => open, - MGT_TX_N_O => open, - MGT_TX_dsbl_O => open, - - RxData_rxclk_to_FITrd_I => RxData_rxclk_from_GBT, --loop back data - IsRxData_rxclk_to_FITrd_I => IsRxData_rxclk_from_GBT, --loop back data - Data_from_FITrd_O => Data_from_FITrd, - IsData_from_FITrd_O => IsData_from_FITrd, - Data_to_GBT_I => Data_from_FITrd, --loop back data - IsData_to_GBT_I => IsData_from_FITrd, --loop back data - - RxData_rxclk_from_GBT_O => RxData_rxclk_from_GBT, - IsRxData_rxclk_from_GBT_O => IsRxData_rxclk_from_GBT, - rx_ph320 => open, - ph_error320 => open, - - FIT_GBT_status_O => GBT_status - ); + FitGbtPrg : entity work.FIT_GBT_project + generic map( + IS_SIMULATION => 1 + ) + + port map( + RESET_I => FSM_Clocks_signal.Reset_dclk, + SysClk_I => FSM_Clocks_signal.System_Clk, + DataClk_I => FSM_Clocks_signal.Data_Clk, + MgtRefClk_I => FSM_Clocks_signal.Data_Clk, +-- RxDataClk_I => GBT_RxFrameClk, -- 40MHz data clock in RX domain (loop back) + RxDataClk_I => RX_CLK, + GBT_RxFrameClk_O => GBT_RxFrameClk, + + IPbusClk_I => IPBUS_CLK, + err_report_fifo_rden_i => '1', + + Board_data_I => board_data_test_const, + Control_register_I => testbench_CONTROL_REG_dynamic, + errors_rden_I => '1', + + MGT_RX_P_I => '0', + MGT_RX_N_I => '0', + MGT_TX_P_O => open, + MGT_TX_N_O => open, + MGT_TX_dsbl_O => open, + + RxData_rxclk_to_FITrd_I => RxData_rxclk_from_GBT, --loop back data +-- IsRxData_rxclk_to_FITrd_I => IsRxData_rxclk_from_GBT, --loop back data + IsRxData_rxclk_to_FITrd_I => IsRxData_rxclk_from_GBT_sim, --loop back data + Data_from_FITrd_O => Data_from_FITrd, + IsData_from_FITrd_O => IsData_from_FITrd, + Data_to_GBT_I => Data_from_FITrd, --loop back data + IsData_to_GBT_I => IsData_from_FITrd, --loop back data + + RxData_rxclk_from_GBT_O => RxData_rxclk_from_GBT, + IsRxData_rxclk_from_GBT_O => IsRxData_rxclk_from_GBT, + + readout_status_o => GBT_status + ); -- ===================================================== --- system and data clocks ============================== -Sys1_process :process - variable was_reset : integer := 0; - variable counter : integer := 0; - --- -- file data ------------------ --- constant infile_num_col : integer := cntr_reg_n_32word*2; --- variable infile_line : line; --- variable outfile_line : line; --- type infile_data_type is array (integer range <>) of integer; - --- variable data_from_file : infile_data_type(0 to infile_num_col-1); --- variable datavec_from_file : cntr_reg_addrreg_type; --- -- ----------------------------- - - begin - - if(was_reset < 8) then - was_reset := was_reset + 1; - RESET <= '1'; - --- data_from_file := (others=>0); - else - RESET <= '0'; - end if; - - SYS_CLK <= '0'; - wait for Sys_period/2; - - counter := counter + 1; - - if(counter <= 4) then DATA_CLK <= '0'; else - DATA_CLK <= '1'; - end if; - - - if(counter = 8) then counter := 0; end if; - - - SYS_CLK <= '1'; - wait for Sys_period/2; + + + +-- system and data clocks ============================== + Sys1_process : process + variable was_reset : integer := 0; + variable counter : integer := 0; + + begin + + -- reset counter + if(was_reset < 32) then + was_reset := was_reset + 1; + RESET <= '1'; + else + RESET <= '0'; + end if; + + + SYS_CLK <= '0'; + wait for Sys_period/2; + + counter := counter + 1; + + if(counter <= 4) then DATA_CLK <= '0'; + else DATA_CLK <= '1'; end if; + + if(counter = 8) then counter := 0; end if; + + SYS_CLK <= '1'; + wait for Sys_period/2; + end process; -- ===================================================== - --- ipbus clock ========================================= -Sys2_process :process - variable was_reset : integer := 0; - variable addr_count : integer := 0; - variable rd_rate_count : integer := 0; - variable read_start_delay : integer := 0; - - begin - - IPBUS_CLK <= '0'; - wait for ipbus_clock_period/2; - - if(was_reset < 2) then - was_reset := was_reset + 1; - IPBUS_gen_rst <= '1'; - else - IPBUS_gen_rst <= '0'; - end if; - if(rd_rate_count < 200) then - rd_rate_count := rd_rate_count + 1; - else - rd_rate_count := 0; - end if; - - if(read_start_delay < 100) then - read_start_delay := read_start_delay + 1; - else - read_start_delay := 100; - end if; - - IPBUS_gen_addr <= std_logic_vector(to_unsigned(20, 12)); - - if(rd_rate_count < 60) then - addr_count := addr_count + 1; - --IPBUS_gen_addr <= std_logic_vector(to_unsigned(addr_count, 12)); - - if(read_start_delay >= 100) then - IPBUS_gen_isrd <= '1'; - else - IPBUS_gen_isrd <= '0'; - end if; - else - addr_count := 0; - --IPBUS_gen_addr <= std_logic_vector(to_unsigned(addr_count, 12)); - IPBUS_gen_isrd <= '0'; - end if; - + + +-- RX clock from CRU =================================== + Sys2_process : process + variable was_reset : boolean := false; + + begin + + -- reset counter + if( not was_reset) then + was_reset := true; + IsRxData_rxclk_from_GBT_sim <= '0'; + wait for rxclk_shift; + end if; + + RX_CLK <= '0'; + wait for Sys_period*4; + + RX_CLK <= '1'; + IsRxData_rxclk_from_GBT_sim <= not IsRxData_rxclk_from_GBT_sim; + wait for Sys_period*4; + + end process; +-- ===================================================== + + + +-- IPbus clock ========================================= + Sys3_process : process + + begin + + IPBUS_CLK <= '0'; + wait for ipbus_clock_period/2; + IPBUS_CLK <= '1'; wait for ipbus_clock_period/2; - + end process; -- ===================================================== +--testbench_CONTROL_REG_dynamic <= func_CNTRREG_getcntrreg(Control_register_from_file); + +-- simulation run ====================================== + process (FSM_Clocks_signal.Data_Clk) + + -- file data ------------------ + variable iter_num : std_logic_vector(63 downto 0) := (others => '0'); + + -- reading / writing + constant infile_num_col : integer := ctrl_reg_size*2; + variable file_line : line; + type infile_data_type is array (integer range <>) of integer; + variable data_from_file : infile_data_type(0 to infile_num_col-1):= (others => 0); + variable is_gbt_data : std_logic_vector(3 downto 0) := x"0"; + -- ----------------------------- + + begin + if (rising_edge(FSM_Clocks_signal.Data_Clk)) then + + GBT_status_reg <= func_STATREG_getaddrreg_sim(GBT_status); + + + if(FSM_Clocks_signal.Reset_dclk = '1') then + + data_from_file := (others => 0); + Control_register_from_file <= (others => (others => '0')); + testbench_CONTROL_REG_dynamic <= test_CONTROL_REG; + + else + + -- clock counter + iter_num := iter_num + 1; + sim_iter_num <= iter_num; + + + -- reading control registers from file + if(not endfile(input_reg_file)) then + + readline(input_reg_file, file_line); + for irow in 0 to infile_num_col-1 loop + read(file_line, data_from_file(irow)); + end loop; + + for irow in 0 to ctrl_reg_size-1 loop + Control_register_from_file(irow)(15 downto 0) <= std_logic_vector(to_unsigned(data_from_file(irow*2+1), 16)); + Control_register_from_file(irow)(31 downto 16) <= std_logic_vector(to_unsigned(data_from_file(irow*2), 16)); + end loop; --- Data ff data clk *********************************** - PROCESS (FSM_Clocks_signal.Data_Clk) - -- file data ------------------ - variable iter_num : std_logic_vector(63 downto 0) := (others=>'0'); - constant infile_num_col : integer := cntr_reg_n_32word*2; - variable infile_line : line; - variable outfile_line : line; - variable temp_line : line; - type infile_data_type is array (integer range <>) of integer; - - variable data_from_file : infile_data_type(0 to infile_num_col-1); - variable datavec_from_file : cntr_reg_addrreg_type; - -- ----------------------------- - BEGIN - IF(FSM_Clocks_signal.Data_Clk'EVENT and FSM_Clocks_signal.Data_Clk = '1') THEN - IF(FSM_Clocks_signal.Reset = '1') THEN - data_from_file := (others=>0); - ELSE - if (DATA_CLK = '1') and (DATA_CLK_ff = '0') then - iter_num := iter_num + 1; - sim_iter_num <= iter_num; - - if(not endfile(input_reg_file)) then - readline(input_reg_file, infile_line); - for irow in 0 to infile_num_col-1 loop - read(infile_line, data_from_file(irow)); - end loop; - for irow in 0 to cntr_reg_n_32word-1 loop - Control_register_from_file(irow)(15 downto 0) <= std_logic_vector(to_unsigned(data_from_file(irow*2+1),16)); - Control_register_from_file(irow)(31 downto 16) <= std_logic_vector(to_unsigned(data_from_file(irow*2),16)); - end loop; - testbench_CONTROL_REG_dynamic <= func_CNTRREG_getcntrreg(Control_register_from_file); - else - stop; - end if; - - if (IsData_from_FITrd = '1') then - outfile_line := ""; - hwrite(outfile_line, Data_from_FITrd); - writeline(output_rd_file, outfile_line); - - outfile_line := ""; - hwrite(outfile_line, iter_num); - writeline(output_rd_info_file, outfile_line); - end if; - - outfile_line := ""; - for ireg in 0 to status_reg_sim_n_32word-1 loop - hwrite(outfile_line, GBT_status_reg(ireg), left, 11); - end loop; - writeline(output_st_reg_file, outfile_line); - - - end if; - END IF; - - - END IF; - - - END PROCESS; + testbench_CONTROL_REG_dynamic <= func_CNTRREG_getcntrreg(Control_register_from_file); + + else + stop; + end if; + + -- writing simulation status + file_line := ""; + is_gbt_data(0) := IsData_from_FITrd; + hwrite(file_line, is_gbt_data, left, 5); + hwrite(file_line, Data_from_FITrd, left, 23); + for ireg in 0 to stat_reg_size_sim-1 loop + hwrite(file_line, GBT_status_reg(ireg), left, 11); + end loop; + writeline(output_dat_file, file_line); + + + end if; + + + end if; + + + end process; -- **************************************************** -END; +end; diff --git a/firmware/common/ipbus/hdl/eth_7s_1000basex.vhd b/firmware/common/ipbus/hdl/eth_7s_1000basex.vhd index e1fd9e2..b65d0b5 100644 --- a/firmware/common/ipbus/hdl/eth_7s_1000basex.vhd +++ b/firmware/common/ipbus/hdl/eth_7s_1000basex.vhd @@ -146,7 +146,7 @@ architecture rtl of eth_7s_1000basex is signal gmii_rx_clk: std_logic; signal clk125, txoutclk_ub, txoutclk, clk125_ub, rxoutclk, rxoutclk_ub : std_logic; signal clk62_5_ub, clk62_5, clkfb: std_logic; - signal rstn, pll_rst, phy_done, mmcm_locked, locked_int: std_logic; + signal rstn, pll_rst, phy_done, mmcm_locked, locked_int : std_logic; signal decoupled_clk: std_logic := '0'; signal status_vector: std_logic_vector(15 downto 0); signal speed10100, speed100, clk_en, sgmii, rst_pcs, rdy : std_logic; @@ -172,23 +172,24 @@ mmcm: MMCM125ETH port map(clkout1 => clk62_5, clkout2 => clk125, clkin1 => txout process(clk_gt125) begin - if rising_edge(clk_gt125) then + if rising_edge(clk_gt125) then locked_int <= mmcm_locked and phy_done; - if (rsti='1') then - sgmii<='1'; to_cnt<= (others=>'0'); rst_cnt<= (others=>'1'); rdy<= '0'; + if (rsti='1') then + sgmii<='0'; to_cnt<= (others=>'0'); rst_cnt<= (others=>'1'); rdy<= '0'; else - if (rst_cnt/="111") then rst_cnt<= rst_cnt+1; end if; - if (locked_int='1') then - if (to_cnt/= "111" & x"FFFFF") then to_cnt<= to_cnt+1; - else - if (rdy='0') then rdy<= '1'; - if (status_vector(0)='0') then sgmii<='0'; rst_cnt<= (others =>'0'); end if; - end if; - end if; - end if; - end if; - end if; + if (rst_cnt/="111") then rst_cnt<= rst_cnt+1; end if; + if (locked_int='1') and (rdy='0') then + if (to_cnt/= "111" & x"FFFFF") then to_cnt<= to_cnt+1; + else + if (status_vector(0)='0') then sgmii<= not sgmii; rst_cnt<= (others =>'0'); + if (sgmii='0') then to_cnt<= (others=>'0'); end if; + end if; + if (sgmii='1') or (status_vector(0)='1') then rdy<='1'; end if; + end if; + end if; + end if; + end if; end process; locked <= locked_int; diff --git a/firmware/common/ipbus/hdl/ipbus_core/transactor_cfg.vhd b/firmware/common/ipbus/hdl/ipbus_core/transactor_cfg.vhd deleted file mode 100644 index 1a03bc4..0000000 --- a/firmware/common/ipbus/hdl/ipbus_core/transactor_cfg.vhd +++ /dev/null @@ -1,48 +0,0 @@ --- Some registers to store the config information for the ipbus controller --- --- Typically used to allow ucontroller to set the mac / ip address --- --- Dave Newbold, January 2012 - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library work; - -entity transactor_cfg is - port( - clk: in std_logic; -- IPbus clock - rst: in std_logic; -- Sync reset - we: in std_logic; -- local bus write enable - addr: in std_logic_vector(1 downto 0); -- local bus address - din: in std_logic_vector(31 downto 0); -- local bus data in - dout: out std_logic_vector(31 downto 0); -- local bus data out - vec_in: in std_logic_vector(127 downto 0); - vec_out: out std_logic_vector(127 downto 0) - ); - -end transactor_cfg; - -architecture rtl of transactor_cfg is - - signal s: integer; - -begin - - s <= to_integer(unsigned(addr)); - - process(clk) - begin - if rising_edge(clk) then - if rst = '1' then - vec_out <= (others => '0'); - elsif we = '1' then - vec_out(31 + s * 32 downto s * 32) <= din; - end if; - end if; - end process; - - dout <= vec_in(31 + s * 32 downto s * 32); - -end rtl; diff --git a/firmware/common/ipbus/hdl/ipbus_core/transactor_sm.vhd b/firmware/common/ipbus/hdl/ipbus_core/transactor_sm.vhd index fa98058..c79f518 100644 --- a/firmware/common/ipbus/hdl/ipbus_core/transactor_sm.vhd +++ b/firmware/common/ipbus/hdl/ipbus_core/transactor_sm.vhd @@ -99,8 +99,6 @@ begin else state <= ST_HDR; end if; - elsif timer = TIMEOUT then - state <= ST_HDR; end if; -- RMW operations when ST_RMW_1 => @@ -190,7 +188,7 @@ begin or rmw_write = '1' else '0'; rx_next <= '1' when state = ST_HDR or state = ST_RMW_1 or state = ST_RMW_2 or (state = ST_ADDR and (write='1' or words_todo = X"00")) or - (state = ST_BUS_CYCLE and (ack and (strobe or cfg_cyc) and (write or last_wd) and not rmw_write) = '1') + (state = ST_BUS_CYCLE and (((ack and strobe) or cfg_cyc) and (write or last_wd) and not rmw_write) = '1') else '0'; rmw_cyc <= '1' when trans_type = TRANS_RMWB or trans_type = TRANS_RMWS else '0'; cfg_cyc <= '1' when trans_type = TRANS_RD_CFG or trans_type = TRANS_WR_CFG else '0'; @@ -211,7 +209,7 @@ begin end if; end process; - ack <= ipb_in.ipb_ack or ipb_in.ipb_err or cfg_cyc; + ack <= ipb_in.ipb_ack; ipb_out.ipb_addr <= std_logic_vector(addr); ipb_out.ipb_write <= write; diff --git a/firmware/common/ipbus/hdl/ipbus_core/udp_ipaddr_block.vhd b/firmware/common/ipbus/hdl/ipbus_core/udp_ipaddr_block.vhd deleted file mode 100644 index f622325..0000000 --- a/firmware/common/ipbus/hdl/ipbus_core/udp_ipaddr_block.vhd +++ /dev/null @@ -1,93 +0,0 @@ --- Handles source of MAC and IP address... --- Parses incoming RARP response to capture real MAC and IP address --- --- Dave Sankey, July 2012 and September 2015 - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity udp_ipaddr_block is - port ( - mac_clk: in std_logic; - rst_macclk_reg: in std_logic; - rx_reset: in std_logic; - enable_125: in std_logic; - rarp_125: in std_logic; - MAC_addr: in std_logic_vector(47 DOWNTO 0); - IP_addr: in std_logic_vector(31 downto 0); - my_rx_data: in std_logic_vector(7 downto 0); - my_rx_error: in std_logic; - my_rx_last: in std_logic; - my_rx_valid: in std_logic; - pkt_drop_rarp: in std_logic; - My_MAC_addr: out std_logic_vector(47 downto 0); - My_IP_addr: out std_logic_vector(31 downto 0); - rarp_mode: out std_logic - ); -end udp_ipaddr_block; - -architecture rtl of udp_ipaddr_block is - - signal MAC_IP_addr_rx_vld: std_logic; - signal MAC_IP_addr_rx: std_logic_vector(79 downto 0); - -begin - -MAC_IP_addr_rx_vld_block: process (mac_clk) - begin - if rising_edge(mac_clk) then --- Valid RARP response received. - if my_rx_last = '1' and pkt_drop_rarp = '0' and - my_rx_error = '0' then - MAC_IP_addr_rx_vld <= '1'; - else - MAC_IP_addr_rx_vld <= '0'; - end if; - end if; - end process; - -MAC_IP_addr_rx_block: process(mac_clk) - variable pkt_mask: std_logic_vector(41 downto 0); - variable MAC_IP_addr_rx_int: std_logic_vector(79 downto 0); - begin - if rising_edge(mac_clk) then - if rx_reset = '1' then - pkt_mask := "111111" & "111111" & "11" & - "11" & "11" & "11" & "11" & "111111" & - "1111" & "000000" & "0000"; - MAC_IP_addr_rx_int := (Others => '0'); - elsif my_rx_valid = '1' then - if pkt_drop_rarp = '1' then - MAC_IP_addr_rx_int := (Others => '0'); - elsif pkt_mask(41) = '0' then - MAC_IP_addr_rx_int := MAC_IP_addr_rx_int(71 downto 0) & my_rx_data; - end if; - pkt_mask := pkt_mask(40 downto 0) & '1'; - end if; - MAC_IP_addr_rx <= MAC_IP_addr_rx_int; - end if; - end process; - -My_MAC_IP_addr_block: process (mac_clk) - variable Got_MAC_IP_addr_rx, last_enable_125: std_logic; - variable My_MAC_IP_addr_int: std_logic_vector(79 downto 0); - begin - if rising_edge(mac_clk) then --- Sample MAC_addr & IP_addr on reset or enable going high... - if (rst_macclk_reg = '1') or - (enable_125 = '1' and last_enable_125 = '0') then - Got_MAC_IP_addr_rx := '0'; - My_MAC_IP_addr_int := MAC_addr & IP_addr; - elsif MAC_IP_addr_rx_vld = '1' and rarp_125 = '1' then - Got_MAC_IP_addr_rx := '1'; - My_MAC_IP_addr_int := MAC_IP_addr_rx; - end if; - last_enable_125 := enable_125; - My_MAC_addr <= My_MAC_IP_addr_int(79 downto 32); - My_IP_addr <= My_MAC_IP_addr_int(31 downto 0); - rarp_mode <= enable_125 and rarp_125 and not Got_MAC_IP_addr_rx; - end if; - end process; - -end rtl; diff --git a/firmware/common/ipbus/hdl/ipbus_core/udp_packet_parser.vhd b/firmware/common/ipbus/hdl/ipbus_core/udp_packet_parser.vhd index 00e3cb4..6625031 100644 --- a/firmware/common/ipbus/hdl/ipbus_core/udp_packet_parser.vhd +++ b/firmware/common/ipbus/hdl/ipbus_core/udp_packet_parser.vhd @@ -150,34 +150,34 @@ end generate primary_mode; -- SPA(4) -- THA(6) = My_MAC_addr -- TPA(4) = MY_IP(4) -rarp: process (mac_clk) - variable pkt_data: std_logic_vector(127 downto 0); - variable pkt_mask: std_logic_vector(21 downto 0); - variable pkt_drop: std_logic; - begin - if rising_edge(mac_clk) then - if rx_reset = '1' then - pkt_mask := "000000" & "111111" & "00" & "00" & "00" & "00" & "00"; - pkt_data := My_MAC_addr & x"8035" & x"0001" & x"0800" & x"0604" & x"0004"; - pkt_drop := not enable_125; - elsif my_rx_last = '1' then - pkt_drop := '1'; - elsif my_rx_valid = '1' then - if pkt_mask(21) = '0' then - if pkt_data(127 downto 120) /= my_rx_data then - pkt_drop := '1'; - end if; - pkt_data := pkt_data(119 downto 0) & x"00"; - end if; - pkt_mask := pkt_mask(20 downto 0) & '1'; - end if; - pkt_drop_rarp_sig <= pkt_drop --- pragma translate_off - after 4 ns --- pragma translate_on - ; - end if; - end process; +--rarp: process (mac_clk) +-- variable pkt_data: std_logic_vector(127 downto 0); +-- variable pkt_mask: std_logic_vector(21 downto 0); +-- variable pkt_drop: std_logic; +-- begin +-- if rising_edge(mac_clk) then +-- if rx_reset = '1' then +-- pkt_mask := "000000" & "111111" & "00" & "00" & "00" & "00" & "00"; +-- pkt_data := My_MAC_addr & x"8035" & x"0001" & x"0800" & x"0604" & x"0004"; +-- pkt_drop := not enable_125; +-- elsif my_rx_last = '1' then +-- pkt_drop := '1'; +-- elsif my_rx_valid = '1' then +-- if pkt_mask(21) = '0' then +-- if pkt_data(127 downto 120) /= my_rx_data then +-- pkt_drop := '1'; +-- end if; +-- pkt_data := pkt_data(119 downto 0) & x"00"; +-- end if; +-- pkt_mask := pkt_mask(20 downto 0) & '1'; +-- end if; +-- pkt_drop_rarp_sig <= pkt_drop +---- pragma translate_off +-- after 4 ns +---- pragma translate_on +-- ; +-- end if; +-- end process; -- IP packet: -- Ethernet DST_MAC(6) = My_MAC_addr, SRC_MAC(6), Ether_Type = x"0800" @@ -294,36 +294,42 @@ ipbus_mask: process(mac_clk) -- IPBus packet header x"20nnnnF0" or x"200000F0" -- IPBus data... bigendian: process (mac_clk) - variable reliable_data: std_logic_vector(31 downto 0); - variable unreliable_data: std_logic_vector(31 downto 0); + variable pkt_mask: std_logic_vector(3 downto 0); +-- variable reliable_data: std_logic_vector(31 downto 0); + variable unreliable_data: std_logic_vector(15 downto 0); variable pkt_drop_reliable_i, pkt_drop_unreliable: std_logic; begin if rising_edge(mac_clk) then if rx_reset = '1' then - reliable_data := x"20" & next_pkt_id & x"F0"; - unreliable_data := x"200000F0"; - pkt_drop_reliable_i := not enable_125; + pkt_mask := "0110"; + -- reliable_data := x"20" & next_pkt_id & x"F0"; + unreliable_data := x"20F0"; +-- pkt_drop_reliable_i := not enable_125; pkt_drop_unreliable := not enable_125; elsif my_rx_last = '1' then - pkt_drop_reliable_i := '1'; +-- pkt_drop_reliable_i := '1'; pkt_drop_unreliable := '1'; elsif my_rx_valid = '1' then if pkt_drop_ipbus_sig = '1' then - pkt_drop_reliable_i := '1'; +-- pkt_drop_reliable_i := '1'; pkt_drop_unreliable := '1'; - elsif ipbus_hdr_mask = '0' then - if reliable_data(31 downto 24) /= my_rx_data then - pkt_drop_reliable_i := '1'; - end if; - if unreliable_data(31 downto 24) /= my_rx_data then + elsif ipbus_hdr_mask = '0' then + +-- if reliable_data(31 downto 24) /= my_rx_data then +-- pkt_drop_reliable_i := '1'; +-- end if; + if pkt_mask(3) = '0' then + if unreliable_data(15 downto 8) /= my_rx_data then pkt_drop_unreliable := '1'; end if; - reliable_data := reliable_data(23 downto 0) & x"00"; - unreliable_data := unreliable_data(23 downto 0) & x"00"; +-- reliable_data := reliable_data(23 downto 0) & x"00"; + unreliable_data := unreliable_data(7 downto 0) & x"00"; + end if; + pkt_mask := pkt_mask(2 downto 0) & '1'; end if; - end if; - pkt_drop_reliable_sig <= pkt_drop_reliable_i; - pkt_drop_payload_sig <= pkt_drop_reliable_i and pkt_drop_unreliable; + end if; + pkt_drop_reliable_sig <= '1'; + pkt_drop_payload_sig <= pkt_drop_unreliable; end if; end process; @@ -331,37 +337,42 @@ bigendian: process (mac_clk) -- IPBus packet header x"F0nnnn20" or x"F0000020" -- IPBus data... littleendian: process (mac_clk) - variable reliable_data: std_logic_vector(31 downto 0); - variable unreliable_data: std_logic_vector(31 downto 0); + variable pkt_mask: std_logic_vector(3 downto 0); +-- variable reliable_data: std_logic_vector(31 downto 0); + variable unreliable_data: std_logic_vector(15 downto 0); variable pkt_drop_reliable_i, pkt_drop_unreliable: std_logic; begin if rising_edge(mac_clk) then if rx_reset = '1' then - reliable_data := x"F0" & next_pkt_id(7 downto 0) & - next_pkt_id(15 downto 8) & x"20"; - unreliable_data := x"F0000020"; - pkt_drop_reliable_i := not enable_125; + pkt_mask := "0110"; +-- reliable_data := x"F0" & next_pkt_id(7 downto 0) & +-- next_pkt_id(15 downto 8) & x"20"; + unreliable_data := x"F020"; + -- pkt_drop_reliable_i := not enable_125; pkt_drop_unreliable := not enable_125; elsif my_rx_last = '1' then - pkt_drop_reliable_i := '1'; +-- pkt_drop_reliable_i := '1'; pkt_drop_unreliable := '1'; elsif my_rx_valid = '1' then if pkt_drop_ipbus_sig = '1' then - pkt_drop_reliable_i := '1'; +-- pkt_drop_reliable_i := '1'; pkt_drop_unreliable := '1'; elsif ipbus_hdr_mask = '0' then - if reliable_data(31 downto 24) /= my_rx_data then - pkt_drop_reliable_i := '1'; - end if; - if unreliable_data(31 downto 24) /= my_rx_data then +-- if reliable_data(31 downto 24) /= my_rx_data then +-- pkt_drop_reliable_i := '1'; +-- end if; + if pkt_mask(3) = '0' then + if unreliable_data(15 downto 8) /= my_rx_data then pkt_drop_unreliable := '1'; end if; - reliable_data := reliable_data(23 downto 0) & x"00"; - unreliable_data := unreliable_data(23 downto 0) & x"00"; +-- reliable_data := reliable_data(23 downto 0) & x"00"; + unreliable_data := unreliable_data(7 downto 0) & x"00"; + end if; + pkt_mask := pkt_mask(2 downto 0) & '1'; end if; end if; - pkt_reliable_drop_sig <= pkt_drop_reliable_i; - pkt_payload_drop_sig <= pkt_drop_reliable_i and pkt_drop_unreliable; + pkt_reliable_drop_sig <= '1'; + pkt_payload_drop_sig <= pkt_drop_unreliable; end if; end process; diff --git a/firmware/common/ipbus/hdl/ipbus_core/udp_status_buffer.vhd b/firmware/common/ipbus/hdl/ipbus_core/udp_status_buffer.vhd index 75afbbc..8562d37 100644 --- a/firmware/common/ipbus/hdl/ipbus_core/udp_status_buffer.vhd +++ b/firmware/common/ipbus/hdl/ipbus_core/udp_status_buffer.vhd @@ -125,7 +125,7 @@ history_block: process (mac_clk) event_data := x"01"; end if; if my_rx_last = '1' then - rarp_arp_ping_ipbus := pkt_drop_rarp & pkt_drop_arp & + rarp_arp_ping_ipbus := '1' & pkt_drop_arp & pkt_drop_ping & pkt_drop_ipbus; payload_status_resend := pkt_drop_payload & pkt_drop_status & pkt_drop_resend; diff --git a/firmware/submodules/gbt-fpga b/firmware/submodules/gbt-fpga deleted file mode 160000 index c9d4366..0000000 --- a/firmware/submodules/gbt-fpga +++ /dev/null @@ -1 +0,0 @@ -Subproject commit c9d43663775574b070b91e7dd506412a24eeeb1d diff --git a/photo/FT0_front.jpg b/photo/FT0_front.jpg new file mode 100644 index 0000000..5381439 Binary files /dev/null and b/photo/FT0_front.jpg differ diff --git a/software/ci/build_local.sh b/software/ci/build_local.sh new file mode 100755 index 0000000..6ca8cac --- /dev/null +++ b/software/ci/build_local.sh @@ -0,0 +1,64 @@ +#!/bin/bash + +#set -x + +if [[ $# -eq 0 ]]; then + echo "USEAGE: build_local.sh project_name [PM/TCM_v1/TCM_proto/FTM_PM/FTM_TCM]" + exit 1 +fi + +PROJECT=$1 + +echo "##########################################################" +echo "################ building ${PROJECT} ##################" +echo "##########################################################" + +start_time=$(date +%s.%N) +sD=$(date +%Y-%m-%d) +sT=$(date +%H:%M:%S) +echo "Start time: " "$sD" "$sT" + + +source /opt/Xilinx/Vivado/2019.2/settings64.sh +cd firmware/FT0/${PROJECT} \ + && rm -rf ../bits/${PROJECT}* \ + && mkdir ../bits/${PROJECT}_logs \ + && rm -fr build \ + && rm -f *.log *.jou \ + && vivado -mode batch -source make.tcl \ + && cp $(find build -name "*.bit") ../bits/${PROJECT}.bit \ + && cp $(find build -name "*.bin") ../bits/${PROJECT}.bin \ + && cp $(find -name "*.log") ../bits/${PROJECT}_logs/ \ + && cp $(find -name "tight_setup_hold_pins.txt") ../bits/${PROJECT}_logs/ + + +echo +echo +echo +echo "##########################################################" +echo "PROJECT NAME: ${PROJECT}" + +end_time=$(date +%s.%N) +eD=$(date +%Y-%m-%d) +eT=$(date +%H:%M:%S) +echo "Start time: " "$sD" "$sT" +echo "Stop time: " "$eD" "$eT" +dt=$(echo "$end_time - $start_time" | bc) +dd=$(echo "$dt/86400" | bc) +dt2=$(echo "$dt-86400*$dd" | bc) +dh=$(echo "$dt2/3600" | bc) +dt3=$(echo "$dt2-3600*$dh" | bc) +dm=$(echo "$dt3/60" | bc) +ds=$(echo "$dt3-60*$dm" | bc) +LC_NUMERIC=C printf "Runtime: %02d:%02d:%02.4f\n" $dh $dm $ds +echo +echo "parsing bits command line:" +echo "scp -r ./firmware/FT0/bits dfinogee@lxplus.cern.ch:/eos/user/d/dfinogee/alice-fit-fpga-artifacts/" +echo +echo "parsing repo command line" +echo "rsync -avz --delete --exclude={'build','nppBackup','__pycache__','.git','.Xil','bits','.idea','*.str','*.bak','*.vhd~','*.jou','*.log','*.tmp','*.coe'} ../alice-fit-fpga dfinogee@lxplus.cern.ch:/eos/user/d/dfinogee/alice-fit-fpga-artifacts/" +echo +echo "Timing summary log:" +echo +grep -A10 "Design Timing Summary" ../bits/${PROJECT}_logs/impl_1_timing_summary.log +echo diff --git a/software/gbt-control-macro/fit_gbt_init.cpp b/software/gbt-control-macro/fit_gbt_init.cpp new file mode 100644 index 0000000..689f50b --- /dev/null +++ b/software/gbt-control-macro/fit_gbt_init.cpp @@ -0,0 +1,92 @@ +/* +Fast PM/TCM readout initialisation (all modules via IPbus/TCM) + + +g++ -g -Wall fit_gbt_init.cpp -o fit_gbt_init.run && ./fit_gbt_init.run + */ + + #include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "ipbus_connection.h" +#include "pmtcm_map.h" + +int main(int argc, char *argv[]) { + printf("\n\n====================================================\n"); + printf( "================ FIT GBT init ===============\n"); + printf("====================================================\n\n\n"); + + ipbus_connection slow_control; + slow_control.set_board_ip("172.20.75.180"); + slow_control.set_board_port(50001); + if (slow_control.connect_to_board() < 0) { + printf("Connection to board failed\n"); + return -1; + } + + + uint32_t ctrl_reg[16] = {0}; + + // writing init Readout registers to all modules + for(uint32_t pmtcm_iter = 0; pmtcm_iter < pmtcm_total; pmtcm_iter+=1){ + if (pmtcm_map[pmtcm_iter][2] == 0) continue; + + uint32_t curr_ctrl_addr = ctrl_addr + pmtcm_map[pmtcm_iter][1]; + uint32_t curr_thrs_cal_addr = trhr_calib_ch0 + pmtcm_map[pmtcm_iter][1]; + + bool is_tcm = (pmtcm_iter == 0); + int res = 0; + uint8_t reg_size = 16; + + printf("%04x addr 0x%08x", pmtcm_map[pmtcm_iter][0], curr_ctrl_addr); + + printf(" init "); + ctrl_reg[0] = 0x00104000; + ctrl_reg[1] = is_tcm ? 0x40:0x10;// trg response mask + ctrl_reg[9] = 0x00220000 + pmtcm_map[pmtcm_iter][0]; // sys id + ctrl_reg[11] = is_tcm ? 0x1C:0x24; //bcid delay + ctrl_reg[12] = 0x10; // trigger select + res = slow_control.write_registers(ctrl_reg, reg_size, curr_ctrl_addr); + + printf(" reset "); + ctrl_reg[0] = 0x00100000; // release reset + res = slow_control.write_registers(ctrl_reg, reg_size, curr_ctrl_addr); + + //threshold calibration + if(not is_tcm){ + ctrl_reg[0] = pmtcm_map[pmtcm_iter][4]; + reg_size = 1; + res = slow_control.write_registers(ctrl_reg, reg_size, curr_thrs_cal_addr); + } + + printf(" done\n"); + + } + + /* + slow_control.read_registers(ctrl_reg, reg_size, ctrl_addr); + for(int i=0; i +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "ipbus_connection.h" +#include "pmtcm_map.h" + +using namespace std; +typedef chrono::high_resolution_clock Clock; + +bool do_adjust = 0; +float noise_rate_set = 20000.0; //kHz + +int main(int argc, char *argv[]) { + printf("\n\n====================================================\n"); + printf( "================ FIT GBT status ===============\n"); + printf("====================================================\n\n\n"); + + ipbus_connection slow_control; + slow_control.set_board_ip("172.20.75.180"); + slow_control.set_board_port(50001); + if (slow_control.connect_to_board() < 0) { + printf("Connection to board failed\n"); + return -1; + } + + int act_iter=0; + uint32_t ctrl_reg[16] = {0}; + uint32_t stat_reg[16] = {0}; + + printf("\nIT FEEID ADDR BR_ON RD_ON BC_SYN CRU BRD ERRORs FIFOs RATE_kHz CNV_DRP SEL_DRP"); + for(uint32_t pmtcm_iter = 0; pmtcm_iter < pmtcm_total; pmtcm_iter+=1){ + + uint32_t curr_ctrl_addr = ctrl_addr + pmtcm_map[pmtcm_iter][1]; + uint32_t curr_stat_addr = stat_addr + pmtcm_map[pmtcm_iter][1]; + uint32_t curr_thrs_cal_addr = trhr_calib_ch0 + pmtcm_map[pmtcm_iter][1]; + + bool is_tcm = (pmtcm_iter == 0); + int res = 0; + uint8_t reg_size = 16; + + printf("\n%02i %04x [0x%04x] %s ",act_iter, pmtcm_map[pmtcm_iter][0], pmtcm_map[pmtcm_iter][1], pmtcm_map[pmtcm_iter][2]? "ON ":"OFF"); + if (pmtcm_map[pmtcm_iter][2] == 0) continue; + + + slow_control.read_registers(ctrl_reg, reg_size, curr_ctrl_addr); + + //reset counters + reg_size = 1; + ctrl_reg[0] |= 1UL << 9; + res = slow_control.write_registers(ctrl_reg, reg_size, curr_ctrl_addr); + ctrl_reg[0] &= ~(1UL << 9); + res = slow_control.write_registers(ctrl_reg, reg_size, curr_ctrl_addr); + reg_size = 16; + + + auto timer1 = Clock::now(); + slow_control.read_registers(stat_reg, reg_size, curr_stat_addr); + + bool is_force_idle = ctrl_reg[0]&(1<<22); + uint8_t bc_sync = (stat_reg[0]&0xF00000)>>20; + uint8_t rd_mode = (stat_reg[0]&0xF0000)>>16; + uint8_t rd_cru_mode = (stat_reg[0]&0xF0000000)>>28; + bool rd_mode_corr = (rd_mode == rd_cru_mode) || is_force_idle; + uint16_t fsm_errs = (stat_reg[2]&0x7FFF0000)>>16; + uint8_t fifos_empty = (stat_reg[2]&0xFF); + uint32_t gbt_cnt0 = stat_reg[5]; + uint32_t event_cnt0 = stat_reg[9] & 0xFFFF; + uint16_t cnv_drop0 = stat_reg[3] & 0xFFFF; + uint16_t sel_drop0 = stat_reg[4] & 0xFFFF; + + + if (not is_force_idle) act_iter++; + + printf("%s ", is_force_idle?"\x1b[31mOFF\x1b[0m":"\x1b[32mON \x1b[0m"); + printf("%s ", bcsync_lbl[bc_sync]); + printf("%s ", run_lbl[rd_cru_mode]); + printf("%s ",rd_mode_corr?run_lbl_g[rd_mode]:run_lbl_r[rd_mode]); + printf("%04x %s ", fsm_errs, fsm_errs!=0?"\x1b[31mER\x1b[0m":"\x1b[32mOK \x1b[0m"); + + if(fsm_errs > 0){ + for (int ibit = 0; ibit <15; ibit++) if((fsm_errs&(1<0) printf(" %i ", ibit); + } + + printf("%04x ", fifos_empty); + + usleep(100000); + auto timer2 = Clock::now(); + slow_control.read_registers(stat_reg, reg_size, curr_stat_addr); + uint32_t gbt_cnt1 = stat_reg[5]; + uint32_t event_cnt1 = stat_reg[9]; + uint16_t cnv_drop1 = stat_reg[3] & 0xFFFF; + uint16_t sel_drop1 = stat_reg[4] & 0xFFFF; + + + double read_time_s = double(std::chrono::duration_cast(timer2 - timer1).count())/1E9; + float gbt_rate = (gbt_cnt1-gbt_cnt0)/read_time_s/1000.; + float gbt_rate_noHB_khz = gbt_rate-11.248*4.; + float event_rate_khz = (event_cnt1-event_cnt0)/read_time_s/1000.; + float cnv_drp_rate_khz = (cnv_drop1-cnv_drop0)/read_time_s/1000.; + float sel_drp_rate_khz = (sel_drop1-sel_drop0)/read_time_s/1000.; + printf(" %8.2f ", event_rate_khz); + //printf(" %8.2f ", gbt_rate_noHB_khz); + printf(" %8.2f ", cnv_drp_rate_khz); + printf(" %8.2f ", sel_drp_rate_khz); + + + // adjusting noise rate + int adjust = 0; + if(rd_cru_mode > 0 and not is_force_idle) + if(not is_tcm){ + ctrl_reg[0] = 0x000009C4;//2500 + reg_size = 1; + res = slow_control.read_registers(ctrl_reg, reg_size, curr_thrs_cal_addr); + + //float rate_diff_hz = (noise_rate_set - event_rate_khz)*500.; + float rate_diff_hz = (noise_rate_set - gbt_rate_noHB_khz)*500.; + + if ((rate_diff_hz > -500.)&&(rate_diff_hz < 500.)){adjust = 0;}else + if (gbt_rate_noHB_khz < 0.01){adjust = -5;}else + if ((gbt_rate_noHB_khz > 0.5)&&(rate_diff_hz < -500.)){adjust = 10; }else + if ((gbt_rate_noHB_khz >= 0.01)&&(rate_diff_hz > 0.)){adjust = -1; }else + if ((gbt_rate_noHB_khz >= 0.01)&&(rate_diff_hz < 0.)){adjust = 1; }else + {adjust = 0; } + + ctrl_reg[0] += adjust; + if (do_adjust) + res = slow_control.write_registers(ctrl_reg, reg_size, curr_thrs_cal_addr); + + printf("(%5i ", ctrl_reg[0]); + printf("%2i) ", adjust); + } + + } + + printf("\n"); + +} + + + + diff --git a/software/gbt-control-macro/fit_rd_restore_test.cpp b/software/gbt-control-macro/fit_rd_restore_test.cpp new file mode 100644 index 0000000..d195082 --- /dev/null +++ b/software/gbt-control-macro/fit_rd_restore_test.cpp @@ -0,0 +1,103 @@ +/* +Test of RUN restore procedure +Set low PMs tresholds, and turning on/off force idle with random delay + +g++ -g -Wall fit_rd_restore_test.cpp -o fit_rd_restore_test.run && ./fit_rd_restore_test.run + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "ipbus_connection.h" +#include "pmtcm_map.h" + +#include + +int main(int argc, char *argv[]) { + printf("\n\n====================================================\n"); + printf( "================ Readout RUN restore TEST ===============\n"); + printf("====================================================\n\n\n"); + + ipbus_connection slow_control; + slow_control.set_board_ip("172.20.75.180"); + slow_control.set_board_port(50001); + if (slow_control.connect_to_board() < 0) { + printf("Connection to board failed\n"); + return -1; + } + + + uint32_t ctrl_reg[16] = {0}; + + //threshold calibration all modules + const uint32_t trsh_val = 500; + + printf("\n\n-----------------------------------------------------------------\n"); + printf("Writing PMs treshold values ... \n\n"); + for(uint32_t pmtcm_iter = 0; pmtcm_iter < pmtcm_total; pmtcm_iter+=1){ + if (pmtcm_map[pmtcm_iter][2] == 0) continue; + + uint32_t curr_ctrl_addr = ctrl_addr + pmtcm_map[pmtcm_iter][1]; + uint32_t curr_thrs_cal_addr = trhr_calib_ch0 + pmtcm_map[pmtcm_iter][1]; + + bool is_tcm = (pmtcm_iter == 0); + int res = 0; + uint8_t reg_size = 1; + + if(not is_tcm){ + //ctrl_reg[0] = pmtcm_map[pmtcm_iter][4]; + ctrl_reg[0] = trsh_val; + res = slow_control.write_registers(ctrl_reg, reg_size, curr_thrs_cal_addr); + printf("writing %04d to 0x%08x: %d\n\n", ctrl_reg[0], curr_ctrl_addr, res); + } + } + printf("-----------------------------------------------------------------\n\n\n"); + + + + + // Turning on/off force idle board by board in cycle + for(int iter=0; iter <= 1000; iter++){ + for(uint32_t pmtcm_iter = 0; pmtcm_iter < pmtcm_total; pmtcm_iter+=1){ + if (pmtcm_map[pmtcm_iter][2] == 0) continue; + + uint32_t curr_ctrl_addr = ctrl_addr + pmtcm_map[pmtcm_iter][1]; + uint32_t curr_thrs_cal_addr = trhr_calib_ch0 + pmtcm_map[pmtcm_iter][1]; + + bool is_tcm = (pmtcm_iter == 0); + int res = 0; + uint8_t reg_size = 1; + + + ctrl_reg[0] = 0x00500000; // force on + res = slow_control.write_registers(ctrl_reg, reg_size, curr_ctrl_addr); + + unsigned int delay_val = rand()%5000;//microseconds + usleep(delay_val); + + ctrl_reg[0] = 0x00100000; // force off + res = slow_control.write_registers(ctrl_reg, reg_size, curr_ctrl_addr); + + + printf("delay: %dus (%.1f orbits)\n", delay_val, float(delay_val)/89.1); + + } + } + + + + +} + + + + diff --git a/software/gbt-control-macro/ipbus_connection.h b/software/gbt-control-macro/ipbus_connection.h new file mode 100644 index 0000000..eb3fe08 --- /dev/null +++ b/software/gbt-control-macro/ipbus_connection.h @@ -0,0 +1,395 @@ +#ifndef IPBUS_CONNECTION_H +#define IPBUS_CONNECTION_H + +#include +#include "udp_socket.h" +#include "ipbus_format.h" + +#define is_debug_print 0 +#define is_action_print 0 + +class ipbus_connection { + +public: + ipbus_connection(); + ~ipbus_connection(); + + void set_board_port(const unsigned short int port) { + board_port = port; + } + void set_board_ip(const char *ip_addr) { + strcpy(board_ip, ip_addr); + } + + void set_local_port(const unsigned short int port) { + local_port = port; + } + void set_local_ip(const char *ip_addr) { + strcpy(local_ip, ip_addr); + } + + int connect_to_board(); + int request_status(); + + int read_registers(uint32_t *data, uint8_t &nwords, uint32_t addr, bool is_noinc = false); + uint32_t read_single(uint32_t addr); + int write_registers(uint32_t *data, uint8_t &nwords, uint32_t addr); + void write_single(uint32_t data, uint32_t addr); + + void printout_buffer(int nwords) { + for (int word = 0; word < (nwords > bufload ? bufload : nwords); word++) + printf("%i: %08x\n", word, buffer[word]); + } + + udp_socket* get_board_socket() { + return &board_socket; + } + + // static const int buflen = 1024; + static const int buflen = 4096; + uint32_t buffer[buflen]; + int bufload; + +private: + + unsigned short int board_port; + char board_ip[20]; + unsigned short int local_port; + char local_ip[20]; + + unsigned int UDP_PACKET_MTU; + unsigned int next_pk_id; + + + udp_socket board_socket; + ipbus_status_packet board_status; + + int send_buffer(); + int recv_buffer(); + int convert_buffer_to_net() { + for (int word = 0; word < bufload; word++) + buffer[word] = htonl(buffer[word]); + } + int convert_buffer_to_hst() { + for (int word = 0; word < bufload; word++) + buffer[word] = ntohl(buffer[word]); + } + + void empty_buff() { + memset(buffer, 0, sizeof(uint32_t) * buflen); + bufload = 0; + } + ; + +}; + +ipbus_connection::ipbus_connection() { + set_board_port(50001); + set_board_ip("172.20.75.95"); + set_local_port(0); //ANY + set_local_ip("0"); //ANY + + empty_buff(); + +// UDP_PACKET_MTU = 256; + UDP_PACKET_MTU = 1024; + next_pk_id = 0; +} + +ipbus_connection::~ipbus_connection() { + if (board_socket.get_status() == 1) { + board_socket.close_socket(); + } else if (board_socket.get_status() < 0) { + board_socket.accept_error(); + board_socket.close_socket(); + } +} + +int ipbus_connection::send_buffer() { + if (bufload * 4 > UDP_PACKET_MTU) { + printf( + "ipbus_connection::send_buffer WARNING buffer load %u (%u byte) more than MTU %u\n", + bufload, bufload * 4, UDP_PACKET_MTU); + bufload = UDP_PACKET_MTU / 4; + } + + if (is_debug_print) { + printf("ipbus_connection::send_buffer sending buffer:\n"); + printout_buffer(buflen); + }; + convert_buffer_to_net(); + if (is_debug_print) { + printf("ipbus_connection::send_buffer network type:\n"); + printout_buffer(buflen); + }; + + board_socket.send_packet(reinterpret_cast(buffer), 4 * bufload); +} + +int ipbus_connection::recv_buffer() { + empty_buff(); + bufload = board_socket.recv_packet(reinterpret_cast(buffer), + UDP_PACKET_MTU) / 4; + if (is_debug_print) { + printf("ipbus_connection::recv_buffer received buffer:\n"); + printout_buffer(buflen); + }; + convert_buffer_to_hst(); + if (is_debug_print) { + printf("ipbus_connection::recv_buffer host type:\n"); + printout_buffer(buflen); + }; +} + +int ipbus_connection::connect_to_board() { + if (board_socket.get_status() == 1) { + printf("connect_to_board: socket in error state, reseting\n"); + board_socket.accept_error(); + } + + if (board_socket.get_status() == 1) + board_socket.close_socket(); + + printf("\nConnecting to the board ...\n"); + + board_socket.set_local_addr(local_ip, local_port); + board_socket.set_remote_addr(board_ip, board_port); + board_socket.open_socket(); + + return request_status(); +} + +int ipbus_connection::request_status() { + + if (board_socket.get_status() != 1) { + printf("request_status: no connection to board\n"); + return 0; + } + + ipbus_header request_header; + request_header.version = 2; //always 2 + request_header.packet_id = 0; //for status + request_header.byte_order = 0xF; //always F + request_header.packet_type = 1; //status request + + empty_buff(); + buffer[0] = request_header; + bufload = 16; + + printf("\nRequesting board status ...\n"); + send_buffer(); + + recv_buffer(); + board_status.clear(); + board_status = buffer; + + printf("Current status:\n"); + board_status.printout(); + + if (is_debug_print) { + board_status.printhex(); + printf("rceived header: "); + board_status.get_header().printout(); + printf("next header: "); + board_status.get_next_header().printout(); + printf("\n\n"); + } + + if ((board_status.get_header().version != 2)) { + printf("request_status: wrong response header version: %u\n", + board_status.get_header().version); + return -1; + } + + if ((board_status.get_header().packet_type != 1)) { + printf("request_status: wrong response header type: %u\n", + board_status.get_header().packet_type); + return -1; + } + + if ((board_status.get_header().packet_id != 0)) { + printf("request_status: wrong response header ID: %u\n", + board_status.get_header().packet_id); + return -1; + } + + UDP_PACKET_MTU = board_status.cnt_MTU; + next_pk_id = board_status.get_next_header().packet_id; + + return 1; +} + +uint32_t ipbus_connection::read_single(uint32_t addr) +{ + uint8_t single_len = 1; + uint32_t data[1] = { 0 }; + read_registers(data, single_len, addr); + return data[0]; +} + +int ipbus_connection::read_registers(uint32_t *data, uint8_t &nwords, + uint32_t addr, bool is_noinc) { + + if(is_action_print) printf("reading %u registers; base address: 0x%08x\n", nwords, addr); + + if (board_socket.get_status() != 1) { + printf("read_registers: no connection to board\n"); + return 0; + } + + //read response must less than MTU + if (4 * (nwords + 2) > UDP_PACKET_MTU) + nwords = UDP_PACKET_MTU / 4 - 2; + + ipbus_header control_header; + control_header.version = 2; //always 2 + control_header.packet_id = next_pk_id++; //next id + control_header.byte_order = 0xF; //always f + control_header.packet_type = 0; //control + //control_header.host_to_net(); + if (is_debug_print) { + printf("read_registers: reading header: "); + control_header.printhex(); + } + + ipbus_trs_header control_trs_header; + control_trs_header.version = 2; //always 2 + control_trs_header.trnsctn_id = 1; //first transaction + control_trs_header.n_words = nwords; //num of fords + control_trs_header.type_id = is_noinc ? 0x2 : 0x0; //read + control_trs_header.info_code = 0xF; //request + //control_trs_header.host_to_net(); + if (is_debug_print) { + printf("read_registers: reading transaction: "); + control_trs_header.printhex(); + } + + empty_buff(); + buffer[0] = control_header; + buffer[1] = control_trs_header; + buffer[2] = addr; + bufload = 3; + + send_buffer(); + + recv_buffer(); + + ipbus_header response_header = buffer[0]; + ipbus_trs_header response_trs_header = buffer[1]; + + if (((uint32_t) response_header != (uint32_t) control_header)) { + printf("read_registers: wrong response header "); + response_header.printout(); + printf("\nmust be: "); + control_header.printout(); + printf("\n"); + return -1; + } + + if (response_trs_header.info_code != 0) { + printf("read_registers: response transaction error: %s\n", + get_info_code(response_trs_header.info_code)); + return -1; + } + + if (is_debug_print) { + printf("registers readed:\naddr : word\n"); + for (int n = 0; n < nwords; n++) + printf("0x%08x : 0x%08x\n", addr + n, buffer[n + 2]); + + } + + memcpy(data, buffer + 2, nwords * 4); + +} +/* + * IPbus packet header (control_header) + * + * IPbus transaction requests (control_trs_header) + * transaction header + * transaction body + * + */ + +void ipbus_connection::write_single(uint32_t data, uint32_t addr) +{ + uint8_t single_len = 1; + uint32_t data_a[1] = { data }; + write_registers(data_a, single_len, addr); +} + +int ipbus_connection::write_registers(uint32_t *data, uint8_t &nwords, uint32_t addr) { + + //printf("writing %u registers; base address: 0x%08x\n", nwords, addr); + + if (board_socket.get_status() != 1) { + printf("write_registers: no connection to board\n"); + return 0; + } + + //read response must less than MTU + if (4 * (nwords + 3) > UDP_PACKET_MTU) + nwords = UDP_PACKET_MTU / 4 - 3; + + if(is_action_print) + { + printf("writing %u registers; base address: 0x%08x\n", nwords, addr); + for (int n = 0; n < nwords; n++) + printf("0x%08x : 0x%08x\n", addr + n, data[n]); + } + + ipbus_header control_header; // IPbus packet header + control_header.version = 2; //always 2 + control_header.packet_id = next_pk_id++; //next id + control_header.byte_order = 0xF; //always f + control_header.packet_type = 0; //control packet + //control_header.host_to_net(); + if (is_debug_print) { + printf("write_registers: reading header: "); + control_header.printhex(); + } + + ipbus_trs_header control_trs_header; //IPBus Transaction Header + control_trs_header.version = 2; //always 2 + control_trs_header.trnsctn_id = 1; //first transaction + control_trs_header.n_words = nwords; //num of fords + control_trs_header.type_id = 1; //non-incrementing read + control_trs_header.info_code = 0xF; //request + //control_trs_header.host_to_net(); + if (is_debug_print) { + printf("write_registers: writing transaction: "); + control_trs_header.printhex(); + } + + empty_buff(); + buffer[0] = control_header; + buffer[1] = control_trs_header; + buffer[2] = addr; + memcpy(buffer + 3, data, nwords * 4); + bufload = nwords + 3; + + send_buffer(); + + recv_buffer(); + + ipbus_header response_header = buffer[0]; + ipbus_trs_header response_trs_header = buffer[1]; + + if (((uint32_t) response_header != (uint32_t) control_header)) { + printf("write_registers: wrong response header "); + response_header.printout(); + printf("\nmust be: "); + control_header.printout(); + printf("\n"); + return -1; + } + + if (response_trs_header.info_code != 0) { + printf("write_registers: response transaction error: %s\n", + get_info_code(response_trs_header.info_code)); + return -1; + } + +} + +#endif //IPBUS_CONNECTION_H diff --git a/software/gbt-control-macro/ipbus_format.h b/software/gbt-control-macro/ipbus_format.h new file mode 100644 index 0000000..44639b9 --- /dev/null +++ b/software/gbt-control-macro/ipbus_format.h @@ -0,0 +1,293 @@ +#ifndef IPBUS_FORMAT_H_ +#define IPBUS_FORMAT_H_ + +#include +#include +#include +#include +#include + +char* get_info_code(uint8_t code) { + switch (code) { + case 0x0: + return "Request handled successfully by target"; + + case 0x1: + return "Bad header"; + + case 0x4: + return "Bus error on read"; + + case 0x5: + return "Bus error on write"; + + case 0x6: + return "Bus timeout on read (256 IPbus clock cycles, 8us)"; + + case 0x7: + return "Bus timeout on write (256 IPbus clock cycles, 8us)"; + + default: + return "Outbound request"; + + } +} + +void print_by_byte(uint8_t *data, int size) { + + for (int byte = 0; byte < size; byte++) { + if (byte % 4 == 0) + printf("\nb%i: ", byte); + printf("%02x ", *(data + byte)); + //if( (byte % 4 == 0) ) printf("\n"); + } + printf("\n"); +} + +struct ipbus_header { + uint packet_type :4; + uint byte_order :4; + uint packet_id :16; + uint rsvd :4; + uint version :4; + + void printout() { + printf("ver: %u; type: %u; pk ID: %u\n", version, packet_type, + packet_id); + } + void printhex() { + printf("%x\n", *((uint32_t*) this)); + } + void clear() { + version = 0; + rsvd = 0; + packet_id = 0; + packet_type = 0; + byte_order = 0; + } + + ipbus_header() { + clear(); + } + + ipbus_header(uint8_t* buffer) { + *this = *(reinterpret_cast(buffer)); + } + ipbus_header(uint8_t buffer) { + *this = *(reinterpret_cast(&buffer)); + } + operator uint8_t*() { + return reinterpret_cast(this); + } + operator uint8_t() { + return *(reinterpret_cast(this)); + } + ipbus_header operator=(uint8_t* buffer) { + *this = *(reinterpret_cast(buffer)); + return *this; + } + ipbus_header operator=(uint8_t buffer) { + *this = *(reinterpret_cast(&buffer)); + return *this; + } + + ipbus_header(uint32_t* buffer) { + *this = *(reinterpret_cast(buffer)); + } + ipbus_header(uint32_t buffer) { + *this = *(reinterpret_cast(&buffer)); + } + operator uint32_t*() { + return reinterpret_cast(this); + } + operator uint32_t() { + return *(reinterpret_cast(this)); + } + ipbus_header operator=(uint32_t* buffer) { + *this = *(reinterpret_cast(buffer)); + return *this; + } + ipbus_header operator=(uint32_t buffer) { + *this = *(reinterpret_cast(&buffer)); + return *this; + } + + operator char*() { + return reinterpret_cast(this); + } + +}; + +struct ipbus_trs_header { + uint info_code :4; + uint type_id :4; + uint n_words :8; + uint trnsctn_id :12; + uint version :4; + + void printout() { + printf("ver: %u; trns id: %u; n words: %u; type id %u; info code: %u\n", + version, trnsctn_id, n_words, type_id, info_code); + } + void printhex() { + printf("%08x\n", *((uint32_t*) this)); + } + void clear() { + version = 0; + trnsctn_id = 0; + n_words = 0; + type_id = 0; + info_code = 0; + } + + ipbus_trs_header() { + clear(); + } + + ipbus_trs_header(uint8_t* buffer) { + *this = *(reinterpret_cast(buffer)); + } + ipbus_trs_header(uint8_t buffer) { + *this = *(reinterpret_cast(&buffer)); + } + operator uint8_t*() { + return reinterpret_cast(this); + } + operator uint8_t() { + return *(reinterpret_cast(this)); + } + ipbus_trs_header operator=(uint8_t* buffer) { + *this = *(reinterpret_cast(buffer)); + return *this; + } + ipbus_trs_header operator=(uint8_t buffer) { + *this = *(reinterpret_cast(&buffer)); + return *this; + } + + ipbus_trs_header(uint32_t* buffer) { + *this = *(reinterpret_cast(buffer)); + } + ipbus_trs_header(uint32_t buffer) { + *this = *(reinterpret_cast(&buffer)); + } + operator uint32_t*() { + return reinterpret_cast(this); + } + operator uint32_t() { + return *(reinterpret_cast(this)); + } + ipbus_trs_header operator=(uint32_t* buffer) { + *this = *(reinterpret_cast(buffer)); + return *this; + } + ipbus_trs_header operator=(uint32_t buffer) { + *this = *(reinterpret_cast(&buffer)); + return *this; + } + + operator char*() { + return reinterpret_cast(this); + } + +}; + +//status response packet 32*16 bits +struct ipbus_status_packet { + uint header :32; + uint cnt_MTU :32; + uint nResponseBuffers :32; + uint next_pkt_header :32; + uint8_t in_trf_hstr[16]; + uint32_t cntr_pkt_hstr_rcvd[4]; + + uint32_t cntr_pkt_hstr_outg[4]; + + ipbus_status_packet() { + clear(); + } + + ipbus_header get_header() { + return header; + } + ipbus_header get_next_header() { + return next_pkt_header; + } + + void printhex(); + void printout() { + printf("MTU: %u; nResponseBuffers: %u; next pID: %u\n", cnt_MTU, + nResponseBuffers, get_next_header().packet_id); + } + + void clear() { + memset(this, 0, sizeof(*this)); + } + + ipbus_status_packet(uint8_t* buffer) { + *this = *(reinterpret_cast(buffer)); + } + ipbus_status_packet(uint8_t buffer) { + *this = *(reinterpret_cast(&buffer)); + } + operator uint8_t*() { + return reinterpret_cast(this); + } + operator uint8_t() { + return *(reinterpret_cast(this)); + } + ipbus_status_packet operator=(uint8_t* buffer) { + *this = *(reinterpret_cast(buffer)); + return *this; + } + ipbus_status_packet operator=(uint8_t buffer) { + *this = *(reinterpret_cast(&buffer)); + return *this; + } + + ipbus_status_packet(uint32_t* buffer) { + *this = *(reinterpret_cast(buffer)); + } + ipbus_status_packet(uint32_t buffer) { + *this = *(reinterpret_cast(&buffer)); + } + operator uint32_t*() { + return reinterpret_cast(this); + } + operator uint32_t() { + return *(reinterpret_cast(this)); + } + ipbus_status_packet operator=(uint32_t* buffer) { + *this = *(reinterpret_cast(buffer)); + return *this; + } + ipbus_status_packet operator=(uint32_t buffer) { + *this = *(reinterpret_cast(&buffer)); + return *this; + } + + operator char*() { + return reinterpret_cast(this); + } + +}; + +void ipbus_status_packet::printhex() { + printf( + "header %08x; MTU: %08x; nResponseBuffers: %08x; next_pkt_header: %08x\n", + header, cnt_MTU, nResponseBuffers, next_pkt_header); + + printf("Incoming traffic history:\n"); + for (int n = 0; n < 16; n++) + printf("%i: %02x\n", n, in_trf_hstr[n]); + + printf("Control packet history, received:\n"); + for (int n = 0; n < 4; n++) + printf("%i: %08x\n", n, cntr_pkt_hstr_rcvd[n]); + + printf("Control packet history, outgoing:\n"); + for (int n = 0; n < 4; n++) + printf("%i: %08x\n", n, cntr_pkt_hstr_outg[n]); +} + +#endif /* IPBUS_FORMAT_H_ */ diff --git a/software/gbt-control-macro/pmtcm_map.h b/software/gbt-control-macro/pmtcm_map.h new file mode 100644 index 0000000..73ed948 --- /dev/null +++ b/software/gbt-control-macro/pmtcm_map.h @@ -0,0 +1,44 @@ +#ifndef PMTCM_MAP +#define PMTCM_MAP + +const uint32_t trhr_calib_ch0 = 0xB0; +const uint32_t ctrl_addr = 0xD8; +const uint32_t stat_addr = 0xE8; + +char run_lbl[][5] = { "IDLE", "CONT", "TRIG" }; +char run_lbl_g[][20] = { "\x1b[32mIDLE\x1b[0m", "\x1b[32mCONT\x1b[0m", "\x1b[32mTRIG\x1b[0m" }; +char run_lbl_r[][20] = { "\x1b[31mIDLE\x1b[0m", "\x1b[31mCONT\x1b[0m", "\x1b[31mTRIG\x1b[0m" }; +char bcsync_lbl[][30] = { "\x1b[31mSTRT\x1b[0m", "\x1b[32mSYNC\x1b[0m", "\x1b[31mLOST\x1b[0m" }; + + +const int pmtcm_total = 20; +const uint32_t pmtcm_map[pmtcm_total][5] = { + +/***/ +//FEE ID ADDR ON RDon +{0xF000, 0x0000, 1, 1, 0}, +{0xF0A0, 0x0200, 1, 1, 1645}, +{0xF0A1, 0x0400, 0, 1, 1785}, +{0xF0A2, 0x0600, 0, 1, 2200}, +{0xF0A3, 0x0800, 0, 1, 2190}, +{0xF0A4, 0x0A00, 0, 1, 1634}, +{0xF0A5, 0x0C00, 0, 1, 1590}, +{0xF0A6, 0x0E00, 0, 1, 2200}, +{0xF0A7, 0x1000, 0, 1, 1830}, +{0xF0A9, 0x1400, 0, 1, 1903}, +{0xF0C0, 0x1600, 0, 1, 1700}, +{0xF0C1, 0x1800, 0, 1, 1728}, +{0xF0C2, 0x1A00, 0, 1, 2200}, +{0xF0C3, 0x1C00, 0, 1, 1825}, +{0xF0C4, 0x1E00, 0, 1, 1697}, +{0xF0C5, 0x2000, 0, 1, 1772}, +{0xF0C6, 0x2200, 0, 1, 1568}, +{0xF0C7, 0x2400, 0, 1, 1897}, +{0xF0C8, 0x2600, 0, 1, 1431}, +{0xF0C9, 0x2800, 0, 1, 1776} +}; +/***/ + + +#endif // PMTCM_MAP + diff --git a/software/gbt-control-macro/udp_socket.h b/software/gbt-control-macro/udp_socket.h new file mode 100644 index 0000000..f050ecc --- /dev/null +++ b/software/gbt-control-macro/udp_socket.h @@ -0,0 +1,187 @@ +#ifndef UDP_SOCKET_H +#define UDP_SOCKET_H + +#include +#include +#include +#include +#include +#include +#include + +// class open connection to server (FPGA board) +// send packets and receive response +class udp_socket { +public: + udp_socket(); + ~udp_socket(); + + void set_local_addr(const char *ip_addr = "", + const unsigned short int port = -1); + void set_remote_addr(const char *ip_addr = "", + const unsigned short int port = -1); + int open_socket(); + int send_packet(char* packet, const int packet_size); + int recv_packet(char* packet, const int packet_size); + int close_socket(); + + int get_status() { + return status; + } + ; + void accept_error() { + status = 0; + } + ; + +private: + struct sockaddr_in local_addr; + struct sockaddr_in remote_addr; + int sck_connection; + int status; // 1-socket opened; 0-socket closed; -1 error + +}; + +udp_socket::udp_socket() { + //set_local_addr(); + //set_remote_addr(); + status = 0; +} + +udp_socket::~udp_socket() { + close_socket(); +} + +void udp_socket::set_local_addr(const char *ip_addr, + const unsigned short int port) { + memset(&local_addr, 0, sizeof(local_addr)); + local_addr.sin_family = AF_INET; + + if (strlen(ip_addr) < 7) { + local_addr.sin_addr.s_addr = htonl(INADDR_ANY); + } else { + local_addr.sin_addr.s_addr = inet_addr(ip_addr); + } + + if (port <= 0) { + local_addr.sin_port = htons((u_short) 50010); + } else { + local_addr.sin_port = htons((u_short) port); + } + printf("set local address IP: %s:%u\n", inet_ntoa(local_addr.sin_addr), + ntohs(local_addr.sin_port)); +} + +void udp_socket::set_remote_addr(const char *ip_addr, + const unsigned short int port) { + memset(&remote_addr, 0, sizeof(remote_addr)); + remote_addr.sin_family = AF_INET; + + if (strlen(ip_addr) < 7) { + remote_addr.sin_addr.s_addr = htonl(INADDR_ANY); + } else { + remote_addr.sin_addr.s_addr = inet_addr(ip_addr); + } + + if (port <= 0) { + remote_addr.sin_port = htons((u_short) 50005); + } else { + remote_addr.sin_port = htons((u_short) port); + } + printf("set remote address IP: %s:%u\n", inet_ntoa(remote_addr.sin_addr), + ntohs(remote_addr.sin_port)); +} + +int udp_socket::open_socket() { + if (status == -1) { + printf("open_socket: udp_socket in error state\n"); + return 0; + } + + if (status == 1) + close_socket(); + + sck_connection = socket(AF_INET, SOCK_DGRAM, 0); + if (sck_connection < 0) { + printf("open_socket: can't create UDP socket\n"); + status = -1; + return 0; + } else { + printf("open_socket: socket created\n"); + } + + if (bind(sck_connection, (struct sockaddr *) &local_addr, + sizeof(local_addr)) < 0) { + printf("open_socket: bind error\n"); + status = -1; + return 0; + } else { + printf("open_socket: loc address binded\n"); + } + + if (connect(sck_connection, (struct sockaddr *) &remote_addr, + sizeof(remote_addr)) < 0) { + printf("open_socket: connect error\n"); + status = -1; + return 0; + } else { + printf("open_socket: socket connected\n"); + } + + status = 1; + return sck_connection; +} + +int udp_socket::send_packet(char* packet, const int packet_size) { + if (status == -1) { + printf("send_packet: udp_socket in error state\n"); + return 0; + } + + int bt_sent = send(sck_connection, packet, packet_size, 0); + + if (bt_sent != packet_size) { + printf("send_packet: packet size %i; sent %i byte\n", packet_size, + bt_sent); + } + + return bt_sent; +} + +int udp_socket::recv_packet(char* packet, const int packet_size) { + if (status == -1) { + printf("recv_packet: udp_socket in error state\n"); + return 0; + } + + int bt_recv = recv(sck_connection, packet, packet_size, 0); + + if (bt_recv != packet_size) { + //printf("recv_packet: buffer size %i; recv %i byte\n", packet_size, bt_recv); + } + + return bt_recv; +} + +int udp_socket::close_socket() { + if (status == -1) { + printf("close_socket: udp_socket in error state\n"); + return 0; + } + + if (status == 0) + return 1; + + int cl_msg = close(sck_connection); + if (cl_msg < 0) { + printf("close_socket: connect error\n"); + status = -1; + } else { + printf("close_socket: socket closed\n"); + status = 0; + } + return cl_msg; +} + +#endif // UDP_SOCKET_H + diff --git a/software/readout-sim/generate_sim_inputs.py b/software/readout-sim/generate_sim_inputs.py new file mode 100644 index 0000000..561124d --- /dev/null +++ b/software/readout-sim/generate_sim_inputs.py @@ -0,0 +1,553 @@ +''' + +Main function for generating inputs for readout simulation + +Dmitry Finogeev dmitry.finogeev@cern.ch +07/2021 + +''' + +import copy +import pickle + +import lib.constants as cnst +from lib.control_reg import control_reg as ctrl_rec +from lib.control_reg import gen_mode, readout_cmd +from lib.run_generator import run_generator as run_generator + + +def generate_sim_inputs(): + run_len = 4 + + # class instances + test_ctrl_reg = ctrl_rec() + run_gen = run_generator(test_ctrl_reg) + run_gen.reset_file() + run_list = [] + + # common control registers parameters + test_ctrl_reg.data_gen = gen_mode.main_gen + test_ctrl_reg.trg_gen = gen_mode.main_gen + test_ctrl_reg.trg_single_val = 0 + test_ctrl_reg.trg_hbr_rate = 0x3 + test_ctrl_reg.rd_bypass = 0 + test_ctrl_reg.is_hb_response = 1 + test_ctrl_reg.force_idle = 0 + test_ctrl_reg.reset_orbc_sync = 0 + test_ctrl_reg.reset_data_counters = 0 + test_ctrl_reg.reset_gensync = 0 + test_ctrl_reg.reset_gbt_rxerror = 0 + test_ctrl_reg.reset_readout = 0 + test_ctrl_reg.reset_gbt = 0 + test_ctrl_reg.reset_rxph_error = 0 + test_ctrl_reg.RDH_FEEID = 0xAAAA + test_ctrl_reg.RDH_SYS_ID = 0xBB + test_ctrl_reg.RDH_PRT_BIT = 0xCC + + # # RENERATING RUN ======================================== + # run_gen.run_comment = """ + # - BC indicator test RUN + # """ + # test_ctrl_reg.trg_rd_command = readout_cmd.continious + # test_ctrl_reg.bcid_offset = 0x50 + # test_ctrl_reg.data_trg_respond_mask = 0x23 + # test_ctrl_reg.data_bunch_pattern = 0x1 + # test_ctrl_reg.data_bunch_freq = 0x0 + # test_ctrl_reg.data_bc_start = 0x0 + # test_ctrl_reg.trg_pattern_0 = 0x1 + # test_ctrl_reg.trg_pattern_1 = 0x0 + # test_ctrl_reg.trg_cont_val = 0x20 + # test_ctrl_reg.trg_bunch_freq = cnst.orbit_size*3 + # test_ctrl_reg.trg_bc_start = 0x600 + # test_ctrl_reg.trg_data_select = cnst.TRG_const_Cal + # run_gen.ctrl_reg = copy.copy(test_ctrl_reg) + # run_gen.generate_ctrl_pattern(200) + # run_list.append(copy.copy(run_gen)) + # # ======================================================= + + # # RENERATING RUN ======================================== + # run_gen.run_comment = """ + # - HB response OFF test + # """ + # test_ctrl_reg.trg_rd_command = readout_cmd.continious + # test_ctrl_reg.bcid_offset = 0x50 + # test_ctrl_reg.data_trg_respond_mask = cnst.TRG_const_Cal + # test_ctrl_reg.data_bunch_pattern = 0xFF011777 + # test_ctrl_reg.data_bunch_freq = cnst.orbit_size + # test_ctrl_reg.data_bc_start = 0x100 + # test_ctrl_reg.trg_pattern_0 = 0xAAFAAFAF + # test_ctrl_reg.trg_pattern_1 = 0xFFAFFAFF + # test_ctrl_reg.trg_cont_val = cnst.TRG_const_Cal + # test_ctrl_reg.trg_bunch_freq = cnst.orbit_size + # test_ctrl_reg.trg_bc_start = 0x600 + # test_ctrl_reg.trg_data_select = cnst.TRG_const_Cal + # test_ctrl_reg.is_hb_response = 0 + # run_gen.ctrl_reg = copy.copy(test_ctrl_reg) + # run_gen.generate_ctrl_pattern(10) + # run_list.append(copy.copy(run_gen)) + # test_ctrl_reg.is_hb_response = 1 + # # ======================================================= + + # # RENERATING RUN ======================================== + # run_gen.run_comment = """ + # - Readout bypass test + # """ + # test_ctrl_reg.trg_rd_command = readout_cmd.continious + # test_ctrl_reg.bcid_offset = 0x50 + # test_ctrl_reg.data_trg_respond_mask = cnst.TRG_const_Cal + # test_ctrl_reg.data_bunch_pattern = 0xFF011777 + # test_ctrl_reg.data_bunch_freq = cnst.orbit_size + # test_ctrl_reg.data_bc_start = 0x100 + # test_ctrl_reg.trg_pattern_0 = 0xAAFAAFAF + # test_ctrl_reg.trg_pattern_1 = 0xFFAFFAFF + # test_ctrl_reg.trg_cont_val = cnst.TRG_const_Cal + # test_ctrl_reg.trg_bunch_freq = cnst.orbit_size + # test_ctrl_reg.trg_bc_start = 0x600 + # test_ctrl_reg.trg_data_select = cnst.TRG_const_Cal + # test_ctrl_reg.rd_bypass = 1 + # run_gen.ctrl_reg = copy.copy(test_ctrl_reg) + # run_gen.generate_ctrl_pattern(10) + # run_list.append(copy.copy(run_gen)) + # test_ctrl_reg.rd_bypass = 0 + # # ======================================================= + + # # RENERATING RUN ======================================== + # run_gen.run_comment = """ + # - RUN with bcid sync lost simulated error + # + # - FSM ERROR must be presents + # - RUN must be failed + # + # """ + # test_ctrl_reg.trg_rd_command = readout_cmd.continious + # test_ctrl_reg.bcid_offset = 0x100 + # test_ctrl_reg.data_trg_respond_mask = cnst.TRG_const_Cal + # test_ctrl_reg.data_bunch_pattern = 0xFF011777 + # test_ctrl_reg.data_bunch_freq = 0x16 + # test_ctrl_reg.data_bc_start = 0x100 + # test_ctrl_reg.trg_pattern_0 = 0xAAFAAFAF + # test_ctrl_reg.trg_pattern_1 = 0xFFAFFAFF + # test_ctrl_reg.trg_cont_val = cnst.TRG_const_Cal + # test_ctrl_reg.trg_bunch_freq = cnst.orbit_size / 2 + # test_ctrl_reg.trg_bc_start = 0x600 + # test_ctrl_reg.trg_data_select = cnst.TRG_const_Cal + # + # test_ctrl_reg_orbit_jump = copy.copy(test_ctrl_reg) + # test_ctrl_reg_orbit_jump.data_orbit_jump = 1 + # + # run_gen.ctrl_reg = copy.copy(test_ctrl_reg) + # run_gen.generate_ctrl_pattern(2, test_ctrl_reg_orbit_jump) + # run_list.append(copy.copy(run_gen)) + # # ======================================================= + + # # RENERATING RUN ======================================== + # run_gen.run_comment = """ + # - RUN with force idle + # + # - HB could be missed + # - One excess stop bit should be found + # """ + # test_ctrl_reg.trg_rd_command = readout_cmd.continious + # test_ctrl_reg.bcid_offset = 0x100 + # test_ctrl_reg.data_trg_respond_mask = cnst.TRG_const_Cal + # test_ctrl_reg.data_bunch_pattern = 0xFF011777 + # test_ctrl_reg.data_bunch_freq = 0x16 + # test_ctrl_reg.data_bc_start = 0x100 + # test_ctrl_reg.trg_pattern_0 = 0xAAFAAFAF + # test_ctrl_reg.trg_pattern_1 = 0xFFAFFAFF + # test_ctrl_reg.trg_cont_val = cnst.TRG_const_Cal + # test_ctrl_reg.trg_bunch_freq = cnst.orbit_size/2 + # test_ctrl_reg.trg_bc_start = 0x600 + # test_ctrl_reg.trg_data_select = cnst.TRG_const_Cal + # + # test_ctrl_reg_force_idle = copy.copy(test_ctrl_reg) + # test_ctrl_reg_force_idle.force_idle = 1 + # + # run_gen.ctrl_reg = copy.copy(test_ctrl_reg) + # run_gen.generate_ctrl_pattern(6, test_ctrl_reg_force_idle) + # run_list.append(copy.copy(run_gen)) + # # ======================================================= + + # RENERATING RUN ======================================== + run_gen.run_comment = """ + - CONTINIOUS RUN + - test simple run + """ + test_ctrl_reg.trg_rd_command = readout_cmd.continious + test_ctrl_reg.bcid_offset = 0x50 + test_ctrl_reg.data_trg_respond_mask = 0 + test_ctrl_reg.data_bunch_pattern = 0x11111111 + test_ctrl_reg.data_bunch_freq = 0x100 + test_ctrl_reg.data_bc_start = 0x100 + test_ctrl_reg.trg_pattern_0 = 0xAAFAAFAF + test_ctrl_reg.trg_pattern_1 = 0xFFAFFAFF + test_ctrl_reg.trg_cont_val = cnst.TRG_const_Cal + test_ctrl_reg.trg_bunch_freq = 0x120 + test_ctrl_reg.trg_bc_start = 0x600 + test_ctrl_reg.trg_data_select = 0x10 + test_ctrl_reg.is_hb_reject = 0 + run_gen.ctrl_reg = copy.copy(test_ctrl_reg) + run_gen.generate_ctrl_pattern(run_len) + run_list.append(copy.copy(run_gen)) + test_ctrl_reg.is_hb_reject = 0 + # ======================================================= + + # RENERATING RUN ======================================== + run_gen.run_comment = """ + - RUN with force idle + - run recovery test + + - HB must be missed + - One excess stop bit must be found + """ + test_ctrl_reg.trg_rd_command = readout_cmd.continious + test_ctrl_reg.bcid_offset = 0x100 + test_ctrl_reg.data_trg_respond_mask = cnst.TRG_const_Cal + test_ctrl_reg.data_bunch_pattern = 0x66666666 + test_ctrl_reg.data_bunch_freq = 10 + test_ctrl_reg.data_bc_start = 0x100 + test_ctrl_reg.trg_pattern_0 = 0xAAFAAFAF + test_ctrl_reg.trg_pattern_1 = 0xFFAFFAFF + test_ctrl_reg.trg_cont_val = cnst.TRG_const_Cal + test_ctrl_reg.trg_bunch_freq = cnst.orbit_size / 2 + test_ctrl_reg.trg_bc_start = 0x600 + test_ctrl_reg.trg_data_select = cnst.TRG_const_Cal + + test_ctrl_reg_force_idle = copy.copy(test_ctrl_reg) + test_ctrl_reg_force_idle.force_idle = 1 + + run_gen.ctrl_reg = copy.copy(test_ctrl_reg) + run_gen.generate_ctrl_pattern(4, test_ctrl_reg_force_idle) + run_list.append(copy.copy(run_gen)) + # ======================================================= + + # RENERATING RUN ======================================== + run_gen.run_comment = """ + - CONTINIOUS RUN + - HB reject + - DATA GEN TEST + - 2 packets per orbit + - no gaps + - lenght 16 + - lenght 1 + - 48 CLB triggers with data response + - without gaps + - gap = 1 + - 0xFFAFFAA... + """ + test_ctrl_reg.trg_rd_command = readout_cmd.continious + test_ctrl_reg.bcid_offset = 0x50 + test_ctrl_reg.data_trg_respond_mask = cnst.TRG_const_Cal + test_ctrl_reg.data_bunch_pattern = 0x11111111 + test_ctrl_reg.data_bunch_freq = cnst.orbit_size + test_ctrl_reg.data_bc_start = 0x100 + test_ctrl_reg.trg_pattern_0 = 0xAAFAAFAF + test_ctrl_reg.trg_pattern_1 = 0xFFAFFAFF + test_ctrl_reg.trg_cont_val = cnst.TRG_const_Cal + test_ctrl_reg.trg_bunch_freq = cnst.orbit_size + test_ctrl_reg.trg_bc_start = 0x600 + test_ctrl_reg.trg_data_select = cnst.TRG_const_Cal + test_ctrl_reg.is_hb_reject = 1 + run_gen.ctrl_reg = copy.copy(test_ctrl_reg) + run_gen.generate_ctrl_pattern(run_len) + run_list.append(copy.copy(run_gen)) + test_ctrl_reg.is_hb_reject = 0 + # ======================================================= + + + # RENERATING RUN ======================================== + run_gen.run_comment = """ + - Very high trg and data rate + - max bc offset + """ + test_ctrl_reg.trg_rd_command = readout_cmd.continious + test_ctrl_reg.bcid_offset = 0xd00 + test_ctrl_reg.data_trg_respond_mask = 0 + test_ctrl_reg.data_bunch_pattern = 0xFF011777 + test_ctrl_reg.data_bunch_freq = 16 + test_ctrl_reg.data_bc_start = 0x65 + test_ctrl_reg.trg_pattern_0 = 0xAAFAAFAF + test_ctrl_reg.trg_pattern_1 = 0xFFAFFAFF + test_ctrl_reg.trg_cont_val = cnst.TRG_const_Cal + test_ctrl_reg.trg_bunch_freq = 65 + test_ctrl_reg.trg_bc_start = 0x600 + test_ctrl_reg.trg_data_select = cnst.TRG_const_Cal + test_ctrl_reg.is_hb_reject = 0 + run_gen.ctrl_reg = copy.copy(test_ctrl_reg) + run_gen.generate_ctrl_pattern(20) + run_list.append(copy.copy(run_gen)) + test_ctrl_reg.is_hb_reject = 0 + # ======================================================= + + # RENERATING RUN ======================================== + run_gen.run_comment = """ + - CONTINIOUS RUN + - HB reject + - DATA GEN TEST + - 2 packets per orbit + - no gaps + - lenght 16 + - lenght 1 + - 48 CLB triggers with data response + - without gaps + - gap = 1 + - 0xFFAFFAA... + """ + test_ctrl_reg.trg_rd_command = readout_cmd.continious + test_ctrl_reg.bcid_offset = 0x50 + test_ctrl_reg.data_trg_respond_mask = cnst.TRG_const_Cal + test_ctrl_reg.data_bunch_pattern = 0xFF011777 + test_ctrl_reg.data_bunch_freq = cnst.orbit_size + test_ctrl_reg.data_bc_start = 0x100 + test_ctrl_reg.trg_pattern_0 = 0xAAFAAFAF + test_ctrl_reg.trg_pattern_1 = 0xFFAFFAFF + test_ctrl_reg.trg_cont_val = cnst.TRG_const_Cal + test_ctrl_reg.trg_bunch_freq = cnst.orbit_size + test_ctrl_reg.trg_bc_start = 0x600 + test_ctrl_reg.trg_data_select = cnst.TRG_const_Cal + test_ctrl_reg.is_hb_reject = 1 + run_gen.ctrl_reg = copy.copy(test_ctrl_reg) + run_gen.generate_ctrl_pattern(run_len) + run_list.append(copy.copy(run_gen)) + test_ctrl_reg.is_hb_reject = 0 + # ======================================================= + + + # RENERATING RUN ======================================== + run_gen.run_comment = """ + - CONTINIOUS VOID RUN + - RUN without data + """ + test_ctrl_reg.trg_rd_command = readout_cmd.continious + test_ctrl_reg.bcid_offset = 0x50 + test_ctrl_reg.data_trg_respond_mask = 0 + test_ctrl_reg.data_bunch_pattern = 0x0 + test_ctrl_reg.data_bunch_freq = cnst.orbit_size + test_ctrl_reg.data_bc_start = 0x100 + test_ctrl_reg.trg_pattern_0 = 0xAAFAAFAF + test_ctrl_reg.trg_pattern_1 = 0xFFAFFAFF + test_ctrl_reg.trg_cont_val = cnst.TRG_const_Cal + test_ctrl_reg.trg_bunch_freq = cnst.orbit_size + test_ctrl_reg.trg_bc_start = 0x600 + test_ctrl_reg.trg_data_select = cnst.TRG_const_Cal + run_gen.ctrl_reg = copy.copy(test_ctrl_reg) + run_gen.generate_ctrl_pattern(5) + run_list.append(copy.copy(run_gen)) + # ======================================================= + + # RENERATING RUN ======================================== + run_gen.run_comment = """ + - CONTINIOUS RUN + - DATA GEN TEST + - 2 packets per orbit + - no gaps + - lenght 16 + - lenght 1 + - 48 CLB triggers with data response + - without gaps + - gap = 1 + - 0xFFAFFAA... + """ + test_ctrl_reg.trg_rd_command = readout_cmd.continious + test_ctrl_reg.bcid_offset = 0x50 + test_ctrl_reg.data_trg_respond_mask = cnst.TRG_const_Cal + test_ctrl_reg.data_bunch_pattern = 0xFF011777 + test_ctrl_reg.data_bunch_freq = cnst.orbit_size + test_ctrl_reg.data_bc_start = 0x100 + test_ctrl_reg.trg_pattern_0 = 0xAAFAAFAF + test_ctrl_reg.trg_pattern_1 = 0xFFAFFAFF + test_ctrl_reg.trg_cont_val = cnst.TRG_const_Cal + test_ctrl_reg.trg_bunch_freq = cnst.orbit_size + test_ctrl_reg.trg_bc_start = 0x600 + test_ctrl_reg.trg_data_select = cnst.TRG_const_Cal + run_gen.ctrl_reg = copy.copy(test_ctrl_reg) + run_gen.generate_ctrl_pattern(run_len) + run_list.append(copy.copy(run_gen)) + # ======================================================= + + # RENERATING RUN ======================================== + run_gen.run_comment = """ + - CONTINIOUS RUN + - data in first RDH + - 4 X 8 packets per orbit + - no gaps + - lenght 16 + - lenght 1 + - 48 CLB triggers with data response + - without gaps + - gap = 1 + - 0xFFAFFAA... + """ + test_ctrl_reg.trg_rd_command = readout_cmd.continious + test_ctrl_reg.bcid_offset = 0x0 + test_ctrl_reg.data_trg_respond_mask = cnst.TRG_const_Cal + test_ctrl_reg.data_bunch_pattern = 0xFF011777 + test_ctrl_reg.data_bunch_freq = int(cnst.orbit_size / 4) + test_ctrl_reg.data_bc_start = cnst.orbit_size - 2 - test_ctrl_reg.bcid_offset + test_ctrl_reg.trg_pattern_0 = 0xAAFAAFAA + test_ctrl_reg.trg_pattern_1 = 0xFFAFFAFF + test_ctrl_reg.trg_cont_val = cnst.TRG_const_Cal + test_ctrl_reg.trg_bunch_freq = int(cnst.orbit_size / 4) + test_ctrl_reg.trg_bc_start = cnst.orbit_size - 2 - cnst.orbit_size / 2 + test_ctrl_reg.trg_data_select = cnst.TRG_const_Cal + run_gen.ctrl_reg = copy.copy(test_ctrl_reg) + run_gen.generate_ctrl_pattern(run_len) + run_list.append(copy.copy(run_gen)) + # ======================================================= + + # RENERATING RUN ======================================== + run_gen.run_comment = """ + - TRIGGER RUN + - data in first RDH + - 4 X 8 packets per orbit + - no gaps + - lenght 16 + - lenght 1 + - 48 CLB triggers with data response + - without gaps + - gap = 1 + - 0xFFAFFAA... + """ + test_ctrl_reg.trg_rd_command = readout_cmd.trigger + test_ctrl_reg.bcid_offset = 0x0 + test_ctrl_reg.data_trg_respond_mask = cnst.TRG_const_Cal + test_ctrl_reg.data_bunch_pattern = 0xFF011777 + test_ctrl_reg.data_bunch_freq = int(cnst.orbit_size / 4) + test_ctrl_reg.data_bc_start = cnst.orbit_size - 2 - test_ctrl_reg.bcid_offset + test_ctrl_reg.trg_pattern_0 = 0xAAFAAFAA + test_ctrl_reg.trg_pattern_1 = 0xFFAFFAFF + test_ctrl_reg.trg_cont_val = cnst.TRG_const_Cal + test_ctrl_reg.trg_bunch_freq = int(cnst.orbit_size / 4) + test_ctrl_reg.trg_bc_start = cnst.orbit_size - 2 - cnst.orbit_size / 2 + test_ctrl_reg.trg_data_select = cnst.TRG_const_Cal + run_gen.ctrl_reg = copy.copy(test_ctrl_reg) + run_gen.generate_ctrl_pattern(run_len) + run_list.append(copy.copy(run_gen)) + # ======================================================= + + # RENERATING RUN ======================================== + run_gen.run_comment = """ + - CONTINIOUS RUN + - high rate 2MHz, dropping data + - lenght 7 + - 48 CLB triggers with data response + - without gaps + - gap = 1 + - 0xFFAFFAA... + """ + test_ctrl_reg.trg_rd_command = readout_cmd.continious + test_ctrl_reg.bcid_offset = 0x0 + test_ctrl_reg.data_trg_respond_mask = cnst.TRG_const_Cal + test_ctrl_reg.data_bunch_pattern = 0xFF011777 + test_ctrl_reg.data_bunch_freq = 20 + test_ctrl_reg.data_bc_start = cnst.orbit_size - 2 - test_ctrl_reg.bcid_offset + test_ctrl_reg.trg_pattern_0 = 0xAAFAAFAA + test_ctrl_reg.trg_pattern_1 = 0xFFAFFAFF + test_ctrl_reg.trg_cont_val = cnst.TRG_const_Cal + test_ctrl_reg.trg_bunch_freq = int(cnst.orbit_size / 4) + test_ctrl_reg.trg_bc_start = cnst.orbit_size - 2 - cnst.orbit_size / 2 + test_ctrl_reg.trg_data_select = cnst.TRG_const_Cal + run_gen.ctrl_reg = copy.copy(test_ctrl_reg) + run_gen.generate_ctrl_pattern(run_len) + run_list.append(copy.copy(run_gen)) + # ======================================================= + + # RENERATING RUN ======================================== + run_gen.run_comment = """ + - TRIGGER RUN + - high rate 2MHz, dropping data + - lenght 7 + - 48 CLB triggers with data response + - without gaps + - gap = 1 + - 0xFFAFFAA... + """ + test_ctrl_reg.trg_rd_command = readout_cmd.trigger + test_ctrl_reg.bcid_offset = 0x0 + test_ctrl_reg.data_trg_respond_mask = cnst.TRG_const_Cal + test_ctrl_reg.data_bunch_pattern = 0xFF011777 + test_ctrl_reg.data_bunch_freq = 20 + test_ctrl_reg.data_bc_start = cnst.orbit_size - 2 - test_ctrl_reg.bcid_offset + test_ctrl_reg.trg_pattern_0 = 0xAAFAAFAA + test_ctrl_reg.trg_pattern_1 = 0xFFAFFAFF + test_ctrl_reg.trg_cont_val = cnst.TRG_const_Cal + test_ctrl_reg.trg_bunch_freq = int(cnst.orbit_size / 4) + test_ctrl_reg.trg_bc_start = cnst.orbit_size - 2 - cnst.orbit_size / 2 + test_ctrl_reg.trg_data_select = cnst.TRG_const_Cal + run_gen.ctrl_reg = copy.copy(test_ctrl_reg) + run_gen.generate_ctrl_pattern(run_len) + run_list.append(copy.copy(run_gen)) + # ======================================================= + + # RENERATING RUN ======================================== + run_gen.run_comment = """ + - CONTINIOUS RUN + - max rate, should not drop data + - data size 6 (max PM) + + - 6 * 508 = 3048 detector words + - 0xdec - 6*514 = 480 + - 3048 + 480-4= 3524 + - 3524/7 = 503 PM packets per orbit + - 503/8 = 62 banch + - 0xdec/62 = 57 freq + + - 48 CLB triggers; no data response + - without gaps + - gap = 1 + - 0xFFAFFAA... + """ + test_ctrl_reg.trg_rd_command = readout_cmd.trigger + test_ctrl_reg.bcid_offset = 0x0 + test_ctrl_reg.data_trg_respond_mask = 0 + test_ctrl_reg.data_bunch_pattern = 0x66666666 + test_ctrl_reg.data_bunch_freq = 57 + test_ctrl_reg.data_bc_start = cnst.orbit_size - 2 - test_ctrl_reg.bcid_offset + test_ctrl_reg.trg_pattern_0 = 0xAAFAAFAA + test_ctrl_reg.trg_pattern_1 = 0xFFAFFAFF + test_ctrl_reg.trg_cont_val = cnst.TRG_const_Cal + test_ctrl_reg.trg_bunch_freq = int(cnst.orbit_size / 20) + test_ctrl_reg.trg_bc_start = cnst.orbit_size - 2 - cnst.orbit_size / 2 + test_ctrl_reg.trg_data_select = cnst.TRG_const_Cal + run_gen.ctrl_reg = copy.copy(test_ctrl_reg) + run_gen.generate_ctrl_pattern(run_len) + run_list.append(copy.copy(run_gen)) + # ======================================================= + + # RENERATING RUN ======================================== + run_gen.run_comment = """ + - TRIGGER RUN + - extrimly high rate 2MHz with max bcid delay + - lenght 7 + - 48 CLB triggers with data response + - without gaps + - gap = 1 + - 0xFFAFFAA... + """ + test_ctrl_reg.trg_rd_command = readout_cmd.continious + test_ctrl_reg.bcid_offset = 0xd00 + test_ctrl_reg.data_trg_respond_mask = cnst.TRG_const_Cal + test_ctrl_reg.data_bunch_pattern = 0xFF011777 + test_ctrl_reg.data_bunch_freq = 20 + test_ctrl_reg.data_bc_start = cnst.orbit_size - 2 + test_ctrl_reg.trg_pattern_0 = 0xAAFAAFAA + test_ctrl_reg.trg_pattern_1 = 0xFFAFFAFF + test_ctrl_reg.trg_cont_val = cnst.TRG_const_Cal + test_ctrl_reg.trg_bunch_freq = int(cnst.orbit_size / 4) + test_ctrl_reg.trg_bc_start = cnst.orbit_size - 2 - cnst.orbit_size / 2 + test_ctrl_reg.trg_data_select = cnst.TRG_const_Cal + run_gen.ctrl_reg = copy.copy(test_ctrl_reg) + run_gen.generate_ctrl_pattern(run_len) + run_list.append(copy.copy(run_gen)) + # ======================================================= + + # print generated runs + for irun in run_list: irun.print_run_meta() + + # saving run metadata + with open(cnst.filename_runmeta, 'wb') as f: + pickle.dump(run_list, f) + + +if __name__ == '__main__': + generate_sim_inputs() diff --git a/software/readout-sim/lib/RDH_data.py b/software/readout-sim/lib/RDH_data.py deleted file mode 100644 index 7bf227c..0000000 --- a/software/readout-sim/lib/RDH_data.py +++ /dev/null @@ -1,228 +0,0 @@ -# class to work with FIT readout unit control registers - -################################################################ -################################################################ -class detector_event_class: - def __init__(self): - self.dw_list = ["00000000000000000000"] - - self.magic = 0 - self.n_words = 0 - self.is_tcm = 0 - self.phase_err = 0 - self.phase = 0 - self.bc = 0 - self.orbit = 0 - self.ch_pmdata = [[0,""]] - - - - def print_struct(self): - print("=== detector data ===") - print(" magic:", hex(self.magic)) - print(" is_tcm:", hex(self.is_tcm)) - print(" n_words:", hex(self.n_words)) - print(" phase_err:", hex(self.phase_err)) - print(" phase:", hex(self.phase)) - print(" bc:", hex(self.bc)) - print(" orbit:", hex(self.orbit)) - print(" ch_pmdata:", self.ch_pmdata) - - def print_raw(self): - print(self.dw_list) - - def read_data(self, line_list, pos): - self.dw_list = [line_list[pos][-21:-1]] - -# - 20-19 19-18 18-17 17-16 16-15 15-14 14-13 13-12 12-11 11-10 10- 9 9 - 8 8 - 7 7 - 6 6 - 5 5 - 4 4 - 3 3 - 2 2 - 1 1 - -# 79-76 75-72 71-68 67-64 63-60 59-56 55-52 51-48 47-44 43-40 39-36 35-32 31-28 27-24 23-20 19-16 15-12 11- 8 7 - 4 3 - 0 - self.magic = int(self.dw_list[0][-20 : -19], base=16) # [79 - 76] - self.n_words = int(self.dw_list[0][-19 : -18], base=16) # [75 - 72] - self.is_tcm = int(self.dw_list[0][-13 : -12], base=16) # [75 - 72] - pherr_ = int(self.dw_list[0][-12: -11], base=16) # [47 - 44] - self.phase = pherr_&0x7 - self.phase_err = (pherr_&0x8 > 0) - self.orbit = int(self.dw_list[0][-10: -3], base=16) # [39 - 12] - self.bc = int(self.dw_list[0][-3 : ], base=16) # [11 - 0] - - self.ch_pmdata = [] - for iword in range(1, self.n_words+1): - self.dw_list.append(line_list[pos + iword][-21:-1]) - if self.is_tcm == 0: - ch1_no = int(self.dw_list[iword][-20: -19], base=16) - ch1_data = int(self.dw_list[iword][-19: -10], base=16) - ch2_no = int(self.dw_list[iword][-10: -9], base=16) - ch2_data = int(self.dw_list[iword][-9 : ], base=16) - - if ch1_no > 0: self.ch_pmdata.append([ch1_no, ch1_data]) - if ch2_no > 0: self.ch_pmdata.append([ch2_no, ch2_data]) - else: - ch_data = int(self.dw_list[iword][-19: ], base=16) - self.ch_pmdata.append([iword, ch_data]) - - - return pos+1+self.n_words -################################################################ -################################################################ -class rdh_header_class: - def __init__(self): - self.dw0 = "00000000000000000000" - self.dw1 = "00000000000000000000" - self.dw2 = "00000000000000000000" - self.dw3 = "00000000000000000000" - - self.header_version = 0 - self.header_size = 0 - self.block_lenght = 0 - self.fee_id = 0 - self.priority_bit = 0 - self.bc = 0 - self.orbit = 0 - self.trg_type = 0 - self.trg_orbit = 0 - self.trg_bc = 0 - self.page_counter = 0 - self.stop_bit = 0 - self.det_field = 0 - self.par_bit = 0 - - - - def print_struct(self): - print("======== RDH ========") - print(" header_version:", hex(self.header_version)) - print(" header_size:", hex(self.header_size)) - print(" block_lenght:", hex(self.block_lenght)) - print(" fee_id:", hex(self.fee_id)) - print(" priority_bit:", hex(self.priority_bit)) - print(" bc:", hex(self.bc)) - print(" orbit:", hex(self.orbit)) - print(" trg_type:", hex(self.trg_type)) - print(" trg_orbit:", hex(self.trg_orbit)) - print(" trg_bc:", hex(self.trg_bc)) - print(" page_counter:", hex(self.page_counter)) - print(" stop_bit:", hex(self.stop_bit)) - print(" det_field:", hex(self.det_field)) - print(" par_bit:", hex(self.par_bit)) - - def print_raw(self): - print(self.dw0) - print(self.dw1) - print(self.dw2) - print(self.dw3) - - def read_data(self, line_list, pos): - #print(line_list[pos][-3:-1]) - #print( int("0x"+self.dw0[-3:-1], base=16) ) - #print(line_list[pos][-5:-3]) - #dw0 = int("0x"+line_list[pos][-5:-1], base=16) - self.dw0 = line_list[pos][-21:-1] - self.dw1 = line_list[pos+1][-21:-1] - self.dw2 = line_list[pos+2][-21:-1] - self.dw3 = line_list[pos+3][-21:-1] - - - self.header_version = int(self.dw0[-2: ], base=16) # [7 - 0] - - if self.header_version == 0x4: -# - 20-19 19-18 18-17 17-16 16-15 15-14 14-13 13-12 12-11 11-10 10- 9 9 - 8 8 - 7 7 - 6 6 - 5 5 - 4 4 - 3 3 - 2 2 - 1 1 - -# 79-76 75-72 71-68 67-64 63-60 59-56 55-52 51-48 47-44 43-40 39-36 35-32 31-28 27-24 23-20 19-16 15-12 11- 8 7 - 4 3 - 0 - self.header_size = int(self.dw0[-4 : -2], base=16) # [15 - 8] - self.block_lenght = int(self.dw0[-8 : -4], base=16) # [31 - 16] - self.fee_id = int(self.dw0[-12: -8], base=16) # [47 - 32] - self.priority_bit = int(self.dw0[-14:-12], base=16) # [55 - 48] - - self.trg_orbit = int(self.dw1[-8 : ], base=16) # [31 - 0] - self.orbit = int(self.dw1[-16: -8], base=16) # [63 - 32] - - self.trg_bc = int(self.dw2[-3 : ], base=16) # [11 - 0] - self.bc = int(self.dw2[-7 : -4], base=16) # [27 - 16] - self.trg_type = int(self.dw2[-16: -8], base=16) # [63 - 32] - - self.det_field = int(self.dw3[-4 : ], base=16) # [15 - 0] - self.par_bit = int(self.dw3[-8 : -4], base=16) # [31 - 16] - self.stop_bit = int(self.dw3[-10: -8], base=16) # [39 - 32] - self.page_counter = int(self.dw3[-14:-10], base=16) # [55 - 40] - - - if self.header_version == 0x6: - # - 20-19 19-18 18-17 17-16 16-15 15-14 14-13 13-12 12-11 11-10 10- 9 9 - 8 8 - 7 7 - 6 6 - 5 5 - 4 4 - 3 3 - 2 2 - 1 1 - - # 79-76 75-72 71-68 67-64 63-60 59-56 55-52 51-48 47-44 43-40 39-36 35-32 31-28 27-24 23-20 19-16 15-12 11- 8 7 - 4 3 - 0 - self.header_size = int(self.dw0[-4: -2], base=16) - self.fee_id = int(self.dw0[-8: -4], base=16) - self.priority_bit = int(self.dw0[-10:-8], base=16) - self.block_lenght = int(self.dw0[-20: -16], base=16) - - self.bc = int(self.dw1[-3:], base=16) - self.orbit = int(self.dw1[-16: -8], base=16) - - self.trg_type = int(self.dw2[-8:], base=16) - self.page_counter = int(self.dw2[-12:-8], base=16) - self.stop_bit = int(self.dw2[-14: -12], base=16) - - self.det_field = int(self.dw3[-8:], base=16) - self.par_bit = int(self.dw3[-12: -8], base=16) - - # not used in RDH v6 - self.trg_orbit = 0 - self.trg_bc = 0 - - - return pos+4 -################################################################ -################################################################ -class rdh_trailer_class: - def __init__(self): - self.dw = "00000000000000000000" - self.magic = 0 - - def print_raw(self): - print(self.dw) - - def print_struct(self): - print("======== trailer ========") - print("magic:", hex(self.magic)) - - def read_data(self, line_list, pos): - self.dw = line_list[pos][-21:-1] - self.magic = int(self.dw[-20:-16], base=16) - return pos+1 -################################################################ -################################################################ -class rdh_data_class: - def __init__(self): - self.rdh_header = rdh_header_class() - self.event_list = [] - self.rdh_trailer = rdh_trailer_class() - - def print_raw(self): - self.rdh_header.print_raw() - for event in self.event_list: event.print_raw() - self.rdh_trailer.print_raw() - - - def print_struct(self): - print("===== RDH DATA =====") - self.rdh_header.print_struct() - for event in self.event_list: event.print_struct() - self.rdh_trailer.print_struct() - - def read_data(self, line_list, pos): - dyn_pos = self.rdh_header.read_data(line_list, pos) - n_dw_in_packet = self.rdh_header.block_lenght / 16 - - packet_start = dyn_pos - while dyn_pos < packet_start + n_dw_in_packet: - dyn_event = detector_event_class() - dyn_pos = dyn_event.read_data(line_list, dyn_pos) - self.event_list.append(dyn_event) - - dyn_pos = self.rdh_trailer.read_data(line_list,dyn_pos) - - return dyn_pos -################################################################ -################################################################ - - - - diff --git a/software/readout-sim/lib/__pycache__/control_reg.cpython-38.pyc b/software/readout-sim/lib/__pycache__/control_reg.cpython-38.pyc deleted file mode 100644 index 8051033..0000000 Binary files a/software/readout-sim/lib/__pycache__/control_reg.cpython-38.pyc and /dev/null differ diff --git a/software/readout-sim/lib/constants.py b/software/readout-sim/lib/constants.py new file mode 100644 index 0000000..e9457ba --- /dev/null +++ b/software/readout-sim/lib/constants.py @@ -0,0 +1,38 @@ +''' + +Testbench constants + +Dmitry Finogeev dmitry.finogeev@cern.ch +07/2021 + +''' + +# files path constants +# control register as simulation inputs +filename_ctrlreg = 'sim_data/sim_in_ctrlreg.txt' +# generated runs meta info +filename_runmeta = 'sim_data/runmeta.pickle' +# readout simulation ouput +filename_simout = 'sim_data/sim_out_data.txt' + +# readout constants +TRG_const_void = 0x00000000 +TRG_const_Orbit = 0x00000001 # 0 +TRG_const_HB = 0x00000002 # 1 +TRG_const_HBr = 0x00000004 # 2 +TRG_const_HC = 0x00000008 # 3 +TRG_const_Ph = 0x00000010 # 4 +TRG_const_PP = 0x00000020 # 5 +TRG_const_Cal = 0x00000040 # 6 +TRG_const_SOT = 0x00000080 # 7 +TRG_const_EOT = 0x00000100 # 8 +TRG_const_SOC = 0x00000200 # 9 +TRG_const_EOC = 0x00000400 # 10 +TRG_const_TF = 0x00000800 # time frame delimiter +TRG_const_FErst = 0x00001000 # FEE reset +TRG_const_RT = 0x00002000 # Run Type; 1=Cont, 0=Trig +TRG_const_RS = 0x00004000 # Running State; 1=Running + +orbit_size = 0xdec + +max_rdh_payload = 512 diff --git a/software/readout-sim/lib/control_reg.py b/software/readout-sim/lib/control_reg.py index aa6e6be..0a22d0e 100644 --- a/software/readout-sim/lib/control_reg.py +++ b/software/readout-sim/lib/control_reg.py @@ -1,5 +1,16 @@ -# class to work with FIT readout unit control registers -from aenum import Enum +''' + +write / reading readout control registers + +Dmitry Finogeev dmitry.finogeev@cern.ch +07/2021 + +''' + +from enum import Enum + +import bitstring + import lib.pylog as pylog log = pylog.log @@ -10,225 +21,183 @@ class gen_mode(Enum): main_gen = 1 tx_gen = 2 + def __str__(self): + return self.name + + @property + def counter(self): + return self.value + + class readout_cmd(Enum): idle = 0 continious = 1 trigger = 2 + def __str__(self): + return self.name + + @property + def counter(self): + return self.value -class control_reg_class: + +class control_reg: def __init__(self): - self.data_gen = gen_mode.main_gen + self.data_gen = gen_mode.no_gen self.data_trg_respond_mask = 0 - self.data_bunch_pattern = 0x0 - self.data_bunch_freq = 0x0 - self.data_freq_offset = 0 + self.data_bunch_pattern = 0 + self.data_bunch_freq = 0 + self.data_bc_start = 0 + self.data_orbit_jump = 0 - self.trg_gen = gen_mode.main_gen + self.trg_gen = gen_mode.no_gen self.trg_rd_command = readout_cmd.idle - self.trg_single_val = 0 self.trg_pattern_0 = 0 self.trg_pattern_1 = 0 self.trg_cont_val = 0 self.trg_bunch_freq = 0 - self.trg_freq_offset = 0 + self.trg_bc_start = 0 + self.trg_hbr_rate = 0 self.rd_bypass = 0 - self.is_hb_response = 1 + self.is_hb_response = 0 + self.is_hb_reject = 0 self.trg_data_select = 0 - self.strt_rdmode_lock = 0 + self.force_idle = 0 + self.rxclk_sync_shift = 0 + + self.bcid_offset = 0 - self.bcid_delay = 0xF - self.crutrg_delay_comp = 0xF - self.max_data_payload = 0xFF self.reset_orbc_sync = 0 - self.reset_drophit_counter = 0 - self.reset_gen_offset = 0 + self.reset_data_counters = 0 + self.reset_gensync = 0 self.reset_gbt_rxerror = 0 + self.reset_readout = 0 self.reset_gbt = 0 self.reset_rxph_error = 0 + self.reset_err_report = 0 - self.RDH_feeid = 0xAAAA - self.RDH_par = 0xCCCC - self.RDH_detf = 0xDDDD - - - def is_equal(self, other): - if self.data_gen != other.data_gen: return 0 - if self.data_trg_respond_mask != other.data_trg_respond_mask: return 0 - if self.data_bunch_pattern != other.data_bunch_pattern: return 0 - if self.data_bunch_freq != other.data_bunch_freq: return 0 - if self.data_freq_offset != other.data_freq_offset: return 0 - if self.trg_gen != other.trg_gen: return 0 - if self.trg_rd_command != other.trg_rd_command: return 0 - if self.trg_single_val != other.trg_single_val: return 0 - if self.trg_pattern_0 != other.trg_pattern_0: return 0 - if self.trg_pattern_1 != other.trg_pattern_1: return 0 - if self.trg_cont_val != other.trg_cont_val: return 0 - if self.trg_bunch_freq != other.trg_bunch_freq: return 0 - if self.trg_freq_offset != other.trg_freq_offset: return 0 - if self.rd_bypass != other.rd_bypass: return 0 - if self.is_hb_response != other.is_hb_response: return 0 - if self.trg_data_select != other.trg_data_select: return 0 - if self.strt_rdmode_lock != other.strt_rdmode_lock: return 0 - if self.bcid_delay != other.bcid_delay: return 0 - if self.crutrg_delay_comp != other.crutrg_delay_comp: return 0 - if self.max_data_payload != other.max_data_payload: return 0 - if self.reset_orbc_sync != other.reset_orbc_sync: return 0 - if self.reset_drophit_counter != other.reset_drophit_counter: return 0 - if self.reset_gen_offset != other.reset_gen_offset: return 0 - if self.reset_gbt_rxerror != other.reset_gbt_rxerror: return 0 - if self.reset_gbt != other.reset_gbt: return 0 - if self.reset_rxph_error != other.reset_rxph_error: return 0 - if self.RDH_feeid != other.RDH_feeid: return 0 - if self.RDH_par != other.RDH_par: return 0 - if self.RDH_detf != other.RDH_detf: return 0 - return 1 - + self.RDH_FEEID = 0 + self.RDH_SYS_ID = 0 + self.RDH_PRT_BIT = 0 def print_struct(self): log.info("======== control reg ========") log.info("data generator param:") - log.info(" data_gen: %s"%(self.data_gen)) - log.info(" data_trg_respond_mask:%s"%( hex(self.data_trg_respond_mask))) - log.info(" data_bunch_pattern: %s"%( hex(self.data_bunch_pattern))) - log.info(" data_bunch_freq: %s"%( hex(self.data_bunch_freq))) - log.info(" data_freq_offset: %s"%( hex(self.data_freq_offset))) + log.info(" data_gen: %s" % (self.data_gen)) + log.info(" data_trg_respond_mask:%s" % (hex(self.data_trg_respond_mask))) + log.info(" data_bunch_pattern: %s" % (hex(self.data_bunch_pattern))) + log.info(" data_bunch_freq: %s" % (hex(self.data_bunch_freq))) + log.info(" data_freq_offset: %s" % (hex(self.data_bc_start))) log.info("trigger generator param:") - log.info(" trg_gen: %s"%( self.trg_gen)) - log.info(" trg_rd_command: %s"%( self.trg_rd_command)) - log.info(" trg_pattern_0: %s"%( hex(self.trg_pattern_0))) - log.info(" trg_pattern_1: %s"%( hex(self.trg_pattern_1))) - log.info(" trg_cont_val: %s"%( hex(self.trg_cont_val))) - log.info(" trg_bunch_freq: %s"%( hex(self.trg_bunch_freq))) - log.info(" trg_freq_offset: %s"%( hex(self.trg_freq_offset))) + log.info(" trg_gen: %s" % (self.trg_gen)) + log.info(" trg_rd_command: %s" % (self.trg_rd_command)) + log.info(" trg_pattern_0: %s" % (hex(self.trg_pattern_0))) + log.info(" trg_pattern_1: %s" % (hex(self.trg_pattern_1))) + log.info(" trg_cont_val: %s" % (hex(self.trg_cont_val))) + log.info(" trg_bunch_freq: %s" % (hex(self.trg_bunch_freq))) + log.info(" trg_freq_offset: %s" % (hex(self.trg_bc_start))) + log.info(" trg_hbr_rate: %s" % (hex(self.trg_hbr_rate))) log.info("readout param:") - log.info(" rd_bypass: %s"%( hex(self.rd_bypass))) - log.info(" is_hb_response: %s"%( hex(self.is_hb_response))) - log.info(" trg_data_select: %s"%( hex(self.trg_data_select))) - log.info(" strt_rdmode_lock: %s"%( hex(self.strt_rdmode_lock))) + log.info(" rd_bypass: %s" % (hex(self.rd_bypass))) + log.info(" is_hb_response: %s" % (hex(self.is_hb_response))) + log.info(" is_hb_rject: %s" % (hex(self.is_hb_reject))) + log.info(" trg_data_select: %s" % (hex(self.trg_data_select))) + log.info(" strt_rdmode_lock: %s" % (hex(self.force_idle))) log.info("delay param:") - log.info(" bcid_delay: %s"%( hex(self.bcid_delay))) - log.info(" crutrg_delay_comp: %s"%( hex(self.crutrg_delay_comp))) - log.info(" max_data_payload: %s"%( hex(self.max_data_payload))) + log.info(" bcid_offset: %s" % (hex(self.bcid_offset))) log.info("reset param:") - log.info(" reset_orbc_sync: %s"%( hex(self.reset_orbc_sync))) - log.info(" reset_drophit_counter: %s"%( hex(self.reset_drophit_counter))) - log.info(" reset_gen_offset: %s"%( hex(self.reset_gen_offset))) - log.info(" reset_gbt_rxerror: %s"%( hex(self.reset_gbt_rxerror))) - log.info(" reset_gbt: %s"%( hex(self.reset_gbt))) - log.info(" reset_rxph_error: %s"%( hex(self.reset_rxph_error))) + log.info(" reset_orbc_sync: %s" % (hex(self.reset_orbc_sync))) + log.info(" reset_data_counters: %s" % (hex(self.reset_data_counters))) + log.info(" reset_gensync: %s" % (hex(self.reset_gensync))) + log.info(" reset_gbt_rxerror: %s" % (hex(self.reset_gbt_rxerror))) + log.info(" reset_gbt: %s" % (hex(self.reset_gbt))) + log.info(" reset_readout: %s" % (hex(self.reset_readout))) + log.info(" reset_rxph_error: %s" % (hex(self.reset_rxph_error))) + log.info(" reset_err_report: %s" % (hex(self.reset_err_report))) log.info("RDH param:") - log.info(" RDH_feeid: %s"%( hex(self.RDH_feeid))) - log.info(" RDH_par: %s"%( hex(self.RDH_par))) - log.info(" RDH_detf: %s"%( hex(self.RDH_detf))) + log.info(" RDH_feeid: %s" % (hex(self.RDH_FEEID))) + log.info(" RDH_SYS_ID: %s" % (hex(self.RDH_SYS_ID))) + log.info(" RDH_PRT_BIT: %s" % (hex(self.RDH_PRT_BIT))) def get_reg(self): - reg_00 = 0xF&self.data_gen.value - reg_00 = reg_00 + ((0xF&self.trg_gen.value) << 4) - - reset_ctrl = (0x1&self.reset_orbc_sync)+ \ - ((0x1&self.reset_drophit_counter) << 1) + \ - ((0x1 & self.reset_gen_offset) << 2) + \ - ((0x1 & self.reset_gbt_rxerror) << 3) + \ - ((0x1 & self.reset_gbt) << 4) + \ - ((0x1 & self.reset_gbt_rxerror) << 5) - reg_00 = reg_00 + ((0xFF&reset_ctrl) << 8) - - reg_00 = reg_00 + ((0xF & self.trg_rd_command.value) << 16) - - rd_mode = (0x1&self.is_hb_response)+ \ - ((0x1&self.rd_bypass) << 1) + \ - ((0x1&self.strt_rdmode_lock) << 2) - - reg_00 = reg_00 + ((0xF&rd_mode) << 20) - - - register = [] - register.append( reg_00 ) - register.append( 0xFFFFFFFF&self.data_trg_respond_mask) - register.append( 0xFFFFFFFF&self.data_bunch_pattern) - register.append( 0xFFFFFFFF&self.trg_single_val) - register.append( 0xFFFFFFFF&self.trg_pattern_1) - register.append( 0xFFFFFFFF&self.trg_pattern_0) - register.append( 0xFFFFFFFF&self.trg_cont_val) - - register.append( ((0xFFFF&self.trg_bunch_freq)<<16) + (0xFFFF&self.data_bunch_freq) ) - register.append( ((0xFFF&self.trg_freq_offset)<<16) + (0xFFF&self.data_freq_offset) ) - register.append( ((0xFFFF&self.RDH_feeid)<<16) + (0xFFFF&self.RDH_par) ) - register.append( ((0xFFFF&self.max_data_payload)<<16) + (0xFFFF&self.RDH_detf) ) - register.append( ((0xFFFF&self.crutrg_delay_comp)<<16) + (0xFFFF&self.bcid_delay) ) - register.append( 0xFFFFFFFF&self.trg_data_select) - return register - - def get_reg_line(self): - return ' '.join( [str(x) for x in self.get_reg()]) - + + bitarray = [] + + reset_field = bitstring.pack('8*uint:1', self.reset_err_report, self.reset_readout, self.reset_rxph_error, self.reset_gbt, + self.reset_gbt_rxerror, + self.reset_gensync, self.reset_data_counters, self.reset_orbc_sync) + rd_mode = bitstring.pack('6*uint:1', self.data_orbit_jump, self.rxclk_sync_shift, self.is_hb_reject, self.force_idle, self.rd_bypass, self.is_hb_response) + + bitarray.append( + bitstring.pack('uint:6=0, uint:6, uint:4, uint:8, 2*uint:4', rd_mode.uint, self.trg_rd_command.value, + reset_field.uint, self.trg_gen.value, self.data_gen.value)) + bitarray.append(bitstring.pack('uint:32', self.data_trg_respond_mask)) + bitarray.append(bitstring.pack('uint:32', self.data_bunch_pattern)) + bitarray.append(bitstring.pack('uint:32=0')) + bitarray.append(bitstring.pack('uint:32', self.trg_pattern_1)) + bitarray.append(bitstring.pack('uint:32', self.trg_pattern_0)) + bitarray.append(bitstring.pack('uint:32', self.trg_cont_val)) + + bitarray.append(bitstring.pack('2*uint:16', self.trg_bunch_freq, self.data_bunch_freq)) + bitarray.append(bitstring.pack('uint:4, uint:12, uint:16', self.trg_hbr_rate, self.trg_bc_start, self.data_bc_start)) + bitarray.append(bitstring.pack('2*uint:8, uint:16', self.RDH_PRT_BIT, self.RDH_SYS_ID, self.RDH_FEEID)) + bitarray.append(bitstring.pack('uint:32=0')) + bitarray.append(bitstring.pack('uint:20=0, uint:12', self.bcid_offset)) + bitarray.append(bitstring.pack('uint:32', self.trg_data_select)) + + return bitarray + + def set_reg(self, bitarray): + + self.data_gen = gen_mode(bitarray[0][-4:].uint) + self.trg_gen = gen_mode(bitarray[0][-8:-4].uint) + self.reset_orbc_sync = bitarray[0][-9:-8].uint + self.reset_data_counters = bitarray[0][-10:-9].uint + self.reset_gensync = bitarray[0][-11:-10].uint + self.reset_gbt_rxerror = bitarray[0][-12:-11].uint + self.reset_gbt = bitarray[0][-13:-12].uint + self.reset_rxph_error = bitarray[0][-14:-13].uint + self.reset_readout = bitarray[0][-15:-14].uint + self.trg_rd_command = readout_cmd(bitarray[0][-20:-16].uint) + self.is_hb_response = bitarray[0][-21:-20].uint + self.rd_bypass = bitarray[0][-22:-21].uint + self.force_idle = bitarray[0][-23:-22].uint + self.is_hb_reject = bitarray[0][-24:-23].uint + self.rxclk_sync_shift = bitarray[0][-25:-24].uint + self.data_orbit_jump = bitarray[0][-26:-25].uint + + self.data_trg_respond_mask = bitarray[1][:].uint + self.data_bunch_pattern = bitarray[2][:].uint + self.trg_pattern_1 = bitarray[4][:].uint + self.trg_pattern_0 = bitarray[5][:].uint + self.trg_cont_val = bitarray[6][:].uint + self.data_bunch_freq = bitarray[7][-16:].uint + self.trg_bunch_freq = bitarray[7][-32:-16].uint + self.data_bc_start = bitarray[8][-16:].uint + self.trg_bc_start = bitarray[8][-32:-16].uint + self.RDH_SYS_ID = bitarray[9][-24:-16].uint + self.RDH_FEEID = bitarray[9][-16:].uint + self.RDH_PRT_BIT = bitarray[10][-32:-24].uint + self.bcid_offset = bitarray[11][-12:].uint + self.trg_data_select = bitarray[12][:].uint + def get_reg_line_16(self): res_str = "" for ireg in self.get_reg(): - res_str = res_str + str( (0xFFFF0000&ireg)>>16 ) + " " - res_str = res_str + str(0xFFFF & ireg) + " " + res_str += str(ireg[-32:-16].uint) + " " + str(ireg[-16:].uint) + " " return res_str - def get_reg_line_hex(self): - return ' '.join( [hex(x) for x in self.get_reg()]) - - def read_reg_line_16(self, line = "0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0"): + def set_reg_line_16(self, line): line_regs = line.split(" ") - regs = [] - for ireg in range(0, len(line_regs)-1, 2): - reg = ( (0xFFFF&int(line_regs[ireg])) << 16) + (0xFFFF & int(line_regs[ireg+1]) ) - regs.append(reg) - - self.data_gen = gen_mode( 0xF®s[0] ) - self.trg_gen = gen_mode( (0xF0®s[0])>>4 ) - self.reset_orbc_sync = 0x1&(regs[0]>>8) - self.reset_drophit_counter = 0x1&(regs[0]>>9) - self.reset_gen_offset = 0x1&(regs[0]>>10) - self.reset_gbt_rxerror = 0x1&(regs[0]>>11) - self.reset_gbt = 0x1&(regs[0]>>12) - self.reset_rxph_error = 0x1&(regs[0]>>13) - self.trg_rd_command = readout_cmd( (0xF0000®s[0])>>16) - self.is_hb_response = 0x1&(regs[0]>>20) - self.rd_bypass = 0x1&(regs[0]>>21) - self.strt_rdmode_lock = 0x1&(regs[0]>>22) - - self.data_trg_respond_mask = regs[1] - self.data_bunch_pattern = regs[2] - self.trg_single_val = regs[3] - self.trg_pattern_1 = regs[4] - self.trg_pattern_0 = regs[5] - self.trg_cont_val = regs[6] - self.data_bunch_freq = (0xFFFF®s[7]) - self.trg_bunch_freq = (0xFFFF0000®s[7])>>16 - self.data_freq_offset = (0xFFF®s[8]) - self.trg_freq_offset = (0xFFF0000®s[8])>>16 - self.RDH_par = (0xFFFF®s[9]) - self.RDH_feeid = (0xFFFF0000®s[9])>>16 - self.RDH_detf = (0xFFFF®s[10]) - self.max_data_payload = (0xFFFF0000®s[10])>>16 - self.bcid_delay = (0xFFFF®s[11]) - self.crutrg_delay_comp = (0xFFFF0000®s[11])>>16 - self.trg_data_select = regs[12] - - def print_raw(self): - print(self.get_reg_line_hex()) - - - - - - - - - - - - + bitarray = [] + for ireg in range(0, len(line_regs) - 1, 2): + bitarray.append(bitstring.pack('0x00000000, 2*uint:16', int(line_regs[ireg]), int(line_regs[ireg + 1]))) + self.set_reg(bitarray) diff --git a/software/readout-sim/lib/gen_simulation.py b/software/readout-sim/lib/gen_simulation.py deleted file mode 100644 index 7d38caf..0000000 --- a/software/readout-sim/lib/gen_simulation.py +++ /dev/null @@ -1,104 +0,0 @@ -# class to work with FIT readout unit control registers - -import lib.control_reg as cntrl_reg -import lib.status_reg as stat_reg -import lib.pylog as pylog -import lib.readout_constants as rd_const - -log = pylog.log - - -class gen_simulation_class: - def __init__(self, ctrl_data_list, status_data_list): - - # data set - self.ctrl_data_list = ctrl_data_list - self.status_data_list = status_data_list - - # simulation results - self.ntotal_reset = 0 - self.trigger_val_list = [] - - -# def print_info(self): - - - def sim_cont_trigger(self): - # simulation continious trigger generator - trg_gen_fsm = 0 # 0 - start; 1 - reset signal done, waiting hb; 2 - counting offset; 3 - trigger period - freq_offset_cnt = 0 - period_cnt = 0 - pattern_cnt = 0 # 0: waiting period - - # main simulation loop ----------------------------------------------- - dyn_ctrl_reg = cntrl_reg.control_reg_class() - dyn_stat_reg = stat_reg.status_reg_class() - - curr_pos = 0 - while curr_pos < len(self.ctrl_data_list): - dyn_ctrl_reg.read_reg_line_16(self.ctrl_data_list[curr_pos]) - dyn_stat_reg.read_reg_line_hex(self.status_data_list[curr_pos]) - - # reset procedure ----------------------------- - if (trg_gen_fsm == 1) and (dyn_stat_reg.cru_trigger & rd_const.TRG_const_HB > 0): - trg_gen_fsm = 2 - freq_offset_cnt = 0 - self.ntotal_reset += 1 - - if (dyn_ctrl_reg.reset_gen_offset == 1): - trg_gen_fsm = 1 - - if (trg_gen_fsm == 2) and (freq_offset_cnt == dyn_ctrl_reg.trg_freq_offset): - trg_gen_fsm = 3 - freq_offset_cnt = 0 - period_cnt = 0 - elif (trg_gen_fsm == 2): - freq_offset_cnt += 1 - - - - - if (trg_gen_fsm == 3): - if (period_cnt < dyn_ctrl_reg.trg_bunch_freq): - period_cnt += 1 - else: - period_cnt = 0 - pattern_cnt = 1 - - - if (pattern_cnt > 0) and (pattern_cnt <= 64): - if (pattern_cnt <= 32): - if (dyn_ctrl_reg.trg_pattern_0&(1<<(pattern_cnt-1)) > 0): - self.trigger_val_list.append([ ]) - - pattern_cnt += 1 - - - - - return - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/software/readout-sim/lib/inputs_gen.py b/software/readout-sim/lib/inputs_gen.py deleted file mode 100644 index 1365b63..0000000 --- a/software/readout-sim/lib/inputs_gen.py +++ /dev/null @@ -1,95 +0,0 @@ -# class to work with FIT readout unit control registers - -import lib.control_reg as cntrl_reg -import lib.pylog as pylog - -log = pylog.log - -class input_generator_class: - def __init__(self, ctrl_file_name = 'simulation_inputs/simple_sig_inputs.txt'): - - self.ctrl_file_name = ctrl_file_name - self.control_reg = cntrl_reg.control_reg_class() - - - # gen parameters - self.goffset_sig_len = 10 - self.empty_len = 3*0xdeb - self.run_len = 10*0xdeb - self.data_gen_delay = 0xf00 - - - # defoult start - self.sigin_file = open(self.ctrl_file_name, 'w') - - - - def gen_gsync_signal(self): - self.gen_empty_cicle(0x500) - - self.control_reg.reset_gen_offset = 0x1 - for i in range(self.goffset_sig_len): self.sigin_file.write(self.control_reg.get_reg_line_16() + '\n') - - self.control_reg.reset_gen_offset = 0x0 - for i in range(self.goffset_sig_len): self.sigin_file.write(self.control_reg.get_reg_line_16() + '\n') - - self.gen_empty_cicle() - return - - def gen_empty_cicle(self, len = 0): - if len == 0: len = self.empty_len - self.control_reg.trg_rd_command = cntrl_reg.readout_cmd.idle - data_pattern = self.control_reg.data_bunch_pattern - self.control_reg.data_bunch_pattern = 0x0 - for i in range(len): self.sigin_file.write(self.control_reg.get_reg_line_16() + '\n') - self.control_reg.data_bunch_pattern = data_pattern - return - - def gen_run(self, mode = cntrl_reg.readout_cmd.continious, len = 0): - if len < self.data_gen_delay: len = self.run_len - - self.gen_empty_cicle() - - data_pattern = self.control_reg.data_bunch_pattern - self.control_reg.data_bunch_pattern = 0x0 - self.control_reg.trg_rd_command = mode - for i in range(self.data_gen_delay): self.sigin_file.write(self.control_reg.get_reg_line_16() + '\n') - - self.control_reg.data_bunch_pattern = data_pattern - for i in range(len - self.data_gen_delay): self.sigin_file.write(self.control_reg.get_reg_line_16() + '\n') - - return - - def gen_run_spam(self, mode = cntrl_reg.readout_cmd.continious, len = 0): - if len < self.run_len: len = self.run_len - - self.control_reg.trg_rd_command = cntrl_reg.readout_cmd.idle - for i in range(self.empty_len): self.sigin_file.write(self.control_reg.get_reg_line_16() + '\n') - - self.control_reg.trg_rd_command = mode - for i in range(len): self.sigin_file.write(self.control_reg.get_reg_line_16() + '\n') - self.control_reg.trg_rd_command = cntrl_reg.readout_cmd.idle - for i in range(self.empty_len): self.sigin_file.write(self.control_reg.get_reg_line_16() + '\n') - return - - - - - - - - - - - - - - - - - - - - - - diff --git a/software/readout-sim/lib/pylog.py b/software/readout-sim/lib/pylog.py index 252a50d..ae91864 100644 --- a/software/readout-sim/lib/pylog.py +++ b/software/readout-sim/lib/pylog.py @@ -28,23 +28,23 @@ def filter(self, logRecord): sh.setFormatter(fmt) log.addHandler(sh) -fmt = logging.Formatter("[%(levelname)s] %(message)s") -sh = logging.FileHandler('logs/testbench.log') -sh.addFilter(MyFilter(logging.INFO)) -sh.setFormatter(fmt) -log.addHandler(sh) +# fmt = logging.Formatter("[%(levelname)s] %(message)s") +# sh = logging.FileHandler('logs/testbench.log') +# sh.addFilter(MyFilter(logging.INFO)) +# sh.setFormatter(fmt) +# log.addHandler(sh) -fmt = logging.Formatter("[%(levelname)s] %(message)s") -sh = logging.StreamHandler(sys.stdout) -sh.setLevel(logging.WARNING) -sh.setFormatter(fmt) -log.addHandler(sh) +# fmt = logging.Formatter("[%(levelname)s] %(message)s") +# sh = logging.StreamHandler(sys.stdout) +# sh.setLevel(logging.WARNING) +# sh.setFormatter(fmt) +# log.addHandler(sh) -fmt = logging.Formatter("[%(levelname)s] %(message)s") -sh = logging.FileHandler('logs/testbench_err.log') -sh.setLevel(logging.WARNING) -sh.setFormatter(fmt) -log.addHandler(sh) +# fmt = logging.Formatter("[%(levelname)s] %(message)s") +# sh = logging.FileHandler('logs/testbench_err.log') +# sh.setLevel(logging.WARNING) +# sh.setFormatter(fmt) +# log.addHandler(sh) # class MyFilter(object): diff --git a/software/readout-sim/lib/rdh_data_packet.py b/software/readout-sim/lib/rdh_data_packet.py new file mode 100644 index 0000000..4644b21 --- /dev/null +++ b/software/readout-sim/lib/rdh_data_packet.py @@ -0,0 +1,217 @@ +''' + +Decode GBT RDH data: RDH, detector packet +Check data consistency + +Dmitry Finogeev dmitry.finogeev@cern.ch +07/2021 + +''' +import lib.constants as cnst +import lib.pylog as pylog +from lib.control_reg import control_reg as ctrl_reg + +log = pylog.log + + +class detector_packet: + def __init__(self): + self.gbt_data = [] + + self.magic = 0 + self.size = 0 + self.is_tcm = 0 + self.phase_err = 0 + self.phase = 0 + self.bc = 0 + self.orbit = 0 + self.payload = [] + self.pck_num = 0 + + def print_struct(self, log): + log.info("magic: 0x%x" % (self.magic)) + log.info("is_tcm: 0x%x" % (self.is_tcm)) + log.info("n_words: 0x%x" % (self.size)) + log.info("phase_err: 0x%x" % (self.phase_err)) + log.info("phase: 0x%x" % (self.phase)) + log.info("bc: 0x%x" % (self.bc)) + log.info("orbit: 0x%x" % (self.orbit)) + log.info("payload: %s" % (str(self.payload))) + # for idata in self.payload: + # log.info("[0x%x, 0x%x]:" % (idata[0], idata[1])) + + def read_data(self, line_list, pos): + # - 20-19 19-18 18-17 17-16 16-15 15-14 14-13 13-12 12-11 11-10 10- 9 9 - 8 8 - 7 7 - 6 6 - 5 5 - 4 4 - 3 3 - 2 2 - 1 1 - + # 79-76 75-72 71-68 67-64 63-60 59-56 55-52 51-48 47-44 43-40 39-36 35-32 31-28 27-24 23-20 19-16 15-12 11- 8 7 - 4 3 - 0 + + # reading header + self.gbt_data.append(line_list[pos]) + self.magic = int(self.gbt_data[0][-20: -19], base=16) # [79 - 76] + self.size = int(self.gbt_data[0][-19: -18], base=16) # [75 - 72] + self.is_tcm = int(self.gbt_data[0][-13: -12], base=16) # [51 - 48] + pherr_ = int(self.gbt_data[0][-12: -11], base=16) # [47 - 44] + self.phase = pherr_ & 0x7 + self.phase_err = (pherr_ & 0x8 > 0) + self.orbit = int(self.gbt_data[0][-10: -3], base=16) # [39 - 12] + self.bc = int(self.gbt_data[0][-3:], base=16) # [11 - 0] + + self.payload = [] + for iword in range(1, self.size + 1): + if pos + iword >= len(line_list): + log.info(pylog.c_FAIL+"Out of GBT data list while detector data reading ... "+pylog.c_ENDC) + return -1 + + self.gbt_data.append(line_list[pos + iword]) + if self.is_tcm == 0: + ch1_no = int(self.gbt_data[-1][-20: -19], base=16) + ch1_data = int(self.gbt_data[-1][-19: -10], base=16) + ch2_no = int(self.gbt_data[-1][-10: -9], base=16) + ch2_data = int(self.gbt_data[-1][-9:], base=16) + self.payload.append(ch1_data) + self.payload.append(ch2_data) + self.pck_num = ch1_data # same for all words + else: + self.pck_num = int(self.gbt_data[-1][-20:], base=16) + self.payload.append(self.pck_num) + + return pos + 1 + self.size + + def check_data(self): + res = 0 + if self.magic != 0xf: res = "wrong magic: %i" % self.magic + if self.size > 0xf: res = "wrong size: %i" % self.size + if len(self.payload) != self.size * (1 if self.is_tcm else 2): res = "wrong payload %i, size %i" % (len(self.payload), self.size) + + if res != 0: + self.print_struct(log) + log.info("Data check error: %s\n%s" % (res, str(self.gbt_data))) + + return res + + +class rdh_header: + def __init__(self): + self.gbt_data_pos = 0 + self.gbt_data = [] + + self.header_version = 0 + self.header_size = 0 + self.det_field = 0 + self.par_bit = 0 + + self.fee_id = 0 + self.sys_id = 0 + self.priority_bit = 0 + self.orbit = 0 + self.bc = 0 + self.trg_type = 0 + self.stop_bit = 0 + self.page_counter = 0 + self.offset_new_packet = 0 + + def print_struct(self, log): + log.info("header_version: 0x%x" % (self.header_version)) + log.info("header_size: 0x%x" % (self.header_size)) + log.info("det_field: 0x%x" % (self.det_field)) + log.info("par_bit: 0x%x" % (self.par_bit)) + log.info("fee_id: 0x%x" % (self.fee_id)) + log.info("sys_id: 0x%x" % (self.sys_id)) + log.info("priority_bit: 0x%x" % (self.priority_bit)) + log.info("orbit: 0x%x" % (self.orbit)) + log.info("bc: 0x%x" % (self.bc)) + log.info("trg_type: 0x%x" % (self.trg_type)) + log.info("stop_bit: 0x%x" % (self.stop_bit)) + log.info("page_counter: 0x%x" % (self.page_counter)) + log.info("offset_new_packet: 0x%x" % (self.offset_new_packet)) + + def read_data(self, line_list, pos): + self.gbt_data_pos = pos + self.gbt_data = line_list[pos:pos + 4] + + self.header_version = int(self.gbt_data[0][-2:], base=16) # [7 - 0] + + if self.header_version == 0x6: + # - 20-19 19-18 18-17 17-16 16-15 15-14 14-13 13-12 12-11 11-10 10- 9 9 - 8 8 - 7 7 - 6 6 - 5 5 - 4 4 - 3 3 - 2 2 - 1 1 - + # 79-76 75-72 71-68 67-64 63-60 59-56 55-52 51-48 47-44 43-40 39-36 35-32 31-28 27-24 23-20 19-16 15-12 11- 8 7 - 4 3 - 0 + self.header_size = int(self.gbt_data[0][-4: -2], base=16) # [15 - 8] + self.fee_id = int(self.gbt_data[0][-8: -4], base=16) # [31 - 16] + self.priority_bit = int(self.gbt_data[0][-10:-8], base=16) # [39 - 32] + self.sys_id = int(self.gbt_data[0][-12: -10], base=16) # [47 - 40] + self.offset_new_packet = int(self.gbt_data[0][-20: -16], base=16) # [79 - 64] + + self.bc = int(self.gbt_data[1][-3:], base=16) # [11 - 0] + self.orbit = int(self.gbt_data[1][-16: -8], base=16) # [63 - 32] + + self.trg_type = int(self.gbt_data[2][-8:], base=16) # [31 - 0] + self.page_counter = int(self.gbt_data[2][-12:-8], base=16) # [47 - 32] + self.stop_bit = int(self.gbt_data[2][-14: -12], base=16) # [55 - 48] + + self.det_field = int(self.gbt_data[3][-8:], base=16) # [31 - 0] + self.par_bit = int(self.gbt_data[3][-12: -8], base=16) # [47 - 32] + return pos + 4 + + def check_data(self, ctrl=ctrl_reg()): + res = 0 + if self.header_version != 0x6: res = "wrong version: 0x%x [0x%x]" % (self.header_version, 0x6) + if self.header_size != 0x40: res = "wrong size: %i [0x%x]" % (self.header_size, 0x40) + if self.det_field != 0x0: res = "wrong det field: 0x%x [0x%x]" % (self.det_field, 0x0) + if self.par_bit != 0x0: res = "wrong par: 0x%x [0x%x]" % (self.par_bit, 0x0) + + if self.fee_id != ctrl.RDH_FEEID: res = "wrong fee id: 0x%x [0x%x]" % (self.fee_id, ctrl.RDH_FEEID) + if self.sys_id != ctrl.RDH_SYS_ID: res = "wrong sys id: 0x%x [0x%x]" % (self.sys_id, ctrl.RDH_SYS_ID) + if self.priority_bit != ctrl.RDH_PRT_BIT: res = "wrong priority_bit: 0x%x [0x%x]" % (self.par_bit, ctrl.RDH_PRT_BIT) + + if self.offset_new_packet > cnst.max_rdh_payload * 16: res = "rdh oversize: 0x%x [0x%x]" % (self.offset_new_packet, cnst.max_rdh_payload*16) + + if res != 0: + log.info("RDH %i, orbit %04x check error [line %i] : %s\n%s" % (self.page_counter, self.orbit, self.gbt_data_pos, res, str(self.gbt_data))) + + return res + + +class rdh_packet: + def __init__(self): + self.rdh_header = rdh_header() + self.event_list = [] + + def print_raw(self): + for igbt in self.rdh_header.gbt_data: print(hex(igbt)) + for event in self.event_list: + for igbt in event.gbt_data: print(hex(igbt)) + + def print_struct(self, log): + log.info("######################## RDH ########################") + self.rdh_header.print_struct(log) + for event in self.event_list: + log.info("=== EVENT ===") + event.print_struct(log) + + def read_data(self, line_list, pos): + dyn_pos = self.rdh_header.read_data(line_list, pos) + n_dw_in_packet = (self.rdh_header.offset_new_packet / 16) - 4 + + packet_start = dyn_pos + while dyn_pos < packet_start + n_dw_in_packet: + dyn_event = detector_packet() + dyn_pos = dyn_event.read_data(line_list, dyn_pos) + if dyn_pos < 0: return -1 + self.event_list.append(dyn_event) + + return dyn_pos + + def check_data(self, ctrl=ctrl_reg()): + + # check correctness of header + res = self.rdh_header.check_data(ctrl) + if res != 0: return res + + # check correctness of data + for event in self.event_list: + res = event.check_data() + if res != 0: return res + + # check orbits in data + for event in self.event_list: + if event.orbit != self.rdh_header.orbit: + return "event orbit 0x%04x != rdh orbit 0x%04x"%(event.orbit, self.rdh_header.orbit) + return 0 diff --git a/software/readout-sim/lib/readout_constants.py b/software/readout-sim/lib/readout_constants.py deleted file mode 100644 index dfbc26f..0000000 --- a/software/readout-sim/lib/readout_constants.py +++ /dev/null @@ -1,18 +0,0 @@ - - -TRG_const_void = 0x00000000 -TRG_const_Orbit = 0x00000001 #0 -TRG_const_HB = 0x00000002 #1 -TRG_const_HBr = 0x00000004 #2 -TRG_const_HC = 0x00000008 #3 -TRG_const_Ph = 0x00000010 #4 -TRG_const_PP = 0x00000020 #5 -TRG_const_Cal = 0x00000040 #6 -TRG_const_SOT = 0x00000080 #7 -TRG_const_EOT = 0x00000100 #8 -TRG_const_SOC = 0x00000200 #9 -TRG_const_EOC = 0x00000400 #10 -TRG_const_TF = 0x00000800 # time frame delimiter -TRG_const_FErst = 0x00001000 # FEE reset -TRG_const_RT = 0x00002000 # Run Type; 1=Cont, 0=Trig -TRG_const_RS = 0x00004000 #Running State; 1=Running diff --git a/software/readout-sim/lib/run_generator.py b/software/readout-sim/lib/run_generator.py new file mode 100644 index 0000000..2bd9698 --- /dev/null +++ b/software/readout-sim/lib/run_generator.py @@ -0,0 +1,106 @@ +''' + +Class include RUN parameters +generate control registers for vhdl simulation +used for simulated run test + +Dmitry Finogeev dmitry.finogeev@cern.ch +07/2021 + +''' +import copy +import lib.pylog as pylog + +from lib.control_reg import control_reg as ctrl_reg +from lib.control_reg import gen_mode, readout_cmd + +from lib.constants import filename_ctrlreg +from lib.constants import orbit_size + + +class run_generator: + def __init__(self, ctrl_reg = ctrl_reg(), run_comment=""): + self.filename_ctrlreg = filename_ctrlreg + self.ctrl_reg = ctrl_reg + self.run_comment = run_comment + + self.run_pos_start = 0 + self.run_pos_stop = 0 + + self.log = pylog.log + + def print_run_meta(self): + self.log.info("file name: %s" % (self.filename_ctrlreg)) + self.log.info("run type: %s"%(str(self.ctrl_reg.trg_rd_command))) + self.log.info(self.run_comment) + self.log.info("run pos range: [%i, %i]"%(self.run_pos_start, self.run_pos_stop)) + + + def reset_file(self): + self.log.info("Rewriting sim input file: %s" % (self.filename_ctrlreg)) + file = open(self.filename_ctrlreg, 'w') + file.close() + + # generate pattern of control registers to start and stop run, ctrl_intrusion used inside run + def generate_ctrl_pattern(self, norbits=3, ctrl_intrusion = 0): + self.log.info("RENERATING %s RUN for %i orbits in file %s" % (self.ctrl_reg.trg_rd_command, norbits, self.filename_ctrlreg)) + + # open file + self.run_pos_start = len(open(self.filename_ctrlreg).readlines()) + file = open(self.filename_ctrlreg, 'a') + + # generate void orbits before run + run_type = self.ctrl_reg.trg_rd_command + self.ctrl_reg.trg_rd_command = readout_cmd.idle + # start of simulation + if self.run_pos_start<2*orbit_size: + # reset orbc sync + self.ctrl_reg.reset_orbc_sync = 1 + reg_line = self.ctrl_reg.get_reg_line_16() + '\n' + for i in range(20): file.write(reg_line) + # generate void orbits to make RX decoder sync + self.ctrl_reg.reset_orbc_sync = 0 + reg_line = self.ctrl_reg.get_reg_line_16() + '\n' + for i in range(2*orbit_size): file.write(reg_line) + + # reset simulation generators and errors + self.ctrl_reg.reset_gensync = 1 + self.ctrl_reg.reset_data_counters = 1 + self.ctrl_reg.reset_err_report = 1 + reg_line = self.ctrl_reg.get_reg_line_16() + '\n' + for i in range(10): file.write(reg_line) + # generate void orbits to make generators in sync + self.ctrl_reg.reset_gensync = 0 + self.ctrl_reg.reset_data_counters = 0 + self.ctrl_reg.reset_err_report = 0 + reg_line = self.ctrl_reg.get_reg_line_16() + '\n' + for i in range(2*orbit_size): file.write(reg_line) + + # generate run + self.ctrl_reg.trg_rd_command = run_type + reg_line = self.ctrl_reg.get_reg_line_16() + '\n' + for i in range(norbits * orbit_size): file.write(reg_line) + + # generate intrusion + if ctrl_intrusion != 0: + ctrl_reg_cp = copy.copy(self.ctrl_reg) + self.ctrl_reg = ctrl_intrusion + reg_line = self.ctrl_reg.get_reg_line_16() + '\n' + for i in range(norbits * orbit_size): file.write(reg_line) + + self.ctrl_reg = ctrl_reg_cp + reg_line = self.ctrl_reg.get_reg_line_16() + '\n' + for i in range(norbits * orbit_size): file.write(reg_line) + + # generate void orbits after run to finish sending data + self.ctrl_reg.trg_rd_command = readout_cmd.idle + reg_line = self.ctrl_reg.get_reg_line_16() + '\n' + for i in range(6 * orbit_size): file.write(reg_line) + self.ctrl_reg.trg_rd_command = run_type + + file.close() + self.run_pos_stop = len(open(self.filename_ctrlreg).readlines()) + + + + diff --git a/software/readout-sim/lib/run_reader.py b/software/readout-sim/lib/run_reader.py new file mode 100644 index 0000000..27515bc --- /dev/null +++ b/software/readout-sim/lib/run_reader.py @@ -0,0 +1,112 @@ +''' + +The class read simulation outputs and decode run data +take run_generator object as run metadata + +Dmitry Finogeev dmitry.finogeev@cern.ch +07/2021 + +''' + +import copy + +import lib.constants as cnst +import lib.pylog as pylog +from lib.constants import TRG_const_HBr +from lib.constants import filename_simout +from lib.control_reg import readout_cmd +from lib.run_generator import run_generator +from lib.status_reg import status_reg + + +class run_reader: + def __init__(self, run_meta=run_generator()): + self.run_meta = run_meta + self.filename_simout = filename_simout + + self.gbt_data = [] + self.gbt_pos_iter = [] # gbt words position in simulation data flow + self.gen_data = [] + self.trg_data = [] + self.last_status = 0 + + self.run_valid = False + self.start_orbit = 0 + self.stop_ortbit = 0 + + self.log = pylog.log + + self.read_run() + + def print_run_info(self): + self.log.info("RUN VALID: %s" % (str(self.run_valid))) + self.log.info("GBT data size: %i" % (len(self.gbt_data))) + self.log.info("GEN data size: %i" % (len(self.gen_data))) + self.log.info("TRG data size: %i" % (len(self.trg_data))) + self.log.info("ORBIT RANGE %i [%04x : %04x]" % (self.stop_ortbit - self.start_orbit + 1, self.start_orbit, self.stop_ortbit)) + + def read_run(self): + self.run_valid = False + simout_list = list(open(self.filename_simout, 'r')) + if self.run_meta.run_pos_stop > len(simout_list): + self.log.error("Simulation ountput is to short. len: %i, run_stop: %i. Check that simulation was finished" % (len(simout_list), self.run_meta.run_pos_stop)) + + self.gbt_data = [] + self.gen_data = [] + self.trg_data = [] + trg_run_ongoing = False + sending_mode = False + + # iteration through simulation outputs + for iline in range(self.run_meta.run_pos_start, self.run_meta.run_pos_stop): + if iline >= len(simout_list): + self.log.info(pylog.c_FAIL + "End of simulation output file reached, check that vivado simulation finished" + pylog.c_ENDC) + return 0 + + line_regs = simout_list[iline].replace('X', '0').split(" ")[:-1] + + # readout status in cycle + istatus = status_reg(line_regs[2:]) + + # check fsm error + if (istatus.fsm_errors & 0x7FFF) > 0 and iline > 10: + self.log.info("FSM ERROR in run found: %s (%04x) [line %i]" % (istatus.get_fsm_err_msg(), istatus.fsm_errors, iline)) + self.log.info(line_regs[2:]) + return 0 + + # collecting GBT data + is_gbt_word = int(line_regs[0], base=16) + gbt_word = line_regs[1] + if is_gbt_word > 0: self.gbt_data.append(gbt_word); self.gbt_pos_iter.append(iline); self.last_status = istatus + + # collecting generated data + if istatus.data_gen_size > 0: + # select data by data_enabled + if istatus.data_enabled: self.gen_data.append( + # size is +1 for zero packets indication + {'size': istatus.data_gen_size, 'pck_num': istatus.data_gen_packnum, 'bc': istatus.data_gen_bc, 'orbit': istatus.data_gen_orbit}) + + # collecting trigger data + if istatus.cru_trigger > 0: + if (istatus.cru_trigger & cnst.TRG_const_SOC) or (istatus.cru_trigger & cnst.TRG_const_SOT): trg_run_ongoing = True; self.start_orbit = istatus.cru_orbit + if trg_run_ongoing and istatus.readout_mode != readout_cmd.idle: self.trg_data.append({'trigger': istatus.cru_trigger, 'bc': istatus.cru_bc, 'orbit': istatus.cru_orbit}) + if (istatus.cru_trigger & cnst.TRG_const_EOC) or (istatus.cru_trigger & cnst.TRG_const_EOT): trg_run_ongoing = False; self.stop_ortbit = istatus.cru_orbit + + # deleting data in HBr orbits + if self.run_meta.ctrl_reg.is_hb_reject: + for itrg in self.trg_data: + if (itrg['trigger'] & TRG_const_HBr) > 0: + for igen in copy.copy(self.gen_data): + if igen['orbit'] == itrg['orbit']: + self.gen_data.remove(igen) + + # deleting data not matched to trigger in trg run + if self.run_meta.ctrl_reg.trg_rd_command == readout_cmd.trigger: + for igen in copy.copy(self.gen_data): + trg_found = False + for itrg in self.trg_data: + if itrg['orbit'] == igen['orbit'] and itrg['bc'] == igen['bc'] and (itrg['trigger'] & self.run_meta.ctrl_reg.trg_data_select) > 0: trg_found = True + if not trg_found: self.gen_data.remove(igen) + + self.run_valid = True + return 1 diff --git a/software/readout-sim/lib/run_sim_data.py b/software/readout-sim/lib/run_sim_data.py deleted file mode 100644 index 940946c..0000000 --- a/software/readout-sim/lib/run_sim_data.py +++ /dev/null @@ -1,204 +0,0 @@ -# class to work with FIT readout unit control registers - -import lib.control_reg as cntrl_reg -import lib.pylog as pylog - -log = pylog.log - - -class run_sim_data_class: - def __init__(self, ctrl_data_list, gbt_info_list): - - # data set - self.ctrl_data_list = ctrl_data_list - self.gbt_info_list = gbt_info_list - - # test bench parameters - self.idle_min_len = 2*0xdec - self.run_min_len = 3*0xdec - - # run parameters - self.pos_run_start = 0 - self.pos_run_stop = 0 - self.pos_run_postidl = 0 - self.run_type = cntrl_reg.readout_cmd.idle - self.pos_gbt_start = 0 - self.pos_gbt_stop = 0 - self.pos_gbt_postidl = 0 - self.pos_last_read = 0 - self.run_control = cntrl_reg.control_reg_class() - - def print_info(self): - log.info("############################# SIMULATION RUN INFO ####################################") - log.info("\ninputs files:") - log.info("data position run start: %d"%(self.pos_run_start)) - log.info("data position run stop: %d"%(self.pos_run_stop)) - log.info("data position post run idle: %d"%(self.pos_run_postidl)) - log.info("\noutputs files:") - if len(self.gbt_info_list) > 0: - log.info("gbt position run start: %d (%d)"%(self.pos_gbt_start, int(self.gbt_info_list[self.pos_gbt_start], base=16))) - log.info("gbt position run stop: %d (%d)"%(self.pos_gbt_stop, int(self.gbt_info_list[self.pos_gbt_stop], base=16))) - log.info("gbt position post run idle: %d (%d)"%(self.pos_gbt_postidl, int(self.gbt_info_list[self.pos_gbt_postidl], base=16))) - log.info("\nrun params:") - log.info("run type: %s"%(self.run_type)) - self.run_control.print_struct() - - - def get_run(self, ctrl_reg_pos): - # one orbit = 3563 BCs - # 1) find idle readout for one orbit - # 2) check next cnt/trg control - # 3) return [code, run start, run stop] - - # find first idle pattern ----------------------------------------------- - idle_len = 0 - curr_pos = ctrl_reg_pos - dyn_ctrl_reg = cntrl_reg.control_reg_class() - while curr_pos < len(self.ctrl_data_list): - dyn_ctrl_reg.read_reg_line_16(self.ctrl_data_list[curr_pos]) - - if (dyn_ctrl_reg.trg_rd_command != cntrl_reg.readout_cmd.idle) and \ - (idle_len >= self.idle_min_len): break - - if dyn_ctrl_reg.trg_rd_command == cntrl_reg.readout_cmd.idle: - idle_len += 1 - else: - idle_len = 0 - - self.pos_last_read = curr_pos - curr_pos += 1 - - if len(self.ctrl_data_list) - curr_pos < self.run_min_len: - return -1 # no space for run - - run_start = curr_pos - - # find uniform run parameters ------------------------------------------- - run_len = 0 - run_type = dyn_ctrl_reg.trg_rd_command - self.run_control = dyn_ctrl_reg - - while curr_pos < len(self.ctrl_data_list): - dyn_ctrl_reg.read_reg_line_16(self.ctrl_data_list[curr_pos]) - - if (dyn_ctrl_reg.trg_rd_command != run_type) and \ - (dyn_ctrl_reg.trg_rd_command != cntrl_reg.readout_cmd.idle): - return -2 # run type switched - - if (not self.run_control.is_equal(dyn_ctrl_reg)): - return -6 #control reg is different - - - if dyn_ctrl_reg.trg_rd_command == cntrl_reg.readout_cmd.idle: - break - - self.pos_last_read = curr_pos - run_len += 1 - curr_pos += 1 - - if (dyn_ctrl_reg.trg_rd_command != cntrl_reg.readout_cmd.idle): - return -3 # run is not stopped - - if (run_len < self.run_min_len): - return -4 # run is too short - - run_stop = curr_pos-1 - - - # post run idle cycle ------------------------------------------- - idle_len = 0 - while curr_pos < len(self.ctrl_data_list): - dyn_ctrl_reg.read_reg_line_16(self.ctrl_data_list[curr_pos]) - if (dyn_ctrl_reg.trg_rd_command != cntrl_reg.readout_cmd.idle): break - - self.pos_last_read = curr_pos - curr_pos += 1 - idle_len += 1 - - if idle_len < self.idle_min_len: - return -5 # post run idle it too short - - - - self.pos_run_start = run_start - self.pos_run_stop = run_stop - self.pos_run_postidl = curr_pos-1 - self.run_type = run_type - return 1 - - def find_gbt_pos(self): - - if len(self.gbt_info_list) == 0: - log.warning(pylog.c_WARNING+"No GBT data !!!"+pylog.c_ENDC) - return - - - - # GBT data run start position - ipos = 0 - while 1: - curr_gbt_num = int(self.gbt_info_list[ipos], base=16) - if curr_gbt_num >= self.pos_run_start: - self.pos_gbt_start = ipos - break - - ipos += 1 - if ipos >= len(self.gbt_info_list): - self.pos_gbt_start = len(self.gbt_info_list)-1 - break - - # GBT data run stop position - ipos = 0 - while 1: - curr_gbt_num = int(self.gbt_info_list[ipos], base=16) - if curr_gbt_num >= self.pos_run_stop: - self.pos_gbt_stop = ipos - break - - ipos += 1 - if ipos >= len(self.gbt_info_list): - self.pos_gbt_stop = len(self.gbt_info_list)-1 - break - - - # GBT data run post idle position - ipos = 0 - while 1: - curr_gbt_num = int(self.gbt_info_list[ipos], base=16) - if curr_gbt_num >= self.pos_run_postidl: - self.pos_gbt_postidl = ipos - break - - ipos += 1 - if ipos >= len(self.gbt_info_list): - self.pos_gbt_postidl = len(self.gbt_info_list)-1 - break - - - - return - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/software/readout-sim/lib/run_testbench.py b/software/readout-sim/lib/run_testbench.py deleted file mode 100644 index cd81224..0000000 --- a/software/readout-sim/lib/run_testbench.py +++ /dev/null @@ -1,352 +0,0 @@ -# class to work with FIT readout unit control registers - -import lib.control_reg as cntrl_reg -import lib.RDH_data as rdh_data -import lib.pylog as pylog -import lib.readout_constants as rdconst - -log = pylog.log - - -class run_testbench_class: - def __init__(self, simulation, run_num=0): - - # data set - self.simulation = simulation - self.run_num = run_num - self.run_data = self.simulation.runs_list[self.run_num] - - # run data - self.rdh_data_list = [] - - # testbench results - self.errors_messages = [] - - - - - # test procedure - log.info("") - log.info("#######################################") - log.info("####### TESTING SIMULATION DATA #######") - log.info("#######################################") - log.info("Run N%i" % (run_num)) - log.info("") - - res = self.read_run_data_check() - - if len(self.errors_messages) == 0: - log.info("Run rdh data successfully read ... ") - else: - log.info(pylog.c_FAIL + (" run rdh data read with %i errors:" % (len(self.errors_messages))) + pylog.c_ENDC) - for message in self.errors_messages: log.info("%s"%(message)) - - if len(self.rdh_data_list) == 0: - log.info( ("Read %i events"%(len(self.rdh_data_list))) ) - else: - log.info(pylog.c_OKGREEN + ("Read %i events"%(len(self.rdh_data_list))) + pylog.c_ENDC) - - self.errors_messages = [] - - log.info("") - log.info("Checking run ... ") - self.check_run_data() - - log.info("") - if len(self.errors_messages) > 0: log.info( pylog.c_FAIL + ("!!! Run tested with %i errors !!!" % (len(self.errors_messages)))+pylog.c_ENDC ) - if len(self.errors_messages) == 0: log.info( pylog.c_OKGREEN + ("!!! Run tested with %i errors !!!" % (len(self.errors_messages)))+pylog.c_ENDC ) - for message in self.errors_messages: log.info("%s"%(message)) - - - - - # def print_info(self): - # log.info("############################# SIMULATION RUN INFO ####################################") - # log.info("\ninputs files:") - # log.info("data position run start: %d"%(self.pos_run_start)) - # log.info("data position run stop: %d"%(self.pos_run_stop)) - # log.info("data position post run idle: %d"%(self.pos_run_postidl)) - - # read continuously rdh data - def read_run_data(self): - self.rdh_data_list = [] - dyn_event = rdh_data.rdh_data_class() - pos = self.run_data.pos_gbt_start - while pos < self.run_data.pos_gbt_postidl: - pos = dyn_event.read_data(self.simulation.gbt_data_list, pos) - dyn_event.print_raw() - dyn_event.print_struct() - self.rdh_data_list.append(dyn_event) - - # read rdh data with errors checking - def read_run_data_check(self): - self.rdh_data_list = [] - - dyn_pos = self.run_data.pos_gbt_start - - # EVENT loop -------------------------------------------- - while dyn_pos < self.run_data.pos_gbt_postidl: - dyn_rdh_header = rdh_data.rdh_header_class() - dyn_rdh_trailer = rdh_data.rdh_trailer_class() - dyn_rdh_data = rdh_data.rdh_data_class() - - - # HEADER -------------------------------------------- - new_dyn_pos = dyn_rdh_header.read_data(self.simulation.gbt_data_list, dyn_pos) - - if dyn_rdh_header.fee_id != self.run_data.run_control.RDH_feeid: - self.errors_messages.append("Wrong FEE ID: %x, expected: %x"%(dyn_rdh_header.fee_id, self.run_data.run_control.RDH_feeid)) - return -1 - - if dyn_rdh_header.par_bit != self.run_data.run_control.RDH_par: - self.errors_messages.append("Wrong PAR ID: %x, expected: %x"%(dyn_rdh_header.par_bit, self.run_data.run_control.RDH_par)) - return -1 - - if dyn_rdh_header.det_field != self.run_data.run_control.RDH_detf: - self.errors_messages.append("Wrong DEF_F ID: %x, expected: %x"%(dyn_rdh_header.det_field, self.run_data.run_control.RDH_detf)) - return -1 - - n_dw_in_packet = (dyn_rdh_header.block_lenght / 16) - 5 - max_payload = (self.run_data.run_control.max_data_payload+5)*16 - # if dyn_rdh_header.block_lenght > max_payload: - # self.errors_messages.append("Block length is too high: %x, expected: %x"%(dyn_rdh_header.block_lenght, max_payload)) - if n_dw_in_packet > self.run_data.run_control.max_data_payload+10: #10=max detector packet lenght - self.errors_messages.append("Block length is too high (n data words): %i, expected: %i" % (n_dw_in_packet, self.run_data.run_control.max_data_payload)) - #return -1 - - dyn_rdh_data.rdh_header = dyn_rdh_header - dyn_pos = new_dyn_pos - - - - # DATA -------------------------------------------- - packet_start = dyn_pos - dyn_rdh_data.event_list = [] - while dyn_pos < packet_start + n_dw_in_packet: - dyn_rdh_detdata = rdh_data.detector_event_class() - new_dyn_pos = dyn_rdh_detdata.read_data(self.simulation.gbt_data_list, dyn_pos) - - if dyn_rdh_detdata.magic != 0xF: - self.errors_messages.append("Wrong detector header magic: %x, expected: %x" % (dyn_rdh_detdata.magic, 0xF)) - return -1 - - dyn_rdh_data.event_list.append(dyn_rdh_detdata) - # dyn_rdh_detdata.print_struct() - dyn_pos = new_dyn_pos - - - - # TRAILER -------------------------------------------- - new_dyn_pos = dyn_rdh_trailer.read_data(self.simulation.gbt_data_list, dyn_pos) - - if dyn_rdh_trailer.magic != 0xFFFF: - self.errors_messages.append("Wrong trailer magic : %x, expected: %x" % (dyn_rdh_detdata.magic, 0xFFFF)) - return -1 - - dyn_rdh_data.rdh_trailer = dyn_rdh_trailer - dyn_pos = new_dyn_pos - - # if len(dyn_rdh_data.event_list) > 2: - # dyn_rdh_data.event_list[0].print_struct() - # dyn_rdh_data.event_list[1].print_struct() - # dyn_rdh_data.print_struct() - self.rdh_data_list.append(dyn_rdh_data) - - return 1 - - - def check_run_data(self): - - - # start and stop triggers -------------------------------------------------------------------------------------- - first_RDH_trg = self.rdh_data_list[0].rdh_header.trg_type - last_RDH_trg = self.rdh_data_list[-1].rdh_header.trg_type - - if self.run_data.run_type == cntrl_reg.readout_cmd.continious: - str_trg_val = rdconst.TRG_const_SOC - stp_trg_val = rdconst.TRG_const_EOC - else: - str_trg_val = rdconst.TRG_const_SOT - stp_trg_val = rdconst.TRG_const_EOT - - is_str_ok = first_RDH_trg & str_trg_val > 0 - is_stp_ok = last_RDH_trg & stp_trg_val > 0 - - - if not is_str_ok: self.errors_messages.append("First RDH don't contains SOx : %x, expected: %x" % (first_RDH_trg, str_trg_val)) - if not is_stp_ok: self.errors_messages.append("Last RDH don't contains EOx : %x, expected: %x" % (last_RDH_trg, stp_trg_val)) - - if is_stp_ok and is_str_ok: - log.info((pylog.c_OKGREEN+"First run trigger: %x [%s]"+pylog.c_ENDC) % (first_RDH_trg, is_str_ok)) - log.info((pylog.c_OKGREEN+"Last run trigger: %x [%s]"+pylog.c_ENDC) % (last_RDH_trg, is_stp_ok)) - else: - log.info((pylog.c_FAIL+"First run trigger: %x [%s]"+pylog.c_ENDC) % (first_RDH_trg, is_str_ok)) - log.info((pylog.c_FAIL+"Last run trigger: %x [%s]"+pylog.c_ENDC) % (last_RDH_trg, is_stp_ok)) - - - # page counter ------------------------------------------------------------------------------------------------- - for ievent in range(1, len(self.rdh_data_list)): - pc_curr = self.rdh_data_list[ievent].rdh_header.page_counter - pc_prev = self.rdh_data_list[ievent-1].rdh_header.page_counter - orbit_curr = self.rdh_data_list[ievent].rdh_header.orbit - orbit_prev = self.rdh_data_list[ievent-1].rdh_header.orbit - - if orbit_curr == orbit_prev+1: - if pc_curr != 0: - self.errors_messages.append("Page counter is not 0x0 with new orbit in event %i;" % (ievent)) - return -1 - elif orbit_curr == orbit_prev: - if pc_curr != pc_prev+1: - self.errors_messages.append("RDH page counter error in event %i : PC: %i, prev PC: %i" % (ievent, pc_curr, pc_prev)) - return -1 - else: - self.errors_messages.append("RDH orbit missed in event %i; orbit curr %x, orbit prev %x" % (ievent, orbit_curr, orbit_prev)) - return -1 - - - log.info(pylog.c_OKGREEN+"RDH page counters are correct ... "+pylog.c_ENDC) - - - # stop bit ----------------------------------------------------------------------------------------------------- - for ievent in range(0, len(self.rdh_data_list)-1): - orbit_curr = self.rdh_data_list[ievent].rdh_header.orbit - orbit_next = self.rdh_data_list[ievent+1].rdh_header.orbit - - if orbit_curr+1 == orbit_next: - if self.rdh_data_list[ievent].rdh_header.stop_bit != 0x1: - self.errors_messages.append("Stop bit is not 0x1 in event %i; curr orbit %x, next orbit %x" % (ievent, orbit_curr, orbit_next)) - return -1 - else: - if self.rdh_data_list[ievent].rdh_header.stop_bit != 0x0: - self.errors_messages.append("Stop bit is not 0x0 in event %i; curr orbit %x, next orbit %x" % (ievent, orbit_curr, orbit_next)) - return -1 - - log.info(pylog.c_OKGREEN+"RDH stop bits are correct ... "+pylog.c_ENDC) - - - # orbit in rdh dara -------------------------------------------------------------------------------------------- - for ievent in range(0, len(self.rdh_data_list)): - orbit_curr = self.rdh_data_list[ievent].rdh_header.orbit - - for idata in self.rdh_data_list[ievent].event_list: - if idata.orbit != orbit_curr: - self.errors_messages.append("Wrong orbit in detector event %i; curr orbit %x, event orbit %x" % (ievent, orbit_curr, idata.orbit)) - return -1 - - log.info(pylog.c_OKGREEN+"Detectors orbits are correct ... "+pylog.c_ENDC) - - - - # data integrity ----------------------------------------------------------------------------------------------- - selected_data = [] - log.info("Data integrity test [%s] ... " % (self.run_data.run_type)) - - sim_dat = self.simulation.data_gen_list - sim_trg = self.simulation.trig_gen_list - first_ORBIT = self.rdh_data_list[0].rdh_header.orbit - last_ORBIT = self.rdh_data_list[-1].rdh_header.orbit - - first_data_line = len(sim_dat) - for i in range(0, len(sim_dat)): - if sim_dat[i][0] >= first_ORBIT: - first_data_line = i - break - - last_data_line = 0 - for i in range(first_data_line, len(sim_dat)): - if sim_dat[i][0] > last_ORBIT: break - last_data_line = i - - prev_trg_ilist = 0 - for dat_iter in range(first_data_line, last_data_line): - - #EOr can contain only data for BC 0 - if sim_dat[dat_iter][0] == last_ORBIT and sim_dat[dat_iter][1] > 0: - continue - - for trg_iter in range(prev_trg_ilist, len(sim_trg)): - - # trg for data found - if sim_dat[dat_iter][0] == sim_trg[trg_iter][0] and sim_dat[dat_iter][1] == sim_trg[trg_iter][1]: - selected_data.append([sim_dat[dat_iter][0], sim_dat[dat_iter][1], sim_trg[trg_iter][2], sim_dat[dat_iter][2]]) - prev_trg_ilist = trg_iter-1 - break - - # no trigger for data - if sim_dat[dat_iter][0] < sim_trg[trg_iter][0] or ( sim_dat[dat_iter][0] == sim_trg[trg_iter][0] and sim_dat[dat_iter][1] < sim_trg[trg_iter][1] ): - if self.run_data.run_type == cntrl_reg.readout_cmd.continious: #select data in continious - selected_data.append([sim_dat[dat_iter][0], sim_dat[dat_iter][1], 0, sim_dat[dat_iter][2]]) - prev_trg_ilist = trg_iter-1 - break - else: # reject data in trigger mode - prev_trg_ilist = trg_iter-1 - break - - log.info("Run orbits: [%x (%i), %x (%i)]; total data packets: %i; selected data: %i" % (first_ORBIT, first_data_line, last_ORBIT, last_data_line, last_data_line-first_data_line, len(selected_data))) - # print(selected_data) - - if len(selected_data) == 0: - log.warning(pylog.c_WARNING+"No data selected !!!"+pylog.c_ENDC) - else: - wrong_ch_num = 0 - events_num_nogen = 0 - for irdh in self.rdh_data_list: - for ievent in irdh.event_list: - #ievent.print_struct() - #print(selected_data) - for isim_data in selected_data: - if isim_data[0] == ievent.orbit and isim_data[1] == ievent.bc: - if ievent.is_tcm == 1: - n_ch_gen = ((isim_data[3] << 1) | (0x1)) # module_data_gen.vhd line 88 - else: - n_ch_gen = isim_data[3] - - if n_ch_gen != ievent.n_words: wrong_ch_num += 1 - selected_data.remove(isim_data) - #print("found !") - break - elif isim_data == selected_data[-1]: - events_num_nogen += 1 - - - - if len(selected_data) > 0: - log.info(pylog.c_FAIL + ("Generated data missed in RDHs %i" % ( len(selected_data))) + pylog.c_ENDC ) - for isdata in selected_data: - print("orbit: %08x bc: %03x trg: %08x nw: %i"%( isdata[0], isdata[1], isdata[2], isdata[3])) - self.errors_messages.append("Generated data missed in RDHs %i" % ( len(selected_data) )) - - if wrong_ch_num > 0: - log.info(pylog.c_FAIL + ("%i events with wrong channels number" % (wrong_ch_num)) + pylog.c_ENDC) - self.errors_messages.append("%i events with wrong channels number" % (wrong_ch_num)) - - if events_num_nogen > 0: - log.info(pylog.c_FAIL + ("%i events not found in gen list" % (events_num_nogen)) + pylog.c_ENDC) - self.errors_messages.append("%i events not found in gen list" % (events_num_nogen)) - - if len(selected_data)+wrong_ch_num+events_num_nogen == 0: - log.info(pylog.c_OKGREEN + "All data in RDHs OK! ... " + pylog.c_ENDC) - - # # data counter ----------------------------------------------------------------------------------------------- - # event_iter = 0 - # for ievent in range(0, len(self.rdh_data_list)-1): - # - # for idata in self.rdh_data_list[ievent].event_list: - # - # for ichdata in idata. - # if idata.orbit != orbit_curr: - # self.errors_messages.append("Wrong orbit in detector event %i; curr orbit %x, умуте orbit %x" % (ievent, orbit_curr, idata.orbit)) - # return -1 - # - # log.info(pylog.c_OKGREEN+"Detectors orbits are correct ... "+pylog.c_ENDC) - - - - - - - #data bc positions - return 1 - - - diff --git a/software/readout-sim/lib/run_tester.py b/software/readout-sim/lib/run_tester.py new file mode 100644 index 0000000..e8f02fa --- /dev/null +++ b/software/readout-sim/lib/run_tester.py @@ -0,0 +1,143 @@ +''' + +Check correctness of RUN data, report results + +Dmitry Finogeev dmitry.finogeev@cern.ch +07/2021 + +''' +import copy + +import lib.constants as cnst +import lib.pylog as pylog +from lib.control_reg import readout_cmd +from lib.rdh_data_packet import rdh_packet +from lib.run_reader import run_reader + + +class run_tester: + def __init__(self, run=run_reader()): + + self.run = run + self.rdh_packet_list = [] + + self.log = pylog.log + + # read all RDH packets in RUN and check data consistency + def read_data(self): + + # reading rdh packets + pos = 0 + while pos < len(self.run.gbt_data): + rdh = rdh_packet() + pos = rdh.read_data(self.run.gbt_data, pos) + if pos < 0: return -1 + + # check RDH after reading + check_res = rdh.check_data(self.run.run_meta.ctrl_reg) + if check_res != 0: + # rdh.print_struct(self.log) + self.log.info(pylog.c_FAIL + "data reading error in rdh %i [pos: %i] : %s" % (len(self.rdh_packet_list), self.run.gbt_pos_iter[pos], check_res) + pylog.c_ENDC) + return check_res + + self.rdh_packet_list.append(rdh) + # rdh.print_struct(self.log) + + return 0 + + # check RDH data and report result + @property + def test_data(self): + + # reading RDH packets and data: + read_report = self.read_data() + if read_report == 0: + self.log.info(pylog.c_OKGREEN + "Data was successfully read ..." + pylog.c_ENDC) + else: + return 0 + + # for irdh in self.rdh_packet_list: self.log.info("RDH %i, orbit %04x, events: %i" % (self.rdh_packet_list.index(irdh), irdh.rdh_header.orbit, len(irdh.event_list))) + + # cheking HB rdh pattern + trg_check_list = [] + for trg in self.run.trg_data: + if (trg['trigger'] & cnst.TRG_const_HB) == 0: continue + + # collecting all rdh for current HB + hb_rdh_list = [] + for irdh in self.rdh_packet_list: + if irdh.rdh_header.orbit == trg['orbit'] and irdh.rdh_header.bc == trg['bc']: hb_rdh_list.append(irdh) + + # HB response + if len(hb_rdh_list) == 0: + self.log.info(pylog.c_FAIL + "no RDH found for %s" % (str(trg)) + pylog.c_ENDC) + return 0 + + # stop bit + if hb_rdh_list[-1].rdh_header.stop_bit != 1: + self.log.info(pylog.c_FAIL + "wrong stop bit for %s" % (str(trg)) + pylog.c_ENDC) + return 0 + for i in range(0, len(hb_rdh_list) - 1): + if hb_rdh_list[i].rdh_header.stop_bit != 0: + self.log.info( + pylog.c_FAIL + "stop bit is 1 in not last event [%i] for %s" % (i, str(trg)) + pylog.c_ENDC) + + # rhd counter + for i in range(0, len(hb_rdh_list)): + if hb_rdh_list[i].rdh_header.page_counter != i: + self.log.info(pylog.c_FAIL + "wrong counter in event [%i]: %i for %s" % (i, hb_rdh_list[i].rdh_header.page_counter, str(trg)) + pylog.c_ENDC) + + trg_check_list.append(trg) + + # strart / stop triggers + run_cnt = self.run.run_meta.ctrl_reg.trg_rd_command == readout_cmd.continious + if (self.rdh_packet_list[0].rdh_header.trg_type & (cnst.TRG_const_SOC if run_cnt else cnst.TRG_const_SOT)) == 0: + self.log.info(pylog.c_FAIL + "SOX not found" % () + pylog.c_ENDC) + if self.rdh_packet_list[-1].rdh_header.trg_type & (cnst.TRG_const_EOC if run_cnt else cnst.TRG_const_EOT) == 0: + self.log.info(pylog.c_FAIL + "EOX not found" % () + pylog.c_ENDC) + + self.log.info(pylog.c_OKGREEN + "HB rdh pattern [hb response, stop bit, rdh counter, XOR] checked for %i HBs:" % (len(trg_check_list)) + pylog.c_ENDC) + if len(trg_check_list) != self.run.stop_ortbit - self.run.start_orbit + 1: self.log.info(pylog.c_FAIL + "HB trigger count is wrong" + pylog.c_ENDC) + self.log.info([("trg: %x; orbc %04x:%03x" % (itrg['trigger'], itrg['orbit'], itrg['bc'])) for itrg in trg_check_list]) + + # counting generated data including to RDH + # self.log.info(str([("[pnum: %x; orbc %04x:%03x; sz: %i]" % (idat['pck_num'], idat['orbit'], idat['bc'], idat['size'])) for idat in self.run.gen_data[-10:]])) + gen_data_list = copy.copy(self.run.gen_data) + read_data_list = [ievent for irdh in self.rdh_packet_list for ievent in irdh.event_list] + read_data_count = len(read_data_list) + for igen in copy.copy(gen_data_list): + for ievent in copy.copy(read_data_list): + if ievent.orbit == igen['orbit'] and ievent.bc == igen['bc']: + if ievent.pck_num != igen['pck_num'] or ievent.size != igen['size']-1: + self.log.info((pylog.c_FAIL) + "data missmatch: [gen pck_num %i; size %i] [read pck_num %i; size %i]" % ( + igen['pck_num'], igen['size'], ievent.pck_num, ievent.size) + pylog.c_ENDC) + + if igen in gen_data_list: gen_data_list.remove(igen) + if ievent in read_data_list: read_data_list.remove(ievent) + + if len(read_data_list) > 0: + self.log.info(pylog.c_FAIL + "Output data not found in generated data: %i; %s" % ( + len(read_data_list), [("[pnum: %x; orbc %04x:%03x; sz: %i]" % (iev.pck_num, iev.orbit, iev.bc, iev.size)) for iev in read_data_list[:50]]) + pylog.c_ENDC) + + #cheking data dropped by selector after data_enable=0 + lost_evet_cont_iter = 0 + for inotrd, igen in zip(reversed(gen_data_list), reversed( self.run.gen_data ) ): + if inotrd['orbit'] != igen['orbit'] or inotrd['bc'] != igen['bc']: break + lost_evet_cont_iter += 1 + + dropped_data = self.run.last_status.sel_drop_cnt + self.run.last_status.cnv_drop_cnt + self.log.info("Generated data: %i; dropped data: %i; Readed data: %i; missed data: %i; last cont %i; excess data: %i" % ( + len(self.run.gen_data), dropped_data, read_data_count, len(gen_data_list)-dropped_data, lost_evet_cont_iter, len(read_data_list))) + + self.log.info((pylog.c_OKGREEN+"data not lost" if lost_evet_cont_iter >= len(gen_data_list)-dropped_data else pylog.c_FAIL+"data lost") + pylog.c_ENDC) + + + # if len(gen_data_list) > 0: + # self.log.info(pylog.c_FAIL + "Generated data not found in RDH packets: %i; %s" % ( + # len(gen_data_list), + # [("[pnum: %x; orbc %04x:%03x; sz: %i]" % (idat['pck_num'], idat['orbit'], idat['bc'], idat['size'])) for idat in gen_data_list[:50]]) + pylog.c_ENDC) + + # + # is_correct = (len(self.run.gen_data) == read_data_count + self.run.last_status.sel_drop_cnt) and len(read_data_list) == 0 + # self.log.info((pylog.c_OKGREEN if is_correct else pylog.c_FAIL) + "Generated data: %i; Readed data: %i; missed data: %i; dropped data: %i; excess data: %i" % ( + # len(self.run.gen_data), read_data_count, len(gen_data_list), self.run.last_status.sel_drop_cnt, len(read_data_list)) + pylog.c_ENDC) diff --git a/software/readout-sim/lib/simulation_data.py b/software/readout-sim/lib/simulation_data.py deleted file mode 100644 index afdf188..0000000 --- a/software/readout-sim/lib/simulation_data.py +++ /dev/null @@ -1,128 +0,0 @@ -# class to work with FIT readout unit control registers - -import lib.control_reg as cntrl_reg -import lib.status_reg as stat_reg -import lib.run_sim_data as run_data -import lib.pylog as pylog - -log = pylog.log - -class simulation_data_class: - def __init__(self, ctrl_file_name = 'simulation_inputs/simple_sig_inputs.txt',\ - gbt_data_file_name = 'simulation_outputs/readout_gbt_output.txt',\ - gbt_info_file_name = 'simulation_outputs/readout_gbt_info_output.txt',\ - status_file_name = 'simulation_outputs/readout_status_reg_output.txt'): - - # data set - self.ctrl_file_name = ctrl_file_name - self.gbt_data_file_name = gbt_data_file_name - self.gbt_info_file_name = gbt_info_file_name - self.status_file_name = status_file_name - - self.gbt_file = open(gbt_data_file_name, 'r') - self.gbt_info_file = open(gbt_info_file_name, 'r') - self.status_file = open(status_file_name, 'r') - self.ctrl_file = open(ctrl_file_name, 'r') - - self.gbt_data_list = list( self.gbt_file ) - self.gbt_info_list = list( self.gbt_info_file ) - self.ctrl_data_list = list( self.ctrl_file ) - self.status_data_list = list( self.status_file ) - - self.trig_gen_list = [] - self.data_gen_list = [] - - self.runs_list = [] - - self.get_gen_lists() - self.print_info() - - # getting run from control reg - search_run_str = 0 - get_run_ret = 0 - - - - while (get_run_ret != -3) and (get_run_ret != -1): - log.info("\n\nSearching run starting from %d/%d"%(search_run_str, len(self.ctrl_data_list)) ) - dyn_run = run_data.run_sim_data_class(self.ctrl_data_list, self.gbt_info_list) - - get_run_ret = dyn_run.get_run(search_run_str) - search_run_str = dyn_run.pos_last_read-1 - search_run_str = dyn_run.pos_run_stop - if get_run_ret == -1: log.debug("[-1] no run found ...") - if get_run_ret == -2: log.debug("[-2] run type switched (no idle command) ...") - if get_run_ret == -3: log.debug("[-3] run is not stopped, file end reached ...") - if get_run_ret == -4: log.debug("[-4] run is too short ...") - if get_run_ret == -5: log.debug("[-5] post run idle is too short ...") - if get_run_ret == -6: log.debug("[-6] control reg was changed while run ...") - if get_run_ret == 1: - log.info("run found: [str: %d, stp: %d, post idle len: %d]"%(dyn_run.pos_run_start, dyn_run.pos_run_stop, dyn_run.pos_run_postidl - dyn_run.pos_run_stop)) - dyn_run.find_gbt_pos() - dyn_run.print_info() - self.runs_list.append(dyn_run) - - - - - - - - def print_info(self): - log.info("#######################################################################################") - log.info("############################# SIMULATION DATA INFO ####################################") - log.info("#######################################################################################") - log.info("\ninputs files:") - log.info("gbt data: %s"%(self.gbt_data_file_name)) - log.info("gbt info: %s"%(self.gbt_info_file_name)) - log.info("control data: %s"%(self.ctrl_file_name)) - log.info("status data: %s"%(self.status_file_name)) - log.info("total triggers: %d"%( len(self.trig_gen_list) )) - log.info("total data: %d"%( len(self.data_gen_list) )) - print("trg gen list [or bc trg]: ", self.trig_gen_list) - print("data gen list [or bc nw]: ", self.data_gen_list) - - - def get_gen_lists(self): - dyn_stat_reg = stat_reg.status_reg_class() - - curr_pos = 5 - while curr_pos < len(self.status_data_list): - dyn_stat_reg.read_reg_line_hex(self.status_data_list[curr_pos]) - - if dyn_stat_reg.cru_trigger > 0: - self.trig_gen_list.append([dyn_stat_reg.cru_orbit, dyn_stat_reg.cru_bc, dyn_stat_reg.cru_trigger]) - - if dyn_stat_reg.data_gen_report > 0: - self.data_gen_list.append([dyn_stat_reg.cru_orbit_corr, dyn_stat_reg.cru_bc_corr, dyn_stat_reg.data_gen_report]) - - curr_pos += 1 - - # print(self.data_gen_list) - # print(self.trig_gen_list) - return - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/software/readout-sim/lib/status_reg.py b/software/readout-sim/lib/status_reg.py index 2678cbe..3aeabce 100644 --- a/software/readout-sim/lib/status_reg.py +++ b/software/readout-sim/lib/status_reg.py @@ -1,102 +1,115 @@ # class to work with FIT readout unit control registers from aenum import Enum -class gen_mode(Enum): - no_gen = 0 - main_gen = 1 - tx_gen = 2 +from lib.control_reg import readout_cmd -class readout_cmd(Enum): - idle = 0 - continious = 1 - trigger = 2 class bcid_smode(Enum): start = 0 sync = 1 lost = 2 + def __str__(self): + return self.name -class status_reg_class: - def __init__(self): - self.gbt_status = 0 + @property + def counter(self): + return self.value + + +class status_reg: + def __init__(self, reg_line=0): self.readout_mode = readout_cmd.idle + self.cru_readout_mode = readout_cmd.idle self.bcid_sync = bcid_smode.start - self.rx_phase = 0x0 - self.cru_readout_mode = readout_cmd.idle + self.fsm_errors = 0x0 + self.cnv_fifo_max = 0x0 + self.cnv_drop_cnt = 0x0 + self.sel_fifo_max = 0x0 + self.sel_drop_cnt = 0x0 + self.cru_orbit = 0x0 self.cru_bc = 0x0 + self.cru_trigger = 0x0 self.cru_orbit_corr = 0x0 self.cru_bc_corr = 0x0 - self.cru_trigger = 0x0 - self.data_gen_report = 0x0 + self.data_gen_orbit = 0x0 + self.data_gen_bc = 0x0 + self.data_gen_size = 0x0 + self.data_gen_packnum = 0 + self.data_enabled = 0 + self.gbt_counter = 0 + self.event_counter = 0 - self.raw_fifo_count = 0x0 + self.ipbusrd_err_report = 0x0 - self.slct_fifo_count = 0x0 - self.slct_frst_hd_orbit = 0x0 - self.slct_last_hd_orbit = 0x0 - self.slct_tot_hd = 0x0 - self.readout_rate = 0x0 + self.fsm_error_msg = {1 << 0: '[RDH builder] reading empty fifo', + 1 << 1: '[Selector] slct fifo is not empty', + 1 << 2: '[Selector] cntpck fifo is not empty', + 1 << 3: '[Selector] trg fifo is not empty', + 1 << 4: '[Selector] trg fifo is full', + 1 << 5: '[Converter] data fifo is not empty', + 1 << 6: '[Converter] header fifo is not empty', + 1 << 7: '[Converter] tcm_data_fifo is full'} + + if reg_line != 0: self.read_reg_line_hex(reg_line) def print_struct(self): print("======== status reg ========") - print(" gbt_status: ", self.gbt_status) print(" readout_mode:", self.readout_mode) + print(" cru_readout_mode: ", self.cru_readout_mode) print(" bcid_sync: ", self.bcid_sync) - print(" rx_phase: ", hex(self.rx_phase)) - print(" cru_readout_mode: ", self.cru_readout_mode) + print(" fsm_errors: ", hex(self.fsm_errors)) + print(" cnv_fifo_max: ", hex(self.cnv_fifo_max)) + print(" cnv_drop_cnt: ", hex(self.cnv_drop_cnt)) + print(" sel_fifo_max: ", hex(self.sel_fifo_max)) + print(" sel_drop_cnt: ", hex(self.sel_drop_cnt)) + print(" cru_orbit: ", hex(self.cru_orbit)) print(" cru_bc: ", hex(self.cru_bc)) + print(" cru_trigger: ", hex(self.cru_trigger)) print(" cru_orbit_corr: ", hex(self.cru_orbit_corr)) print(" cru_bc_corr: ", hex(self.cru_bc_corr)) - print(" cru_trigger: ", hex(self.cru_trigger)) - print(" data_gen_report: ", hex(self.data_gen_report)) + print(" data_gen_orbit: ", hex(self.data_gen_orbit)) + print(" data_gen_bc: ", hex(self.data_gen_bc)) + print(" data_gen_size: ", hex(self.data_gen_size)) + print(" data_enabled: ", hex(self.data_enabled)) - print(" raw_fifo_count: ", hex(self.raw_fifo_count)) + print(" gbt_counter: ", hex(self.gbt_counter)) + print(" event_counter: ", hex(self.event_counter)) - print(" slct_fifo_count: ", hex(self.slct_fifo_count)) - print(" slct_frst_hd_orbit: ", hex(self.slct_frst_hd_orbit)) - print(" slct_last_hd_orbit: ", hex(self.slct_last_hd_orbit)) - print(" slct_tot_hd: ", hex(self.slct_tot_hd)) - print(" readout_rate: ", hex(self.readout_rate)) - - - def read_reg_line_hex(self, line = "0 0 0 0 0 0 0 0 0 0 0 0"): - line = line.replace('X', '0') - line_regs = line.split(" ")[:-1] - #print(line_regs) + def get_fsm_err_msg(self): + res = "" + for key in self.fsm_error_msg: + if (self.fsm_errors & key) > 0: res += self.fsm_error_msg[key] + " " + return res + def read_reg_line_hex(self, line_regs): # - 20-19 19-18 18-17 17-16 16-15 15-14 14-13 13-12 12-11 11-10 10- 9 9 - 8 8 - 7 7 - 6 6 - 5 5 - 4 4 - 3 3 - 2 2 - 1 1 - # 79-76 75-72 71-68 67-64 63-60 59-56 55-52 51-48 47-44 43-40 39-36 35-32 31-28 27-24 23-20 19-16 15-12 11- 8 7 - 4 3 - 0 - self.gbt_status = int(line_regs[0][ -4: ], base=16) - self.readout_mode = readout_cmd( int(line_regs[0][ -5: -4], base=16) ) - self.bcid_sync = bcid_smode( int(line_regs[0][ -6: -5], base=16) ) - self.rx_phase = int(line_regs[0][ -7: -6], base=16) - self.cru_readout_mode = readout_cmd( int(line_regs[0][ -8: -7], base=16) ) - - self.cru_orbit = int(line_regs[1][ -8: ], base=16) - self.cru_bc = int(line_regs[2][ -3: ], base=16) - self.raw_fifo_count = int(line_regs[3][ -4: ], base=16) - self.slct_fifo_count = int(line_regs[3][ -8: -4], base=16) - self.slct_frst_hd_orbit = int(line_regs[4][ -8: ], base=16) - self.slct_last_hd_orbit = int(line_regs[5][ -8: ], base=16) - self.slct_tot_hd = int(line_regs[6][ -8: ], base=16) - self.readout_rate = int(line_regs[7][ -4: ], base=16) - self.cru_orbit_corr = int(line_regs[8][ -8: ], base=16) - self.cru_bc_corr = int(line_regs[9][ -3: ], base=16) - self.cru_trigger = int(line_regs[10][ -3: ], base=16) - self.data_gen_report = int(line_regs[11][ -3: ], base=16) - - - - - - - - - + self.readout_mode = readout_cmd(int(line_regs[0][-5: -4], base=16)) + self.cru_readout_mode = readout_cmd(int(line_regs[0][-8: -7], base=16)) + self.bcid_sync = bcid_smode(int(line_regs[0][-6: -5], base=16)) + self.cru_orbit = int(line_regs[1][-8:], base=16) + self.fsm_errors = int(line_regs[2][-8: -4], base=16) + self.cnv_drop_cnt = int(line_regs[3][-4:], base=16) + self.cnv_fifo_max = int(line_regs[3][-8: -4], base=16) + self.sel_drop_cnt = int(line_regs[4][-4:], base=16) + self.sel_fifo_max = int(line_regs[4][-8: -4], base=16) + self.gbt_counter = int(line_regs[5][-8:], base=16) + self.event_counter = int(line_regs[9][-8:], base=16) + self.ipbusrd_err_report = int(line_regs[10][-8:], base=16) + + self.cru_orbit_corr = int(line_regs[11][-8:], base=16) + self.cru_bc = int(line_regs[12][-7:-4], base=16) + self.cru_bc_corr = int(line_regs[12][-3:], base=16) + self.cru_trigger = int(line_regs[13][-3:], base=16) + self.data_gen_orbit = int(line_regs[14][-8:], base=16) + self.data_gen_bc = int(line_regs[15][-3:], base=16) + self.data_gen_size = int(line_regs[15][-5:-4], base=16) + self.data_enabled = int(line_regs[15][-7:-6], base=16) + self.data_gen_packnum = int(line_regs[16][-8:], base=16) diff --git a/software/readout-sim/simple_inputs.py b/software/readout-sim/simple_inputs.py deleted file mode 100644 index 637ecc7..0000000 --- a/software/readout-sim/simple_inputs.py +++ /dev/null @@ -1,90 +0,0 @@ -# this file generate simple text file -# used as inputs source in vhdl simulation -# data used as control register @40 MHz data clock - -#Dmitry Finogeev dmitry.fiongeev@cern.ch - -import lib.control_reg as cntrl_reg - -control_reg = cntrl_reg.control_reg_class() - - -sigin_file = open('simulation_inputs/simple_sig_inputs.txt', 'w') - - -# generators setup ============================ -control_reg.trg_rd_command = cntrl_reg.readout_cmd.idle -control_reg.trg_data_select = 0xFFFFFFFF -control_reg.bcid_delay = 0x2 - -control_reg.data_gen = cntrl_reg.gen_mode.main_gen -control_reg.data_trg_respond_mask = 0 -control_reg.data_bunch_pattern = 0x0 -control_reg.data_bunch_freq = 0xdec -control_reg.data_freq_offset = 0xdeb-5 -control_reg.trg_gen = cntrl_reg.gen_mode.main_gen -control_reg.trg_pattern_0 = 0x1 -control_reg.trg_pattern_1 = 0x0 -control_reg.trg_cont_val = 0x10 -control_reg.trg_bunch_freq = 0xdec -control_reg.trg_freq_offset = 0xdeb-5 - -control_reg.print_struct() -control_reg.print_raw() - - - -# start empty cycle =========================== -for i in range(1*0xdec): - sigin_file.write(control_reg.get_reg_line_16() + '\n') - - - -# gen offset sync ============================= -control_reg.reset_gen_offset = 0x1 -for i in range(10): sigin_file.write(control_reg.get_reg_line_16() + '\n') -control_reg.reset_gen_offset = 0x0 -for i in range(10): sigin_file.write(control_reg.get_reg_line_16() + '\n') -for i in range(2*0xdec): - sigin_file.write(control_reg.get_reg_line_16() + '\n') - - -# start empty cycle =========================== -for i in range(1*0xdec): - sigin_file.write(control_reg.get_reg_line_16() + '\n') -# continious run =========================== -print("continious run =================== ") -control_reg.trg_rd_command = cntrl_reg.readout_cmd.continious -for i in range(1*0xdec): - sigin_file.write(control_reg.get_reg_line_16() + '\n') -control_reg.data_bunch_pattern = 0x11111111 -for i in range(6*0xdec): - sigin_file.write(control_reg.get_reg_line_16() + '\n') -# end empty cycle =========================== -control_reg.trg_rd_command = cntrl_reg.readout_cmd.idle -control_reg.data_bunch_pattern = 0x0 -for i in range(2*0xdec): - sigin_file.write(control_reg.get_reg_line_16() + '\n') - - - -# start empty cycle =========================== -for i in range(2*0xdec): - sigin_file.write(control_reg.get_reg_line_16() + '\n') -# trigger run =========================== -print("trigger run =================== ") -control_reg.trg_rd_command = cntrl_reg.readout_cmd.trigger -for i in range(1*0xdec): - sigin_file.write(control_reg.get_reg_line_16() + '\n') -control_reg.data_bunch_pattern = 0x11111111 -for i in range(6*0xdec): - sigin_file.write(control_reg.get_reg_line_16() + '\n') -# end empty cycle =========================== -control_reg.trg_rd_command = cntrl_reg.readout_cmd.idle -for i in range(2*0xdec): - sigin_file.write(control_reg.get_reg_line_16() + '\n') - - - - -sigin_file.close() diff --git a/software/readout-sim/simple_reader.py b/software/readout-sim/simple_reader.py deleted file mode 100644 index 723e403..0000000 --- a/software/readout-sim/simple_reader.py +++ /dev/null @@ -1,43 +0,0 @@ -import lib.RDH_data as rdh_data -import lib.control_reg as cntrl_reg -import lib.status_reg as status_reg - - -gbt_out_file = open('simulation_outputs/readout_gbt_output.txt', 'r') -status_reg_out_file = open('simulation_outputs/readout_status_reg_output.txt', 'r') -ctrl_reg_in_file = open('simulation_inputs/simple_sig_inputs.txt', 'r') - -flines_status = list(status_reg_out_file) - -dynamic_status_reg = status_reg.status_reg_class() -dynamic_status_reg.read_reg_line_hex(flines_status[30200]) -dynamic_status_reg.print_struct() - - - -# file_lines = list(gbt_out_file) -# ctrl_reg_lines = list(ctrl_reg_in_file) - - -# dynamic_cntrl_reg = cntrl_reg.control_reg_class() -# dynamic_cntrl_reg.read_reg_line_16(ctrl_reg_lines[0]) -# dynamic_cntrl_reg.print_struct() - -# print( file_lines ) -#dynamic_rdh = rdh_data.rdh_header_class() -#dynamic_ddata = rdh_data.detector_event_class() - -# newp = dynamic_rdh.read_rdh(file_lines, pos = 0) -# dynamic_rdh.print_raw() -# dynamic_rdh.print_struct() -# -# dynamic_ddata.read_data(file_lines, newp) -# dynamic_ddata.print_raw() -# dynamic_ddata.print_struct() - -# dyn_event = rdh_data.rdh_data_class() -# pos = dyn_event.read_data(file_lines, 0) -# dyn_event.print_raw() -# dyn_event.print_struct() -# -# print(file_lines[pos]) diff --git a/software/readout-sim/testbench.py b/software/readout-sim/testbench.py deleted file mode 100644 index b91018f..0000000 --- a/software/readout-sim/testbench.py +++ /dev/null @@ -1,76 +0,0 @@ -# testbench - run file - - -# simulation_data_class: file info -# * list of run_sim_data_class (run parameters from inputs file) -# -# run_testbench_class: data reading + tesbench procedure + report per run - - - - - - -import lib.simulation_data as sim_data -import lib.run_testbench as run_test -import lib.inputs_gen as in_file_gen -import lib.RDH_data as rdh_data -import lib.control_reg as cntrl_reg -import lib.status_reg as status_reg - - - - -# generates inputs file -infile_gen = in_file_gen.input_generator_class() - -infile_gen.control_reg.trg_data_select = 0xFFFFFFFF -infile_gen.control_reg.bcid_delay = 0x2 -infile_gen.control_reg.data_trg_respond_mask = 0 -infile_gen.control_reg.data_bunch_pattern = 0x11111111 -infile_gen.control_reg.data_bunch_freq = 0xdec -infile_gen.control_reg.data_freq_offset = 0xdeb-5 -infile_gen.control_reg.trg_pattern_0 = 0x1 -infile_gen.control_reg.trg_pattern_1 = 0x0 -infile_gen.control_reg.trg_cont_val = 0x10 -infile_gen.control_reg.trg_bunch_freq = 0xdec -infile_gen.control_reg.trg_freq_offset = 0xdeb-5 - -# reset generators -infile_gen.gen_gsync_signal() - -# normal continious -infile_gen.gen_run(cntrl_reg.readout_cmd.continious) - -# normal trigger -infile_gen.gen_run(cntrl_reg.readout_cmd.trigger) - -# reset generators -infile_gen.control_reg.data_bunch_freq = 0x100 -infile_gen.control_reg.max_data_payload = 0xFF -infile_gen.gen_gsync_signal() - -# load continious -infile_gen.gen_run(cntrl_reg.readout_cmd.continious) - -# spam continious -infile_gen.gen_run_spam(cntrl_reg.readout_cmd.continious) - -# stop idle -infile_gen.gen_empty_cicle() - - - -#======================================================= -# vivado simulation should be run here -#======================================================= - - - - - -# run testbench -simulation_data = sim_data.simulation_data_class() -for irun in range(0, len(simulation_data.runs_list)): - run_testbench = run_test.run_testbench_class(simulation_data, irun) - diff --git a/software/readout-sim/time_test.py b/software/readout-sim/time_test.py new file mode 100644 index 0000000..89b7b1c --- /dev/null +++ b/software/readout-sim/time_test.py @@ -0,0 +1,9 @@ +import cProfile +import pstats +import verify_sim_outputs + +cProfile.run('verify_sim_outputs.verify_sim_outputs()', 'restats') + +p = pstats.Stats('restats') +p.sort_stats('time') +p.print_stats() diff --git a/software/readout-sim/verify_sim_outputs.py b/software/readout-sim/verify_sim_outputs.py new file mode 100644 index 0000000..8163f60 --- /dev/null +++ b/software/readout-sim/verify_sim_outputs.py @@ -0,0 +1,42 @@ +''' + +Main function to verify readout simulation outputs + +Dmitry Finogeev dmitry.finogeev@cern.ch +07/2021 + +''' + +import pickle + +import lib.constants as cnst +import lib.pylog as pylog +from lib.run_reader import run_reader +from lib.run_tester import run_tester + +log = pylog.log + + +def verify_sim_outputs(): + # loading run metadata + with open(cnst.filename_runmeta, 'rb') as f: + run_list = pickle.load(f) + + for irun in run_list: + log.info("============================================") + irun.print_run_meta() + log.info("============================================") + + sim_run = run_reader(irun) + if not sim_run.run_valid: + log.info(pylog.c_FAIL + "RUN reader failed\n\n\n\n" + pylog.c_ENDC) + continue + + sim_run.print_run_info() + run_test = run_tester(sim_run) + run_test.test_data + log.info("============================================\n\n\n\n") + + +if __name__ == '__main__': + verify_sim_outputs()