@@ -75,16 +75,13 @@ class HCIDriver : public CordioHCIDriver {
7575public:
7676 HCIDriver (
7777 ble::vendor::cypress_ble::CyH4TransportDriver& transport_driver,
78- PinName bt_power_name,
79- bool ps_enabled,
80- uint8_t host_wake_irq,
81- uint8_t dev_wake_irq
78+ bool ps_enabled,
79+ uint8_t host_wake_irq,
80+ uint8_t dev_wake_irq
8281 ) : CordioHCIDriver(transport_driver),
83- bt_power_name (bt_power_name),
84- bt_power(bt_power_name, PIN_OUTPUT, PullUp, 0 ),
85- is_powersave_enabled(ps_enabled),
86- host_wake_irq(host_wake_irq),
87- dev_wake_irq(dev_wake_irq),
82+ is_powersave_enabled (ps_enabled),
83+ host_wake_irq(host_wake_irq),
84+ dev_wake_irq(dev_wake_irq),
8885 service_pack_index(0 ),
8986 service_pack_ptr(0 ),
9087 service_pack_length(0 ),
@@ -101,9 +98,6 @@ class HCIDriver : public CordioHCIDriver {
10198
10299 virtual void do_initialize ()
103100 {
104- rtos::ThisThread::sleep_for (500ms);
105- bt_power = 1 ;
106- rtos::ThisThread::sleep_for (500ms);
107101 }
108102
109103 virtual void do_terminate () { }
@@ -419,68 +413,68 @@ class HCIDriver : public CordioHCIDriver {
419413
420414 void set_sleep_mode ()
421415 {
422- uint8_t *pBuf;
423- if ((pBuf = hciCmdAlloc (HCI_VS_CMD_SET_SLEEP_MODE, 12 )) != NULL )
424- {
425- if (is_powersave_on ()) {
426- pBuf[HCI_CMD_HDR_LEN] = 0x01 ; // sleep
427- } else {
428- pBuf[HCI_CMD_HDR_LEN] = 0x00 ; // no sleep
429- }
430- pBuf[HCI_CMD_HDR_LEN + 1 ] = 0x00 ; // no idle threshold host (N/A)
431- if (is_powersave_on ()) {
432- pBuf[HCI_CMD_HDR_LEN + 2 ] = 0x05 ; // no idle threshold HC (N/A)
433- } else {
434- pBuf[HCI_CMD_HDR_LEN + 2 ] = 0x00 ; // no idle threshold HC (N/A)
435- }
436- if (is_powersave_on ()) {
437- pBuf[HCI_CMD_HDR_LEN + 3 ] = dev_wake_irq; // BT WAKE
438- } else {
439- pBuf[HCI_CMD_HDR_LEN + 3 ] = 0x00 ; // BT WAKE
440- }
441- if (is_powersave_on ()) {
442- pBuf[HCI_CMD_HDR_LEN + 4 ] = host_wake_irq; // HOST WAKE
443- } else {
444- pBuf[HCI_CMD_HDR_LEN + 4 ] = 0x00 ; // HOST WAKE
445- }
446- pBuf[HCI_CMD_HDR_LEN + 5 ] = 0x00 ; // Sleep during SCO
447- pBuf[HCI_CMD_HDR_LEN + 6 ] = 0x00 ; // Combining sleep mode and SCM
448- pBuf[HCI_CMD_HDR_LEN + 7 ] = 0x00 ; // Tristate TX
449- pBuf[HCI_CMD_HDR_LEN + 8 ] = 0x00 ; // Active connection handling on suspend
450- pBuf[HCI_CMD_HDR_LEN + 9 ] = 0x00 ; // resume timeout
451- pBuf[HCI_CMD_HDR_LEN + 10 ] = 0x00 ; // break to host
452- pBuf[HCI_CMD_HDR_LEN + 11 ] = 0x00 ; // Pulsed host wake
453- hciCmdSend (pBuf);
416+ uint8_t *pBuf;
417+ if ((pBuf = hciCmdAlloc (HCI_VS_CMD_SET_SLEEP_MODE, 12 )) != NULL )
418+ {
419+ if (is_powersave_on ()) {
420+ pBuf[HCI_CMD_HDR_LEN] = 0x01 ; // sleep
421+ } else {
422+ pBuf[HCI_CMD_HDR_LEN] = 0x00 ; // no sleep
423+ }
424+ pBuf[HCI_CMD_HDR_LEN + 1 ] = 0x00 ; // no idle threshold host (N/A)
425+ if (is_powersave_on ()) {
426+ pBuf[HCI_CMD_HDR_LEN + 2 ] = 0x05 ; // no idle threshold HC (N/A)
427+ } else {
428+ pBuf[HCI_CMD_HDR_LEN + 2 ] = 0x00 ; // no idle threshold HC (N/A)
429+ }
430+ if (is_powersave_on ()) {
431+ pBuf[HCI_CMD_HDR_LEN + 3 ] = dev_wake_irq; // BT WAKE
432+ } else {
433+ pBuf[HCI_CMD_HDR_LEN + 3 ] = 0x00 ; // no BT WAKE
434+ }
435+ if (is_powersave_on ()) {
436+ pBuf[HCI_CMD_HDR_LEN + 4 ] = host_wake_irq; // HOST WAKE
437+ } else {
438+ pBuf[HCI_CMD_HDR_LEN + 4 ] = 0x00 ; // no HOST WAKE
454439 }
440+ pBuf[HCI_CMD_HDR_LEN + 5 ] = 0x00 ; // Sleep during SCO
441+ pBuf[HCI_CMD_HDR_LEN + 6 ] = 0x00 ; // Combining sleep mode and SCM
442+ pBuf[HCI_CMD_HDR_LEN + 7 ] = 0x00 ; // Tristate TX
443+ pBuf[HCI_CMD_HDR_LEN + 8 ] = 0x00 ; // Active connection handling on suspend
444+ pBuf[HCI_CMD_HDR_LEN + 9 ] = 0x00 ; // resume timeout
445+ pBuf[HCI_CMD_HDR_LEN + 10 ] = 0x00 ; // break to host
446+ pBuf[HCI_CMD_HDR_LEN + 11 ] = 0x00 ; // Pulsed host wake
447+ hciCmdSend (pBuf);
448+ }
455449 }
456450
457451 // 0x18, 0xFC, 0x06, 0x00, 0x00, 0xC0, 0xC6, 0x2D, 0x00, //update uart baudrate 3 mbp
458452 void HciUpdateUartBaudRate ()
459453 {
460- uint8_t *pBuf;
461- if ((pBuf = hciCmdAlloc (HCI_VS_CMD_UPDATE_UART_BAUD_RATE, 6 )) != NULL )
462- {
463- pBuf[HCI_CMD_HDR_LEN] = 0x00 ; // encoded_baud_rate
464- pBuf[HCI_CMD_HDR_LEN + 1 ] = 0x00 ; // use_encoded_form
465- pBuf[HCI_CMD_HDR_LEN + 2 ] = 0xC0 ; // explicit baud rate bit 0-7
466- pBuf[HCI_CMD_HDR_LEN + 3 ] = 0xC6 ; // explicit baud rate bit 8-15
467- pBuf[HCI_CMD_HDR_LEN + 4 ] = 0x2D ; // explicit baud rate bit 16-23
468- pBuf[HCI_CMD_HDR_LEN + 5 ] = 0x00 ; // explicit baud rate bit 24-31
469- hciCmdSend (pBuf);
470- }
454+ uint8_t *pBuf;
455+ if ((pBuf = hciCmdAlloc (HCI_VS_CMD_UPDATE_UART_BAUD_RATE, 6 )) != NULL )
456+ {
457+ pBuf[HCI_CMD_HDR_LEN] = 0x00 ; // encoded_baud_rate
458+ pBuf[HCI_CMD_HDR_LEN + 1 ] = 0x00 ; // use_encoded_form
459+ pBuf[HCI_CMD_HDR_LEN + 2 ] = 0xC0 ; // explicit baud rate bit 0-7
460+ pBuf[HCI_CMD_HDR_LEN + 3 ] = 0xC6 ; // explicit baud rate bit 8-15
461+ pBuf[HCI_CMD_HDR_LEN + 4 ] = 0x2D ; // explicit baud rate bit 16-23
462+ pBuf[HCI_CMD_HDR_LEN + 5 ] = 0x00 ; // explicit baud rate bit 24-31
463+ hciCmdSend (pBuf);
464+ }
471465 }
472466
473467 static const uint16_t HCI_OPCODE_WRITE_LE_HOST_SUPPORT = 0x0C6D ;
474468
475469 void HciWriteLeHostSupport ()
476470 {
477- uint8_t *pBuf;
478- if ((pBuf = hciCmdAlloc (HCI_OPCODE_WRITE_LE_HOST_SUPPORT, 2 )) != NULL )
479- {
480- pBuf[HCI_CMD_HDR_LEN] = 0x01 ;
481- pBuf[HCI_CMD_HDR_LEN + 1 ] = 0x00 ;
482- hciCmdSend (pBuf);
483- }
471+ uint8_t *pBuf;
472+ if ((pBuf = hciCmdAlloc (HCI_OPCODE_WRITE_LE_HOST_SUPPORT, 2 )) != NULL )
473+ {
474+ pBuf[HCI_CMD_HDR_LEN] = 0x01 ;
475+ pBuf[HCI_CMD_HDR_LEN + 1 ] = 0x00 ;
476+ hciCmdSend (pBuf);
477+ }
484478 }
485479
486480 void hciCoreReadResolvingListSize (void )
@@ -503,7 +497,7 @@ class HCIDriver : public CordioHCIDriver {
503497
504498 void hciCoreReadMaxDataLen (void )
505499 {
506- /* if LE Data Packet Length Extensions is supported by Controller and included */
500+ /* if LE Data Packet Length Extensions is supported by Controller and included */
507501 if ((hciCoreCb.leSupFeat & HCI_LE_SUP_FEAT_DATA_LEN_EXT) &&
508502 (hciLeSupFeatCfg & HCI_LE_SUP_FEAT_DATA_LEN_EXT))
509503 {
@@ -522,9 +516,6 @@ class HCIDriver : public CordioHCIDriver {
522516 return (is_powersave_enabled);
523517 }
524518
525- PinName bt_power_name;
526- mbed::DigitalInOut bt_power;
527-
528519 bool is_powersave_enabled;
529520 uint8_t host_wake_irq;
530521 uint8_t dev_wake_irq;
@@ -546,12 +537,12 @@ ble::CordioHCIDriver& ble_cordio_get_hci_driver()
546537{
547538 static ble::vendor::cypress_ble::CyH4TransportDriver& transport_driver =
548539 ble_cordio_get_h4_transport_driver ();
540+
549541 static ble::vendor::cypress::HCIDriver hci_driver (
550542 transport_driver,
551- /* bt_power */ CYBSP_BT_POWER,
552- transport_driver.get_enabled_powersave (),
553- transport_driver.get_host_wake_irq_event (),
554- transport_driver.get_dev_wake_irq_event ()
543+ transport_driver.get_enabled_powersave (),
544+ transport_driver.get_host_wake_irq_event (),
545+ transport_driver.get_dev_wake_irq_event ()
555546 );
556547 return hci_driver;
557548}
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